KR20130011265A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and an operating method thereof are provided to reduce data transition in a data operating unit by sequentially operating all even gate lines to apply a scan signal. CONSTITUTION: A receiving unit(410) receives a timing signal and image data from a system. An image data processing unit(430) outputs the received image data by rearranging the same. A pattern detecting unit(440) analyzes the image data to detect a specific pattern. A control signal generating unit(420) generates a control signal. The control signal operates a gate operating unit. [Reference numerals] (410) Receiving unit; (420) Control signal generating unit; (430) Image data processing unit; (440) Pattern detecting unit; (450) Transmission unit

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device using a Z-inversion method and a driving method thereof.

A liquid crystal display device displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

To this end, a liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving unit for driving the liquid crystal panel.

On the other hand, such a liquid crystal display device drives the liquid crystal panel in an inversion manner in order to prevent degradation of the liquid crystal and to improve display quality. Inversion methods include Frame Inversion System, Line Inversion System, Column Inversion System, Dot Inversion System, or Z-Inversion ( Z-Inversion System) method is used.

Among the inversion schemes described above, the Z-inversion scheme includes a data line in which the thin film transistor TFT and the pixel electrode PXL are arranged in a zigzag shape in which the left and right sides are alternately arranged along the data line D. For example, the pixel signals are supplied in a column inversion manner. That is, the Z-inversion method is an improved structure of the column inversion method, and the circuit driving method uses the column inversion method. However, the direction of the thin film transistor TFT of the liquid crystal panel is reversed for each line. The screen display is implemented in the same way as the dot inversion system. In detail, the Z-inversion method has an effect similar to that of the dot inversion method in terms of image quality, but also uses a column inversion method in terms of data. This is a way to significantly reduce the cost.

FIG. 1 is an exemplary view showing a part of a liquid crystal panel of a conventional liquid crystal display device using a Z-inversion method, and FIG. 2 shows a relationship between various patterns and power consumption applied to the liquid crystal display device shown in FIG. FIG. 3 is a diagram illustrating various waveforms output from a data driver of a conventional liquid crystal display device using a Z-inversion method.

First, as described in FIG. 1 and Patent Application No. 10-2002-0070305, a thin film transistor (TFT) 11 formed on the liquid crystal panel 10 of the liquid crystal display device using the Z-inversion method. And the pixel electrodes PXL 12 are arranged in a zigzag pattern in which positions are alternated left and right along the data line D. FIG.

In other words, the thin film transistors TFT 11 and the pixel electrode PXL 12 included in the same column are alternately connected to adjacent data lines D for each horizontal line.

Therefore, when scan signals are sequentially input from the first gate line G1 to the third gate line G3, the pixel electrodes 12 connected to the left and right sides of the second data line D2 are illustrated in FIG. It is sequentially driven along the arrow direction shown in 1 to display an image.

Meanwhile, FIG. 2 is an exemplary diagram showing the power consumption according to various patterns applied to the liquid crystal panel shown in FIG. 1, (a) shows power consumption for a general pattern, and (b) shows specific power patterns. It shows the power consumption.

That is, in the specific pattern, black data is input to the m-th column line as in the vertical lines pattern (Lines Vertical) shown in (b), and white data is input to the m + 1 column line adjacent thereto. The m-th column line and the m-th + 1th column line is a pattern that is repeatedly represented, or black data is input to the n-th horizontal line, such as the horizontal line pattern (Lines Horizontal), and adjacent to the n-th horizontal line Denotes a pattern in which white data is input and the nth horizontal line and the nth horizontal line are repeatedly expressed.

On the other hand, as shown in Figure 2, in the liquid crystal display device using the Z-inversion method, the power consumption is large in the specific patterns as shown in (b), in particular, vertical of the specific patterns It can be seen that the power consumption of the lines pattern is large.

The reason why the power consumption is large in the vertical line pattern is because a data transition occurs, as shown in FIG.

For example, when the liquid crystal display device using the Z-inversion method is driven under normal driving conditions, if the same image data signal (for example, black data) is output from the data driver, the third data line D3 is used by the data driver. As shown in (a) of FIG. 3, the waveform of the signal outputted in FIG. 3 will have a constant value without data transition, and therefore, power consumption will be low.

Further, even when the value of the output image data signal is changed (that is, changed from white to black or changed from black to white), in the general pattern as shown in FIG. As shown in (b) of 3, since it is changed to have a period larger than 3 horizontal periods (3H), it can be seen that the data transition is not large and power consumption is low.

However, especially when the vertical line pattern among the specific patterns is input, the period of the waveform according to the data transition is shorter than 2 horizontal periods (2H), so that the output voltage of the image data signal output from the data driver suddenly changes. Therefore, power consumption in the data driver is large.

For example, if a pattern (vertical line pattern) in which white is output to the first column C1 and all black are output to the second column C2 is input in FIG. 1, the odd-numbered gate line G1, Pixels in the radix columns C1, C3, ... driven by G3, ...) and radix data lines D2, D4, ... are shown in white, even gate lines and even Pixels of even-numbered columns C2, C4, ... driven by the first data line are displayed in black.

Therefore, assuming that the voltage value of the image data signal when displayed in white is 16V, and the voltage value of the image data signal when displayed in black is 8V, when the vertical line pattern is input as a specific pattern, As the voltage value of the data signal is a reference to one data line, a section in which a sudden change from 8V to 16V occurs for each adjacent gate line, and power consumption due to the data transition is increasing.

That is, in the liquid crystal display device using the Z-inversion method, there is a problem in that the output voltage value of the data signal is suddenly changed by a specific pattern, so that the power consumption due to the data transition may increase.

The present invention is to solve the above-described problem, when a specific pattern that requires a lot of power consumption when the Z-Inversion method is driven, the scan signal is applied by sequentially driving all odd-numbered gate lines in one frame It is a technical object of the present invention to provide a liquid crystal display device and a method of driving the same, in which all even-numbered gate lines are sequentially driven to apply a scan signal.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel having a plurality of pixels formed by crossing gate lines and data lines, and driven by a Z-inversion method; A gate driver for applying a scan signal to the gate lines; A data driver for applying an image data signal to the data lines; When driving in the Z-inversion method, it is determined whether a specific pattern which is set to consume a large amount of power is input. When the specific pattern is not input, the scan signal is sequentially applied to the gate lines. The gate driver is driven in a first mode, and when the specific pattern is applied, all odd-numbered gate lines are sequentially driven in one frame to apply a scan signal, and then all even-numbered gate lines are sequentially applied. And a timing controller for driving the gate driver in a second mode to drive the gate signal by applying a scan signal.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: determining whether a specific pattern having a high power consumption is input when driven in a Z-inversion method; Driving the gate driver in a first mode in which scan signals are sequentially applied to gate lines when the specific pattern is not input; And when the specific pattern is applied, driving all the odd-numbered gate lines sequentially in one frame to apply a scan signal, and then driving all of the even-numbered gate lines sequentially to apply a scan signal. Driving the gate driver.

According to the above solution, the present invention provides the following effects.

That is, in the present invention, when a specific pattern that requires a lot of power consumption is input when driven in a Z-inversion scheme, the odd-numbered gate lines are applied after sequentially driving all odd-numbered gate lines in one frame. By sequentially driving all of them and applying a scan signal, the data transition in the data driver can be reduced, thereby reducing the power consumption.

1 is an exemplary view showing a part of a liquid crystal panel of a conventional liquid crystal display device using a Z-inversion method.
FIG. 2 is an exemplary diagram illustrating a relationship between various patterns and power consumption applied to the liquid crystal display shown in FIG. 1.
3 is a diagram illustrating various waveforms outputted from a data driver in a conventional liquid crystal display device using a Z-inversion method.
4 is an exemplary view showing a configuration of a liquid crystal display device according to the present invention.
5 is an exemplary view showing an internal configuration of a timing controller of a liquid crystal display according to the present invention.
6 is an exemplary view showing a gate driver which is controlled by a timing controller in the liquid crystal display according to the present invention and outputs a scan signal to a gate line.
7 is an exemplary view showing waveforms of control signals generated by a timing controller in a liquid crystal display according to the present invention.
8 is an exemplary view illustrating a state in which pixels are driven in a liquid crystal panel of a liquid crystal display according to the present invention.
9 is an exemplary view showing waveforms output from a data driver of a liquid crystal display according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an exemplary view showing a configuration of a liquid crystal display according to the present invention.

As shown in FIG. 4, the liquid crystal display according to the present invention includes a liquid crystal panel 100 having a liquid crystal cell matrix, a gate driver 200 for driving gate lines GL1 to GLn of the liquid crystal panel, and a liquid crystal panel. And a timing controller 400 for controlling the data driver 300 for driving the data lines DL1 to DLm, the gate driver, and the data driver.

First, the liquid crystal panel 100 includes a thin film transistor TFT formed at each region defined by the intersection of the gate lines GL1 to GLn 110 and the data lines DL1 to DLm, and the pixel electrode PXL 140. It comprises a liquid crystal cell comprising a.

The thin film transistor TFT supplies the pixel signal (image data signal) from the data lines DL1 to DLm to the pixel electrode PXL 140 in response to the scan signal from the gate line GL. The pixel electrode PXL 140 adjusts the light transmittance by driving a liquid crystal positioned between the common electrode and the common electrode in response to the pixel signal.

In particular, the thin film transistor TFT and the pixel electrode PXL are arranged in a zigzag shape in which their positions alternate left and right along the data line DL. That is, the thin film transistors TFT and the pixel electrode PXL included in the same column are alternately connected to different adjacent data lines DL for each horizontal line.

For example, in FIG. 4, the thin film transistor TFT and the pixel electrode PXL of the odd horizontal line connected to the odd gate lines GL1, GL3, GL5,. The mth data lines DL2 to DLm are respectively connected. Accordingly, the pixel electrode PXL of the odd horizontal line charges the pixel signal from the data line DL adjacent to the right through the thin film transistor TFT.

On the other hand, the thin film transistor TFT and the pixel electrode PXL of the even-numbered horizontal line connected to the even-numbered gate lines GL2, GL4, GL6,... Here, m is connected to even) data lines DL1 to DLm, respectively. Accordingly, the pixel electrode PXL of the even-th horizontal line charges the pixel signal from the data line adjacent to the left through the thin film transistor TFT.

Next, the timing controller 400 generates control signals for controlling the gate driver 200 and the data driver 300, and supplies image data to the data driver 300. The gate control signals generated by the timing controller 400 include a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like. In addition, the data control signals generated by the timing controller 400 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

Meanwhile, the timing controller 400 applied to the present invention determines whether a specific pattern requiring a large amount of power is input. When a specific pattern is input, the timing controller 400 sequentially drives all of the odd-numbered gate lines in one frame to scan. After the signal is applied, all even-numbered gate lines are sequentially driven to apply a scan signal, thereby minimizing data transition in the data driver to minimize power consumption.

This will be described in detail with reference to FIGS. 5 and 6 below.

Next, the gate driver 200 supplies a scan signal to the gate lines GL1 to GLn using the gate control signals. Accordingly, the thin film transistors TFT are driven in units of horizontal lines in response to the scan signal.

Finally, the data driver 300 converts the input image data into an analog pixel signal (image data signal) and converts the pixel signal of one horizontal line into one horizontal line every one horizontal period in which the scan signal is supplied to the gate line GL. To DL1 to DLm. In this case, the data driver 300 converts the image data into a pixel signal (image data signal) using gamma voltages supplied from the gamma voltage generator (not shown).

The data driver 300 supplies pixel signals in a column inversion manner so that pixel signals supplied to each of the data lines DL1 to DLm have polarities opposite to those of the adjacent data lines DL, and their polarities are frame-by-frame. Let it be reversed. In other words, the data driver 300 supplies pixel signals of opposite polarities to the odd data lines DL1, DL3,... And even data lines DL2, DL4,. Polarities of the pixel signals supplied to the fields are reversed in units of frames.

In this case, since the pixel electrodes PXL 140 are arranged in a zigzag pattern based on the data lines DL1 to DLm to which the pixel signals are supplied in a column inversion manner, the liquid crystal cell including the pixel electrodes PXL. They are driven in a dot inversion manner.

5 is an exemplary view showing an internal configuration of a timing controller of a liquid crystal display according to the present invention.

The timing controller 400 applied to the present invention uses the vertical / horizontal synchronization signals Vsync and Hsync and the dot clock signal DCLK supplied from a system (not shown) to control the gate driver 200. The data control signal DCS for controlling the signal GCS and the data driver 300 are output.

To this end, as shown in FIG. 5, the timing controller includes a receiver 410 for receiving image data and a timing signal from a system, an image data processor 430 for rearranging and outputting image data received through the receiver; The pattern detector 440 detects each frame whether or not a specific pattern requires a large amount of power consumption by analyzing the received image data, and in the first mode, the gate driver using the timing signal received through the receiver. By generating the gate control signal GCS and the data control signal DCS for controlling the data driver, the gate lines are sequentially driven, and a signal indicating that a specific pattern is detected from the pattern detector (hereinafter, simply referred to as a 'pattern detection signal'). Is received, the scan signal for driving the gate lines is switched to the second mode and the odd gate A control signal generator for generating a control signal (hereinafter, simply referred to as an enable signal ENS) for controlling the gate driver to be sequentially output to the even-numbered gate lines and then sequentially to the even-numbered gate lines ( 420 and a transmitter 450 for outputting a control signal transmitted from the control signal generator and an image data transmitted from the image data processor or the pattern detector.

First, the receiver 110 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock DCLK, a data enable signal DE, and an image data RGB from an external system (not shown). As a function to perform the function, it may be configured as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface.

Next, the image data processor 430 rearranges the image signal RGB input from the external system to match the resolution of the liquid crystal panel 102 and supplies the image signal RGB to the data driver 300.

Next, the pattern detector 440 performs a function of detecting a predetermined specific pattern. Here, in the liquid crystal display according to the present invention, which is driven by the Z-inversion method, more power consumption is required than power consumption in the data driver when the gate line is driven in the first mode. As a pattern, a mode for driving the gate line when the specific pattern is input is called a second mode.

The specific pattern may be any one of the specific patterns described with reference to FIG. 2. In the following, in particular, the vertical patterns, which are determined to consume the most power consumption, are considered as an example of the specific pattern. The invention is described.

As a method of detecting such a specific pattern, the following method may be used.

That is, the pattern detection unit 440 stores the image data received through the image data processing unit or the reception unit for each frame, and then the previous frame (hereinafter, simply referred to as the 'n-th frame') and the next frame (hereinafter, simply 'n'). The gray level value of each pixel of the + 1st frame 'is compared with each other, so that at least one column is represented in black as a specific pattern (Lines Vertical) shown in FIG. By determining whether the gray level values of the left and right columns are displayed in white, it is possible to determine whether or not they are a specific pattern.

In detail, the pattern detecting unit compares and analyzes each pixel in a frame unit so that black is displayed in the column direction, and white, that is, R, G, and B are brightest in the adjacent columns. If it is determined that the input is, it is recognized as a specific pattern having a vertical lines pattern (Lines Vertical). However, various methods may be applied to the method of detecting a specific pattern in addition to the above method.

Meanwhile, when the specific pattern as described above is detected, the pattern detector 440 transmits a pattern detection signal (PDS) to the control signal generator 420.

That is, the pattern detection unit detects whether a specific pattern is being received, and if a specific pattern is detected, transmits a pattern detection signal (PDS) informing the control signal generator to drive the gate line in the second mode. The control signal generator generates a control signal capable of generating a control signal.

In this second mode, scan signals are sequentially supplied to odd-numbered gate lines (or even-numbered gate lines) among the gate lines, and then sequentially scanned to even-numbered gate lines (or odd-numbered gate lines). The signal is supplied.

That is, in the first mode, the scan signals are sequentially supplied to all the gate lines. In the second mode, the odd-numbered gate lines and the even-numbered gate lines are grouped to sequentially supply the scan signals.

Next, the control signal generator 420 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable, dot clock signal (CLK), and the like, and the data driver 300 and the gate. A function of generating data control signals DCS and gate control signals GCS for controlling the operation timing of the driver 200 is performed.

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate clock (GCKL), and a gate output enable signal (GOE). Included.

The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), and a polarity control signal (POL). Etc. are included.

That is, the control signal generator generates a gate control signal capable of driving the gate driver by using the timing signal and transmits the gate control signal to the gate driver to sequentially apply the scan signal to the gate line. The mode in which the lines are sequentially driven is called a first mode.

Meanwhile, when the pattern detection signal PDS is received from the pattern detector 440, the control signal generator generates an enable signal ENS as a control signal for driving the gate line in the second mode as described above.

Here, the enable signal is sequentially supplied to even-numbered gate lines (or odd-numbered gate lines) after a scan signal is sequentially supplied to odd-numbered gate lines (or even-numbered gate lines) among the gate lines. It is a control signal for supplying a signal.

For example, the enable signal ENS is applied to the switching unit formed at the output terminal of the first stage Stage1 of the shift register from the gate driver configured as shown in FIG. 7 to be described below. The first scan signal output from the stage and applied to the first gate line GL1 is supplied to the third stage, so that the third stage outputs the third scan signal to be applied to the third gate line. Can be.

In addition to the configuration shown in FIG. 7 to be described below, the enable signal ENS may be applied to the gate driver configured in another form so that the gate line outputs the scan signal in the second mode as described above. .

In addition, the enable signal ENS may allow the timing controller or the gate driver to generate another gate control signal for causing the gate line to output the scan signal in the second mode as described above. That is, the gate driver may include various gates such as a gate start pulse (GSP), a gate shift clock signal (GSC), a gate clock (GCKL), and a gate output enable signal (GOE). As driven by the control signal, the gate driver may be driven in the second mode by generating a new gate control signal in which the gate control signals are changed.

Finally, the transmitter 450 may transmit various gate control signals and data control signals output from the control signal generator, and image data transmitted from the pattern detector or the image data processor to the gate driver and the data driver. have

FIG. 6 is an exemplary view showing a gate driver controlled by a timing controller and outputting a scan signal to a gate line in a liquid crystal display according to the present invention. In particular, a gate in panel (GIP) mounted in a liquid crystal panel is shown. The shift register of the gate drive of the method is shown. However, the present invention is not limited to the gate driver of the gate-in panel method, and thus, the gate driver that is not mounted on the liquid crystal panel may be configured in various forms using the principles described below.

The gate driver sequentially supplies scan signals (gate driving signals) to the gate lines GL so that pixels (pixels) are selected one horizontal line on the liquid crystal panel. The data driver supplies an RGB image data signal to the data line DL every time the gate line GL is sequentially selected. Accordingly, the light transmittance of the liquid crystal layer is controlled by an electric field formed between the pixel electrode and the common electrode according to the image data signal supplied for each pixel, thereby displaying an image.

Meanwhile, as shown in FIG. 6, the gate driver in the GIP type liquid crystal display device includes N stages 210, a switching unit 220, and a clock supply unit 230 for receiving and driving four clock signals. It may include a shift register.

That is, the shift register sequentially drives all the odd-numbered gate lines in one frame of the second mode and a plurality of stages 210 for outputting the scan signal to each gate line, so that the scan signal is applied. In order to drive all the first gate lines sequentially so that a scan signal is applied, a switching unit 220 connected to an output terminal of each of the stages and a clock supply unit for applying a clock and a control signal necessary for the stage and the switching unit ( 230).

Herein, the switching unit 220 is driven by the control signal ENS transmitted from the timing controller in the second mode, and the scan signal output from the odd stage among the stages 210 is applied to the next odd stage. The scan signal output from the even-numbered stage of the stages is input as the start signal, and the scan signal output from the even-numbered stage of the next stage is input, and the scan signal output from the last odd-numbered stage is the most advanced of the even-numbered stages. It can be input as the start signal of the stage.

That is, in the first mode, the first stage Stage1 of the stage circuits constituting the shift register receives the first clock signal CLK1 and the start signal VstN and transmits the gate driving signal Vout1 to the first gate line. (Scan signal), and the Nth stage receives the gate driving signal Vout (N-1) of the N-1st stage as the start signal VstN, and outputs the Nth gate driving signal VoutN. Done.

On the other hand, when a specific pattern is detected by the pattern detector, the pattern detector generates the pattern detection signal PDS and transmits it to the control signal generator. Accordingly, the control signal generator switches to the second mode to enable the signal ENS. May be generated and transmitted to the gate driver.

As shown in FIG. 6, the enable signal ENS transmitted to the gate driver is applied to the clock supply unit 230 and the switching unit 220 so that an output signal output from the odd stage including the first stage is included. It can be applied as the start signal of the next odd stage, the output signal output from the last odd stage (n-th switching unit) is applied as the start signal of the second stage, the second stage through the second stage The second scan signal to be applied to the gate line may be output, and the second scan signal may be applied as the start signal of the next even-numbered stage, thereby sequentially driving the even-numbered stage.

That is, according to the present invention, after the odd-numbered stages are sequentially driven by the enable signal ENS to sequentially drive the scan signals to the odd-numbered gate lines, the even-numbered stages are sequentially driven. The scan signals may be sequentially driven to even-numbered gate lines.

Meanwhile, the enable signal ENS may be applied to another type of gate driver in addition to the gate driver configured as shown in FIG. 7 to perform the above function.

To this end, the clock supply unit 230, the stage 210 and the switching unit 220 may be configured in various circuit forms.

Hereinafter, when a specific pattern is detected with reference to FIGS. 7 to 9, the liquid crystal display according to the present invention can reduce power consumption by the specific pattern in the Z-inversion scheme by driving the gate line in the second mode. The method is described in detail.

7 is an exemplary view illustrating waveforms of control signals generated by a timing controller in the liquid crystal display according to the present invention. FIG. 8 is an exemplary view showing a state in which pixels are driven in a liquid crystal panel of the liquid crystal display according to the present invention, and black data is applied to even-numbered columns C2, C4, ... including the second column. And a specific pattern in which white data is applied to the odd-numbered columns C1, C3, ... including the first column. 9 is an exemplary view showing a waveform output from the data driver of the liquid crystal display according to the present invention.

First, the liquid crystal display according to the present invention sequentially drives each gate line in the first mode until a specific pattern is detected (S702).

Here, as a method of detecting a specific pattern, a method of comparing and analyzing a frame and a frame may be applied as described above, but a method of determining whether a specific pattern is output by analyzing only one frame may be applied.

For example, as shown in FIG. 7, a specific pattern (Normal (Mosaic) Pattern) until the N'th frame (N'th Frame), but is vulnerable to the Z-inversion scheme from the Nth frame (particularly, If the pattern detection unit of the timing controller is changed to Lines Vertical, data coming in one data line and the next data line (adjacent data line) of the frame data is always displayed. It counts the number of different data) and resets the count at the beginning of every frame.

That is, the pattern detection unit analyzes the image data of each pixel of one frame and counts the number of pixels having a value corresponding to a specific pattern. When the count value exceeds a preset value, the pattern detection unit converts the pattern into a specific pattern. You can judge.

Next, the pattern detecting unit detects the Nth frame at the point A shown in FIG. 7 and outputs all the Nth frames, and if the count number of other data in the adjacent data line is determined to be the number corresponding to the specific pattern, the pattern detection unit detects the pattern. The signal PDS is set to 1 and transmitted to the control signal generator.

In this case, when the control signal generator 420 sets the enable signal ENS to High according to the pattern detection signal PDS set to 1 and transmits the enable signal ENS to High, the gate driver is set to 1. After driving in the second mode (Interlace method) as described above according to the pattern detection signal, the scan signal is sequentially supplied to the odd-numbered gate lines (or even-numbered gate lines) among the gate lines, The scan signals are sequentially supplied to the gate lines (or odd gate lines) (S704).

This operation method is as shown in FIG. 8. That is, as shown in (a) of FIG. 8, first, a scan signal is transmitted to the first gate line G1 of the gate lines, and the data voltage is supplied to the pixels on the first horizontal line. After that, the scan signal is transmitted to the third gate line G3 during the next horizontal period, and the data voltage is supplied to the pixels on the third horizontal line.

In addition, the scan signal is supplied to all the odd gate lines by the method shown in (a), and the scan signal is transmitted to the even-numbered second gate line G2 as shown in (b) of FIG. 8. After the data voltage is supplied to the pixels on the second horizontal line, the scan signal is transmitted to the fourth gate line (not shown) during the next horizontal period, and the data voltage is supplied to the pixels on the fourth horizontal line. do.

Therefore, assuming that the LCD according to the present invention has a total of 768 gate lines, the gate lines are scanned in the order of G1 → G3 → G5 ... G767 → G2 → G4 → G6 ... → G768 for one frame. A signal can be applied.

The above process may be repeatedly performed every frame until the general pattern is detected again.

Accordingly, as shown in FIG. 9B, the third gate line D3 to which the positive electrode is applied is about 16 V during one frame period while the scan signal is first applied to the odd-numbered gate lines. The data voltage corresponding to the black voltage is applied, and while the scan signal is applied to the even-numbered gate lines, the data voltage (white) corresponding to about 8V is applied. Here, 16V and 8V are voltages used by the data driver to display black or white data, and these voltages may be changed to various values according to the characteristics of the data driver.

That is, the waveform diagram shown in (b) of FIG. 9 is an example of the third data line D3 to which a specific pattern as shown in FIG. 8 is applied. Referring to FIG. The pixels driven by the odd gate line are represented in black, and the pixels driven by the even-numbered gate line (EP: Even Pixel) are represented in white. Such a pattern includes the specific patterns described above. In particular, it can be seen that the vertical lines pattern (Lines Vertical). Accordingly, it can be seen that the odd-numbered columns (C1, C3, ...) are displayed in white, and the even-numbered columns (C2, C4, ...) are displayed in black.

In detail, when the third data line is taken as an example, while the specific pattern as shown in FIG. 8 is input, the data driving unit preferentially has the odd-numbered gate line as shown in FIG. The data voltage of about 16V is used to output the image data signal having a black value during the period in which the scan signal is applied to the fields G1, G3, ..., and the next even gate lines G2, G4. The data voltage of about 8V is used to output an image data signal having a white value while the scan signal is applied.

That is, according to the present invention, the data driver continuously transmits the image data signals having the voltage value of 16V to the pixels of the odd-numbered gate lines having the black value in the specific pattern, and then the even-numbered gate line having the white value. Since the image data signals having the voltage value of 8V are continuously transmitted to the pixels of the pixel, it is necessary to change the data voltage value every gate line as in the conventional liquid crystal display device shown in FIG. none. Therefore, according to the present invention, it can be seen that power consumption of the data driver due to the data transition can be reduced.

In other words, in the conventional LCD, when a specific pattern to which black and white data are alternately applied is input, data of the third data line D3 and the fourth data line D4 are input. As shown in (a) of FIG. 9, the data transition is continuously performed for one frame.

However, referring to the data driving sequence of the data driver in the liquid crystal display according to the present invention when a specific pattern is input, as shown in FIG. 9 (b), there is no data transition during 1/2 frame. It can be seen that black data enters the odd gate lines, and the same white data is applied to even-numbered gate lines after one transition during the remaining 1/2 frame.

That is, according to the present invention, since the number of data transitions can be reduced, it can be seen that power consumption due to the transition in the data driver is reduced.

In addition, it can be seen that the fourth data line D4 having the negative polarity is driven with a property opposite to that of the third data line D3 as described above.

Finally, the pattern detector detects the K'th frame at the point B shown in FIG. 7 and counts the number of other data in adjacent data lines, but fails to exceed the number corresponding to the specific pattern. The pattern is determined as a general pattern, the pattern detection signal PDS is reset to 0, and then transmitted to the control signal generator.

At this time, when the enable signal ENS is set low again according to the pattern detection signal PDS reset to 0 and transmitted to the gate driver, the gate driver generates a pattern detection signal set to zero. As described above, the first mode is driven again to sequentially supply scan signals to the gate lines (S706).

The present invention as described above is summarized as follows.

According to an embodiment of the present invention, when a specific pattern with high power consumption is detected in a state of driving in a Z-inversion scheme, an interface for collectively driving the odd-numbered gate lines and the even-numbered gate lines instead of the sequential driving method is used. By applying the (Interace) method, the data driver can reduce power consumption for data transition.

That is, a conventional liquid crystal display device driven by a Z-inversion method has a problem in that power consumption increases when a specific pattern occurs. As a main factor of the phenomenon, first, a data transition is applied to a data transition. Increase in load, second, increase in load of Vcom Feedback stage due to increase of data transition, and third, decrease in VDD booster efficiency of power stage due to increase in load of common voltage feedback stage (80%- > 77%), the present invention, in particular, reduces the power consumption by reducing the first and second causes.

On the other hand, the present invention is a technique for reducing the first and second causes, the present invention through the pattern recognition algorithm (Algorithm) in the pattern detection unit, after recognizing a specific pattern vulnerable to power consumption in the Z-inversion method (S702) During 1/2 Frame (Odd), scan signal is applied to odd gate lines G1, G3, G5, ..., G767, and the remaining 1/2 Frame (Even). In the meantime, an H-Interlace method for driving Even Gate Lines G2, G4, G6, ..., G768 is used.

Therefore, when a specific pattern is applied, the data transition is performed only once for one frame, and thus the power consumption of the data driver may be reduced.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal panel 100 200: gate driver
210: stage 220: switching unit
230: clock supply unit 300: data driver
400: timing controller 410: receiver
420: control signal generation unit 430: image data processing unit
440: pattern detection unit 440 450: transmission unit

Claims (13)

A liquid crystal panel having a plurality of pixels formed by the intersection of the gate lines and the data lines, and driven by a Z-inversion method;
A gate driver for applying a scan signal to the gate lines;
A data driver for applying an image data signal to the data lines;
When driving in the Z-inversion method, it is determined whether a specific pattern which is set to consume a large amount of power is input. When the specific pattern is not input, the scan signal is sequentially applied to the gate lines. The gate driver is driven in a first mode, and when the specific pattern is applied, all odd-numbered gate lines are sequentially driven in one frame to apply a scan signal, and then all even-numbered gate lines are sequentially applied. And a timing controller for driving the gate driver in a second mode to drive the gate signal by applying a scan signal. The method of claim 1,
In the specific pattern, black data is input to the m-th column line, white data is input to the m + 1 column line adjacent thereto, and the m-th column line and the m-th + 1 column line are repeatedly Black data is input to the pattern being expressed or the nth horizontal line, white data is input to the nth horizontal line adjacent thereto, and the nth horizontal line and the nth horizontal line are repeatedly expressed. Liquid crystal display device characterized in that the pattern. The method of claim 1,
The timing controller includes:
A receiver for receiving image data and a timing signal from a system;
An image data processor for rearranging and outputting image data received through the receiver;
A pattern detector configured to analyze the image data to detect whether the image is the specific pattern; And
And a control signal generator for generating a control signal for driving the gate driver in the first mode or the second mode according to the pattern detection signal applied from the pattern detector and transmitting the generated control signal to the gate driver. The method of claim 3, wherein
The pattern detection unit,
When the specific pattern is detected, the pattern detection signal is set to 1 and transmitted to the control signal generator so that the control signal generator generates a control signal for driving the gate driver in the second mode. If not detected, the pattern detection signal is reset to zero and transmitted to the control signal generator so that the control signal generator generates a control signal for driving the gate driver in the first mode. Display. The method of claim 1,
Wherein the gate driver comprises:
A plurality of stages for outputting a scan signal to each gate line; And
In order to apply the scan signal by sequentially driving all the odd-numbered gate lines in one frame of the second mode, and to output the scan signal by sequentially driving all the even-numbered gate lines, an output terminal of each stage And a shift register including a switching unit connected to the liquid crystal display. The method of claim 5, wherein
The switching unit includes:
Driven by a control signal transmitted from the timing controller in the second mode, the scan signal output from the odd stage among the stages is input as a start signal of the next odd stage, and the even of the stages is excellent. The scan signal output from the first stage is input as the start signal of the next even-numbered stage, and the scan signal output from the last odd-numbered stage is input as the start signal of the earliest stage among the even-numbered stages. A liquid crystal display device. The method of claim 1,
The data driver may include:
In the second mode, after all the odd-numbered gate lines are sequentially driven for one frame and a scan signal is applied, generating one data transition at a time when the even-numbered gate lines start to be sequentially driven. A liquid crystal display device. Determining whether a specific pattern which is set to have high power consumption is input when driven in a Z-inversion method;
Driving the gate driver in a first mode in which scan signals are sequentially applied to gate lines when the specific pattern is not input; And
When the specific pattern is applied, the odd-numbered gate lines are sequentially driven in one frame to apply the scan signal, and then the even-numbered gate lines are sequentially driven in the second mode to apply the scan signal. And driving the gate driver. The method of claim 8,
The specific pattern is,
Black data is input to the m-th column line, and white data is input to the m + 1 column line adjacent thereto, and the m-th column line and the m-th + 1 column line are repeatedly represented. Alternatively, black data is input to the n-th horizontal line, white data is input to the n-th horizontal line adjacent thereto, and the n-th horizontal line and the n-th horizontal line are repeatedly represented. A liquid crystal display device driving method. The method of claim 8,
Determining whether or not the specific pattern is input,
After storing the image data received from the system every frame, the gray level value of each pixel of the previous frame and the next frame is compared with each other, and at least one column line is represented by black data, and the adjacent column line is white. By a method of analyzing whether or not it is represented as data, or by a method of analyzing whether at least one or more horizontal lines are represented by black data and adjacent horizontal lines are represented by white data. A liquid crystal display device driving method, characterized in that. The method of claim 8,
Determining whether or not the specific pattern is input,
Analyzing the image data of each pixel of one frame with each other to count the number of pixels having a value corresponding to a specific pattern, if the count value exceeds a predetermined value, the liquid crystal display device characterized in that it is determined as a specific pattern Driving method. The method of claim 8,
The driving of the gate driver in the second mode may include:
In the second mode, the gate driver inputs a scan signal output to an odd gate line among the gate lines as a start signal of a stage for outputting a scan signal to a next odd gate line. The scan signal output to the even-numbered gate line among the gate lines is input as a start signal of a stage for outputting the scan signal to the next even-numbered gate line, and the scan signal output to the last odd-numbered gate line. And inputting it as a start signal of a stage for outputting a scan signal to the most advanced gate line among the even-numbered gate lines. The method of claim 8,
The data driver for supplying an image data signal to data lines intersecting the gate lines, in the second mode, all odd-numbered gate lines of the gate lines are sequentially driven during one frame to scan signals. And applying one data stream to generate one data transition when the even-numbered gate lines start to be sequentially driven.

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