KR20080047882A - Liquid crystal display and driving apparatus thereof - Google Patents

Abstract

A liquid crystal display and its driving method are provided to improve picture quality by minimizing flickering at a particular data pattern by charging a data voltage of a vertical 2-dot inversion type in liquid crystal cells by using dispositions of TFTs(Thin Film Transistors). A plurality of gate lines(G1A-GnB) cross a plurality of data lines(D1-Dm/2). A plurality of liquid crystal cells are formed at respective pixel areas defined by the data lines and the gate lines. TFTs are connected in zigzags with the data lines. A data driving circuit supplies a data voltage having polarity inserted by units of about 1/2 horizontal periods to the data lines. A gate driving circuit(42) sequentially supplies scan pulses to scan lines. Liquid crystal cells which are adjacent horizontally are charged with data voltages each having the mutually opposite polarity.

Description

Liquid Crystal Display and Driving Method {Liquid Crystal Display and Driving Apparatus}

1 is a circuit diagram showing a liquid crystal display device employing a conventional data line sharing technology.

FIG. 2 is a diagram for describing vertical line noise appearing in the liquid crystal display shown in FIG. 1. FIG.

3 is a waveform diagram showing a data voltage of the liquid crystal display shown in FIG.

4 is a view showing a liquid crystal display device according to an embodiment of the present invention.

5 is a circuit diagram showing a pixel array according to the first embodiment of the present invention.

FIG. 6 is a waveform diagram illustrating a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 5. FIG.

FIG. 7 is a waveform diagram illustrating another example of a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 5. FIG.

8 is a circuit diagram showing a pixel array according to a second embodiment of the present invention.

FIG. 9 is a waveform diagram illustrating a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 8. FIG.

FIG. 10 is a waveform diagram illustrating another example of a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 8. FIG.

11 is a circuit diagram showing a pixel array according to a third embodiment of the present invention.

FIG. 12 is a waveform diagram illustrating a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 11.

FIG. 13 is a waveform diagram illustrating another example of a data voltage and a scan pulse supplied to the pixel arrays shown in FIG. 11. FIG.

<Description of Symbols for Main Parts of Drawings>

41: data driving circuit 42: gate driving circuit

43: liquid crystal display panel 44: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for reducing the number of data lines and data drive integrated circuits and minimizing image degradation.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tube or cathode ray tube, which is currently mainstream, has a problem of weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electroluminescence (EL). Most of these are commercially available and commercially available.

Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

This liquid crystal display has a large number of data lines D1 to Dm formed in the liquid crystal display panel 13 and a drive integrated circuit of the data driving circuit 11 for supplying a data voltage to the data lines D1 to Dm. Due to the cost burden is a big problem. This cost burden is increased as the resolution is increased or the liquid crystal display panel 13 is made larger.

In order to solve the problems caused by the increase of data lines and data drive integrated circuits, data line sharing (Data Line Sharing) can reduce the number of data lines and drive integrated circuits by driving two columns of liquid crystal cells with one data line. DLS) technology has been developed. The liquid crystal display device to which the data line sharing technology is applied is shown in FIG. 3. The liquid crystal display device connects TFTs for driving different liquid crystal cells to the left and right of the data lines D1, D2, and D3 in the pixel array, and sequentially scans two gate lines G1 in synchronization with data. The number of data lines is reduced by time-division driving the two liquid crystal cells Clc1 and Clc2 disposed on the left and right sides by applying to G2).

In the liquid crystal display, as shown in FIGS. 2 and 3, the polarity is inverted in units of two liquid crystal cells neighboring in the horizontal direction and the polarity is inverted in units of one liquid crystal cell neighboring in the vertical direction. Charge the voltage. In the horizontal two-dot inversion scheme, the liquid crystal cell Clc1 to which the positive data voltage (+) rising from the negative data voltage (−) is applied, and another positive data voltage (+) following the positive data voltage (+) The amount of data to be charged in the liquid crystal cell Clc2 supplied with +) is different. Further, the liquid crystal cell Clc3 to which the negative data voltage falling from the positive data voltage (+) is applied, and the liquid crystal cell Clc4 to which another negative data voltage (-) is applied following the negative data voltage (-). ), The amount of data to be charged is different. The polarities of these data voltages are inverted in units of frame periods. For this reason, in the liquid crystal display device employing the data line sharing technology, the two liquid crystal cells horizontally adjacent to each other even at the same data voltage have a luminance difference due to the difference in the amount of data charge, resulting in vertical stripes and positive polarity as shown in FIG. 3. Since the pixels P1 (RGB) and the pixels having a negative polarity (P2 (RGB)) have a spatial periodicity and their polarities are reversed in units of frame periods, they have a periodicity in time so that flicker is severe. There is a problem that appears.

Accordingly, an object of the present invention is to provide a liquid crystal display and a driving method thereof which reduce the number of data lines and data drive integrated circuits and minimize image degradation.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention comprises a plurality of data lines; A plurality of gate lines orthogonal to the data lines; A plurality of liquid crystal cells formed for each pixel area defined by the data lines and the gate lines; TFTs connected in zigzag form to the data lines; A data driving circuit configured to supply a data voltage whose polarity is inverted to the data lines in units of approximately 1/2 horizontal periods; And a gate driving circuit sequentially supplying scan pulses to the scan lines; The liquid crystal cells adjacent to left and right charge data voltages having opposite polarities.

The liquid crystal cells may include a plurality of first liquid crystal cells arranged in a fourth i (i is a positive integer) + 1 subpixel column in a fourth k (k is a positive integer) + 1 horizontal line and a fourth k + 2 horizontal line; A plurality of second liquid crystal cells arranged in a fourth i + 2 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of third liquid crystal cells arranged in the fourth i + 1 subpixel column in a fourth k + 3 horizontal line and a fourth k + 4 horizontal line; And a plurality of fourth liquid crystal cells arranged in the fourth i + 2 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line.

The TFTs are connected between the left side of the odd data lines and the first liquid crystal cells in the 4k + 1 horizontal line and the 4k + 2 horizontal line to respond to the scan pulses from the odd gate lines. A plurality of first TFTs supplying the data voltages from the lines to the first liquid crystal cells; The odd data in response to the scan pulses from the even gate lines connected between the second liquid crystal cells and the right side of each of the odd data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of second TFTs supplying the data voltages from the lines to the second liquid crystal cells; The odd data in response to scan pulses from the even gate lines connected between the third liquid crystal cells and the left side of each of the odd data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line. A plurality of third TFTs supplying the data voltages from the lines to the third liquid crystal cells; And the radix in response to scan pulses from the radix gate lines connected between the fourth liquid crystal cells and the right side of each of the radix data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line. And a plurality of fourth TFTs for supplying the data voltages from the data lines to the fourth liquid crystal cells.

The polarities of the data voltages simultaneously supplied to the data lines are the same.

The pulse width of the scan pulse is approximately 1/2 horizontal period.

The scan pulse is a first scan pulse generated in synchronization with the data voltage of a first polarity; And a second scan pulse generated in synchronization with another data voltage of the first polarity generated after the data voltage of the second polarity; The first scan pulse supplied to the n-th gate line overlaps the second scan pulse supplied to the n-th gate line.

The liquid crystal cells may include: a plurality of fifth liquid crystal cells arranged in the fourth i + 3 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of sixth liquid crystal cells arranged in a fourth i + 4 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of seventh liquid crystal cells arranged in the fourth i + 3 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; And a plurality of eighth liquid crystal cells arranged in the fourth i + 4 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line.

The TFTs are connected between the left side of the even data lines and the fifth liquid crystal cells in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line to respond to the scan pulses from the even gate lines. A plurality of fifth TFTs supplying the data voltages from the lines to the fifth liquid crystal cells; The even data in response to scan pulses from the odd gate lines connected between the fourth liquid crystal cells and the right side of each of the even data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line; A plurality of sixth TFTs supplying the data voltages from the lines to the sixth liquid crystal cells; The even data in response to scan pulses from the odd gate lines connected between the fourth liquid crystal cell and the left side of each of the even data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line, respectively. A plurality of seventh TFTs supplying the data voltages from the lines to the seventh liquid crystal cells; And the rainwater in response to scan pulses from the rainy gate lines connected between the right and the eighth liquid crystal cells of each of the even data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line. And a plurality of eighth TFTs for supplying the data voltages from the data lines to the eighth liquid crystal cells.

Polarities of the data voltages simultaneously supplied to the odd data lines and the even data lines are opposite to each other.

The data voltages charged in the liquid crystal cells arranged in the vertical direction are inverted in polarity in units of two liquid crystal cells.

The liquid crystal cells are arranged in a plurality of first pixels arranged in the 8i (i is a positive integer) +1 and the 8i +3 subpixel columns in the 4k (k is a positive integer) +1 horizontal line and the 4k + 2 horizontal line. Liquid crystal cells; A plurality of second liquid crystal cells arranged in eighth + 2 and eighti + 4 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of third liquid crystal cells arranged in the eighth + 1 and eighti + 3 subpixel columns in a fourth k + 3 horizontal line and a fourth k + 4 horizontal line; A plurality of fourth liquid crystal cells arranged in the eighth + 2 and eighti + 4 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; A plurality of fifth liquid crystal cells arranged in eighth + 5 and eighti + 7 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of sixth liquid crystal cells arranged in eighth + 6 and eighti + 8 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of seventh liquid crystal cells arranged in the eighth + 5 and eighti + 7 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; And a plurality of eighth liquid crystal cells arranged in the eighth + 6 and eighti + 8 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line.

The TFTs are connected between the first liquid crystal cells and the left side of one of the fourth i + 1 and fourth i + 2 data lines in the fourth and fourth k + 1 horizontal lines and the odd gate. A plurality of first TFTs for supplying the data voltage from one of the fourth and fourth data lines to the first liquid crystal cells in response to a scan pulse from the lines; The even gate lines are connected between the right side of any one of the 4i + 1 and 4i + 2 data lines and the second liquid crystal cells in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of second TFTs for supplying the data voltage from any one of the fourth and fourth data lines to the second liquid crystal cells in response to a scan pulse from the second liquid crystal cell; The even gate lines connected between the third liquid crystal cells and the left side of any one of the fourth and second data lines in the fourth and fourth horizontal lines 4k + 3 and 4k + 4 A plurality of third TFTs for supplying the data voltage from any one of the fourth and fourth data lines to the third liquid crystal cells in response to a scan pulse from the first and second data lines; The odd gate lines are connected between the right side of any one of the fourth i + 1 and fourth i + 2 data lines and the fourth liquid crystal cells in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. A plurality of fourth TFTs for supplying the data voltages from any one of the fourth and fourth data lines to the fourth liquid crystal cells in response to a scan pulse from the first and second data lines; The fourth k + 1 horizontal line and the fourth k + 2 horizontal line are connected between the left side of any one of the fourth i + 3 and fourth i + 4 data lines and the fifth liquid crystal cells to separate from the even gate lines; A plurality of fifth TFTs supplying the data voltages from any one of the fourth and fourth data lines to the fifth liquid crystal cells in response to a scan pulse of the first and second data lines; The odd gate lines are connected between the sixth liquid crystal cell and the right side of any one of the 4i + 3 and 4i + 4 data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of sixth TFTs supplying the data voltages from any one of the fourth and fourth data lines to the sixth liquid crystal cells in response to a scan pulse from the plurality of fourth lines; The fourth k + 3 horizontal line and the fourth k + 4 horizontal line are connected between the left side of any one of the fourth i + 3 and fourth i + 4 data lines and the seventh liquid crystal cells and are separated from the odd gate lines; A plurality of seventh TFTs supplying the data voltages from any one of the fourth and fourth data lines to the seventh liquid crystal cells in response to a scan pulse of the fourth liquid crystal cells; And the even gate line connected to the right side of the one of the fourth i + 3 and fourth i + 4 data lines and the eighth liquid crystal cells in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. And a plurality of eighth TFTs for supplying the data voltage from one of the fourth and fourth data lines to the eighth liquid crystal cells in response to the scan pulse from the plurality of data lines.

The polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i4 and i are identical, and the polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i and i are identical.

The polarities of the data voltages simultaneously supplied to the fourth and fourth i + 1 data lines are opposite to the polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i and i.

According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device includes a plurality of data lines, a plurality of gate lines orthogonal to the data lines, and pixel regions defined by the data lines and the gate lines. A driving method of a liquid crystal display device having a plurality of liquid crystal cells each formed, the method comprising: connecting TFTs to the data lines in a zigzag form; Supplying the data lines with a data voltage whose polarity is inverted in approximately 1/2 horizontal periods; And sequentially supplying scan pulses to the scan lines, wherein the liquid crystal cells adjacent to the left and right charge data voltages having opposite polarities.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 10.

4 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 43 in which m × n liquid crystal cells Clc are arranged in a matrix type, and 1/2 horizontal period (1/2 H). For supplying scan pulses to the data driving circuit 41 and the gate lines G1A to GnB, which supply the analog data voltage having polarity reversed to the m / 2 data lines D1 to Dm / 2. A timing controller 44 for controlling the gate driving circuit 42, the data driving circuit 41, and the gate driving circuit 42 is provided.

In the liquid crystal display panel 43, liquid crystal molecules are injected between two glass substrates. The m data lines D1 to Dm / 2 and the n gate lines G1A to GnB formed on the lower glass substrate of the liquid crystal display panel 43 are orthogonal to each other. TFTs are connected to intersections of the data lines D1 to Dm / 2 and the gate lines G1A to GnB. Source electrodes of the TFTs are connected in zigzag form to the data lines D1 to Dm / 2. The two TFTs for switching the data voltages supplied to each of the horizontally neighboring liquid crystal cells are turned on and off by scan pulses from different gate lines, respectively. These TFTs are connected to the same data line to supply data voltages from the same data line to different liquid crystal cells. For this purpose, the gate electrode of the TFT is connected to the gate lines G1A to GnB, and the drain electrode is connected to the data lines D1 to Dm / 2. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The common voltage is supplied to the common electrode facing the pixel electrode.

Storage capacitors are formed in each of the liquid crystal cells of the liquid crystal display panel 43. The storage capacitor is formed by the gate lines G1A to GnB and the pixel electrode overlapping each other with a dielectric interposed therebetween. This storage capacitor keeps the voltage of the liquid crystal cell constant.

A black matrix, a color filter, and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal display panel 43. On the other hand, the common electrode is formed on the upper glass substrate in the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode In the horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 43, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner side of the liquid crystal display panel 43 in contact with the liquid crystal.

The data driving circuit 41 is composed of a plurality of data drive integrated circuits each including a shift register, a latch, a digital-to-analog converter and an output buffer. The data driving circuit 41 latches digital video data under the control of the timing controller 44 and converts the digital video data into a positive / negative analog gamma compensation voltage to generate a positive / negative data voltage. The data voltages are supplied to the data lines D1 to Dm / 2 while inverting polarities in units of approximately 1/2 horizontal periods.

The gate driving circuit 42 includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1A to GnB, respectively. It consists of a plurality of gate drive integrated circuits. The gate driving circuit 42 sequentially outputs scan pulses in units of approximately 1/2 horizontal period so as to be synchronized with the data voltages supplied to the data lines D1 to Dm / 2. The scan pulses may be non-overlapping and may overlap with other scan pulses so that the data voltages are sufficiently charged in the liquid crystal cells Clc1 and Clc2.

The timing controller 44 receives a vertical / horizontal synchronization signal and a clock signal and receives a gate control signal GDC for controlling the gate driving circuit 42 and a data control signal DDC for controlling the data driving circuit 41. Occurs. The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock signal (GSC) for driving a shift register, a gate output enable signal (GOE), and the like. . The gate start pulse GSP, the gate shift clock signal GSC, and the like are generated with a pulse width of approximately 1/2 horizontal period such that the pulse width of the scan pulse is approximately 1/2 horizontal period. The data control signal (DDC) includes a source start pulse (GSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL). do. Here, the source output signal SOE, the polarity signal POL, and the like are generated at approximately 1/2 horizontal periods such that the positive / negative data voltage is output for approximately 1/2 horizontal period.

In addition to timing control of the driving circuits 41 and 42, the timing controller 44 serves to supply the data driving circuit 41 by rearranging and rearranging the digital video data RGB.

Since the liquid crystal display of the present invention supplies the data voltages to each of the adjacent liquid crystal cells left and right through one data line, the number of data lines D1 to Dm / 2 can be reduced to 1/2. Of course, as shown in FIG. 5, polarity is inverted in units of two vertically neighboring liquid crystal cells, and data voltages of opposite polarities are supplied to neighboring liquid crystal cells to the left and right, so that image quality deterioration such as a vertical line or flicker may be reduced in a display image. Factors can be minimized.

5 shows a first embodiment of the pixel array formed in the liquid crystal display panel 43. FIG.

Referring to FIG. 5, the liquid crystal cells of the pixel array according to the first exemplary embodiment of the present invention have polarities inverted in units of two liquid crystal cells neighboring up and down in the vertical direction and polarities in units of one liquid crystal cell in the horizontal direction. The inverted vertical two-dot inversion type data voltage is charged. Arrows indicate the charging order of data voltages in adjacent 2x2 liquid crystal cells vertically and horizontally.

The plurality of first liquid crystal cells are arranged in the odd subpixel columns CL1 and CL3 in the 4k (k is a positive integer) +1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. A plurality of second liquid crystal cells Clc2 arranged in even-numbered subpixel columns CL2 and CL4 in the liquid crystal cell Clc1, the fourth k + 1 horizontal lines HL1 and HL5, and the fourth k + 2 horizontal lines HL2 and HL6. ), A plurality of third liquid crystal cells Clc3 disposed in the odd subpixel columns CL1 and CL3 in the fourth k + 3 horizontal lines HL3 and HL7 and the fourth k + 4 horizontal lines HL4 and HL8. A plurality of fourth liquid crystal cells Clc4 are disposed in the even subpixel columns CL2 and CL4 in the 4k + 3 horizontal lines HL3 and HL7 and the fourth k + 4 horizontal lines HL4 and HL8.

The TFTs are disposed between the left side of each of the data lines D1 to Dm / 2 and the first liquid crystal cells Clc1 in the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. Right and first sides of the data lines D1 to Dm / 2 in the plurality of connected first TFTs TFT1, the 4k + 1 horizontal lines HL1 and HL5, and the 4k + 2 horizontal lines HL2 and HL6, respectively. Data lines D1 through to a plurality of second TFTs TFT2, 4k + 3 horizontal lines HL3 and HL7, and 4k + 4 horizontal lines HL4 and HL8 connected between the second liquid crystal cells Clc2. Dm / 2) a plurality of third TFTs TFT3 connected between the left and third liquid crystal cells Clc3, respectively, and the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 And a plurality of fourth TFTs TFT4 connected between the right side of each of the data lines D1 to Dm / 2 and the fourth liquid crystal cells Clc4 in HL8.

The first TFTs TFT1 are connected to scan pulses from the odd gate lines G1A, G2A, G5A, and G6A at the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. In response, data voltages from the data lines D1 to Dm / 2 are supplied to the first liquid crystal cells Clc1. The second TFTs TFT2 respond to scan pulses from even gate lines G1B, G2B, G5B, and G6B at 4k + 1 horizontal lines HL1 and HL5 and 4k + 2 horizontal lines HL2 and HL6. The data voltages from the data lines D1 to Dm / 2 are supplied to the second liquid crystal cells Clc2. The third TFTs TFT3 are connected to scan pulses from the even gate lines G3B, G4B, G7B, and G8B on the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, data voltages from the data lines D1 to Dm / 2 are supplied to the third liquid crystal cells Clc3. The fourth TFTs TFT4 are connected to scan pulses from the odd gate lines G3A, G4A, G7A, and G8A at the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, data voltages from the data lines D1 to Dm / 2 are supplied to the fourth liquid crystal cells Clc4.

The data voltages supplied to the data lines D1 to Dm / 2 are inverted in units of 1/2 horizontal periods (1/2 H) as shown in FIGS. 6 and 7, and also in units of frame periods. In addition, the data lines D1 to Dm / 2 are simultaneously supplied with a data voltage having the same polarity. The scan pulse SP may be sequentially supplied to each of the gate lines G1A to GnB in a non-overlapping manner in synchronization with the data voltage as shown in FIG. 6.

Two scan pulses SP1 and SP1 may be generated at approximately 1/2 horizontal period intervals so that the scan pulses may be synchronized with data voltages having the same polarity, respectively. Among these scan pulses, the first scan pulse SP1 overlaps the previous scan pulse SP2. The first scan pulse SP1 supplied to the n-th gate line overlaps the second scan pulse SP2 supplied to the n-th gate line. The scan pulses SP1 and SP2 as shown in FIG. 7 are first charged with the same data voltage of the same polarity to the liquid crystal cells Clc1 to Clc8, and then the data voltages to be displayed are charged to the liquid crystal cells Clc1 to Clc4. The data voltage is sufficiently charged. That is, due to the scan pulses SP1 and SP2 as shown in FIG. 7, the liquid crystal cells Clc1 to Clc4 may sufficiently and quickly charge the data voltage with a precharging effect.

8 shows a second embodiment of the pixel array formed in the liquid crystal display panel 43. FIG.

Referring to FIG. 8, the liquid crystal cells of the pixel array according to the second exemplary embodiment of the present invention have polarities reversed in units of two liquid crystal cells neighboring up and down in the vertical direction and polarized in units of one liquid crystal cell in the horizontal direction. Charges the data voltage in the form of inverted vertical two dot inversion. Arrows indicate the charging order of data voltages in adjacent 2x2 liquid crystal cells vertically and horizontally.

The plurality of liquid crystal cells are arranged in the 4i (i is a positive integer) + 1 subpixel columns CL1 and CL5 in the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. The plurality of first liquid crystal cells Clc1, the fourth k + 1 horizontal lines HL1 and HL5 and the fourth k + 2 horizontal lines HL2 and HL6 are arranged in the fourth i + 2 subpixel columns CL2 and CL6. A plurality of agents disposed in the fourth i + 1 subpixel columns CL1 and CL3 in the second liquid crystal cell Clc2, the fourth k + 3 horizontal lines HL3 and HL7, and the fourth k + 4 horizontal lines HL4 and HL8. A plurality of fourths arranged in the fourth i + 2 subpixel columns CL2 and CL6 in the liquid crystal cell Clc3, the fourth k + 3 horizontal lines HL3 and HL7, and the fourth k + 4 horizontal lines HL4 and HL8. A plurality of fifth liquid crystals arranged in the fourth i + 3 subpixel columns CL3 and CL7 in the liquid crystal cell Clc4, the fourth k + 1 horizontal lines HL1 and HL5, and the fourth k + 2 horizontal lines HL2 and HL6. A plurality of sixth liquid crystals arranged in the fourth i + 4 subpixel columns CL4 and CL8 in the cell Clc5, the fourth k + 1 horizontal lines HL1 and HL5, and the fourth k + 2 horizontal lines HL2 and HL6. Cell Clc6, 4k + 3 horizontal lines HL3, HL7 and 4k + 4 horizontal lines HL4, HL8 ) A plurality of seventh liquid crystal cells Clc7 disposed in the fourth i + 3 subpixel columns CL3 and CL7, and the fourth k + 3 horizontal lines HL3 and HL7 and the fourth k + 4 horizontal lines HL4 and HL8. ) Includes a plurality of eighth liquid crystal cells Clc8 arranged in the fourth i + 4 subpixel columns CL4 and CL8.

The TFTs are connected between the left side of each of the odd data lines D1 and D3 and the first liquid crystal cells Clc1 in the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. Right and second liquid crystals of the odd data lines D1 and D3 in the plurality of first TFTs TFT1, the 4k + 1 horizontal lines HL1 and HL5, and the 4k + 2 horizontal lines HL2 and HL6, respectively. Radix data lines D1 and D3 in the plurality of second TFTs TFT2, the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8 connected between the cells Clc2. In the plurality of third TFTs TFT3, 4k + 3 horizontal lines HL3 and HL7 and 4k + 4 horizontal lines HL4 and HL8 connected between the left and third liquid crystal cells Clc3, respectively. A plurality of fourth TFTs TFT4, fourth k + 1 horizontal lines HL1 and HL5, and fourth k + 2 connected between the right side of each of the odd data lines D1 and D3 and the fourth liquid crystal cells Clc4. A plurality of fifth TFTs TFT5 and 4k + 1 horizontally connected between the left side of each of the even data lines D2 and D4 and the fifth liquid crystal cells Clc5 in the horizontal lines HL2 and HL6. A plurality of sixth TFTs connected between the right side of each of the even data lines D2 and D4 and the sixth liquid crystal cells Clc6 in the phosphorus HL1 and HL5 and the fourth k + 2 horizontal lines HL2 and HL6. TFT6) between the left and seventh liquid crystal cells Clc7 of each of the even data lines D2 and D4 in the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. On the right side of each of the plurality of seventh TFTs TFT7 and the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8 connected to the right data lines D2 and D4, respectively. A plurality of eighth TFTs TFT8 connected between the eighth liquid crystal cells Clc8 are included.

The first TFTs TFT1 are connected to scan pulses from the odd gate lines G1A, G2A, G5A, and G6A at the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. In response, data voltages from the odd data lines D1 and D3 are supplied to the first liquid crystal cells Clc1. The second TFTs TFT2 respond to scan pulses from even gate lines G1B, G2B, G5B, and G6B at 4k + 1 horizontal lines HL1 and HL5 and 4k + 2 horizontal lines HL2 and HL6. The data voltages from the odd data lines D1 and D3 are supplied to the second liquid crystal cells Clc2. The third TFTs TFT3 are connected to scan pulses from the even gate lines G3B, G4B, G7B, and G8B on the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, data voltages from the odd data lines D1 and D3 are supplied to the third liquid crystal cells Clc3. The fourth TFTs TFT4 are connected to scan pulses from the odd gate lines G3A, G4A, G7A, and G8A at the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, data voltages from the odd data lines D1 and D3 are supplied to the fourth liquid crystal cells Clc4. The fifth TFTs TFT5 are connected to scan pulses from the even gate lines G1B, G2B, G5B, and G6B at the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. In response, data voltages from even data lines D2 and D4 are supplied to fifth liquid crystal cells Clc5. The sixth TFTs TFT6 respond to scan pulses from the odd gate lines G1A, G2A, G5A, and G6A at the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6. The data voltages from even data lines D2 and D4 are supplied to sixth liquid crystal cells Clc6. The seventh TFTs TFT7 are connected to scan pulses from the odd gate lines G3A, G4A, G7A, and G8A at the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, data voltages from the even data lines D2 and D4 are supplied to the seventh liquid crystal cells Clc7. The eighth TFTs TFT8 are connected to scan pulses from the even gate lines G3B, G4B, G7B, and G8B on the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8. In response, the data voltages from the even data lines D2 and D4 are supplied to the eighth liquid crystal cells Clc8.

The voltages supplied to the data lines D1 to Dm / 2 are inverted in units of 1/2 horizontal periods (1/2 H) as shown in FIGS. 8 and 9, and are also inverted in units of frame periods. In this embodiment, the polarities of the data voltages supplied simultaneously to the odd data lines D1 and D3 and the even data lines D2 and D4 are opposite. The scan pulse SP may be sequentially supplied to each of the gate lines G1A to GnB in a non-overlapping manner in synchronization with the data voltage as shown in FIG. 9.

In addition, two scan pulses SP1 and SP1 may be generated at approximately 1/2 horizontal period intervals so that the scan pulses may be synchronized with data voltages having the same polarity, respectively. Among these scan pulses, the first scan pulse SP1 overlaps the previous scan pulse SP2. The scan pulses SP1 and SP2 as shown in FIG. 10 are first charged with the same data voltage of the same polarity to the liquid crystal cells Clc1 to Clc8 and then the data voltages to be displayed are charged to the liquid crystal cells Clc1 to Clc4. The data voltage is sufficiently charged. That is, due to the scan pulses SP1 and SP2 as shown in FIG. 10, the liquid crystal cells Clc1 to Clc4 may sufficiently and quickly charge the data voltage with the precharging effect.

11 shows a third embodiment of the pixel array formed in the liquid crystal display panel 43. FIG.

The liquid crystal cells of this embodiment are vertical two dot inversions in which polarities are inverted in units of two liquid crystal cells neighboring up and down in the vertical direction and polarities are inverted in units of one liquid crystal cell in the horizontal direction as in the above-described embodiments. Charge type data voltage. Arrows indicate the charging order of data voltages in adjacent 2x2 liquid crystal cells vertically and horizontally.

Liquid crystal cells disposed on the 4k + 1th horizontal lines HL1 and HL5 and the 4k + 2th horizontal lines HL2 and HL6 and disposed in the 8i + 1 to 8i + 4 subpixel columns CL1 to CL4. Clc1 and Clc2 have substantially the same structure as the liquid crystal cells disposed in the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6 in the first embodiment. Liquid crystal cells disposed on the fourth k + 3 horizontal lines HL3 and HL7 and the fourth k + 4 horizontal lines HL4 and HL8 and disposed in the 8i + 1 to 8i + 4 subpixel columns CL1 to CL4. Clc3 and Clc4 have substantially the same structure as the liquid crystal cells disposed in the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8 in the first embodiment. Liquid crystal cells disposed on the 4k + 1th horizontal lines HL1 and HL5 and the 4k + 2th horizontal lines HL2 and HL6 and disposed in the 8i + 5 to 8i + 8 subpixel columns CL5 to CL8. Clc5 and Clc6 have substantially the same structure as the liquid crystal cells disposed in the 4k + 3 horizontal lines HL3 and HL7 and the 4k + 4 horizontal lines HL4 and HL8 in the first embodiment. Liquid crystal cells disposed on the 4k + 3th horizontal lines HL3 and HL7 and the 4k + 4th horizontal lines HL4 and HL8 and disposed in the 8i + 5 to 8i + 8 subpixel columns CL5 to CL8. Clc7 and Clc8 have substantially the same structure as the liquid crystal cells arranged in the 4k + 1 horizontal lines HL1 and HL5 and the 4k + 2 horizontal lines HL2 and HL6 in the first embodiment.

The polarities of the data voltages are inverted in units of 1/2 horizontal periods (1/2 H) as shown in FIGS. 12 and 13 so that the liquid crystal cells can charge the data voltages in a vertical 2-dot inversion form. The scan pulse SP may be sequentially supplied to each of the gate lines G1A to GnB in a non-overlapping manner in synchronization with the data voltage as shown in FIG. 12.

In addition, two scan pulses SP1 and SP1 may be generated at approximately 1/2 horizontal period intervals so that the scan pulses may be synchronized with data voltages having the same polarity, respectively. Among these scan pulses, the first scan pulse SP1 overlaps the previous scan pulse SP2. Scan pulses SP1 and SP2 as shown in FIG. 13 are first charged with the same data voltage of the same polarity to the liquid crystal cells Clc1 to Clc8, and then the data voltages to be displayed are charged to the liquid crystal cells Clc1 to Clc4. The data voltage is sufficiently charged. That is, due to the scan pulses SP1 and SP2 as shown in FIG. 13, the liquid crystal cells Clc1 to Clc4 may sufficiently and quickly charge the data voltage with a precharging effect.

As described above, the liquid crystal display according to the present invention is time-divisionally supplied to the liquid crystal cells adjacent to the left and right through one data line, so that the liquid crystal display device has data lines of about 1/2 of the horizontal resolution of the liquid crystal display panel. Since the liquid crystal display panel can be driven, the number of data lines and data drive integrated circuits can be reduced, and a vertical two-dot inversion type data voltage is charged in the liquid crystal cells by using TFT arrangement. Image quality can be improved by minimizing flicker on certain data patterns such as noise and mosaic patterns.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (19)

Multiple data lines; A plurality of gate lines orthogonal to the data lines; A plurality of liquid crystal cells formed for each pixel area defined by the data lines and the gate lines; TFTs connected in zigzag form to the data lines; A data driving circuit configured to supply a data voltage whose polarity is inverted to the data lines in units of approximately 1/2 horizontal periods; And A gate driving circuit sequentially supplying scan pulses to the scan lines; The liquid crystal cells adjacent to the left and right are charged with data voltages having opposite polarities. The method of claim 1, The liquid crystal cells, A plurality of first liquid crystal cells disposed in a fourth i (i is a positive integer) + 1 subpixel column in a fourth k (k is a positive integer) + 1 horizontal line and a fourth k + 2 horizontal line; A plurality of second liquid crystal cells arranged in a fourth i + 2 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of third liquid crystal cells arranged in the fourth i + 1 subpixel column in a fourth k + 3 horizontal line and a fourth k + 4 horizontal line; And And a plurality of fourth liquid crystal cells arranged in the fourth i + 2 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. The method of claim 2, The TFTs, Connected between the left side of the odd data lines and the first liquid crystal cells in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line and the first data line from the odd data lines in response to a scan pulse from the odd gate lines. A plurality of first TFTs for supplying the data voltage of the first liquid crystal cells; The odd data in response to the scan pulses from the even gate lines connected between the second liquid crystal cells and the right side of each of the odd data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of second TFTs supplying the data voltages from the lines to the second liquid crystal cells; The odd data in response to scan pulses from the even gate lines connected between the third liquid crystal cells and the left side of each of the odd data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line. A plurality of third TFTs supplying the data voltages from the lines to the third liquid crystal cells; And The radix data in response to scan pulses from the radix gate lines connected between the fourth liquid crystal cells and the right side of each of the radix data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line. And a plurality of fourth TFTs for supplying the data voltages from the lines to the fourth liquid crystal cells. The method of claim 3, wherein And the polarities of the data voltages simultaneously supplied to the data lines are the same. The method of claim 1, And the pulse width of said scan pulse is approximately one-half horizontal period. The method of claim 1, The scan pulse, A first scan pulse generated in synchronization with the data voltage of a first polarity; And A second scan pulse generated in synchronization with another data voltage of the first polarity generated after a data voltage of a second polarity; And the first scan pulse supplied to the n-th gate line overlaps the second scan pulse supplied to the n-th gate line. The method of claim 2, The liquid crystal cells, A plurality of fifth liquid crystal cells arranged in the fourth i + 3 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of sixth liquid crystal cells arranged in a fourth i + 4 subpixel column in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of seventh liquid crystal cells arranged in the fourth i + 3 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; And And a plurality of eighth liquid crystal cells arranged in the fourth i + 4 subpixel column in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. The method of claim 7, wherein The TFTs, Connected between the left side of the even data lines and the fifth liquid crystal cells in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line and the fifth data line from the even data lines in response to a scan pulse from the even gate lines. A plurality of fifth TFTs supplying the data voltages of the plurality of fifth liquid crystal cells to the fifth liquid crystal cells; The even data in response to scan pulses from the odd gate lines connected between the fourth liquid crystal cells and the right side of each of the even data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line; A plurality of sixth TFTs supplying the data voltages from the lines to the sixth liquid crystal cells; The even data in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line connected between the left side of each of the even data lines and the seventh liquid crystal cells in response to the scan pulses from the odd gate lines. A plurality of seventh TFTs supplying the data voltages from the lines to the seventh liquid crystal cells; And The even data in response to scan pulses from the even gate lines connected between the right and the eighth liquid crystal cells of each of the even data lines in the 4k + 3 horizontal line and the 4k + 4 horizontal line, respectively. And a plurality of eighth TFTs for supplying the data voltages from the lines to the eighth liquid crystal cells. The method of claim 8, And polarities of the data voltages simultaneously supplied to the odd data lines and the even data lines are opposite to each other. The method of claim 1, And the data voltages charged in the liquid crystal cells arranged in the vertical direction are inverted in polarity in units of two liquid crystal cells. The method of claim 1, The liquid crystal cells, A plurality of first liquid crystal cells arranged in the 8i (i is a positive integer) +1 and the 8i + 3 subpixel columns in the 4k (k is positive integer) +1 horizontal line and the 4k + 2 horizontal line; A plurality of second liquid crystal cells arranged in eighth + 2 and eighti + 4 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of third liquid crystal cells arranged in the eighth + 1 and eighti + 3 subpixel columns in a fourth k + 3 horizontal line and a fourth k + 4 horizontal line; A plurality of fourth liquid crystal cells arranged in the eighth + 2 and eighti + 4 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; A plurality of fifth liquid crystal cells arranged in eighth + 5 and eighti + 7 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of sixth liquid crystal cells arranged in eighth + 6 and eighti + 8 subpixel columns in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line; A plurality of seventh liquid crystal cells arranged in the eighth + 5 and eighti + 7 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line; And And a plurality of eighth liquid crystal cells arranged in the eighth + 6 and eighti + 8 subpixel columns in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. . The method of claim 11, The TFTs, A fourth liquid crystal cell connected to a left side of one of the fourth i + 1 and fourth i + 2 data lines and the first liquid crystal cells in the fourth k + 1 horizontal line and the fourth k + 2 horizontal line, A plurality of first TFTs supplying the data voltage from one of the fourth and fourth data lines to the first liquid crystal cells in response to a scan pulse of the first liquid crystal cell; The even gate lines are connected between the right side of any one of the 4i + 1 and 4i + 2 data lines and the second liquid crystal cells in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of second TFTs for supplying the data voltage from any one of the fourth and fourth data lines to the second liquid crystal cells in response to a scan pulse from the second liquid crystal cell; The even gate lines connected between the third liquid crystal cells and the left side of any one of the fourth and second data lines in the fourth and fourth horizontal lines 4k + 3 and 4k + 4 A plurality of third TFTs for supplying the data voltage from any one of the fourth and fourth data lines to the third liquid crystal cells in response to a scan pulse from the first and second data lines; The odd gate lines are connected between the right side of any one of the fourth i + 1 and fourth i + 2 data lines and the fourth liquid crystal cells in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line. A plurality of fourth TFTs for supplying the data voltages from any one of the fourth and fourth data lines to the fourth liquid crystal cells in response to a scan pulse from the fourth liquid crystal cells; The fourth k + 1 horizontal line and the fourth k + 2 horizontal line are connected between the left side of any one of the fourth i + 3 and fourth i + 4 data lines and the fifth liquid crystal cells to separate from the even gate lines; A plurality of fifth TFTs supplying the data voltages from any one of the fourth and fourth data lines to the fifth liquid crystal cells in response to a scan pulse of the first and second data lines; The odd gate lines are connected between the sixth liquid crystal cell and the right side of any one of the 4i + 3 and 4i + 4 data lines in the 4k + 1 horizontal line and the 4k + 2 horizontal line. A plurality of sixth TFTs supplying the data voltages from any one of the fourth and fourth data lines to the sixth liquid crystal cells in response to a scan pulse from the plurality of fourth lines; The fourth k + 3 horizontal line and the fourth k + 4 horizontal line are connected between the left side of any one of the fourth i + 3 and fourth i + 4 data lines and the seventh liquid crystal cells and are separated from the odd gate lines; A plurality of seventh TFTs supplying the data voltages from any one of the fourth and fourth data lines to the seventh liquid crystal cells in response to a scan pulse of the fourth liquid crystal cells; And The even gate lines connected between the right side of the one of the fourth i + 3 and fourth i + 4 data lines and the eighth liquid crystal cells in the fourth k + 3 horizontal line and the fourth k + 4 horizontal line And a plurality of eighth TFTs for supplying the data voltage from one of the fourth and fourth data lines to the eighth liquid crystal cells in response to a scan pulse from the eighth liquid crystal cell. LCD display device. The method of claim 12, Polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i and i are the same, The polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i, i, and i are identical, The polarities of the data voltages simultaneously supplied to the fourth and fourth data may be opposite to the polarities of the data voltages simultaneously supplied to the fourth and fourth data lines. LCD display device. A method of driving a liquid crystal display device having a plurality of data lines, a plurality of gate lines orthogonal to the data lines, and a plurality of liquid crystal cells formed for each pixel region defined by the data lines and the gate lines. To Coupling TFTs to the data lines in a zigzag form; Supplying the data lines with a data voltage whose polarity is inverted in approximately 1/2 horizontal periods; And Sequentially supplying scan pulses to the scan lines; And the liquid crystal cells adjacent to the left and right side charge data voltages having opposite polarities. The method of claim 14, And the polarities of the data voltages simultaneously supplied to the data lines are the same. The method of claim 14, And the pulse width of said scan pulse is approximately one-half horizontal period. The method of claim 14, The scan pulse, A first scan pulse generated in synchronization with the data voltage of a first polarity; And A second scan pulse generated in synchronization with another data voltage of the first polarity generated after a data voltage of a second polarity; And the first scan pulse supplied to the n-th gate line overlaps the second scan pulse supplied to the n-th gate line. The method of claim 14, And the polarities of the data voltages simultaneously supplied to the odd data lines and the even data lines are opposite to each other. The method of claim 14, The polarities of the data voltages simultaneously supplied to the fourth i (i is a positive integer) +1 and fourth i + 2 data lines are the same, The polarities of the data voltages simultaneously supplied to the fourth and fourth data lines i and i are the same, The polarities of the data voltages simultaneously supplied to the fourth and fourth data may be opposite to the polarities of the data voltages simultaneously supplied to the fourth and fourth data lines. Driving method of liquid crystal display device.

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