KR20170109375A - Apparatus for frequency adaptation to transfer asynchronous data - Google Patents

Abstract

Disclosed is a frequency adaptation apparatus to transmit asynchronous data. The frequency adaptation apparatus to transmit asynchronous data comprises: a buffer which is formed with a dual port RAM having two different frequency characteristics; a divider which converts a host clock and a client clock respectively into a divided clock signal of the host clock and a divided clock signal of the client clock; a phase detector which outputs a set signal and a clear signal by each of the converted divided clocks in the divider; a threshold generator which receives the set signal and the clear signal outputted from the phase detector and outputs the signals during a predetermined period so that a PD-DET value becomes one; and a threshold value detector which continuously outputs data stored in the buffer by setting a dummy_sel signal to zero if the PD_DET signal outputted by the threshold generator maintains one during the predetermined period. Thus, the present invention can transmit asynchronous data easily.

Description

[0001] APPARATUS FOR FREQUENCY ADAPTATION TO TRANSFER ASYNCHRONOUS DATA [0002]

The present invention relates to a frequency adaptation apparatus for transmitting asynchronous data, and more particularly, to a frequency adaptation apparatus for transmitting data having a host frequency for transmitting seamless data having asynchronous characteristics to a client frequency at a predetermined frequency ratio, To a frequency adaptation apparatus for transmitting asynchronous data for easily transmitting data by matching data having a frequency to a host frequency at a predetermined frequency ratio.

Coherent optical orthogonal frequency-division multiplexing (OFDM) is a recently-noted modulation method in the field of optical communications. It is made by combining two powerful techniques of coherent optical detection and OFDM. In particular, OFDM corresponds to the interface technology of the physical layer that has been spotlighted in wireless communication for the last 10 years. When an OFDM optical transceiver using a plurality of carriers is used by using this technique, a channel having a higher bandwidth can be efficiently supported as compared with the case of using a single carrier.

In particular, when receiving FEC for OFDM and long distance transmission, it is important to synchronize frame by frame at the receiving end. For this purpose, it is necessary to adjust the size of the FEC code block unit and the size of the frame to be transmitted using OFDM in units of multiples. In this case, the data bit rate transmitted from the host transmits the OTU frame, but the frequency adaptation block for matching the data bit rate of the operation frequency of the two signals, Design is required. For reference, the operating frequency of the host is generally slower than the operating frequency of the client.

Conventional designs for transferring data in asynchronous networks with different clock frequencies and matching clock frequencies often use an elastic buffer. However, this is mainly used in the physical layer of the transmitting / receiving function having a frequency difference of several hundreds of ppm, but it is difficult to use it when the difference in clock frequency occurs a lot.

In order to overcome the problems described above, an object of the present invention is to provide an asynchronous data transfer method and an asynchronous data transfer method capable of easily transferring asynchronous data by adding or removing dummy data having a predetermined format according to a frequency ratio of a host and a client clock, And to provide a frequency adaptation device for the transmission of the signal.

According to an aspect of the present invention, there is provided a frequency adaptation apparatus for transmitting asynchronous data, the apparatus including: a buffer buffer having a dual port RAM having two different frequency characteristics; A phase detector for outputting a SET signal and a CLEAR signal in accordance with the divided clocks respectively converted in the frequency divider; A threshold generator for receiving the SET signal and the CLEAR signal and outputting a PD_DET value of '1' for a predetermined period, and a dummy_sel signal being set to '0' when the PD_DET signal output from the threshold generator maintains '1' And a threshold detector for continuously outputting data stored in the buffer buffer.

According to the frequency adaptation apparatus for transmitting asynchronous data as described above, it is possible to easily transmit data by periodically adding and deleting dummy data to asynchronous data, thereby providing an effect of seamlessly performing frequency conversion at a constant rate.

1 is a block diagram showing the configuration of a device using a general buffer buffer.
2 is a block diagram illustrating a configuration of an apparatus for receiving data synchronized with a host clock frequency from a host apparatus according to an embodiment of the present invention and supplying data synchronized with a client clock frequency to a client apparatus.
3 is a block diagram showing a configuration of an apparatus for receiving data synchronized with a client clock frequency from a client and supplying data synchronized with the host clock frequency to the host.
4 is a timing chart for each signal of an apparatus for transmitting data when a phase difference between clock signals of a host clock and a client clock is generated.
5 is a timing chart for each signal of an apparatus for transmitting dummy data when a phase difference between divided clock signals of a host clock and a client clock does not occur under the same condition as FIG.
FIG. 6 shows a signal-specific timing diagram of an apparatus for receiving data when a phase difference between a clock signal of a host clock and a clock signal of a client clock is generated.
FIG. 7 is a timing chart for each signal of the apparatus for receiving dummy data when the phase difference between the divided clock signals of the host clock and the client clock does not occur under the same condition as FIG.
8 is a flowchart illustrating a method for receiving data synchronized with a host clock frequency from a host device according to an embodiment of the present invention and supplying data synchronized with the client clock frequency to the client device.
9 is a flowchart illustrating a method for receiving data synchronized with a client clock frequency from a client and supplying data synchronized with the host clock frequency to the host.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. And is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined by the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that " comprises, " or "comprising," as used herein, means the presence or absence of one or more other components, steps, operations, and / Do not exclude the addition.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or similar components, and in the following description of the present invention, Detailed explanations of the detailed description will be omitted when the gist of the present invention can be obscured.

1 is a block diagram showing the configuration of a device using a general buffer buffer.

Referring to FIG. 1, an elastic buffer 101 is used to transfer data in an asynchronous network having different clock frequencies and to adjust a clock frequency. However, this is mainly used in the physical layer of the transmitting and receiving function having a frequency difference of several hundreds of ppm, but it is difficult to use when the difference in the clock frequency is large.

2 is a block diagram illustrating a configuration of an apparatus for receiving data synchronized with a host clock frequency from a host apparatus according to an embodiment of the present invention and supplying data synchronized with a client clock frequency to a client apparatus.

2, the apparatus of the present invention includes a circular buffer or an elastic buffer 201, a plurality of divider units 202 and 203, a phase detector 204, A threshold generator 205, and a threshold detector 206. The threshold generator 206 may be implemented as a digital filter.

The buffer buffer 201 is composed of a dual port RAM having two different frequency characteristics. The write address and the read address are generated by circulating a sine value of a buffer having a size of N, circulate.

Separate from the address of the buffer 201, the divider 202 or 203 counts each time the write and read operations are performed, and divides by 1 / n. First, in the frequency divider 202, data received from the host in accordance with the host clock is continuously written to the buffer buffer 201. On the other hand, the divider 203 reads the data stored in the buffer 201 in accordance with the client clock through a read operation. At this time, since the frequency of the host clock is slower than the frequency of the client clock, data is read by the client clock at a time when it is not stored by the host clock, and underflow phenomenon may occur. In the present invention, dummy data is periodically output as client data instead of data stored in the buffer buffer 201 to prevent this. Here, the time point at which the dummy data is transmitted is as follows.

The time point at which dummy data is generated in the present invention is determined as follows.

First, the host clock and the client clock are converted into the frequency-divided clock count_wr signal of the host clock and the frequency-divided clock count_rd signal of the client clock through the frequency dividers 202 and 203 having the predetermined frequency division number (n), respectively. The respective frequency-divided clocks are input to the phase detector 204.

The phase detector 204 performs SET at a time point when the count_wr that performs the write operation according to the input dividing clock rises to '1', so that the PD_DET value becomes '1'. Then, when the count_rd value for performing the read operation rises to '1', CLEAR is performed so that the PD_DET value becomes '0'.

As described above, the count_wr and count_rd signals are clock signals obtained by dividing each clock by 1 / n. When the phase of the frequency-divided count_wr signal and the frequency of the count_rd signal are different, a constant interval in which the PD_DET value becomes '1' occurs due to the SET and CLEAR signals output from the phase detector 204, do. This means that the readable data is stored by the operation of reading the stored data by the writing operation. Therefore, if the PD_DET value is '1' before performing the read operation, it means that the data stored in the buffer buffer 201 can be output to the client.

The SET and CLEAR signals described above are control signals operated by different clocks. Therefore, logic for retiming the SET signal synchronized to the host clock to the client clock is necessary to control the SET and CLEAR signals to operate in synchronization with the client clock, which is the clock reading the PD_DET value. Retiming the signal using two commonly used flip-flops can solve the meta-stability problem caused by asynchronous signals. Therefore, the SET signal to be described in the following description has the same meaning as the signal (SETr) synchronized with the client clock after the meta-stability is solved.

The threshold generator 205 receives the generated SET signal and CLEAR signal, and outputs the PD_DET value so that the PD_DET value is '1' for a predetermined period. When the SET signal is received, the PD_DET signal is set to '1', and when the CLEAR signal is received, the PD_DET signal is set to '0'.

The threshold detector 206 continuously outputs the data stored in the buffer 201 by setting the dummy_sel signal to '0' when the PD_DET signal output from the threshold generator 205 holds '1' for a predetermined period.

As described above, since the frequency of the host clock is slower than the frequency of the client clock, the phase difference between the count_rd signal and the count_wr, which is the frequency-divided clock signal of the client clock, is gradually reduced. As a result, there is a case where the time of SET by count_wr and the time of CLEAR by count_rd occur at the same time. In this case, the PD_DET value of the threshold generator 205 continuously maintains '0', and the threshold detector 206 keeps '1' during one cycle of the dummy_sel signal in the interval where the PD_DET value becomes '0' Dummy data is output.

3 is a block diagram showing a configuration of an apparatus for receiving data synchronized with a client clock frequency from a client and supplying data synchronized with the host clock frequency to the host.

3, the apparatus of the present invention includes a circular buffer or an elastic buffer 301, a divider 302 and 303, a phase detector 304, A threshold generator 305, and a threshold detector 306. The threshold generator 306 may be implemented by a processor.

The buffer buffer 301 is composed of a dual port RAM having two different frequency characteristics as described in FIG.

Separate from the address of the buffer buffer 301, the divider 302 and 303 counts each time the write and read operations are performed, and divides by 1 / n. First, in the frequency divider 302, the data received from the client according to the client clock continuously performs a write operation to the buffer 301. On the other hand, in the frequency divider 303, the data stored in the buffer 301 is read by performing a read operation in accordance with the host clock. At this time, because the frequency of the client clock is faster than the frequency of the host clock, the data is read by the host clock at a time when the client clock does not store the data, thereby causing an overflow phenomenon. To prevent this, there is a need for a dummy data removal logic that periodically discards the dummy data included in the general data and disposes the data so as not to be stored in the circular buffer.

The point at which dummy data is removed is determined as follows.

First, the host clock and the client clock are converted into the clocks count_rd and count_wr signals divided through the dividers 302 and 303 having the predetermined division number (1 / n), respectively. Each converted clock is input to a phase detector 304.

The phase detector 304 performs SET at a time point when the count_wr that performs the write operation according to the inputted divided clock rises to '1', so that the PD_DET value becomes '1'. Then, CLEAR is performed at the time when the count_rd value rises to '1', so that the PD_DET value becomes '0'. As described above, the count_wr and count_rd signals are clock signals obtained by dividing each clock by 1 / n.

The SET and CLEAR signals output from the phase detector 304 correspond to a period in which the PD_DET value is '1' constant, that is, a phase difference occurs when the count_wr and count_rd signals differ in phase. This means that the readable data is stored by the operation of reading the stored data by the writing operation. Therefore, if the PD_DET value is '1' before performing the write operation, the general data is stored in the buffer 301 so that the host can read it.

As described above, since the frequency of the client clock is faster than the frequency of the host clock, the phase difference between the count_wr signal and the count_rd of the frequency-divided clock signal of the client clock gradually increases. As a result, it may happen that the time set by count_wr and the time cleared by count_rd occur at the same time. In this case, the PD_DET value is continuously maintained at '1', and the operation of removing and storing the predetermined dummy data is stopped.

4 is a timing chart for each signal of an apparatus for transmitting data when a phase difference between clock signals of a host clock and a client clock is generated.

Referring to FIG. 4, the address size of buffer buffer is 18, count_wr and count_rd are divided by 10, and n corresponds to 10. In FIG. 4, signals DATA_HOST, wrAddr, count_wr, and SET belonging to the yellow part A are signals synchronized with the CLK_HOST clock signal, and signals belonging to the green part B, such as SETr, PD_DET, CLEAR, count_rd, rdAddr, DATA_CLIENT , and dummy_sel signals are signals that operate in synchronization with the CLK_CLIENT clock.

First, since the buffer size of the buffer is 18, wrAddr assumes an address value from ad1 to ad18, and the data is assumed to be a block of code blocks and 10 data blocks as one code block. Therefore, the count_wr value operates to divide by 10.

As shown in FIG. 4, whenever the count_wr is divided, the SET signal becomes '1' for one clock cycle. This SET signal is retimed to the SETr signal which is a signal synchronized with the CLK_CLIENT clock, and the SETr signal sets the PD_DET value to '1'. On the other hand, rdAddr also has address values from ad1 to ad18, and count_rd value operates by 10 times because 10 data blocks are assumed to be one code block. Each time the Count_rd value is divided, the CLEAR signal becomes '1' for one clock cycle, and this CLEAR signal resets the PD_DET value to '0'. In addition, when the count_rd is divided, that is, when the CLEAR signal becomes '1', 10 code blocks are read. If the PD_DET holds '1' at this time, the data stored in the buffer can be read. Therefore, dummy_sel has a value of '0'.

5 is a timing chart for each signal of an apparatus for transmitting dummy data when a phase difference between divided clock signals of a host clock and a client clock does not occur under the same condition as FIG.

4, the SETr signal is retimed at a time when the count_wr is divided and the PD_DET value is set to '1', and at the same time, the C_LEAR signal also sets the PD_DET value to '0'. When SET and CLEAR occur simultaneously, the PD_DET value is set to '1' in the present invention.

Therefore, the PD_DET value is '0' at the first time when the count_rd is divided, but the PD_DET value is maintained at '1' when the count_rd is divided. Therefore, during one cycle, the dummy_sel maintains '1' to select and transmit the dummy data, and during the remaining cycles, the dummy_sel value is maintained at '0' to select and transmit the data stored in the buffer.

FIG. 6 shows a signal-specific timing diagram of an apparatus for receiving data when a phase difference between a clock signal of a host clock and a clock signal of a client clock is generated. In FIG. 6, for example, the address size of the buffer buffer is 18, and count_wr and count_rd are divided by 10 and the value of n is 10.

7 is a timing chart for each signal of the apparatus for receiving dummy data when the phase difference between the divided clock signals of the host clock and the client clock does not occur under the same condition as in Fig.

8 is a flowchart illustrating a method for receiving data synchronized with a host clock frequency from a host device according to an embodiment of the present invention and supplying data synchronized with the client clock frequency to the client device.

Referring to FIG. 8, the buffer buffer circulates an address value of a buffer having a size N to a write address and a read address through a remaining calculation (S801).

Subsequently, the frequency divider is counted and divided by 1 / n every time the write and read operations are performed separately from the address of the buffer buffer (S802). At this time, the data input from the host according to the host clock continuously performs the write operation to the buffer buffer. Also, the data stored in the buffer buffer is read through the read operation in accordance with the client clock. At this time, since the frequency of the host clock is slower than the frequency of the client clock, data is read by the client clock at a time when it is not stored by the host clock, and underflow phenomenon may occur. In order to prevent this, the present invention periodically outputs dummy data as client data instead of data stored in the buffer. Here, the dummy data is generated. The host clock and the client clock are respectively converted into a frequency-divided clock count_wr signal of the host clock and a frequency-divided clock count_rd signal of the client clock through a frequency divider having a predetermined frequency division number (n) . The converted divided clocks are input to the phase detector.

Then, the phase detector sets a PD_DET value to '1' by performing a SET at a time when count_wr, which performs a write operation according to the inputted dividing clock, rises to '1', and counts a count_rd value CLEAR at the time of rising to '1' so that the PD_DET value becomes '0' (S803). At this time, the count_wr and count_rd signals are clock signals in which each clock is divided by 1 / n. When the phase of the divided clock count_wr signal and the signal of the count_rd signal differ from each other, a constant interval in which the PD_DET value becomes '1' occurs due to the SET and CLEAR signals output from the phase detector, which corresponds to a period in which a phase difference occurs. This means that the readable data is stored by the operation of reading the stored data by the writing operation. Therefore, if the PD_DET value is '1' before performing the read operation, it means that the data stored in the buffer buffer can be output to the client.

The SET and CLEAR signals described above are control signals operated by different clocks. Therefore, logic for retiming the SET signal synchronized to the host clock to the client clock is necessary to control the SET and CLEAR signals to operate in synchronization with the client clock, which is the clock reading the PD_DET value. Retiming the signal using two commonly used flip-flops can solve the meta-stability problem caused by asynchronous signals. Therefore, the SET signal to be described in the following description has the same meaning as the signal (SETr) synchronized with the client clock after the meta-stability is solved.

Subsequently, the threshold generator receives the generated SET signal and CLEAR signal, and outputs the PD_DET value so that the PD_DET value becomes '1' (S804). When the SET signal is received, the PD_DET signal is set to '1', and when the CLEAR signal is received, the PD_DET signal is set to '0'.

If the PD_DET signal output from the threshold generator maintains '1' for a predetermined period, the threshold detector sets the dummy_sel signal to '0' to continuously output the data stored in the buffer buffer (S805). At this time, since the frequency of the host clock is slower than the frequency of the client clock, the phase difference between the count_rd signal and the count_wr, which is the frequency-divided clock signal of the client clock, gradually decreases. As a result, there is a case where the time of SET by count_wr and the time of CLEAR by count_rd occur at the same time. In this case, the PD_DET value of the threshold generator keeps '0' continuously, and the threshold detector keeps '1' during the cycle of the dummy_sel signal in the interval where the PD_DET value becomes '0' to output the determined dummy data .

9 is a flowchart illustrating a method for receiving data synchronized with a client clock frequency from a client and supplying data synchronized with the host clock frequency to the host.

Referring to FIG. 9, in the buffer buffer, the write address and the read address are circulated through the remaining calculation of the address value of the buffer having the size N (S901).

Next, the frequency divider is counted and divided by 1 / n every time the write and read operations are performed separately from the address of the buffer buffer (S902). At this time, the data received from the client according to the client clock continuously performs a write operation to the buffer. On the other hand, the data stored in the buffer buffer according to the host clock is read by reading. At this time, because the frequency of the client clock is faster than the frequency of the host clock, the data is read by the host clock at a time when the client clock does not store the data, thereby causing an overflow phenomenon. To prevent this, there is a need for a dummy data removal logic that periodically discards the dummy data included in the general data and disposes the data so as not to be stored in the circular buffer.

The host clock and the client clock are respectively converted into clocks count_rd and count_wr signals divided through a frequency divider having a predetermined frequency division ratio (1 / n), and the converted clocks are input to the phase detector do.

Then, the phase detector sets the PD_DET value to '1' and count_rd value is '1' by performing the SET at the time when the count_wr that performs the write operation according to the inputted divided clock rises to '1' CLEAR is performed at the time when the PD_DET value is increased to '0' (S903). At this time, the count_wr and count_rd signals are clock signals in which each clock is divided by 1 / n. The SET and CLEAR signals output from the phase detector correspond to a period in which the PD_DET value is '1', that is, a period in which a phase difference occurs, when the count_wr and count_rd signals differ in phase. This means that the readable data is stored by the operation of reading the stored data by the writing operation. Therefore, if the PD_DET value is '1' before performing the write operation, the general data is stored in the buffer to allow the host to read it.

Then, the threshold generator sets the PD_DET signal to '1' upon receiving the SET signal, and sets the PD_DET signal to '0' upon receiving the CLEAR signal (S904).

Then, since the frequency of the client clock is faster than the frequency of the host clock, the phase difference between the count_wr signal and the count_rd signal gradually increases, which is the divided clock signal of the client clock. As a result, it may happen that the time set by count_wr and the time cleared by count_rd occur at the same time. In this case, the threshold detector keeps the PD_DET constantly at '1', so that the operation of removing and storing the dummy data set once can be stopped (S905).

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

201, 301: buffer buffer
202, 203, 302, and 303:
204, 304: phase detector
205, 305: threshold value generator
206, 306: Threshold detector

Claims (1)

A frequency adaptation device for transmission of asynchronous data,
A buffer buffer composed of dual port RAMs having two different frequency characteristics;
A frequency divider for converting the host clock and the client clock into a divided clock signal of the host clock and a divided clock signal of the client clock, respectively;
A phase detector for outputting a SET signal and a CLEAR signal according to the frequency-divided clocks respectively converted in the frequency divider;
A threshold generator for receiving a SET signal and a CLEAR signal output from the phase detector and outputting a PD_DET value of '1' for a predetermined period; And
And a threshold detector for continuously outputting data stored in the buffer by setting a dummy_sel signal to '0' when the PD_DET signal output from the threshold generator keeps '1' for a predetermined period, Adaptive device.

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