KR20170106006A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device. The semiconductor device comprises: a substrate including a first region and a second region; first and second dielectric layers respectively formed on the substrate of the first region and the second region; and first and second gate stacks formed on the first and second dielectric layers respectively. The first gate stack comprises a first TiAlC film in contact with the first dielectric layer, a first barrier layer, and a first metal layer sequentially deposited on the first TiAlC layer. The second gate stack includes a second lanthanum oxide (LaO) film in contact with the second dielectric layer, a second TiAlC layer, a second barrier layer, and a second metal layer sequentially deposited on the second lanthanum oxide layer. The threshold voltage of a plurality of transistors is able to be adjusted.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device.

The semiconductor device may include transistors having different threshold voltages. Examples of transistors having different threshold voltages include a logic transistor and a combination of a static random access memory (SRAM) or a dynamic random access memory (DRAM) transistor.

Meanwhile, various methods for controlling the threshold voltage of the transistors included in the semiconductor device have been studied.

A problem to be solved by the present invention is to provide a semiconductor device in which threshold voltages of a plurality of transistors are adjusted.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; First and second dielectric layers formed on the substrate of the first and second regions, respectively; And first and second gate stacks formed on the first and second dielectric layers, respectively, wherein the first gate stack comprises a first TiAlC film in contact with the first dielectric layer, and a second TiAlC film on the first TiAlC film Wherein the second gate stack comprises a second lanthanum oxide (LaO) film in contact with the second dielectric layer, and a second oxide lanthanum (LaO) layer sequentially deposited on the second lanthanum oxide layer 2 TiAlC film, a second barrier film, and a second metal layer.

In some embodiments of the present invention, the second TiAlC film may be in contact with the second lanthanum oxide film.

In some embodiments of the present invention, the first and second gate stacks may comprise tantalum nitride (TaN).

In some embodiments of the present invention, the substrate further includes a third region and a fourth region, and third and fourth dielectric films respectively formed on the substrate of the third region and the fourth region; And third and fourth gate stacks formed on the third and fourth dielectric layers, respectively, wherein the third gate stack comprises a third TiN film, a third TiAlC film, and a third TiN film sequentially stacked on the third dielectric film, Wherein the fourth gate stack comprises a fourth lanthanum film, a fourth TiN film, a fourth TiAlC film, a fourth barrier film, and a fourth dielectric film sequentially stacked on the fourth dielectric film, Metal layer.

In some embodiments of the present invention, the first through fourth gate stacks form first through fourth transistors, respectively, and the threshold voltages of the first through fourth transistors may be different from each other.

In some embodiments of the present invention, the first to fourth transistors may be N-type transistors.

In some embodiments of the present invention, the third TiN film and the fourth TiN film may have different thicknesses.

In some embodiments of the present invention, the semiconductor device may further include first and second interface films respectively formed between the substrate and the first and second dielectric films.

In some embodiments of the present invention, each of the first and second dielectric layers may extend upwardly along the bottom and sidewalls of the first and second gate stacks.

According to an aspect of the present invention, there is provided a semiconductor device including: a substrate including first to fourth regions; First to fourth dielectric layers formed on the substrate of the first to fourth regions, respectively; And first to fourth gate stacks formed on the first to fourth dielectric layers, respectively, wherein the first gate stack includes a first TiAlC film sequentially stacked on the first dielectric film, 1 metal layer, the second gate stack comprising a second lanthanum oxide (LaO) film, a second TiAlC film, a second barrier film and a second metal layer sequentially deposited on the second dielectric layer, Wherein the gate stack comprises a third TiN film, a third TiAlC film, a third barrier film and a third metal layer sequentially stacked on the third dielectric layer, A fourth TiAlC film, a fourth TiAlC film, a fourth barrier film and a fourth metal layer, wherein the second TiAlC film is in contact with the second lanthanum oxide film.

In some embodiments of the present invention, the first through fourth gate stacks may comprise tantalum nitride (TaN).

In some embodiments of the present invention, the first through fourth gate stacks form first through fourth transistors, respectively, and the threshold voltages of the first through fourth transistors may be different from each other.

In some embodiments of the present invention, the first to fourth transistors may be N-type transistors.

In some embodiments of the present invention, the third TiN film and the fourth TiN film may have different thicknesses.

In some embodiments of the present invention, each of the first to fourth dielectric layers may extend upward along the bottom surface and the sidewalls of the first to fourth gate stacks.

Other specific details of the invention are included in the detailed description and drawings.

1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
2 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
3 to 20 are a perspective view and a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
21 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
22 to 24 are a perspective view and a cross-sectional view for explaining a semiconductor device according to some embodiments.
25 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
26 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
27 is a block diagram of an electronic system including a semiconductor device manufactured in accordance with some embodiments of the present invention.
28 is an exemplary semiconductor system to which a semiconductor device fabricated in accordance with some embodiments of the present invention may be applied

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In the drawings relating to the semiconductor device according to some embodiments of the present invention, a pinned transistor (FinFET) including a channel region of a pin-shaped pattern shape is exemplarily shown, but the present invention is not limited thereto. The semiconductor device according to some embodiments of the present invention may include a tunneling FET, a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor . Further, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and the like.

Next, a semiconductor device according to some embodiments of the present invention will be described with reference to FIG.

1 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 1, a substrate 101 of a semiconductor device according to the present embodiment includes first and second regions I and II. The first region (I) and the second region (II) may be connected to each other or may be separated from each other.

The first region I may include a first fin F1, a first dielectric layer 143 and a first gate stack 170. The second region II may include a second fin F2, A dielectric film 243 and a second gate stack 270 can be formed.

Here, the substrate 101 may be, for example, bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate 101 may be a silicon substrate or it may include other materials such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide .

Alternatively, the substrate 101 may have an epilayer formed on the base substrate. When an active layer is formed using an epi layer formed on a base substrate, the epi layer may include silicon or germanium, which is an element semiconductor material. In addition, the epi layer may include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor. Specifically, as an example of the IV-IV group compound semiconductor, the epi layer may be a binary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn) A ternary compound or a compound doped with a Group IV element thereon. For example, the epitaxial layer of the III-V group compound semiconductor is a Group III element and includes at least one of aluminum (Al), gallium (Ga), and indium (In) and a group V element such as phosphorus (P), arsenic (As) Monovalent compound, or a siliceous compound in which one of mononuclear (Sb) is formed by bonding.

In this embodiment, the first and second transistors TR1 and TR2 may be formed in the first and second regions I and II of the substrate 101, respectively. Although not shown, the first and second transistors TR1 and TR2 may be separated from each other by a device isolation film formed in the substrate 101. [ Such an element isolation film may be, for example, Shallow Trench Isolation (STI) or Deep Trench Isolation (DTI).

The first and second transistors TR1 and TR2 are connected to the first and second source and drain regions 123 and 223 and the first and second spacers 121 and 221 and the first and second interface films 141 and 142, 241, first and second dielectric layers 143, 243, and first and second gate stacks 170, 270.

Specifically, the first transistor TR1 formed in the first region I of the substrate 101 includes a first source-drain region 123, a first spacer 121, a first interface film 141, 1 dielectric layer 143 and a first gate stack 170. Here, the first gate stack 170 may include a first TiAlC film 151, a second barrier film 153, and a first metal layer 155.

The second transistor TR2 formed in the second region II of the substrate 101 has a second source-drain region 223, a second spacer 221, a second interface film 241, A dielectric layer 243, and a second gate stack 260. Here, the second gate stack 260 may include a second TiAlC film 251, a second barrier film 253, and a second metal layer 255.

The first and second source-drain regions 123 and 223 may be formed by implanting a predetermined impurity into the substrate 101 as shown in the figure. When the first and second transistors TR1 and TR2 according to this embodiment are NMOS transistors, n-type impurities may be implanted into the first and second source-drain regions 123 and 223.

Meanwhile, the first and second source-drain regions 123 and 223 may be formed in an elevated shape as shown in the figure. In this case, the first and second source-drain regions 123, 223 may be formed in the form of an epilayer in the trench formed in the substrate 101. However, the shape of each of the first and second source-drain regions 123, 223 is not limited to that shown.

The interlayer insulating layer 130 may include a first trench 135 and a second trench 235 formed on the first and second regions I and II of the substrate 101, respectively. The first and second spacers 121 and 221 may be disposed on both sides of the first trench 135 and the second trench 235, respectively.

Each of the first and second spacers (121, 221) are, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon shot nitride (SiOCN) and at least one of a combination of One can be included.

Although each of the first and second spacers 121 and 221 is shown as a single film, it is for convenience of explanation, but is not limited thereto. When the first and second spacers 121 and 221 are a plurality of films, at least one of the films included in each of the first and second spacers 121 and 221 has a low dielectric constant material such as silicon oxynitride (SiOCN) . ≪ / RTI >

In addition, when the first and second spacers 121 and 221 are a plurality of films, at least one of the films included in the first and second spacers 121 and 221 may have an L shape .

In some cases, the first and second spacers 121 and 221 may serve as guides for forming Self Aligned Contacts. Accordingly, the first and second spacers 121 and 221 may include a material having an etch selectivity to the interlayer insulating layer 130.

The first and second trenches 135 and 235 formed in the first and second regions I and II of the substrate 101 are provided with first and second interface films 141 and 241, 1 and the second dielectric layers 143 and 243 and the first and second gate stacks 170 and 270 may be sequentially formed.

The first and second interface films 141 and 241 may prevent a poor interface between the substrate 101 and the first and second dielectric layers 143 and 243. The first and second interface films 141 and 241 may be formed of a low dielectric material layer having a dielectric constant k of 9 or less such as a silicon oxide film (k is about 4) or a silicon oxynitride film (k About 4 to 8). Alternatively, each of the first and second interface films 141 and 241 may be made of a silicate or a combination of the films exemplified above.

The first and second dielectric layers 143 and 243 may be made of a material having a high dielectric constant. In some embodiments of the present invention, the first and second dielectric layers 143 and 243 may be made of a material such as, for example, HfO 2, Al 2 O 3, ZrO 2, or TaO 2, but the present invention is not limited thereto

Referring again to FIG. 1, each of the first and second dielectric layers 143 and 243 is formed in a first direction (for example, the up-down direction in FIG. 1) along the sidewalls of the first and second spacers 121 and 221 And can be arranged in an elongated shape. In this embodiment, the first and second dielectric layers 143 and 243 have the same shape as the first and second dielectric layers 143 and 243 in the replacement process (or gate last process) process).

However, the present invention is not limited thereto, and the shapes of the first and second dielectric layers 143 and 243 can be modified into any other form. That is, in some other embodiments of the present invention, the shapes of the first and second dielectric layers 143 and 243 may be different from those shown in FIG. 1 by using a gate first process, May not extend upwardly along the sidewalls of the first and second portions 121 and 221.

Referring again to FIG. 1, first and second gate metals 170 and 270 are formed on first and second dielectric layers 143 and 243 of first and second regions I and II of the substrate 101, respectively. Can be formed.

Specifically, the first gate metal 150 may include a first TiAlC film 151, a first barrier film 153, and a first metal layer 155 sequentially formed on the first dielectric layer 143, The second gate metal layer 250 is formed on the second dielectric layer 243 by sequentially forming a second lanthanum oxide layer 245, a second TiAlC layer 251, a second barrier layer 253, and a second metal layer 255, . ≪ / RTI >

The first and second TiAlC films 151 and 251 may include TiAlC. The first and second barrier layers 153 and 253 may comprise TiN, for example, and the materials that the first and second metal layers 155 and 255 may comprise may include first and second TiAlC layers 151 and 152, 251 from being diffused. The first and second metal layers 155 and 255 may include Al, W and the like and fill the remaining portions of the first and second trenches 135 and 235 in the first and second regions I and II .

On the other hand, the second region (II) may include a second lanthanum oxide film (245) unlike the first region (I). The second lanthanum oxide film 245 may comprise, for example, LaO. Accordingly, the first transistor TR1 formed in the first region I and the second transistor TR2 formed in the second region II may have different threshold voltages. More specifically, the threshold voltage Vt2 of the second transistor TR2 including the second lanthanum oxide film 245 may be smaller than the threshold voltage Vt1 of the first transistor TR1. However, the present invention is not limited thereto.

The first and second gate stacks 170 and 270 according to the present invention include tantalum nitride (TaN) as a work function control material. Therefore, the threshold voltages Vt1 and Vt2 of the first and second transistors TR1 and TR2 can be controlled through the presence or absence of the second lanthanum oxide film 245, respectively.

Next, a semiconductor device according to some embodiments of the present invention will be described with reference to FIG.

2 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

The semiconductor device according to this embodiment is substantially the same as the semiconductor device described with reference to Fig. 1 except that it includes a capping film on the gate stack. Accordingly, like reference numerals refer to like elements, and repeated descriptions may be omitted.

Referring to FIG. 2, the semiconductor device according to the present embodiment includes first and second regions I and II. The first and second transistors TR1 and TR2 may be formed in the first and second regions I and II of the substrate 101, respectively.

The first and second transistors TR1 and TR2 are connected to the first and second source and drain regions 123 and 223 and the first and second spacers 121 and 221 and the first and second interface films 141 and 142, 241, first and second dielectric layers 143, 243, and first and second gate stacks 170, 270.

Also, the first and second capping films 180 and 280 may be disposed on the first and second gate stacks 170 and 270, respectively. Specifically, the first and second capping films 180 and 280 may be formed on the first and second gate stacks 170 and 270, respectively, and may cover the first and second trenches 135 and 235. The first and second capping films 180 and 280 may comprise a nitride (e.g., at least one of SiN, SiON, SiCON) or an oxide. The first and second capping films 180 and 280 may block the first and second gate stacks 170 and 270 from being exposed to the outside to prevent a change in performance of the first and second gate stacks 170 and 270 . For example, oxygen atoms may penetrate into the first and second gate stacks 170 and 270, where the threshold voltage of the first and second gate stacks 170 and 270 may be varied. Accordingly, the first and second capping films 180 and 280 may be formed to keep the threshold voltages of the first and second gate stacks 170 and 270 constant.

Next, with reference to FIGS. 3 to 20, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described.

3 to 20 are a perspective view and a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention. FIGS. 3 to 6 and 18 are perspective views, and FIGS. 7 to 17, 19 and 20 are sectional views.

Referring to FIG. 3, a first fin F1 and a second fin F2 are formed on a substrate 101, respectively. The first region I and the second region II may be defined on the substrate 101. [ The first region (I) and the second region (II) may be attached to each other or may be separated from each other.

The first pin F1 may be formed in the first region I and the second pin F2 may be formed in the second region II. The first and second pins F1 and F2 may protrude in the third direction Z1. The first and second pins F1 and F2 may extend along the second longitudinal direction Y1 and may have a long side of the second direction Y1 and a short side of the first direction X1 . However, the present invention is not limited thereto. For example, the long side direction may be the first direction X1 and the short side direction may be the second direction Y1.

The first and second pins F1 and F2 may be part of the substrate 101 and may include an epitaxial layer grown from the substrate 101. [ For example, Si or SiGe.

Referring to FIG. 4, a field insulating layer 110 is formed on the substrate 101 so as to cover sidewalls of the first and second fins F1 and F2. The field insulating film 110 may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring to FIG. 5, the upper portion of the field insulating film 110 is recessed to expose the upper portions of the first and second pins F1 and F2. The recess process may include an optional etch process.

On the other hand, a part of the first and second pins F1 and F2 protruding above the field insulating film 110 may be formed by an epitaxial process. For example, after the formation of the field insulating film 110, the first and second fins F1 and F2 exposed by the field insulating film 110 without a recess process are epitaxially grown on the upper surfaces of the first and second fins F1 and F2. A part of the second pins F1 and F2 may be formed.

Also, doping for threshold voltage adjustment can be performed on the exposed first and second fins F1 and F2. For example, the first fin F1 of the first region I may be doped with boron (B) as an impurity, and the second fin F2 of the second region II may be doped with impurities P) or arsenic (As). However, the present invention is not limited thereto, and the first and second fins F1 and F2 may be doped with the same kind of impurity.

Next, first and second dummy gate structures 111 and 211 are formed on the first and second fins F1 and F2, respectively, which intersect the first and second fins F1 and F2. Although the first and second dummy gate structures 111 and 211 are shown as crossing the first and second pins F1 and F2 at right angles in the first direction X1 in FIG. 5, And the first and second dummy gate structures 111 and 211 may intersect the first and second pins F1 and F2 at an acute angle and / or an obtuse angle with the first direction X1, respectively .

The first and second dummy gate structures 111 and 211 may include dummy gate insulating films 113 and 213 and dummy gate electrodes 115 and 215, respectively. The dummy gate insulating films 113 and 213 and the dummy gate electrodes 115 and 215 may be sequentially stacked.

The dummy gate insulating films 113 and 213 may be conformally formed on the upper and upper surfaces of the sidewalls of the exposed first and second fins F1 and F2 without being covered by the field insulating film 110. [ The dummy gate insulating films 113 and 213 may be disposed between the dummy gate electrodes 115 and 215 and the field insulating film 110.

The dummy gate electrodes 115 and 215 may be formed on the dummy gate insulating films 113 and 213.

For example, the dummy gate electrodes 115 and 215 may include silicon oxide, and the dummy gate insulating films 113 and 213 may include polysilicon.

Each of the dummy hard mask films 117 and 217 may be formed on the first and second dummy gate structures 111 and 211. The dummy hard mask films 117 and 217 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Referring to FIG. 7, which is a cross-sectional view illustrating A-A and B-B in FIG. 6 and FIG. 6, spacers 121 and 221 are formed on both side walls of the first and second dummy gate structures 111 and 211. 7 is a cross-sectional view showing A-A and B-B in Fig.

The spacers 121 and 221 may expose the upper surfaces of the hard mask films 117 and 217. Spacers 121 and 221 may be silicon nitride or silicon oxynitride.

Then, the first and second fins F1 and F2 are etched without exposing the first and second dummy gate structures 111 and 211, respectively. The first and second fins F1 and F2 can be etched using the spacers 121 and 221 and the first and second dummy gate structures 111 and 211 as an etch mask.

Then, first and second source / drain regions 123 and 223 are formed in the etched portions of the first and second fins F1 and F2. The first source / drain region 123 can be formed in the first fin F1 and the second source / drain region 223 can be formed in the second fin F2. The first and second source / drain regions 123 and 223 may be elevated source / drain regions. Therefore, as shown in FIG. 20, the upper surfaces of the first and second source / drain regions 123 and 223 may be higher than the upper surfaces of the first and second pins F1 and F2.

The first source / drain region 123 and / or the second source / drain region 223 may comprise a tensile stress material. The first source / drain region 123 and / or the second source / drain region 223 may be the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 is Si, the first source / drain region 123 and / or the second source / drain region 223 may be Si or a material having a smaller lattice constant than Si (e.g., SiC, SiP).

However, the first source / drain region 123 and / or the second source / drain region 223 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The first and second source / drain regions 123 and 223 can be formed by epitaxial growth.

6, the first and second source / drain regions 123 and 223 are pentagonal. However, the present invention is not limited thereto. For example, the first and second source / 223 may have a shape such as a rectangle, a circle, or a hexagon.

Referring to FIG. 8, an interlayer insulating film 130 is formed to cover the first and second source / drain regions 123 and 223. The interlayer insulating film 130 may cover the sidewalls of the spacers 121 and 221 and expose the upper surfaces of the hard mask films 117 and 217. The interlayer insulating film 130 may include, for example, silicon oxide.

Referring to FIG. 9, first and second trenches 135 and 235 are formed to expose the tops of the first and second pins F1 and F2. First, the hard mask films 117 and 217 are removed. The hard mask films 117 and 217 can be removed through a planarization process or the like, and if the planarization process is performed, the interlayer insulating film 130 can also be partially etched.

Then, the first and second dummy gate structures 111 and 211 are removed. The dummy gate electrodes 115 and 215 and the dummy gate insulating films 113 and 213 are removed to expose the first and second pins F1 and F2. The first trench 135 is formed at a position where the first dummy gate structure 111 was present and the second trench 235 is formed at a place where the second dummy gate structure 211 was located. The sidewalls of the spacers 121 and 221 can be exposed by the first and second trenches 135 and 235.

Referring to FIG. 10, first and second interface films 141 and 241 are formed in first and second trenches 135 and 235, respectively. The first and second interface films 141 and 241 may be formed along the upper surface of the first and second pins F1 and F2 and the upper surface of the sidewall.

The first and second interface films 141 and 241 may be formed by oxidizing the exposed first and second fins F1 and F2 in the first and second trenches 135 and 235 . The first and second interface films 141 and 241 may be formed along the bottom surfaces of the first and second trenches 135 and 235, respectively.

A first dielectric layer 143a is formed in the first trench 135 and a second dielectric layer 243a is formed in the second trench 235. Next, Specifically, the first dielectric layer 143a may be conformally formed along the sidewalls and the bottom surface of the first trench 135, and may include a field insulating layer 110, It can be formed into a foam. The second dielectric layer 243a may be conformally formed along the sidewalls and the bottom surface of the second trench 235 and may conform to the top surface and top surface of the sidewall of the field insulating layer 210, . Also, the first and second dielectric layers 143a and 243a may be formed on the dielectric interlayer 130 as well.

The first and second dielectric layers 143a and 243a may include a dielectric material having a higher dielectric constant than the silicon oxide layer. For example, the first and the second dielectric layer (143a, 243a) is, HfSiON, HfO _2, ZrO _2, Ta ₂ O _5, TiO _2, SrTiO _3, or selected from the group consisting of such as (Ba, Sr) TiO ₃ ≪ / RTI > The first and second dielectric layers 143a and 243a may be formed to have an appropriate thickness depending on the type of device to be formed.

Referring to FIG. 11, a first lanthanum oxide film 145a is formed in the first trench 135 and a second lanthanum oxide film 245a is formed in the second trench 235. The first and second lanthanum oxide films 145a and 245a may be conformally formed along the sidewalls and the bottom surface in the first and second trenches 145 and 245, respectively. Further, it may be formed along the upper and upper surfaces of the side walls of the first and second pins F1 and F2. The first and second lanthanum oxide films 145a and 245a may include, but are not limited to, LaO.

Referring to FIG. 12, the first lanthanum oxide film 145a of the first region I is removed through the first mask pattern 1001. Specifically, a first mask pattern 1001 can be formed by forming a mask layer covering the first and second regions I and II, and patterning the mask layer. Then, the first lanthanum oxide film 145a of the first region I may be removed by an etching process using the first mask pattern 1001 as an etching mask. Accordingly, the first dielectric layer 143a can be exposed.

Referring to FIG. 13, the first and second diffusion layers 147 and 247 and the first and second isolation layers 149 and 249 are sequentially formed. A first diffusion film 147 is formed in the first trench 135 and a second diffusion film 247 is formed in the second trench 235. The first and second diffusion films 147 and 247 may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 135 and 235, respectively. Further, it may be formed along the upper and upper surfaces of the side walls of the first and second pins F1 and F2. The first and second diffusion films 147 and 247 may include, but are not limited to, TiN.

Then, first and second blocking films 149 and 249 are formed on the first and second diffusion films 147 and 247, respectively. The first and second blocking films 149 and 249 may fill the first and second trenches 135 and 235 and may cover the first and second diffusion films 147 and 247 so as not to be exposed to the outside . The first and second blocking films 149 and 249 may comprise, for example, Si.

Annealing 150 is then performed. The first and second dielectric layers 143a and 243a contain oxygen atoms. The oxygen atoms are bonded to other materials (for example, Hf, Zr, Ta, Ti, etc.) in the first and second dielectric layers 143a and 243a. If the coupling is broken, a leak current or the like may be generated and the performance of the transistor may deteriorate. To prevent this problem, annealing 150 is performed to bond the oxygen atoms to the broken part of the bond. When the annealing 150 is performed, oxygen atoms contained in the first diffusion layer 147 can be provided to the first dielectric layer 143a. In addition, the oxygen atoms contained in the second diffusion film 247 and / or the second lanthanum film 245a may be provided to the second dielectric film 243a.

On the other hand, if the first and second diffusion films 147 and 247 are exposed during the annealing 150, the oxygen atoms outside the first and second diffusion films 147 and 247 penetrate into the first and second diffusion films 147 and 247 during the annealing 150 The number of oxygen atoms moving to the lower portion of the first and second diffusion films 147 and 247 increases. When oxygen atoms are supplied in excess of the required number of oxygen atoms of the first and second dielectric layers 143a and 243a, excess oxygen atoms are supplied to the first and second pins 135 and 235 in the first and second trenches 135 and 235 F1, < / RTI > F2). As a result, the thickness of the first and second interface films 141 and 241 becomes thick, and the performance of the transistor may deteriorate. The first and second barrier films 149 and 249 are formed on the first and second diffusion films 147 and 247 so that the first and second diffusion films 147 and 247 are exposed to the outside The supply amount of oxygen atoms can be appropriately adjusted by blocking.

The annealing 150 may be performed at a temperature of 500 ° C to 1500 ° C.

The thickness of the first and second diffusion layers 147 and 247 may vary depending on the number of oxygen atoms to be supplied.

Referring to FIG. 14, the first and second shielding films 149 and 249 and the first and second diffusion films 147 and 247 are sequentially removed. Accordingly, the first dielectric layer 143a and the second lanthanum oxide layer 245a can be exposed.

Next, referring to FIG. 15, first and second TiAlC films 151a and 251a are formed on the first dielectric layer 143a and the second lanthanum oxide layer 245a, respectively. The first and second TiAlC films 151a and 251a may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 135 and 235, respectively. In addition, the first and second barrier films 151a and 251a may include, for example, TiAlC.

Then, first and second barrier films 153a and 253a are formed on the first and second TiAlC films 151a and 251a, respectively. Specifically, the first and second barrier layers 153a and 253a may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 130 and 230, respectively. The first and second barrier films 153a and 253a may include, for example, TiN. The first and second barrier films 153a and 253a can prevent the materials included in the first and second metal films 155a and 255a from diffusing into the first and second trenches 130 and 230. [

First and second metal films 155a and 255a are formed on the first and second barrier films 153a and 253a, respectively. The first and second metal films 155a and 255a may fill the remaining portions of the first and second trenches 130 and 230. [ The first and second metal films 155a and 255a may include, for example, Al, W, and the like.

Referring to FIG. 16, first and second gate structures 170 and 270 are formed. 15, the first gate structure 170 can be formed in the first region I and the second gate structure 170 can be formed in the second region II by performing the planarization process so that the interlayer insulating film 130 is exposed. The structure 270 can be formed.

Referring to FIG. 17, first and second capping films 180 and 280 are formed on the first and second gate structures 170 and 270, respectively.

The first and second gate structures 170 and 270 may be partially removed to adjust the height of the first and second gate structures 170 and 270 before forming the first and second capping layers 180 and 280 . The first and second dielectric films 143 and 243 and the first and second barrier films 153 and 253 and the first and second TiAlC films 151 and 251 in the first and second trenches 135 and 235 ), The first and second metal films 155 and 255, and the second lanthanum oxide film 245 may be partially removed. In this case, the sidewalls of the first and second capping films 180 and 280 can contact the sidewalls of the spacers 121 and 221, respectively. In addition, the upper surfaces of the first and second capping films 180 and 280 may be disposed on the same plane as the interlayer insulating film 130.

18 to 20, a first transistor TR1 may be formed in the first region I, and a second transistor TR2 may be formed in the second region II. 19 is a cross-sectional view taken along the line A-A and B-B in Fig. 18, and Fig. 20 is a cross-sectional view taken along the line C-C and D-D in Fig.

Second interlayer insulating films 132 and 232 are formed on the interlayer insulating film 130. The second interlayer insulating films 132 and 232 may cover the first and second capping films 180 and 280. The second interlayer insulating films 132 and 232 may include the same material as the interlayer insulating film 130, and may include, for example, silicon oxide.

First and second silicide films 191 and 291 are formed on the first and second source and drain regions 123 and 223 and the first and second source and drain regions 123 and 223 are formed on the first and second source / The first and second contacts 193 and 293 penetrating the insulating film 130 and the second interlayer insulating films 132 and 232 may be formed to form the semiconductor device according to the present embodiment. However, the technical idea of the present invention is not limited thereto. The first and second silicide layers 191 and 291 may reduce the surface resistance and the contact resistance of the first and second source and drain regions 123 and 223. For example, , Co, and the like. The first and second contacts 193 and 293 may include, for example, W, Al Cu, and the like.

Next, referring to FIG. 21, a semiconductor device according to some embodiments of the present invention will be described. 21 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. The semiconductor device according to the present embodiment can correspond to Fig. 20 of the above-described semiconductor device. Therefore, the semiconductor device according to this embodiment is substantially the same as the embodiment of FIG. 21 except that it further includes a second field insulating film between the fin and the field insulating film. Accordingly, like reference numerals refer to like elements and repeated descriptions may be omitted.

Referring to FIG. 21, a second field insulating film 105 and 205 may be further disposed between the first and second fins F1 and F2 and the field insulating film 110. Referring to FIG. Specifically, the second field insulating films 105 and 205 may cover the upper surface of the substrate 101 and the sidewalls of the first and second pins F1 and F2. The second field insulating films 105 and 205 may be conformally formed along the sidewalls of the upper surface and the first and second fins F1 and F2.

Next, with reference to Figs. 22 to 24, a semiconductor device according to some embodiments of the present invention will be described.

22 to 24 are a perspective view and a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention. 22 is a perspective view of the semiconductor device according to the present embodiment. FIG. 23 is a sectional view taken along line A1-A1 and B1-B1 in FIG. 22, and FIG. 24 is a sectional view taken along line C1-C1 and D1-D1 in FIG.

The semiconductor device according to the present embodiment is substantially the same as the semiconductor device described above with reference to Figs. 18 to 20 except that each of the first and second gate stacks further includes a first TiN film and a second TiN film. Do. Accordingly, like reference numerals refer to like elements, and repeated descriptions may be omitted.

18 to 20, the substrate 101 may include first and second regions I and II, and each of the first and second regions I and II may include first and second regions I and II, 2 transistors TR1 and TR2 may be formed.

The first and second transistors TR1 and TR2 are connected to the first and second source and drain regions 123 and 223 and the first and second spacers 121 and 221 and the first and second interface films 141 and 142, 241, first and second dielectric layers 143, 243, and first and second gate stacks 170, 270.

The first transistor TR1 includes a first source-drain region 123, a first spacer 121, a first interface film 141, a first dielectric layer 143, and a first gate stack 170 . Here, the first gate stack 170 may include a first TiN film 157, a first TiAlC film 151, a second barrier film 153, and a first metal layer 155.

The second transistor TR2 includes a second source-drain region 223, a second spacer 221, a second interface film 241, a second dielectric layer 243 and a second gate stack 260 . Here, the second gate stack 260 includes a second lanthanum film 245, a second TiN film 257, a second TiAlC film 251, a second barrier film 253, and a second metal layer 255 .

In this embodiment, each of the first and second transistors TR1 and TR2 may include a first TiN film 157 and a second TiN film 257 through which the first and second transistors TR1 and TR2 TR1 and TR2, respectively. In the present embodiment, the first TiN film 157 and the second TiN film 257 may include TiN and may have different thicknesses.

Next, a semiconductor device according to some embodiments of the present invention will be described with reference to FIG.

25 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

The semiconductor device according to the present embodiment may include the first to fourth regions I to IV. Each of the first to fourth regions I to IV may include first to fourth transistors T1, T2, T3, and T4.

The first transistor T1 is substantially the same as the first transistor TR1 described with reference to FIG. 1 and the second transistor T2 is substantially the same as the second transistor TR2 described with reference to FIG. Accordingly, like reference numerals refer to like elements, and repeated descriptions may be omitted.

The third transistor T3 is substantially the same as the first transistor TR1 described with reference to FIG. 23, and the fourth transistor T4 is substantially the same as the second transistor TR2 described with reference to FIG.

More specifically, the third transistor T3 includes a third source-drain region 323, a third spacer 321, a third interface film 341, a third dielectric layer 343, and a third gate stack 370, And the third gate stack 370 may include a third TiN film 357, a third TiAlC film 351, a third barrier film 353, and a third metal layer 355.

Here, the third source-drain region 323, the third spacer 321, the third interface film 341, the third dielectric layer 343 and the third gate stack 370, the third TiN film 357, Each of the third TiAlC film 351, the third barrier film 353 and the third metal layer 355 includes a first source-drain region 123 included in the first transistor TR1 in FIG. 23, The first TiN film 157, the first TiAlC film 151, the first barrier film 153, the first dielectric film 121, the first interface film 141, the first dielectric film 143 and the first gate stack 170, And the first metal layer 155, as shown in FIG.

The fourth transistor T4 includes a fourth source-drain region 423, a fourth spacer 421, a fourth interface film 441, a fourth dielectric layer 443, a fourth lanthanum oxide film 445, And a fourth gate stack 460. The fourth gate stack 460 may include a fourth TiN film 457, a fourth TiAlC film 451, a fourth barrier film 453 and a fourth metal layer 455).

Here, the fourth source-drain region 423, the fourth spacer 421, the fourth interface film 441, the fourth dielectric layer 443, the fourth gate stack 460, the fourth TiN film 457, The fourth TiAlC film 451, the fourth barrier film 453, the fourth metal layer 455 and the fourth lanthanum oxide film 445 are formed by the second source-drain A second dielectric film 243, a second gate stack 260, a second TiN film 257, a second TiAlC film 251, The second barrier layer 253, the second metal layer 255, and the second lanthanum oxide layer 245, as shown in FIG.

In the present embodiment, each of the first to fourth transistors T1 to T4 may have different threshold voltages. Specifically, the second and fourth transistors T2 and T4 include second and fourth lanthanum oxide films 245 and 445 including LaO, and the first and third transistors T1 and T3 include LaO do not include. Furthermore, the third and fourth transistors T3 and T4 include a third TiN film 357 and a fourth TiN film 457, respectively, including TiN. In addition, the first and second transistors T1 and T2 do not include a configuration corresponding to the third TiN film 357 and the fourth TiN film 457. [ On the other hand, each of the first to fourth transistors T1 to T4 includes TaN.

That is, in this embodiment, each of the first to fourth transistors T1 to T4 does not include TaN, and some of the transistors include LaO and the remaining transistors do not include LaO, Can be different. Meanwhile, in the present embodiment, each of the first to fourth transistors T1 to T4 may be an N-type transistor, but is not limited thereto.

Each of the first to fourth transistors T1 to T4 is an N-type transistor in which the second transistor T2, the first transistor T1, the fourth transistor T4 and the third transistor T3, But is not limited thereto.

Next, referring to FIG. 26, a semiconductor device according to some embodiments of the present invention will be described.

26 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. The semiconductor device according to this embodiment is substantially the same as the semiconductor device described above with reference to FIG. 25 except that it further includes first and second TiN films 157 and 257. Accordingly, like reference numerals refer to like elements, and repeated descriptions may be omitted.

Referring to FIG. 26, the first transistor T1 may further include a first TiN film 157, and the second transistor T2 may further include a second TiN film 257. Referring to FIG. Each of the first to fourth TiN films 157, 257, 357, and 457 may have different thicknesses. Although the first, second and fourth TiN films 157, 257 and 457 are illustrated as having a multilayer structure, the first, second and fourth TiN films 157, 257 and 457 are not limited thereto. May be formed as a single layer.

In the present embodiment, each of the first to fourth transistors T1 to T4 may have different threshold voltages. Specifically, the second and fourth transistors T2 and T4 include second and fourth lanthanum oxide films 245 and 445 including LaO, and the first and third transistors T1 and T3 include LaO do not include. On the other hand, each of the first to fourth transistors T1 to T4 includes TaN.

That is, in this embodiment, each of the first to fourth transistors T1 to T4 does not include TaN, and some of the transistors include LaO and the remaining transistors do not include LaO, Can be different. Meanwhile, in the present embodiment, each of the first to fourth transistors T1 to T4 may be a P-type transistor, but is not limited thereto.

Each of the first to fourth transistors T1 to T4 is a P-type transistor in which the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4, But is not limited thereto.

Figure 27 is a block diagram of an electronic system including a semiconductor device in accordance with some embodiments of the present invention.

27, an electronic system 11000 according to an embodiment of the present invention includes a controller 11100, an input / output (I / O) device 11200, a memory device 11300, an interface 11400, 11500, bus). The controller 11100, the input / output device 11200, the storage device 11300, and / or the interface 11400 may be coupled to each other via the bus 11500. [ Bus 11500 corresponds to a path through which data is moved.

The controller 11100 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 11200 may include a keypad, a keyboard, a display device, and the like. The storage device 11300 may store data and / or instructions and the like. The interface 11400 may perform functions to transmit data to or receive data from the communication network. Interface 11400 may be in wired or wireless form. For example, the interface 11400 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 11000 is an operation memory for improving the operation of the controller 11100, and may further include a high-speed DRAM and / or an SRAM. The semiconductor devices 1-11 according to some embodiments of the present invention may be provided in the storage device 11300 or may be provided as a part of the controller 11100, the input / output device 11200, the I / O device, and the like.

The electronic system 11000 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a smart phone, a mobile phone, ), A digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

28 is an exemplary semiconductor system to which a semiconductor device according to some embodiments of the present invention may be applied. 2 shows a tablet PC. The semiconductor device manufactured according to some embodiments of the present invention can be used for a tablet PC, a notebook computer, and the like. It will be apparent to those skilled in the art that semiconductor devices fabricated in accordance with some embodiments of the present invention may be applied to other integrated circuit devices not illustrated.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

110: substrate 130: interlayer insulating film
123, 223, 323, 423: source / drain regions
121, 221, 321, 421: spacers
135, 235, 335, 435: trenches 141, 241, 341, 441:
143, 243, 343, 443: Dielectric layer 170, 270, 370, 470: Gate stack

Claims (10)

A substrate comprising a first region and a second region;
First and second dielectric layers formed on the substrate of the first and second regions, respectively; And
And first and second gate stacks formed on the first and second dielectric layers, respectively,
Wherein the first gate stack comprises a first TiAlC film in contact with the first dielectric layer, a first barrier layer and a first metal layer sequentially deposited on the first TiAlC layer,
Wherein the second gate stack comprises a second lanthanum oxide (LaO) film in contact with the second dielectric film, a second TiAlC film, a second barrier film and a second metal layer sequentially deposited on the second lanthanum oxide film A semiconductor device. The method according to claim 1,
And the second TiAlC film is in contact with the second lanthanum oxide film. 3. The method of claim 2,
Wherein said first and second gate stacks comprise tantalum nitride (TaN). 3. The method of claim 2,
Wherein the substrate further comprises a third region and a fourth region,
Third and fourth dielectric layers respectively formed on the substrate of the third region and the fourth region; And
Further comprising third and fourth gate stacks formed on the third and fourth dielectric layers, respectively,
The third gate stack includes a third TiN film, a third TiAlC film, a third barrier film, and a third metal layer sequentially deposited on the third dielectric layer,
Wherein the fourth gate stack comprises a fourth lanthanum film, a fourth TiN film, a fourth TiAlC film, a fourth barrier film, and a fourth metal layer sequentially deposited on the fourth dielectric layer. 5. The method of claim 4,
Wherein the first through fourth gate stacks form first through fourth transistors, respectively, and the threshold voltages of the first through fourth transistors are different from each other. 6. The method of claim 5,
And the first to fourth transistors are N-type transistors. 5. The method of claim 4,
Wherein the third TiN film and the fourth TiN film have different thicknesses. The method according to claim 1,
And first and second interface films respectively formed between the substrate and the first and second dielectric films. The method according to claim 1,
Wherein each of the first and second dielectric layers extends upwardly along lower and sidewalls of the first and second gate stacks. A substrate comprising first to fourth regions;
First to fourth dielectric layers formed on the substrate of the first to fourth regions, respectively; And
And first to fourth gate stacks formed on the first to fourth dielectric layers, respectively,
Wherein the first gate stack comprises a first TiAlC film sequentially deposited on the first dielectric layer, a first barrier layer and a first metal layer,
Wherein the second gate stack comprises a second lanthanum oxide (LaO) film, a second TiAlC film, a second barrier film and a second metal layer sequentially deposited on the second dielectric layer,
The third gate stack includes a third TiN film, a third TiAlC film, a third barrier film, and a third metal layer sequentially deposited on the third dielectric layer,
Wherein the fourth gate stack comprises a fourth lanthanum film, a fourth TiN film, a fourth TiAlC film, a fourth barrier film, and a fourth metal layer sequentially deposited on the fourth dielectric layer,
And the second TiAlC film is in contact with the second lanthanum oxide film.

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