KR102382555B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. A semiconductor device includes a substrate including a first region and a second region, first and second dielectric films respectively formed on the substrate in the first region and the second region, and formed on the first and second dielectric films, respectively and a first and second gate stacks, the first gate stack comprising a first TiAlC film in contact with the first dielectric film, a first barrier film and a first metal layer sequentially stacked on the first TiAlC film; wherein the second gate stack includes a second lanthanum oxide (LaO) film in contact with the second dielectric film, a second TiAlC film, a second barrier film, and a second metal layer sequentially stacked on the second lanthanum oxide film includes..

Description

semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device.

The semiconductor device may include transistors having different threshold voltages. Examples of the transistors having different threshold voltages include a combination of a logic transistor and a static random access memory (SRAM) or dynamic random access memory (DRAM) transistor.

On the other hand, various methods for adjusting the threshold voltage of transistors included in the semiconductor device are being studied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which threshold voltages of a plurality of transistors are adjusted.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above technical problem, a semiconductor device according to some embodiments of the present invention includes: a substrate including a first region and a second region; first and second dielectric layers respectively formed on the substrate in the first region and the second region; and first and second gate stacks respectively formed on the first and second dielectric layers, wherein the first gate stack includes a first TiAlC layer in contact with the first dielectric layer and on the first TiAlC layer a first barrier layer and a first metal layer sequentially stacked, wherein the second gate stack includes a second lanthanum oxide (LaO) layer in contact with the second dielectric layer and a second lanthanum oxide (LaO) layer sequentially stacked on the second lanthanum oxide layer 2 may include a TiAlC layer, a second barrier layer, and a second metal layer.

In some embodiments of the present invention, the second TiAlC layer may be in contact with the second lanthanum oxide layer.

In some embodiments of the present invention, the first and second gate stacks may not include tantalum nitride (TaN).

In some embodiments of the present invention, the substrate further includes a third region and a fourth region, and the third and fourth dielectric layers are respectively formed on the substrate in the third region and the fourth region; and third and fourth gate stacks respectively formed on the third and fourth dielectric layers, wherein the third gate stack includes a third TiN layer and a third TiAlC layer sequentially stacked on the third dielectric layer; a third barrier layer and a third metal layer, wherein the fourth gate stack includes a fourth lanthanum oxide layer, a fourth TiN layer, a fourth TiAlC layer, a fourth barrier layer, and a fourth sequentially stacked on the fourth dielectric layer It may include a metal layer.

In some embodiments of the present invention, the first to fourth gate stacks may form first to fourth transistors, respectively, and threshold voltages of the first to fourth transistors may be different from each other.

In some embodiments of the present invention, the first to fourth transistors may be N-type transistors.

In some embodiments of the present invention, the third TiN layer and the fourth TiN layer may have different thicknesses.

In some embodiments of the present invention, first and second interface layers respectively formed between the substrate and the first and second dielectric layers may be further included.

In some embodiments of the present invention, each of the first and second dielectric layers may extend upwardly along lower surfaces and sidewalls of the first and second gate stacks.

In order to solve the above technical problem, a semiconductor device according to some embodiments of the present invention includes: a substrate including first to fourth regions; first to fourth dielectric layers respectively formed on the substrate in the first to fourth regions; and first to fourth gate stacks respectively formed on the first to fourth dielectric layers, wherein the first gate stack includes a first TiAlC layer, a first barrier layer and a second layer sequentially stacked on the first dielectric layer. 1 , the second gate stack includes a second lanthanum oxide (LaO) layer, a second TiAlC layer, a second barrier layer, and a second metal layer sequentially stacked on the second dielectric layer, and the third The gate stack includes a third TiN layer, a third TiAlC layer, a third barrier layer, and a third metal layer sequentially stacked on the third dielectric layer, and the fourth gate stack is a fourth gate stack sequentially stacked on the fourth dielectric layer. 4 lanthanum oxide layer, a fourth TiN layer, a fourth TiAlC layer, a fourth barrier layer, and a fourth metal layer, wherein the second TiAlC layer may be in contact with the second lanthanum oxide layer.

In some embodiments of the present invention, the first to fourth gate stacks may not include tantalum nitride (TaN).

In some embodiments of the present invention, the first to fourth gate stacks may form first to fourth transistors, respectively, and threshold voltages of the first to fourth transistors may be different from each other.

In some embodiments of the present invention, the first to fourth transistors may be N-type transistors.

In some embodiments of the present invention, the third TiN layer and the fourth TiN layer may have different thicknesses.

In some embodiments of the present invention, each of the first to fourth dielectric layers may extend upwardly along lower surfaces and sidewalls of the first to fourth gate stacks.

Other specific details of the invention are included in the detailed description and drawings.

1 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
2 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
3 to 20 are perspective and cross-sectional views illustrating a method of manufacturing a semiconductor device according to some embodiments of the present invention.
21 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
22 to 24 are perspective views and cross-sectional views illustrating semiconductor devices according to some embodiments.
25 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
26 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
27 is a block diagram of an electronic system including a semiconductor device manufactured in accordance with some embodiments of the present invention.
28 is an exemplary semiconductor system to which a semiconductor device manufactured according to some embodiments of the present disclosure may be applied.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When one element is referred to as “connected to” or “coupled to” with another element, it means that it is directly connected or coupled to another element, or with the other element intervening. including all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that another element is not interposed therebetween. Like reference numerals refer to like elements throughout. “and/or” includes each and every combination of one or more of the recited items.

It should be understood that although first, second, etc. are used to describe various elements, components, and/or sections, these elements, components, and/or sections are not limited by these terms. These terms are only used to distinguish one element, component, or sections from another. Accordingly, it goes without saying that the first element, the first element, or the first section mentioned below may be the second element, the second element, or the second section within the spirit of the present invention.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and/or "comprising" refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

In the drawings of semiconductor devices according to some embodiments of the present invention, for example, a fin-type transistor (FinFET) including a channel region having a fin-type pattern shape is illustrated, but the present invention is not limited thereto. Of course, the semiconductor device according to some embodiments of the present invention may include a tunneling transistor (FET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. . In addition, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), or the like.

Next, semiconductor devices according to some exemplary embodiments will be described with reference to FIG. 1 .

1 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 1 , a substrate 101 of a semiconductor device according to the present exemplary embodiment includes first and second regions I and II. The first region (I) and the second region (II) may be connected to each other or may be separated from each other.

A first fin F1 , a first dielectric layer 143 , and a first gate stack 170 may be formed in the first region I, and the second region II includes a second fin F2 and a second A dielectric layer 243 and a second gate stack 270 may be formed.

Here, the substrate 101 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 101 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead tellurium, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. .

Alternatively, the substrate 101 may have an epitaxial layer formed on the base substrate. When the active fin is formed using the epitaxial layer formed on the base substrate, the epitaxial layer may include silicon or germanium, which is an elemental semiconductor material. Also, the epitaxial layer may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Specifically, taking the group IV-IV compound semiconductor as an example, the epitaxial layer is a binary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn); It may be a ternary compound or a compound doped with a group IV element. Taking a group III-V compound semiconductor as an example, the epitaxial layer includes at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element, and phosphorus (P), arsenic (As) and anti It may be one of a binary compound, a ternary compound, or a quaternary compound formed by combining one of monium (Sb).

In the present exemplary embodiment, first and second transistors TR1 and TR2 may be respectively formed in the first and second regions I and II of the substrate 101 . Although not shown, the first and second transistors TR1 and TR2 may be separated from each other by an isolation layer formed in the substrate 101 . The device isolation layer may be, for example, shallow trench isolation (STI) or deep trench isolation (DTI).

The first and second transistors TR1 and TR2 include first and second source-drain regions 123 and 223 , first and second spacers 121 and 221 , and first and second interface layers 141 , respectively. 241 , first and second dielectric layers 143 and 243 , and first and second gate stacks 170 and 270 .

Specifically, the first transistor TR1 formed in the first region I of the substrate 101 includes a first source-drain region 123 , a first spacer 121 , a first interface layer 141 , and a first transistor TR1 . It may include a first dielectric layer 143 and a first gate stack 170 . Here, the first gate stack 170 may include a first TiAlC layer 151 , a second barrier layer 153 , and a first metal layer 155 .

In addition, the second transistor TR2 formed in the second region II of the substrate 101 includes a second source-drain region 223 , a second spacer 221 , a second interface layer 241 , and a second It may include a dielectric layer 243 and a second gate stack 260 . Here, the second gate stack 260 may include a second TiAlC layer 251 , a second barrier layer 253 , and a second metal layer 255 .

The first and second source-drain regions 123 and 223 may be formed by implanting a predetermined impurity into the substrate 101 as illustrated. When the first and second transistors TR1 and TR2 according to the present exemplary embodiment are NMOS transistors, n-type impurities may be implanted into the first and second source-drain regions 123 and 223 .

Meanwhile, the first and second source-drain regions 123 and 223 may be formed in an elevated shape as shown. In this case, the first and second source-drain regions 123 and 223 may be formed in the form of an epitaxial layer in a trench formed in the substrate 101 . However, the shape of each of the first and second source-drain regions 123 and 223 is not limited to the illustrated one.

The interlayer insulating layer 130 may include a first trench 135 and a second trench 235 respectively formed in the first and second regions I and II of the substrate 101 . In addition, first and second spacers 121 and 221 may be disposed on both sides of each of the first trench 135 and the second trench 235 as shown.

Each of the first and second spacers 121 and 221 may be, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and combinations thereof. may contain one.

Although each of the first and second spacers 121 and 221 is illustrated as being a single layer, it is only for convenience of description and is not limited thereto. When the first and second spacers 121 and 221 are a plurality of films, at least one of the films included in each of the first and second spacers 121 and 221 may be formed of a low-k material such as silicon oxycarbonitride (SiOCN). may include

Also, when the first and second spacers 121 and 221 are a plurality of layers, at least one of the layers included in each of the first and second spacers 121 and 221 may have an L-shape. .

In some cases, the first and second spacers 121 and 221 may serve as guides for forming a self-aligned contact. Accordingly, the first and second spacers 121 and 221 may include a material having an etch selectivity with respect to the interlayer insulating layer 130 .

In the first and second trenches 135 and 235 formed in each of the first and second regions I and II of the substrate 101 , the first and second interface layers 141 and 241 , the second First and second dielectric layers 143 and 243 and first and second gate stacks 170 and 270 may be sequentially formed.

The first and second interface layers 141 and 241 may serve to prevent a defective interface between the substrate 101 and the first and second dielectric layers 143 and 243 . The first and second interface layers 141 and 241 are formed of a low-k material layer having a dielectric constant k of 9 or less, for example, a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k depending on the content of oxygen atoms and nitrogen atoms). may include about 4 to 8). Alternatively, each of the first and second interface layers 141 and 241 may be made of silicate, or a combination of the aforementioned layers.

The first and second dielectric layers 143 and 243 may be formed of a material having a high dielectric constant. In some embodiments of the present invention, the first and second dielectric layers 143 and 243 may be made of, for example, HfO2, Al2O3, ZrO2, TaO2, etc., but the present invention is not limited thereto.

Referring back to FIG. 1 , each of the first and second dielectric layers 143 and 243 moves along sidewalls of the first and second spacers 121 and 221 in a first direction (eg, in the vertical direction of FIG. 1 ). It may be arranged in an extended shape. In this embodiment, the shape of the first and second dielectric layers 143 and 243 is such that the first and second dielectric layers 143 and 243 are subjected to a replacement process (or gate last process). This may be because it was formed through process)).

However, the present invention is not limited thereto, and the shapes of the first and second dielectric layers 143 and 243 may be modified into other shapes. That is, in some other embodiments of the present invention, the shapes of the first and second dielectric layers 143 and 243 are different from those shown in FIG. 1 by using a gate first process, so that the first and second spacers are different from those shown in FIG. 1 . It may not extend upward along the sidewalls of (121, 221).

Referring back to FIG. 1 , the first and second gate metals 170 and 270 on the first and second dielectric layers 143 and 243 of the first and second regions I and II of the substrate 101 , respectively. can be formed.

Specifically, the first gate metal 150 may include a first TiAlC film 151 , a first barrier film 153 , and a first metal layer 155 sequentially formed on the first dielectric film 143 , The second gate metal 250 includes a second lanthanum oxide film 245 , a second TiAlC film 251 , a second barrier film 253 , and a second metal layer 255 sequentially formed on the second dielectric film 243 . may include

The first and second TiAlC layers 151 and 251 may include TiAlC. The first and second barrier layers 153 and 253 may include, for example, TiN, and the material included in the first and second metal layers 155 and 255 is the first and second TiAlC layers 151 , 251) can be prevented from spreading. The first and second metal layers 155 and 255 may include Al, W, or the like, and fill the remaining portions of the first and second trenches 135 and 235 in the first and second regions I and II. can

Meanwhile, the second region (II) may include a second lanthanum oxide layer 245, unlike the first region (I). The second lanthanum oxide layer 245 may include, for example, LaO. Accordingly, the first transistor TR1 formed in the first region I and the second transistor TR2 formed in the second region II may have different threshold voltages. More specifically, the threshold voltage Vt2 of the second transistor TR2 including the second lanthanum oxide layer 245 may be smaller than the threshold voltage Vt1 of the first transistor TR1 . However, the present invention is not limited thereto.

The first and second gate stacks 170 and 270 according to the present invention do not include tantalum nitride (TaN) as a work function control material. Accordingly, each of the threshold voltages Vt1 and Vt2 of the first and second transistors TR1 and TR2 may be controlled through the presence or absence of the second lanthanum oxide layer 245 .

Next, semiconductor devices according to some exemplary embodiments will be described with reference to FIG. 2 .

2 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

The semiconductor device according to the present exemplary embodiment is substantially the same as the semiconductor device described with reference to FIG. 1 , except that a capping layer is included on the gate stack. Accordingly, the same reference numerals refer to the same components, and repeated descriptions may be omitted.

Referring to FIG. 2 , the semiconductor device according to the present exemplary embodiment includes first and second regions I and II. First and second transistors TR1 and TR2 may be respectively formed in the first and second regions I and II of the substrate 101 .

The first and second transistors TR1 and TR2 include first and second source-drain regions 123 and 223 , first and second spacers 121 and 221 , and first and second interface layers 141 , respectively. 241 , first and second dielectric layers 143 and 243 , and first and second gate stacks 170 and 270 .

Also, first and second capping layers 180 and 280 may be disposed on the first and second gate stacks 170 and 270 , respectively. Specifically, the first and second capping layers 180 and 280 may be formed on the first and second gate stacks 170 and 270 , respectively, and may cover the first and second trenches 135 and 235 . The first and second capping layers 180 and 280 may include nitride (eg, at least one of SiN, SiON, and SiCON) or oxide. The first and second capping layers 180 and 280 may block the first and second gate stacks 170 and 270 from the outside to prevent performance change of the first and second gate stacks 170 and 270 . . For example, oxygen atoms may penetrate into the first and second gate stacks 170 and 270 , and in this case, threshold voltages of the first and second gate stacks 170 and 270 may be changed. Accordingly, the first and second capping layers 180 and 280 may be formed to constantly maintain the threshold voltages of the first and second gate stacks 170 and 270 .

Next, a method of manufacturing a semiconductor device according to some exemplary embodiments will be described with reference to FIGS. 3 to 20 .

3 to 20 are perspective and cross-sectional views illustrating a method of manufacturing a semiconductor device according to some embodiments of the present invention. 3 to 6 and 18 are perspective views, and FIGS. 7 to 17, 19 and 20 are cross-sectional views.

Referring to FIG. 3 , a first fin F1 and a second fin F2 are respectively formed on the substrate 101 . A first region (I) and a second region (II) may be defined in the substrate 101 . The first region (I) and the second region (II) may be adjacent to each other or separated from each other.

The first fin F1 may be formed in the first region I, and the second fin F2 may be formed in the second region II. The first and second fins F1 and F2 may protrude in the third direction Z1. The first and second fins F1 and F2 may extend long in the second direction Y1 which is the longitudinal direction, and may have a long side in the second direction Y1 and a short side in the first direction X1 . . However, the present invention is not limited thereto, and for example, the long side direction may be the first direction X1 and the short side direction may be the second direction Y1 .

The first and second fins F1 and F2 may be a part of the substrate 101 and may include an epitaxial layer grown from the substrate 101 . For example, it may include Si or SiGe.

Referring to FIG. 4 , a field insulating layer 110 is formed on the substrate 101 to cover sidewalls of the first and second fins F1 and F2 . The field insulating layer 110 may be formed of a material including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Referring to FIG. 5 , upper portions of the field insulating layer 110 are recessed to expose upper portions of the first and second fins F1 and F2 . The recess process may include a selective etching process.

Meanwhile, a portion of the first and second fins F1 and F2 protruding above the field insulating layer 110 may be formed by an epitaxial process. For example, after forming the field insulating layer 110 , the first and second fins F1 and F2 exposed by the field insulating layer 110 are subjected to an epitaxial process as seeds without a recess process. A portion of the second fins F1 and F2 may be formed.

In addition, doping for adjusting the threshold voltage may be performed on the exposed first and second fins F1 and F2 . For example, the first fin F1 of the first region (I) may be doped with boron (B) as an impurity, and the second fin F2 of the second region (II) may be doped with phosphorus ( P) or arsenic (As) may be used for doping. However, the present invention is not limited thereto, and the first and second fins F1 and F2 may be doped with the same type of impurities.

Next, first and second dummy gate structures 111 and 211 crossing the first and second fins F1 and F2 are formed on the first and second fins F1 and F2, respectively. In FIG. 5 , the first and second dummy gate structures 111 and 211 are shown to intersect the first and second fins F1 and F2 at a right angle, that is, in the first direction X1, but the present invention is not limited thereto. Although not limited thereto, the first and second dummy gate structures 111 and 211 may cross the first and second fins F1 and F2 respectively while forming acute and/or obtuse angles with the first direction X1 . .

The first and second dummy gate structures 111 and 211 may include dummy gate insulating layers 113 and 213 and dummy gate electrodes 115 and 215 , respectively. The dummy gate insulating layers 113 and 213 and the dummy gate electrodes 115 and 215 may be sequentially stacked.

The dummy gate insulating layers 113 and 213 may be conformally formed on top and top surfaces of sidewalls of the first and second fins F1 and F2 exposed without being covered by the field insulating layer 110 . Also, the dummy gate insulating layers 113 and 213 may be disposed between the dummy gate electrodes 115 and 215 and the field insulating layer 110 .

The dummy gate electrodes 115 and 215 may be formed on the dummy gate insulating layers 113 and 213 .

For example, the dummy gate electrodes 115 and 215 may include silicon oxide, and the dummy gate insulating layers 113 and 213 may include polysilicon.

Each of the dummy hard mask layers 117 and 217 may be formed on the first and second dummy gate structures 111 and 211 . The dummy hard mask layers 117 and 217 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

6 and 7 , which is a cross-sectional view taken along lines A-A and B-B of FIGS. 6 and 6 , spacers 121 and 221 are formed on both sidewalls of the first and second dummy gate structures 111 and 211 . 7 is a cross-sectional view taken along lines A-A and B-B of FIG. 6 .

The spacers 121 and 221 may expose top surfaces of the hard mask layers 117 and 217 . The spacers 121 and 221 may be silicon nitride or silicon oxynitride.

Next, the first and second fins F1 and F2 exposed without covering the first and second dummy gate structures 111 and 211 are etched. The first and second fins F1 and F2 may be etched using the spacers 121 and 221 and the first and second dummy gate structures 111 and 211 as etch masks.

Next, first and second source/drain regions 123 and 223 are formed in the etched portions of the first and second fins F1 and F2 . A first source/drain region 123 may be formed in the first fin F1 and a second source/drain region 223 may be formed in the second fin F2 . The first and second source/drain regions 123 and 223 may be elevated source/drain regions. Accordingly, as shown in FIG. 20 , upper surfaces of the first and second source/drain regions 123 and 223 may be higher than upper surfaces of the first and second fins F1 and F2 .

The first source/drain region 123 and/or the second source/drain region 223 may include a tensile stress material. The first source/drain region 123 and/or the second source/drain region 223 may be formed of the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 is made of Si, the first source/drain region 123 and/or the second source/drain region 223 may be Si or a material having a smaller lattice constant than Si (eg, SiC, SiP).

However, the present invention is not limited thereto, and the first source/drain region 123 and/or the second source/drain region 223 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, for example, SiGe. The first and second source/drain regions 123 and 223 may be formed by epitaxial growth.

Meanwhile, although the first and second source/drain regions 123 and 223 are illustrated as having a pentagonal shape in FIG. 6 , the present invention is not limited thereto. For example, the first and second source/drain regions 123 and 223 are not limited thereto. 223) may have a shape such as a rectangle, a circle, or a hexagon.

Referring to FIG. 8 , an interlayer insulating layer 130 covering the first and second source/drain regions 123 and 223 is formed. The interlayer insulating layer 130 may cover sidewalls of the spacers 121 and 221 , and expose top surfaces of the hard mask layers 117 and 217 . The interlayer insulating layer 130 may include, for example, silicon oxide.

Referring to FIG. 9 , first and second trenches 135 and 235 exposing upper portions of the first and second fins F1 and F2 are formed. First, the hard mask layers 117 and 217 are removed. The hard mask layers 117 and 217 may be removed through a planarization process or the like, and when the planarization process is performed, the interlayer insulating layer 130 may also be partially etched.

Next, the first and second dummy gate structures 111 and 211 are removed. The first and second fins F1 and F2 are exposed by removing the dummy gate electrodes 115 and 215 and the dummy gate insulating layers 113 and 213 . The first trench 135 is formed at the site of the first dummy gate structure 111 , and the second trench 235 is formed at the site of the second dummy gate structure 211 . Sidewalls of the spacers 121 and 221 may be exposed by the first and second trenches 135 and 235 .

Referring to FIG. 10 , first and second interface layers 141 and 241 are formed in the first and second trenches 135 and 235 . The first and second interface layers 141 and 241 may be formed along top surfaces of the first and second fins F1 and F2 and upper portions of sidewalls.

The first and second interface layers 141 and 241 may be formed by oxidizing the exposed first and second fins F1 and F2 in the first and second trenches 135 and 235 , but are not limited thereto. . The first and second interface layers 141 and 241 may be formed along bottom surfaces of the first and second trenches 135 and 235 , respectively.

Next, a first dielectric layer 143a is formed in the first trench 135 and a second dielectric layer 243a is formed in the second trench 235 . Specifically, the first dielectric layer 143a may be conformally formed along the sidewall and the bottom surface of the first trench 135 , and the field insulating layer 110 and the first dielectric layer 143a may be conformally formed along the sidewall top and top surface of the first fin F1 . It can be foamed. The second dielectric layer 243a may be conformally formed along the sidewall and bottom surface of the second trench 235 , and conformally along the field insulating layer 210 and the sidewall top and top surface of the second fin F2 . can be formed. Also, the first and second dielectric layers 143a and 243a may be formed on the interlayer insulating layer 130 .

The first and second dielectric layers 143a and 243a may include a high dielectric material having a higher dielectric constant than that of the silicon oxide layer. For example, the first and second dielectric layers 143a and 243a may be selected from the group consisting of HfSiON, HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ or (Ba,Sr)TiO ₃ , and the like. material may be included. The first and second dielectric layers 143a and 243a may be formed to have an appropriate thickness according to the type of device to be formed.

Referring to FIG. 11 , a first lanthanum oxide film 145a is formed in the first trench 135 , and a second lanthanum oxide film 245a is formed in the second trench 235 . The first and second lanthanum oxide films 145a and 245a may be conformally formed along sidewalls and bottom surfaces of the first and second trenches 145 and 245 , respectively. In addition, the first and second fins F1 and F2 may be formed along the upper sidewalls and upper surfaces of the first and second fins F1 and F2 . The first and second lanthanum oxide layers 145a and 245a may include, for example, LaO, but are not limited thereto.

Referring to FIG. 12 , the first lanthanum oxide layer 145a of the first region I is removed through the first mask pattern 1001 . Specifically, a first mask pattern 1001 may be formed by forming a mask layer covering the first and second regions I and II, and patterning the mask layer. Subsequently, the first lanthanum oxide layer 145a of the first region (I) may be removed through an etching process using the first mask pattern 1001 as an etching mask. Accordingly, the first dielectric layer 143a may be exposed.

Referring to FIG. 13 , first and second diffusion films 147 and 247 and first and second blocking films 149 and 249 are sequentially formed. A first diffusion layer 147 is formed in the first trench 135 , and a second diffusion layer 247 is formed in the second trench 235 . The first and second diffusion layers 147 and 247 may be conformally formed along sidewalls and bottom surfaces of the first and second trenches 135 and 235, respectively. In addition, the first and second fins F1 and F2 may be formed along the upper sidewalls and upper surfaces of the first and second fins F1 and F2 . The first and second diffusion layers 147 and 247 may include, for example, TiN, but are not limited thereto.

Next, first and second blocking layers 149 and 249 are formed on the first and second diffusion layers 147 and 247 . The first and second blocking layers 149 and 249 may fill the first and second trenches 135 and 235, respectively, and cover the first and second diffusion layers 147 and 247 so as not to be exposed to the outside. . The first and second blocking layers 149 and 249 may include, for example, Si.

Then, annealing 150 is performed. The first and second dielectric layers 143a and 243a include oxygen atoms. Oxygen atoms are bonded to other materials (eg, Hf, Zr, Ta, Ti, etc.) in the first and second dielectric layers 143a and 243a, and some bonds may be broken. If the coupling is broken, leakage current or the like may occur, which may deteriorate the performance of the transistor. In order to prevent such a problem, annealing 150 is performed to bond oxygen atoms to the portion where the bond is broken. When the annealing 150 is performed, oxygen atoms included in the first diffusion layer 147 may be provided to the first dielectric layer 143a. In addition, oxygen atoms included in the second diffusion layer 247 and/or the second lanthanum oxide layer 245a may be provided to the second dielectric layer 243a.

On the other hand, if the first and second diffusion films 147 and 247 are exposed when the annealing 150 is performed, external oxygen atoms penetrate the first and second diffusion films 147 and 247 during the annealing 150 . Accordingly, the number of oxygen atoms moving to the lower portions of the first and second diffusion layers 147 and 247 increases. When oxygen atoms are supplied in excess of the number of oxygen atoms required for the first and second dielectric layers 143a and 243a, the excess oxygen atoms are released into the first and second fins (135, 235) in the first and second trenches (135, 235). It can react with F1, F2). Accordingly, the thickness of the first and second interface layers 141 and 241 is increased, and the performance of the transistor may be deteriorated. Accordingly, the first and second blocking films 149 and 249 are formed on the first and second diffusion films 147 and 247 to separate the first and second diffusion films 147 and 247 from the outside during annealing 150 . By blocking, the supply amount of oxygen atoms can be appropriately controlled.

Annealing 150 may be performed at a temperature of 500 °C to 1500 °C.

The thickness of the first and second diffusion layers 147 and 247 may vary depending on the number of oxygen atoms to be supplied.

Referring to FIG. 14 , the first and second blocking layers 149 and 249 and the first and second diffusion layers 147 and 247 are sequentially removed. Accordingly, the first dielectric layer 143a and the second lanthanum oxide layer 245a may be exposed.

Next, referring to FIG. 15 , first and second TiAlC films 151a and 251a are respectively formed on the first dielectric film 143a and the second lanthanum oxide film 245a. The first and second TiAlC layers 151a and 251a may be conformally formed along sidewalls and bottom surfaces of the first and second trenches 135 and 235 , respectively. In addition, the first and second barrier layers 151a and 251a may include, for example, TiAlC.

Next, first and second barrier films 153a and 253a are formed on the first and second TiAlC films 151a and 251a, respectively. Specifically, the first and second barrier layers 153a and 253a may be conformally formed along sidewalls and bottom surfaces of the first and second trenches 130 and 230 , respectively. The first and second barrier layers 153a and 253a may include, for example, TiN. The first and second barrier layers 153a and 253a may prevent materials included in the first and second metal layers 155a and 255a from diffusing into the first and second trenches 130 and 230 .

First and second metal layers 155a and 255a are formed on the first and second barrier layers 153a and 253a, respectively. The first and second metal layers 155a and 255a may fill the remaining portions of the first and second trenches 130 and 230 . The first and second metal layers 155a and 255a may include, for example, Al, W, or the like.

Referring to FIG. 16 , first and second gate structures 170 and 270 are formed. In the result of FIG. 15 , if the planarization process is performed to expose the interlayer insulating layer 130 , the first gate structure 170 may be formed in the first region (I) and the second gate structure in the second region (II) A structure 270 may be formed.

Referring to FIG. 17 , first and second capping layers 180 and 280 are formed on the first and second gate structures 170 and 270 , respectively.

Before forming the first and second capping layers 180 and 280 , the first and second gate structures 170 and 270 may be partially removed to adjust the heights of the first and second gate structures 170 and 270 . can Accordingly, the first and second dielectric films 143 and 243, the first and second barrier films 153 and 253, and the first and second TiAlC films 151 and 251 in the first and second trenches 135 and 235 . ), the first and second metal layers 155 and 255 , and the second lanthanum oxide layer 245 may be partially removed. In this case, the sidewalls of each of the first and second capping layers 180 and 280 may be in contact with the sidewalls of the spacers 121 and 221 . In addition, top surfaces of the first and second capping layers 180 and 280 may be disposed on the same plane as the interlayer insulating layer 130 .

Subsequently, referring to FIGS. 18 to 20 , a first transistor TR1 may be formed in the first region I, and a second transistor TR2 may be formed in the second region II. For reference, FIG. 19 is a cross-sectional view taken along lines A-A and B-B of FIG. 18 , and FIG. 20 is a cross-sectional view taken along line C-C and D-D of FIG. 18 .

Second interlayer insulating layers 132 and 232 are formed on the interlayer insulating layer 130 . The second interlayer insulating layers 132 and 232 may cover the first and second capping layers 180 and 280 . The second interlayer insulating layers 132 and 232 may include the same material as the interlayer insulating layer 130 , for example, silicon oxide.

First and second silicide layers 191 and 291 are respectively formed on the first and second source/drain regions 123 and 223 , and interlayers are formed on the first and second source/drain regions 123 and 223 , respectively. The semiconductor device according to the present exemplary embodiment may be formed by forming the first and second contacts 193 and 293 penetrating the insulating layer 130 and the second interlayer insulating layers 132 and 232 . However, the technical spirit of the present invention is not limited thereto. The first and second silicide layers 191 and 291 may serve to reduce sheet resistance and contact resistance of the first and second source/drain regions 123 and 223 , for example, Pt or Ni. , Co and the like. The first and second contacts 193 and 293 may include, for example, W, Al Cu, or the like.

Next, referring to FIG. 21 , semiconductor devices according to some exemplary embodiments will be described. 21 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention. The semiconductor device according to the present embodiment may correspond to FIG. 20 of the above-described semiconductor device. Accordingly, the semiconductor device according to this embodiment is substantially the same as the embodiment of FIG. 21 except that a second field insulating film is further included between the fin and the field insulating film. Accordingly, the same reference numerals refer to the same components, and repeated descriptions may be omitted.

Referring to FIG. 21 , second field insulating layers 105 and 205 may be further included between the first and second fins F1 and F2 and the field insulating layer 110 . Specifically, the second field insulating layers 105 and 205 may cover the top surface of the substrate 101 and sidewalls of the first and second fins F1 and F2 . The second field insulating layers 105 and 205 may be conformally formed along the top surface and sidewalls of the first and second fins F1 and F2 .

Next, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 22 to 24 .

22 to 24 are perspective and cross-sectional views illustrating semiconductor devices according to some embodiments of the present disclosure. 22 is a perspective view of a semiconductor device according to the present embodiment. 23 is a cross-sectional view taken along lines A1-A1 and B1-B1 of FIG. 22 , and FIG. 24 is a cross-sectional view taken along lines C1-C1 and D1-D1 of FIG. 22 .

The semiconductor device according to this embodiment is substantially the same as the semiconductor device described with reference to FIGS. 18 to 20 , except that the first and second gate stacks further include a first TiN layer and a second TiN layer, respectively. Do. Accordingly, the same reference numerals refer to the same components, and repeated descriptions may be omitted.

18 to 20 , the substrate 101 may include first and second regions (I and II) regions, and the first and second regions (I and II) respectively include first and second regions. Two transistors TR1 and TR2 may be formed.

The first and second transistors TR1 and TR2 include first and second source-drain regions 123 and 223 , first and second spacers 121 and 221 , and first and second interface layers 141 , respectively. 241 , first and second dielectric layers 143 and 243 , and first and second gate stacks 170 and 270 .

The first transistor TR1 may include a first source-drain region 123 , a first spacer 121 , a first interface layer 141 , a first dielectric layer 143 , and a first gate stack 170 . can Here, the first gate stack 170 may include a first TiN layer 157 , a first TiAlC layer 151 , a second barrier layer 153 , and a first metal layer 155 .

The second transistor TR2 may include a second source-drain region 223 , a second spacer 221 , a second interface layer 241 , a second dielectric layer 243 , and a second gate stack 260 . can Here, the second gate stack 260 includes a second lanthanum oxide film 245 , a second TiN film 257 , a second TiAlC film 251 , a second barrier film 253 , and a second metal layer 255 . may include

In the present embodiment, each of the first and second transistors TR1 and TR2 may include a first TiN film 157 and a second TiN film 257 , through which the first and second transistors TR1 and TR2 TR1, TR2) each threshold voltage can be controlled. In this embodiment, the first TiN layer 157 and the second TiN layer 257 may include TiN and may have different thicknesses.

Next, semiconductor devices according to some exemplary embodiments will be described with reference to FIG. 25 .

25 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

The semiconductor device according to the present exemplary embodiment may include first to fourth regions I to IV. Each of the first to fourth regions I to IV may include first to fourth transistors T1 , T2 , T3 , and T4 .

The first transistor T1 is substantially the same as the first transistor TR1 described with reference to FIG. 1 , and the second transistor T2 is substantially the same as the second transistor TR2 described with reference to FIG. 1 . Accordingly, the same reference numerals refer to the same components, and repeated descriptions may be omitted.

Also, the third transistor T3 is substantially the same as the first transistor TR1 described with reference to FIG. 23 , and the fourth transistor T4 is substantially the same as the second transistor TR2 described with reference to FIG. 23 .

More specifically, the third transistor T3 includes a third source-drain region 323 , a third spacer 321 , a third interface layer 341 , a third dielectric layer 343 , and a third gate stack 370 . The third gate stack 370 may include a third TiN layer 357 , a third TiAlC layer 351 , a third barrier layer 353 , and a third metal layer 355 .

Here, the third source-drain region 323 , the third spacer 321 , the third interface layer 341 , the third dielectric layer 343 and the third gate stack 370 , the third TiN layer 357 , Each of the third TiAlC layer 351 , the third barrier layer 353 , and the third metal layer 355 includes a first source-drain region 123 and a first spacer included in the first transistor TR1 of FIG. 23 . 121 , a first interface layer 141 , a first dielectric layer 143 , a first gate stack 170 , a first TiN layer 157 , a first TiAlC layer 151 , and a first barrier layer 153 . and substantially corresponding to the first metal layer 155 .

In addition, the fourth transistor T4 includes a fourth source-drain region 423 , a fourth spacer 421 , a fourth interface layer 441 , a fourth dielectric layer 443 , and a fourth lanthanum oxide layer 445 . and a fourth gate stack 460 , wherein the fourth gate stack 460 includes a fourth TiN film 457 , a fourth TiAlC film 451 , a fourth barrier film 453 , and a fourth metal layer ( 455) may be included.

Here, the fourth source-drain region 423 , the fourth spacer 421 , the fourth interface layer 441 , the fourth dielectric layer 443 , the fourth gate stack 460 , the fourth TiN layer 457 , The fourth TiAlC film 451 , the fourth barrier film 453 , the fourth metal layer 455 , and the fourth lanthanum oxide film 445 are included in the second transistor TR2 of FIG. 23 as a second source-drain Region 223 , second spacer 221 , second interface layer 241 , second dielectric layer 243 , second gate stack 260 , second TiN layer 257 , and second TiAlC layer 251 . , the second barrier layer 253 , the second metal layer 255 , and the second lanthanum oxide layer 245 may substantially correspond to each other.

In this embodiment, each of the first to fourth transistors T1 to T4 may have different threshold voltages. Specifically, the second and fourth transistors T2 and T4 include second and fourth lanthanum oxide films 245 and 445 including LaO, and the first and third transistors T1 and T3 include LaO. do not include. Furthermore, the third and fourth transistors T3 and T4 include a third TiN film 357 and a fourth TiN film 457 including TiN, respectively. In addition, the first and second transistors T1 and T2 do not include a configuration corresponding to that of the third TiN layer 357 and the fourth TiN layer 457 . Meanwhile, each of the first to fourth transistors T1 to T4 does not include TaN.

That is, in the present embodiment, each of the first to fourth transistors T1 to T4 does not contain TaN, some transistors contain LaO, and the other transistors do not contain LaO, thereby increasing the threshold voltage. can be different Meanwhile, in the present embodiment, each of the first to fourth transistors T1 to T4 may be an N-type transistor, but is not limited thereto.

When each of the first to fourth transistors T1 to T4 is an N-type transistor, the threshold voltage of the second transistor T2 , the first transistor T1 , the fourth transistor T4 , and the third transistor T3 is sequentially applied. may be large, but is not limited thereto.

Next, referring to FIG. 26 , semiconductor devices according to some exemplary embodiments will be described.

26 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention. The semiconductor device according to the present embodiment is substantially the same as the semiconductor device described with reference to FIG. 25 , except that the first and second TiN layers 157 and 257 are further included. Accordingly, the same reference numerals refer to the same components, and repeated descriptions may be omitted.

Referring to FIG. 26 , the first transistor T1 may further include a first TiN layer 157 , and the second transistor T2 may further include a second TiN layer 257 . Each of the first to fourth TiN layers 157 , 257 , 357 , and 457 may have different thicknesses. Meanwhile, although the first, second and fourth TiN films 157 , 257 , and 457 are illustrated as having a multilayer structure, the present invention is not limited thereto, and the first, second and fourth TiN films 157 , 257 and 457 are not limited thereto. may be formed in one layer.

In this embodiment, each of the first to fourth transistors T1 to T4 may have different threshold voltages. Specifically, the second and fourth transistors T2 and T4 include second and fourth lanthanum oxide films 245 and 445 including LaO, and the first and third transistors T1 and T3 include LaO. do not include. Meanwhile, each of the first to fourth transistors T1 to T4 does not include TaN.

That is, in the present embodiment, each of the first to fourth transistors T1 to T4 does not contain TaN, some transistors contain LaO, and the other transistors do not contain LaO, thereby increasing the threshold voltage. can be different Meanwhile, in the present embodiment, each of the first to fourth transistors T1 to T4 may be a P-type transistor, but is not limited thereto.

When each of the first to fourth transistors T1 to T4 is a P-type transistor, the threshold voltage of the first transistor T1 , the second transistor T2 , the third transistor T3 , and the fourth transistor T4 is sequentially may be large, but is not limited thereto.

27 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the present disclosure;

Referring to FIG. 27 , an electronic system 11000 according to an embodiment of the present invention includes a controller 11100, an input/output device 11200, I/O, a memory device 11300, a memory device, an interface 11400, and a bus ( 11500, bus). The controller 11100 , the input/output device 11200 , the memory device 11300 , and/or the interface 11400 may be coupled to each other through the bus 11500 . The bus 11500 corresponds to a path through which data is moved.

The controller 11100 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing functions similar thereto. The input/output device 11200 may include a keypad, a keyboard, and a display device. The memory device 11300 may store data and/or instructions. The interface 11400 may perform a function of transmitting data to or receiving data from a communication network. The interface 11400 may be in a wired or wireless form. For example, the interface 11400 may include an antenna or a wired/wireless transceiver. Although not shown, the electronic system 11000 may further include a high-speed DRAM and/or SRAM as an operational memory for improving the operation of the controller 11100 . The semiconductor devices 1 to 11 according to some embodiments of the present invention may be provided in the memory device 11300 , or may be provided as a part of the controller 11100 , the input/output device 11200 , I/O, and the like.

The electronic system 11000 includes a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a smart phone, and a mobile phone. ), a digital music player, a memory card, or any electronic product capable of transmitting and/or receiving information in a wireless environment.

28 is an exemplary semiconductor system to which a semiconductor device according to some embodiments of the present invention may be applied. 2 shows a tablet PC. The semiconductor device manufactured according to some embodiments of the present invention may be used in a tablet PC, a notebook computer, and the like. It is apparent to those skilled in the art that the semiconductor device manufactured according to some embodiments of the present invention may also be applied to other integrated circuit devices not illustrated.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

110: substrate 130: interlayer insulating film
123, 223, 323, 423: source/drain area
121, 221, 321, 421: spacers
135, 235, 335, 435: trench 141, 241, 341, 441: interface film
143, 243, 343, 443: dielectric layers 170, 270, 370, 470: gate stack

Claims (10)

a substrate comprising a first region and a second region;
first and second dielectric layers respectively formed on the substrate in the first region and the second region; and
and first and second gate stacks respectively formed on the first and second dielectric layers;
the first gate stack includes a first TiAlC film in contact with the first dielectric film, a first barrier film and a first metal layer sequentially stacked on the first TiAlC film;
The second gate stack includes a second lanthanum oxide (LaO) film in contact with the second dielectric film, and a second TiAlC film, a second barrier film, and a second metal layer sequentially stacked on the second lanthanum oxide film semiconductor device. The method of claim 1,
The second TiAlC film is in contact with the second lanthanum oxide film. 3. The method of claim 2,
The first and second gate stacks do not include tantalum nitride (TaN). 3. The method of claim 2,
The substrate further includes a third region and a fourth region,
third and fourth dielectric layers respectively formed on the substrate in the third region and the fourth region; and
Further comprising third and fourth gate stacks respectively formed on the third and fourth dielectric layers,
the third gate stack includes a third TiN film, a third TiAlC film, a third barrier film, and a third metal layer sequentially stacked on the third dielectric film;
and the fourth gate stack includes a fourth lanthanum oxide film, a fourth TiN film, a fourth TiAlC film, a fourth barrier film, and a fourth metal layer sequentially stacked on the fourth dielectric film. 5. The method of claim 4,
The first to fourth gate stacks form first to fourth transistors, respectively, and threshold voltages of the first to fourth transistors are different from each other. 6. The method of claim 5,
The first to fourth transistors are N-type transistors. 5. The method of claim 4,
The third TiN layer and the fourth TiN layer have different thicknesses. The method of claim 1,
and first and second interface layers respectively formed between the substrate and the first and second dielectric layers. The method of claim 1,
Each of the first and second dielectric layers extends upward along lower surfaces and sidewalls of the first and second gate stacks. a substrate including first to fourth regions;
first to fourth dielectric layers respectively formed on the substrate in the first to fourth regions; and
and first to fourth gate stacks respectively formed on the first to fourth dielectric layers;
the first gate stack includes a first TiAlC film, a first barrier film, and a first metal layer sequentially stacked on the first dielectric film;
the second gate stack includes a second lanthanum oxide (LaO) film, a second TiAlC film, a second barrier film, and a second metal layer sequentially stacked on the second dielectric film;
the third gate stack includes a third TiN film, a third TiAlC film, a third barrier film, and a third metal layer sequentially stacked on the third dielectric film;
wherein the fourth gate stack includes a fourth lanthanum oxide film, a fourth TiN film, a fourth TiAlC film, a fourth barrier film, and a fourth metal layer sequentially stacked on the fourth dielectric film;
The second TiAlC film is in contact with the second lanthanum oxide film.

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