KR102114345B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a pair of source / drain regions and a channel region, a semiconductor layer extending in a first direction, a gate extending over the semiconductor layer to cover the channel region, and a gate interposed between the channel region and the gate It includes a dielectric film. Corner insulating spacers extend along the side walls of the gate. The corner insulating spacer has a first surface covering at least a portion of the sidewall of the gate from one side of the gate dielectric film and a second surface covering a portion of the semiconductor layer. Above the corner insulation spacer, the outer insulation spacer covers the sidewall of the gate. The outer insulating spacer has a dielectric constant smaller than that of the corner insulating spacer.

Description

Semiconductor device {Semiconductor device}

The technical idea of the present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor.

As the miniaturization and high integration of integrated circuit devices are required, to improve characteristics related to operating speed, power dissipation and economic efficiency, in order to improve the overall operation stability of transistors, which are important factors for determining the performance of integrated circuits. Efforts are being made.

A technical problem to be achieved by the technical idea of the present invention is to provide a semiconductor device having a transistor capable of improving operating speed and reducing power consumption by reducing fringing capacitance and parasitic capacitance. will be.

A semiconductor device according to an aspect of the inventive concept includes a pair of source / drain regions and a semiconductor layer extending in a first direction with a channel region extending between the pair of source / drain regions, and A gate extending in a second direction over the semiconductor layer to cover a channel region, a gate dielectric layer interposed between the channel region and the gate, and a gate dielectric layer extending in the second direction along sidewalls of the gate A corner insulating spacer having a first surface covering at least a portion of the sidewall of the gate from a side of the gate and a second surface covering a portion of the semiconductor layer, and covering the sidewall of the gate on the corner insulating spacer, and the corner insulating spacer And an outer insulating spacer having a dielectric constant smaller than that of.

In some embodiments, the sidewall of the gate has a first height, and the first surface of the corner insulating spacer can cover the sidewall of the gate to a second height less than the first height.

In some embodiments, the outer insulating spacer may have a surface facing the sidewall of the gate.

In some embodiments, the outer insulating spacer may have a third height greater than the first height.

In a semiconductor device according to an aspect of the inventive concept, the semiconductor layer may be part of a bulk semiconductor substrate. The corner insulating spacer may extend along a sidewall of the gate at a reentrant corner portion formed between the gate and the pair of source / drain regions.

The semiconductor device according to an aspect of the inventive concept may further include a semiconductor substrate disposed under the gate. In addition, the semiconductor layer may include a semiconductor fin protruding from the semiconductor substrate and extending in a first direction.

In some embodiments, the device isolation layer may further include a device isolation layer that contacts both sidewalls of the semiconductor fin on the semiconductor substrate and has a lower level upper surface than the upper surface of the semiconductor fin. In addition, the gate extends in the second direction on the semiconductor fin and the device isolation layer, and the corner insulation spacer is a concave corner formed between the gate, the semiconductor fin, and the device isolation layer. It may extend from the semiconductor fin along the sidewall of the gate.

The semiconductor device according to an aspect of the inventive concept may further include a substrate disposed under the gate and a buried insulating layer interposed between the substrate and the gate. In addition, the semiconductor layer may have a base portion extending in the first direction on the buried insulating layer and contacting the buried insulating layer.

In some embodiments, the gate extends in the second direction over the semiconductor fin and the buried insulating layer, and the corner insulating spacer is formed between the gate, the semiconductor fin, and the buried insulating layer. A recessed corner may extend from the semiconductor fin along a sidewall of the gate.

In some embodiments, the pair of source / drain regions include a source / drain extension region having a first impurity doping concentration, and a deep source / drain region having a second impurity doping concentration higher than the first doping concentration. In addition, the corner insulating spacer may cover the source / drain extension region by a width smaller than a horizontal separation distance between the gate and the deep source / drain region from the sidewall of the gate.

The corner insulating spacer may have a width in a horizontal direction selected within a range of 1/2 of a horizontal separation distance between the gate and the deep source / drain region from the sidewall of the gate.

A semiconductor device according to another aspect of the inventive concept includes a semiconductor layer having a channel region and extending in a first direction, an insulating layer covering at least a portion of the semiconductor layer, and the semiconductor over the channel region and the insulating layer. A gate extending in a second direction intersecting a layer, a gate dielectric layer interposed between the channel region and the gate, and extending along a sidewall of the gate from the semiconductor layer and covering at least a portion of the sidewall of the gate A corner insulating spacer having a first surface and a second surface covering a portion of the semiconductor layer, and an outer insulating spacer covering the sidewall of the gate on the corner insulating spacer and having a dielectric constant smaller than that of the corner insulating spacer. Includes.

In some embodiments, the corner insulating spacer may have a width smaller than a horizontal separation distance from the sidewall of the gate to the outer wall of the outer insulating spacer along the first direction.

In some embodiments, the corner insulating spacer may have a third surface covering the insulating layer by a width less than a horizontal separation distance from the sidewall of the gate to the outer wall of the outer insulating spacer along the first direction.

The semiconductor device according to the technical concept of the present invention includes a corner insulating spacer made of an insulating material having a relatively high dielectric constant in an inner portion of the insulating spacer region formed on the sidewall of the gate, which has a relatively large effect on the performance of the transistor. Therefore, it is possible to suppress the occurrence of fringing capacitance and improve the "ON" and "OFF" current characteristics of the transistor, and to prevent the performance of the transistor from deteriorating. In addition, the outer portion of the insulating spacer region having a relatively small influence on the performance of the transistor includes an outer insulating spacer made of an insulating material having a small dielectric constant compared to the corner insulating spacer. Therefore, it is possible to reduce parasitic capacitance, improve the operation speed of the transistor, and reduce power consumption.

1 is a cross-sectional view of a semiconductor device according to embodiments of the inventive concept.
2 is a cross-sectional view of a semiconductor device according to embodiments of the inventive concept.
3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence.
4A to 4C are views for explaining a main configuration of a semiconductor device according to embodiments of the inventive concept, FIG. 4A is a partial perspective view of a semiconductor device, and FIG. 4B is 4B-4B 'of FIG. 4A It is a vertical sectional view along the line, and FIG. 4C is a vertical sectional view along the line 4C-4C 'of FIG. 4A.
5A to 5K are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence.
6 is a perspective view illustrating a main configuration of a semiconductor device according to embodiments of the inventive concept.
7A and 7B are views for explaining a main configuration of a semiconductor device according to embodiments of the inventive concept, FIG. 7A is a partial perspective view of a semiconductor device, and FIG. 7B is 7B-7B 'of FIG. 7A It is a vertical section along the line.
8A to 8G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence.
9 is a perspective view illustrating a main configuration of a semiconductor device according to embodiments of the inventive concept.
10 is a plan view of a memory module according to the inventive concept.
11 is a schematic block diagram of a display driver IC (DDI) and a display device including the DDI according to embodiments of the inventive concept.
12 is a circuit diagram of a CMOS inverter according to embodiments of the inventive concept.
13 is a circuit diagram of a CMOS SRAM device according to embodiments of the inventive concept.
14 is a circuit diagram of a CMOS NAND circuit according to embodiments of the inventive concept.
15 is a block diagram illustrating an electronic system according to embodiments of the inventive concept.
16 is a block diagram of an electronic system according to embodiments of the inventive concept.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for them are omitted.

The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, and the scope of the present invention It is not limited to the following embodiments. Rather, these examples are provided to make the present disclosure more faithful and complete and to fully convey the spirit of the present invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various members, regions, layers, parts and / or components, these members, parts, regions, layers, parts and / or components are used in these terms. It is obvious that it should not be limited by. These terms do not imply a specific order, top or bottom, or superiority, and are only used to distinguish one member, region, site, or component from another member, region, site, or component. Accordingly, the first member, region, part or component described below may refer to the second member, region, part or component without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used terms, as defined in the dictionary, should be interpreted as having meanings consistent with what they mean in the context of related technologies, and in excessively formal meanings unless explicitly defined herein. It will be understood that it should not be interpreted.

When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to that described.

In the accompanying drawings, for example, depending on manufacturing techniques and / or tolerances, deformations of the illustrated shapes can be expected. Therefore, the embodiments of the present invention should not be interpreted as being limited to a specific shape of a region shown in the present specification, but should include a change in shape resulting from, for example, a manufacturing process.

1 is a cross-sectional view of a semiconductor device 100A according to embodiments of the inventive concept. 1 illustrates a semiconductor device 100A made of a MOS transistor implemented on a bulk semiconductor substrate 102.

The active region 106 is defined by the device isolation layer 104 on the semiconductor substrate 102. The active region 106 includes a pair of source / drain regions 110 and a channel region 112 extending between the pair of source / drain regions 110.

The semiconductor substrate 102 may include Si (silicon), for example, crystalline Si, polycrystalline Si, or amorphous Si. In some other embodiments, the substrate 102 is a semiconductor such as germanium (Ge), or silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP) ) May include a compound semiconductor.

A gate 120 covering the active region 106 is formed between the pair of source / drain regions 110 on the semiconductor substrate 102. The gate 120 has a sidewall 120S extending from a main surface 102M of the semiconductor substrate 102 to a predetermined height (HAG) along a direction perpendicular to the main surface 102M extending direction (Z direction in FIG. 1). Have In the following description, "height" means the shortest distance extending in a direction perpendicular to the main surface extending direction of the semiconductor substrate 102 (Z direction in FIG. 1), unless otherwise defined.

In some embodiments, the gate 120 may be made of doped polysilicon, metal, conductive metal nitride, metal silicide, alloy, or a combination thereof. For example, the gate 120 may include at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf, or a nitride thereof.

The upper surface of the gate 120 is covered by an insulating capping layer 122. In some embodiments, the insulating capping layer 122 may be formed of a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 124 is interposed between the channel region 112 and the gate 120. In some embodiments, the gate dielectric layer 124 may be formed of a silicon oxide layer or a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer.

A pair of corner insulating spacers 130 extending along side surfaces of the gate 120 and the top surface of the source / drain regions 110 are formed on both sides of the gate 120, respectively.

The pair of corner insulating spacers 130 may be formed of the gate 120 at a reentrant corner portion C1 formed between the gate 120 and the pair of source / drain regions 110. It extends along the sidewall 120S.

The pair of corner insulating spacers 130 may include a first surface (at least partially covering at least a portion of the sidewall 120S of the gate 120 from one side of the gate dielectric layer 124 adjacent to the sidewall 120S of the gate 120). 132), and a second surface 134 covering a portion of the source / drain regions 110 from one side of the gate dielectric layer 124.

The first surface 132 of the pair of corner insulating spacers 130 may directly contact at least a portion of the sidewall 120S of the gate 120. The second surface 134 may directly contact the rest of the pair of source / drain regions 110.

As illustrated in FIG. 1, the first surface 132 of the pair of corner insulating spacers 130 is up to a first height HA1 smaller than the height HAG of the sidewall 120S of the gate 120. The sidewall 120S may be covered. However, the technical spirit of the present invention is not limited to this. For example, the first surface 132 of the pair of corner insulating spacers 130 may vary the sidewalls 120S within a range not exceeding the height (HAG) of the sidewalls 120S of the gate 120. Can be covered with height.

A pair of outer insulating spacers 140 are formed on the pair of corner insulating spacers 130. The pair of outer insulating spacers 140 may extend on the semiconductor substrate 102 to a second height HA2 greater than the first height HA1. In FIG. 1, the second height HA2 of the pair of outer insulating spacers 140 extends to the upper surface of the insulating capping layer 122, but the technical spirit of the present invention is not limited thereto. For example, the second height HA2 of the outer insulating spacer 140 is the height (HAG) of the sidewall 120S of the gate 120, that is, the insulating capping layer 122 from the top surface of the gate 120. It can be appropriately selected within a range reaching the top surface.

The pair of outer insulating spacers 140 may have a surface facing a portion of the sidewalls 120S of the gate 120 that are not covered by the corner insulating spacers 130. The pair of outer insulating spacers 140 may have a surface directly contacting a portion of the sidewalls 120S of the gate 120 that is not covered by the corner insulating spacers 130. In some embodiments, when the sidewall 120S of the gate 120 is completely covered by a corner insulating spacer 130, the outer insulating spacer 140 is an insulating capping layer on the corner insulating spacer 130 ( The side wall of 122) may be covered.

The pair of outer insulating spacers 140 has a dielectric constant smaller than that of the pair of corner insulating spacers 130.

In some embodiments, the pair of corner insulating spacers 130 may be formed of a high dielectric film having a higher dielectric constant than a silicon oxide film. For example, the pair of corner insulating spacers 130 may have a dielectric constant of about 10 to 25. In some embodiments, the pair of corner insulating spacers 130 includes hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), and lanthanum oxide (LaO). , Lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium Strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO) Can be. However, the materials constituting the pair of corner insulating spacers 130 are not limited to those illustrated above.

For example, the pair of corner insulating spacers 130 may be made of a silicon oxide film. In this case, the pair of outer insulating spacers 140 may be formed of a film having a lower dielectric constant than the silicon oxide film. For example, at least a portion of the pair of outer insulating spacers 140 may be formed of air spacers. In some embodiments, the pair of outer insulating spacers 140 may be formed of a silicon oxide spacer, a silicon nitride spacer, an air spacer, or a combination thereof. In some embodiments, the pair of corner insulating spacers 130 may be made of a silicon oxide film, and the pair of outer insulating spacers 140 may have a multi-layer structure including an air spacer. For example, the pair of outer insulating spacers 140 may include an air spacer adjacent to the corner insulating spacer 130 and a silicon oxide film spaced apart from the corner insulating spacer 130 with the air spacer interposed therebetween. It may be formed of a double-layer structure including. In some other embodiments, the pair of corner insulating spacers 130 is made of a silicon nitride film, and the pair of outer insulating spacers 140 is a single layer structure made of a silicon oxide film, or a multiple including an air spacer It can have a layer structure. In some other embodiments, the pair of corner insulating spacers 130 is made of a hafnium oxide film, and the pair of outer insulating spacers 140 is a silicon oxide film, a silicon nitride film, an air spacer, or a combination thereof. It can be done. According to the technical idea of the present invention, the material combination of the pair of corner insulating spacers 130 and the pair of outer insulating spacers 140 is not limited to the above-described examples. The pair of corner insulating spacers 130 are made of an insulating material having a relatively high dielectric constant, and the pair of outer insulating spacers 140 have various combinations under conditions having a small dielectric constant compared to the corner insulating spacers 130 This is possible.

The pair of source / drain regions 110 each have a source / drain extension region 110A having a relatively low impurity doping concentration, and a deep source / drain having a higher impurity doping concentration than the source / drain extension region 110A. Area 110B is included.

Each of the pair of corner insulating spacers 130 may cover the source / drain extension region 110A by a width smaller than a predetermined horizontal separation distance L1 from the sidewall 120S of the gate 120, respectively. In the present specification, unless otherwise defined, the “horizontal separation distance” is in the same direction (the X direction in FIG. 1) as the direction in which the main surface of the semiconductor substrate 102 extends, particularly the channel formed in the channel region 106. It means the shortest distance.

In some embodiments, the horizontal separation distance L1 may be a horizontal separation distance from the sidewall 120S of the gate 120 to the deep source / drain region 110B. That is, the pair of corner insulating spacers 130 each have a width smaller than the horizontal separation distance L1 from the sidewall 120S of the gate 120 to the deep source / drain region 110B. (110A) can be covered. In some other embodiments, the horizontal separation distance L1 may be a horizontal distance from the sidewall 120S of the gate 120 to the outer wall of the outer insulating spacer 140. That is, each of the pair of corner insulating spacers 130 has the source / drain extension area by a width smaller than the horizontal separation distance L1 from the sidewall 120S of the gate 120 to the outer wall of the outer insulating spacer 140. (110A) can be covered.

In some embodiments, the pair of corner insulating spacers 130 has a horizontal separation distance (L1) between the gate 120 and the deep source / drain region 110B from the sidewall 120S of the gate 120. It can have a horizontal width selected within a range up to a distance of 1/2 of. In some other embodiments, the pair of corner insulating spacers 130 is a distance of 1/2 of the horizontal separation distance L1 from the sidewall 120S of the gate 120 to the outer wall of the outer insulating spacer 140. It may have a width in the horizontal direction selected within the range up to.

The semiconductor device 100A illustrated in FIG. 1 is an insulating spacer region formed in a concave corner portion C1 formed between a source / drain region 110 formed on the semiconductor substrate 102 and a sidewall of the gate 120. In the middle, a corner insulating spacer 130 made of an insulating material having a relatively high dielectric constant is disposed in an inner portion that has a relatively large effect on performance of the transistor, and thus, between the source / drain regions 110 and the gate 120. It is possible to suppress the occurrence of fringing capacitance. Accordingly, it is possible to improve the "ON" current characteristic and the "OFF" current characteristic of the transistor, and to prevent the performance of the transistor from deteriorating. In addition, the outer portion of the insulating spacer region formed in the concave corner portion C1 at both sides of the gate 120 has a relatively small dielectric constant compared to the corner insulating spacer 130 in the outer portion having a relatively small influence on the performance of the transistor. By forming the outer insulating spacer 140 made of an insulating material, parasitic capacitance in the semiconductor device 100A can be reduced. Accordingly, an operation speed of the transistor including the gate 120 may be improved and power consumption may be reduced.

2 is a cross-sectional view of a semiconductor device 100B according to embodiments of the inventive concept. In Fig. 2, the same reference numerals as in Fig. 1 denote the same members, and therefore detailed descriptions thereof are omitted here.

Referring to FIG. 2, the semiconductor device 110B includes corner insulating spacers 130P extending along side surfaces of the gate 120 and upper surfaces of the source / drain regions 110, respectively, on both sides of the gate 120. do.

The corner insulating spacer 130P includes a first surface 132P covering the sidewall 120S of the gate 120 from one side of the gate dielectric layer 124 adjacent to the sidewall 120S of the gate 120 and the gate dielectric layer It has a second surface 134P covering a portion of the pair of source / drain regions 110 from one side of 124. The first surface 132P may have a height HA1 ′ that covers the sidewall 120S of the gate 120 up to the height of the upper surface of the gate 120. Accordingly, the first surface 132P may substantially cover the sidewalls 120S of the gate 120. The first surface 132P may directly contact the sidewall 120S of the gate 120. The second surface 134P may directly contact a portion of the pair of source / drain regions 110.

The pair of outer insulating spacers 140P covering the pair of corner insulating spacers 130P are spaced apart from the gate 120 with the corner insulating spacers 130P interposed therebetween. The pair of outer insulating spacers 140P may cover at least a portion of both side walls of the insulating capping layer 122.

The pair of outer insulating spacers 140P has a dielectric constant smaller than that of the pair of corner insulating spacers 130P. For more details of the pair of corner insulating spacers 130P and the pair of outer insulating spacers 140P, referring to FIG. 1, a pair of corner insulating spacers 130 and a pair of outer insulating spacers 140 See what has been described for.

The semiconductor device 100B illustrated in FIG. 2 is an insulating spacer region formed in a concave corner portion C1 formed between a source / drain region 110 formed on the semiconductor substrate 102 and a sidewall of the gate 120. In the middle, a corner insulating spacer 130P made of an insulating material having a relatively high dielectric constant is disposed on an inner portion that has a relatively large influence on the performance of the transistor, thereby fringing capacitance between the source / drain regions 110 and the gate 120. Can be suppressed from occurring. Accordingly, it is possible to improve the "ON" current characteristic and the "OFF" current characteristic of the transistor, and to prevent the performance of the transistor from deteriorating. In addition, the outer portion of the insulating spacer region formed in the concave corner portion C1 at both sides of the gate 120 has a relatively small dielectric constant compared to the corner insulating spacer 130P in the outer portion having a relatively small influence on the performance of the transistor. By forming the outer insulating spacer 140P made of an insulating material, parasitic capacitance can be reduced in the semiconductor device 100B. Accordingly, an operation speed of the transistor including the gate 120 may be improved and power consumption may be reduced.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence. In this example, a process for manufacturing the semiconductor device 100A illustrated in FIG. 1 will be described as an example. However, within the scope of the technical spirit of the present invention, the processes described with reference to FIGS. 3A to 3F can be applied to the manufacturing process of the semiconductor device 100B illustrated in FIG. 2. 3A to 3F, the same reference numerals as in FIG. 1 denote the same members, and thus detailed descriptions thereof are omitted here.

Referring to FIG. 3A, an isolation layer 104 defining an active region 106 is formed on a semiconductor substrate 102.

The device isolation film 104 may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

A dielectric film 124L, a conductive layer 120L, and an insulating layer 122L are sequentially formed on the semiconductor substrate 102.

The dielectric film 124L may be made of silicon oxide or a high dielectric film. In some embodiments, the high dielectric film is hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO) ), Zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), It may be made of at least one material selected from barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). In some embodiments, to form the dielectric layer 124L, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a thermal oxidation process may be used.

The conductive layer 120L may be made of doped polysilicon, metal, conductive metal nitride, metal silicide, alloy, or a combination thereof. For example, the conductive layer 120L may include nitride of at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf. The conductive layer 120L may have a single layer or multiple layers. In some embodiments, a chemical vapor deposition (CVD) process, a metal organic CVD (MOCVD) process, an atomic layer deposition (ALD) process, or a metal organic ALD (MOALD) process is used to form the conductive layer 120L. However, it is not limited thereto.

The insulating layer 122L may be formed of a silicon nitride film, a silicon oxide film, or a combination thereof.

Referring to FIG. 3B, after forming a mask pattern (not illustrated) on the insulating layer 122L illustrated in FIG. 3A, the insulating layer 122L is etched using the mask pattern as an etching mask to insulate the insulating capping layer. A gate 120 and a gate dielectric layer 124 are formed by sequentially forming the 122 and sequentially etching the conductive layer 120L and the dielectric layer 124L using the insulating capping layer 122 as an etching mask.

In some embodiments, the gate 120 may be formed to have a line width WL1 of about 10 to 30 nm. In this case, the gate 120 may have a gate length corresponding to the line width WL1. However, according to the technical idea of the present invention, the line width of the gate 120 is not limited to the above-described examples, and may be formed to have various line widths.

On both sides of the gate 120, concave corner portions C1 to which the gate dielectric layer 124 are exposed are provided between the gate 120 and the semiconductor substrate 102, respectively.

Referring to FIG. 3C, impurity ions (IIP1) having a first doping concentration are implanted into the semiconductor substrate 102 using the insulating capping layer 122 as an ion implantation mask, so that the semiconductor substrates are formed on both sides of the gate 120. A source / drain extension region 110A having a relatively shallow depth is formed in 102. In some embodiments, the first doping concentration of the impurity ions IIP1 may be variously determined according to the design of the semiconductor device 100A.

In some embodiments, an impurity ion (IIP1) implantation process for forming the source / drain extension region 110A is not performed at this stage, and a pair of corner insulating spacers 130 described with reference to FIG. 3D It may also be performed after the forming process.

In some embodiments, before performing an impurity ion (IIP1) implantation process to form the source / drain extension region 110A, protecting the exposed surface of the semiconductor substrate 102 and the exposed surface of the gate 120 After forming the oxide thin film, and after the source / drain extension region 110A is formed, a process of removing the oxide thin film by a wet etching process may be performed.

Referring to FIG. 3D, after forming a stacked structure of the gate 120 and the insulating capping layer 122 and a first insulating spacer film (not shown) that conformally extends along the exposed surface of the semiconductor substrate 102. , The first insulating spacer film is etched back to form a corner insulating spacer 130 in the concave corner portion C1.

In some embodiments, the corner insulating spacer 130 may have a shape of a pair of corner insulating spacers 130 positioned one on each side of the gate 120. In some other embodiments, the corner insulating spacer 130 may have a ring shape surrounding the gate 120 around the gate 120.

The width (CW1) of the corner insulating spacer 130 may be controlled by the thickness of the first insulating spacer film. The height CHA1 of the pair of corner insulating spacers 130 may be controlled by a time during which the etch-back process of the first insulating spacer film is performed. In some embodiments, the corner insulating spacer 130 is selected to have a width (CW1) selected in the range of about 1-20 nm and a height (CHA1) selected in the range of about 3-60 nm. It may be, but is not limited to this. The height CHA1 of the pair of corner insulating spacers 130 may correspond to the first height HA1 illustrated in FIG. 1.

In some embodiments, the process of forming the source / drain extension region 110A described with reference to FIG. 3C may not be performed before the process of forming the corner insulating spacer 130. In this case, the impurity ion (IIP1) implantation process for forming the source / drain extension region 110A as described with reference to FIG. 3C may be performed after the pair of corner insulation spacer 130 formation processes described with reference to FIG. 3D. Can be. In this case, after implanting the impurity ions IIP1 into the semiconductor substrate 102, the impurity ions IIP1 implanted into the semiconductor substrate 102 are diffused in a horizontal direction to the edge portion of the sidewall 120S of the gate 120. I can do it. At this time, by controlling the horizontal diffusion distance of the impurity ions IIP1 in the semiconductor substrate 102, the overlap area between the gate 120 and the source / drain extension region 110A can be reduced. Accordingly, an effective gate length of the MOS transistor may be increased, and a gate induced drain leakage (GIDL) and overlap capacitor generated in the MOS transistor may be reduced.

Referring to FIG. 3E, a stacked structure of the gate 120, an insulating capping layer 122, and a corner insulating spacer 130 and an exposed surface of the semiconductor substrate 102 are formed on a result of forming a corner insulating spacer 130. After forming a second insulating spacer film (not shown) that conformally extends, the second insulating spacer film is etched back to cover the corner insulating spacer 130 in the concave corner portion C1 (see FIG. 3C). The outer insulating spacer 140 is formed.

The second insulating spacer film and the outer insulating spacer 140 obtained therefrom are made of a material having a dielectric constant smaller than that of the constituent material of the corner insulating spacer 130.

In some embodiments, the outer insulating spacer 140 may have a shape of a pair of outer insulating spacers 140 positioned one on each side of the gate 120. In some other embodiments, the outer insulating spacer 140 may have a ring shape surrounding the gate 120 around the gate 120.

The width OW1 of the outer insulating spacer 140 may be controlled by the thickness of the second insulating spacer film. The height OHA1 of the outer insulating spacer 140 may be controlled by a time during which the etch-back process of the second insulating spacer film is performed. By controlling the width OW1 of the outer insulating spacer 140, a ratio occupied by the corner insulating spacer 130 among the widths of the sidewall spacers determined by the corner insulating spacer 130 and the outer insulating spacer 140 is determined. Can be. The width of the sidewall spacer may correspond to the width OW1 of the outer insulating spacer 140. The height OHA1 of the outer insulating spacer 140 may correspond to the second height HA2 illustrated in FIG. 1.

Referring to FIG. 3F, impurity ions having a second doping concentration higher than the first doping concentration to the semiconductor substrate 102 using the insulating capping layer 122 and the outer insulating spacer 140 as an ion implantation mask (IIP2) ) Is implanted to form deep source / drain regions 110B in the semiconductor substrate 102 on both sides of the gate 120. In some embodiments, the second doping concentration of the impurity ion (IIP2) may be variously determined according to the design of the semiconductor device 100A.

The source / drain extension region 110A and the deep source / drain region 110B constitute the source / drain region 110.

In some embodiments, before performing an implantation process of impurity ions (IIP2) to form the deep source / drain regions 110B, an oxide thin film is formed to protect the exposed surface of the semiconductor substrate 102, After the deep source / drain region 110B is formed, a process of removing the oxide thin foil by a wet etching process may be performed.

Subsequently, a result of forming the corner insulating spacer 130, the outer insulating spacer 140, and the pair of source / drain regions 110 may be covered with an interlayer insulating film to perform a conventional contact forming process.

4A to 4C are views for explaining a main configuration of a semiconductor device 200A according to embodiments of the inventive concept, and FIG. 4A is a partial perspective view of the semiconductor device 200A, and FIG. 4B is a view. 4A is a vertical sectional view along the 4B-4B 'line, and FIG. 4C is a vertical sectional view along the 4C-4C' line in FIG. 4A. 4A to 4C illustrate a semiconductor device 200A made of a finFET manufactured from an SOI wafer.

The semiconductor device 200A is implemented on an SOI wafer 208 that includes a substrate 202, a semiconductor fin 204, and a buried insulating layer 206 interposed therebetween. The semiconductor fin 204 extends in one direction (X direction in FIG. 4A) on the buried insulating layer 206. 4A to 4C, the semiconductor device 200A having one semiconductor pin 204 is illustrated, but the technical spirit of the present invention is not limited thereto. The semiconductor device according to the technical concept of the present invention may include various numbers of semiconductor pins as required in the design. Also, the number of the semiconductor fins 204 may be determined according to other factors, for example, the physical size of the finFET constituting the semiconductor device, the operating voltage, or the current.

In some embodiments, the substrate 202 may be made of Si. In some embodiments, the semiconductor fin 204 may include Si, for example, crystalline Si, polycrystalline Si, or amorphous Si. In some other embodiments, the semiconductor fin 204 may include a semiconductor such as Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, and InP. The buried insulating layer 206 may be formed of an oxide film.

The semiconductor fin 204 includes a channel region 212 extending between a pair of source / drain regions 210 and the pair of source / drain regions 210.

A gate 220 is formed on the channel region 212 of the semiconductor fin 204. The gate 220 extends in a direction intersecting the extending direction of the semiconductor fin 204 (the X direction in FIG. 4A) (the Y direction in FIG. 4A).

The gate 220 constitutes a MOS transistor TR1. The MOS transistor TR1 is formed of a MOS transistor having a three-dimensional structure in which channels are formed on the top and both sides of the semiconductor fin 204.

The portion of the gate 220 positioned above the semiconductor fin 204 may have a thickness equal to or greater than the thickness along the vertical direction (the Z direction in FIG. 4A) of the semiconductor fin 204, but the portion of the present invention The technical idea is not limited to this.

The gate 220 has a sidewall 220S extending from the buried insulating layer 206 to a predetermined height (HBG) in a vertical direction (Z direction in FIG. 4A).

In some embodiments, the gate 220 may be made of doped polysilicon, metal, conductive metal nitride, metal silicide, alloy, or a combination thereof. For example, the gate 220 may include nitride of at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf.

The upper surface of the gate 220 is covered by an insulating capping layer 222. In some embodiments, the insulating capping layer 222 may be formed of a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 224 is interposed between the channel region 212 and the gate 220. The gate dielectric layer 224 may be formed of a silicon oxide layer or a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer.

Corner insulating spacers 230 extending along the surfaces of the sidewalls 220S of the gate 220 and the buried insulating layer 206 are formed on both sides of the gate 220, respectively.

The corner insulating spacer 230 is a concave corner portion C2 formed between the gate 220, a pair of source / drain regions 210 formed in the semiconductor fins 204, and the buried insulating layer 206. ) (See FIG. 5D) along the sidewall 220S of the gate 220.

As can be seen in FIG. 4B, the corner insulating spacer 230 may remove at least a portion of the sidewall 220S of the gate 220 from one side of the gate dielectric layer 224 adjacent to the sidewall 220S of the gate 220. It has a first surface 232 that covers, and a second surface 234 that covers a portion of the pair of source / drain regions 210 (see FIG. 5E). The first surface 232 of the corner insulating spacer 230 may directly contact at least a portion of the sidewall 220S of the gate 220. The second surface 234 may directly contact a portion of the pair of source / drain regions 210.

The first surface 232 of the corner insulating spacer 230 covers the sidewall 220S of the gate 220 to a first height HB1 smaller than the height HBG of the sidewall 220S. However, the technical spirit of the present invention is not limited to this. For example, the first surface 232 of the corner insulating spacer 230 covers the side walls 220S at various heights within a range not exceeding the height HBG of the side walls 120S of the gate 120. Can be.

A pair of outer insulating spacers 240 are formed on the pair of corner insulating spacers 230. The pair of outer insulating spacers 240 may extend on the buried insulating layer 206 to a second height HB2 greater than the first height HB1. 4A to 4C, the second height HB2 of the outer insulating spacer 240 is higher than the height HBG of the sidewall 220S of the gate 220, that is, higher than the upper surface of the gate 220, and the insulating capping layer ( 222) is illustrated to reach a level lower than the upper surface, but the technical spirit of the present invention is not limited thereto. For example, the second height HB2 of the outer insulating spacer 140 is necessary within a range between the first height HB1 of the corner insulating spacer 230 and the height of the top surface of the insulating capping layer 122. It can be selected accordingly.

The outer insulating spacer 240 may have a surface facing the other portion of the sidewall 220S of the gate 220 that is not covered by the corner insulating spacer 230. The outer insulating spacer 240 may have a surface that directly contacts a portion of the sidewalls 220S of the gate 220 that is not covered by the corner insulating spacer 230. In some embodiments, when the sidewall 220S of the gate 220 is completely covered by a corner insulating spacer 230, the outer insulating spacer 240 is an insulating capping layer above the corner insulating spacer 230 ( 222) may be covered.

The outer insulating spacer 240 has a dielectric constant smaller than that of the corner insulating spacer 230.

For more details of the corner insulating spacer 230 and the outer insulating spacer 240, refer to the description of the corner insulating spacer 130 and the outer insulating spacer 140 with reference to FIG. 1.

Each of the pair of source / drain regions 210 has a source / drain extension region 210A having a relatively low impurity doping concentration, and a deep source / drain having a higher impurity doping concentration than the source / drain extension region 210A. The region 210B may be included.

Each of the corner insulating spacers 230 has a width (CW2) smaller than the horizontal separation distance L2 from the sidewall 220S of the gate 220 to the outer wall of the outer insulating spacer 240 along the sidewall of the semiconductor fin 204. (See FIG. 4B). The corner insulating spacer 230 covers the source / drain region 110 formed in the semiconductor fin 204 on the sidewall of the semiconductor fin 204 by the width CW2. In addition, the corner insulating spacer 230 covers the buried insulating layer 206 by the width CW2 within a distance corresponding to the horizontal separation distance L2 from the sidewall 220S of the gate 220.

In some embodiments, the horizontal width CW2 of the corner insulating spacer 230 may be selected within a range of 1/2 of the horizontal separation distance L2 from the sidewall 220S of the gate 220. have.

In some embodiments, the source / drain extension region 210A may be omitted from the source / drain region 110. In this case, the deep source / drain region 210B may be formed over a region further extended from the region illustrated in FIG. 4C to the edge side of the sidewall 220S of the gate 220.

The semiconductor fin 204, the gate 220, and the buried insulating layer 206 among the insulating spacer regions extending along the sidewall 220S of the gate 220 in the semiconductor device 200A illustrated in FIGS. 4A to 4C. A corner insulating spacer 230 made of an insulating material having a relatively high dielectric constant is disposed in the inner portion of the concave corner portion C2 (see FIG. 5D) formed between the fruits. Therefore, it is possible to suppress the occurrence of fringing capacitance in the semiconductor device 200A, improve the "ON" current characteristic and the "OFF" current characteristic of the transistor, and deteriorate the performance of the transistor. Can be prevented. In addition, an outer insulating spacer 240 made of an insulating material having a smaller dielectric constant than the corner insulating spacer 230 is formed on an outer portion of the insulating spacer region formed in the concave corner portion C2. Therefore, parasitic capacitance is reduced in the semiconductor device 200A, thereby improving the operation speed of the transistor and reducing power consumption.

5A to 5K are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence. In this example, a process for manufacturing the semiconductor device 200A illustrated in FIGS. 4A to 4C will be described as an example. 5A to 5K, the same reference numerals as in FIGS. 4A to 4C denote the same members, and thus detailed descriptions thereof will be omitted here.

Referring to FIG. 5A, after preparing an SOI wafer 208 including two semiconductor layers and a buried insulating layer 206 therebetween, an upper semiconductor on top of the buried insulating layer 206 among the two semiconductor layers The layer is partially removed so that the semiconductor fin pattern 204X remains on the buried insulating layer 206. The semiconductor layer under the buried insulating layer 206 among the two semiconductor layers may remain as the substrate 202.

The semiconductor fin pattern 204X extends in one direction (X direction in FIG. 5) on the buried insulating layer 206. The semiconductor fin pattern 204X has a base portion 204B in contact with the buried insulating layer 206.

Although only one semiconductor pin pattern 204X is illustrated in FIG. 5A, the technical idea of the present invention is not limited thereto, and various numbers of semiconductor pin patterns 204X may be formed as required in the design. .

In some embodiments, the substrate 202 and the semiconductor fin pattern 204X may each be made of silicon.

Referring to FIG. 5B, a dielectric film 224L covering the exposed surface of the semiconductor fin pattern 204X illustrated in FIG. 5A and the exposed surface of the buried insulating layer 206 is formed, and a planarized top surface is formed on the dielectric film 224L. The branch forms the conductive layer 220L for gate formation.

The dielectric film 224L may be made of silicon oxide or a high dielectric film. The conductive layer 220L may be made of doped polysilicon, metal, conductive metal nitride, metal silicide, alloy, or a combination thereof. For more details on the dielectric film 224L and the conductive layer 220L, see the description of the dielectric film 124L and the conductive layer 120L with reference to FIG. 3A.

Referring to FIG. 5C, an insulating capping layer 222 is formed on the conductive layer 220L illustrated in FIG. 5B using a photolithography process, and the insulating capping layer 222 is used as an etching mask to form a conductive layer ( 220L) and the dielectric film 224L are sequentially etched to form the gate 220 and the gate dielectric film 224.

The gate 220 extends in a direction intersecting the extending direction of the semiconductor fin pattern 204X (Y direction in FIG. 5C). In some embodiments, the gate 220 may be formed to have a line width WL2 of about 10 to 30 nm, but is not limited thereto.

Using the insulating capping layer 222 as an etch mask, the conductive layer 220L and the dielectric film 224L are sequentially etched to form the gate 220 and the gate dielectric film 224.

The gate 220 extends in a direction intersecting the extending direction of the semiconductor fin pattern 204X (Y direction in FIG. 5C). In some embodiments, the gate 220 may be formed to have a line width WL2 of about 10 to 30 nm, but is not limited thereto.

Concave corner portions C2 are provided on both sides of the gate 220 between the gate 220, the semiconductor fin pattern 204X, and the buried insulating layer 206, respectively. The gate dielectric layer 224 is exposed in the concave corner portion C2.

Referring to FIG. 5D, by using an insulating capping layer 222 as an ion implantation mask, impurity ions (IIP1) having a first doping concentration are implanted into the semiconductor fin pattern 204X to form semiconductor fin patterns on both sides of the gate 220. A source / drain extension region 210A is formed in 204X. The first doping concentration of the impurity ions IIP1 may be variously determined according to the design of the semiconductor device 200A.

In some embodiments, the process of implanting impurity ions (IIP1) for forming the source / drain extension region 210A is not performed in this step, but the corner insulating spacer 230 formation process described with reference to FIG. 5E It may be performed later.

In some embodiments, before performing an impurity ion (IIP1) implantation process to form the source / drain extension region 210A, the exposed surface of the semiconductor fin pattern 204X and the exposed surface of the gate 220 are protected. After forming the oxide thin film to form the source / drain extension region 210A, a process of removing the oxide thin film by a wet etching process may be performed.

The gate 220, the gate dielectric layer 224, the source / drain extension region 210A, and the buried insulating layer 206 are exposed in the concave corner portions C2 on both sides of the gate 220.

In some embodiments, the impurity ion (IIP1) implantation process described with reference to FIG. 5D may be omitted, so a source / drain extension region 210A may not be formed in the semiconductor fin pattern 204X.

Referring to FIG. 5E, a stacked structure of the gate 220 and the insulating capping layer 222 and a first insulating spacer film (not shown) that conformally extend along the exposed surface of the semiconductor fin pattern 204X are formed. Thereafter, the first insulating spacer film is etched back to form corner insulating spacers 230 in the concave corner portions C2, respectively. In forming the corner insulating spacer 230, the etch-back time of the first insulating spacer film may be controlled so that a first insulating spacer film does not remain on the upper surface of the semiconductor fin pattern 204X.

In forming the corner insulating spacer 230, the vertical direction (Z direction in FIG. 5E) of the stacked structure of the gate 220 and the insulating capping layer 222 is the vertical height of the semiconductor fin pattern 204X. Is bigger than. Here, the height of the stacked structure of the gate 220 and the insulating capping layer 222 may be formed to be sufficiently large compared to the vertical height of the semiconductor fin pattern 204X. By doing this, while etching the first insulating spacer film until the corner insulating spacers 230 each having a desired height are left on both sidewalls of the gate 220, the sidewalls of the sidewalls of the semiconductor fin pattern 204X are The first insulating spacer layer may be completely removed on the sidewall portion spaced from the gate 220. As a result, sidewalls of the semiconductor fin pattern 204X may be exposed in the concave corner portion C2.

The corner insulation spacer 230 may be selected to have a width (CW2) selected within a range of about 1 to 20 nm and a height (CH2) selected within a range of about 3 to 60 nm, but is not limited thereto. It does not work. The height CH2 may correspond to the first height HB1 illustrated in FIGS. 4A and 4B.

In some embodiments, the process of forming the source / drain extension region 210A described with reference to FIG. 5D may not be performed before the process of forming the corner insulating spacer 230. In this case, an impurity ion (IIP1) implantation process for forming the source / drain extension region 210A as described with reference to FIG. 5D may be performed after the corner insulation spacer 230 formation process described with reference to FIG. 5E. . In this case, after implanting the impurity ions IIP1 into the semiconductor fin pattern 204X, the impurity ions IIP1 implanted into the semiconductor fin pattern 204X may be diffused to a sidewall edge portion of the gate 220.

Referring to FIG. 5F, an exposed surface of a laminated structure of a gate 220, an insulating capping layer 222, and a corner insulating spacer 130 is formed on a result of forming corner insulating spacers 230 on both sides of the gate 220. After forming the second insulating spacer film (not shown) conformally extending along the exposed surface of the semiconductor fin pattern 204X and the exposed surface of the buried insulating film 206, the second insulating spacer film is etched back. , A pair of outer insulating spacers 240 covering the pair of corner insulating spacers 230 in a concave corner portion C2 (see FIG. 5E).

The outer insulating spacer 240 is made of a material having a dielectric constant smaller than that of the constituent material of the corner insulating spacer 230.

The width OW2 of the outer insulating spacer 240 may be controlled by the thickness of the second insulating spacer film. The height OH2 of the outer insulating spacer 240 may be controlled by a time during which the etch-back process of the second insulating spacer film is performed. The height OH2 of the outer insulating spacer 240 may correspond to the second height HB2 illustrated in FIGS. 4A and 4B.

Referring to FIG. 5G, an epitaxial semiconductor layer 210EP is formed on an exposed surface of the semiconductor fin pattern 204X illustrated in FIG. 5F to form a semiconductor composed of the semiconductor fin pattern 204X and the epitaxial semiconductor layer 210EP. A fin 204 is formed.

In order to form the epitaxial semiconductor layer 210EP, a semiconductor layer may be epitaxially grown from the exposed surface of the semiconductor fin pattern 204X using a selective epitaxial growth (SEG) process.

In some embodiments, the epitaxial semiconductor layer 210EP may be made of the same semiconductor material as the semiconductor material constituting the semiconductor fin pattern 204X. In some other embodiments, the epitaxial semiconductor layer 210EP may be made of a semiconductor material different from the semiconductor material constituting the semiconductor fin pattern 204X. For example, the epitaxial semiconductor layer 210EP may be made of Si, Ge, SiGe, SiC, or a combination thereof.

In some embodiments, a reduced pressure CVD (RPCVD) process may be used to form the epitaxial semiconductor layer 210EP. The precursor that can be used when forming the epitaxy semiconductor layer 210EP may include a Si-containing gas such as SiH ₄ , GeH ₄ , and / or a Ge-containing gas, depending on the composition to be formed. When the SiGe layer is formed as the epitaxial semiconductor layer 210EP, the atomic ratio of Ge to Si can be controlled by controlling the partial pressures of the Si-containing gas and the Ge-containing gas.

During the epitaxial growth process for forming the epitaxial semiconductor layer 210EP, facets may be formed due to different growth rates on different crystal surfaces. For example, the growth rate in the (111) plane may be lower than the growth in other planes such as the (110) plane and the (100) plane. In order to remove the facets formed due to the difference in the growth rate of different crystal faces, an etching gas such as HCl gas may be added to the process gas during the epitaxial growth process. In this case, epitaxial growth and etching are performed in-situ in the same chamber, so that the epitaxial semiconductor layer 210EP may be formed to have a round-shaped surface profile.

The epitaxy semiconductor layer 210EP forms a source / drain region through a subsequent ion implantation process with the semiconductor fin pattern 204X.

Depending on the channel type in the channel region of the semiconductor fin 204, the epitaxy semiconductor layer 210EP may be formed of a material that causes tensile strain or compressive strain. Such strain can contribute to improving the performance of the transistor, for example, mobility. For example, the epitaxial semiconductor layer 210EP constituting the semiconductor fin 204 on which the N channel is formed is formed of SiC to induce tensile strain, and the epi constituting semiconductor fin 204 on which the P channel is formed. The taxi semiconductor layer 210EP may be formed of SiGe to cause compression strain, but the technical spirit of the present invention is not limited thereto.

Since the semiconductor fin 204 includes an epitaxial semiconductor layer 210EP, a source / drain formed in the semiconductor fin 204 may have a raised source / drain (RSD) structure.

Referring to FIG. 5H, an impurity ion (IIP2) having a second doping concentration higher than the first doping concentration is applied to the semiconductor fin 204 using the insulating capping layer 222 and the outer insulating spacer 240 as an ion implantation mask. Is implanted to form deep source / drain regions 210B (see FIG. 4C) on the semiconductor fins 204 on both sides of the gate 220 to form source / drain regions 210.

In some embodiments, the process of forming the source / drain extension region 210A described with reference to FIG. 5D may be omitted. In this case, the source / drain regions 210 may be formed in the semiconductor fins 204 only by implanting the impurity ions IIP2 described with reference to FIG. 5H.

Since the source / drain region 210 has an RSD structure including an epitaxial semiconductor layer 210EP, the thickness of the source / drain region 210 is increased to reduce overall parasitic resistance.

Although not shown, a metal silicide film may be formed by performing a salicide process on the surface of the source / drain region 210 to reduce the resistance in the source / drain region 210. In some embodiments, the metal silicide film may include a metal made of cobalt, nickel, platinum, palladium, vanadium, titanium, tantalum, ytterbium, zirconium, or a combination thereof. In order to form the metal silicide film, a process of forming a metal film on the surface of the source / drain region 210, a process of reacting the metal film and the source / drain region 210, and an unreacted portion of the metal film And removing.

Referring to FIG. 5I, an insulating material is deposited on a result including a semiconductor fin 204 having a source / drain region 210 formed thereon to form an interlayer insulating film 260 having a flattened top surface.

In some embodiments, the interlayer insulating film 260 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an ultra low dielectric constant K (ULK) film having an ultra low dielectric constant K of about 2.2 to 2.4, eg For example, it may be made of an SiOC film or a SiCOH film.

Referring to FIG. 5J, the interlayer insulating layer 260 is partially etched to form a slot-shaped opening 260S exposing the source / drain region 210 of the semiconductor fin 204.

In this example, the case where the opening 260S has a slot shape is illustrated, but the technical spirit of the present invention is not limited thereto. For example, the opening 260S may have a hole shape.

Referring to FIG. 5K, after forming a conductive layer by depositing a conductive material inside the opening 260S illustrated in FIG. 5J and on the interlayer insulating film 260, the conductive layer is subjected to the conductivity using a chemical mechanical polishing (CMP) or etchback process. A portion of the layer is removed until the top surface of the interlayer insulating film 260 is exposed, thereby forming a contact plug 270 that contacts the source / drain region 210 in the opening 260S.

6 is a perspective view illustrating a main configuration of a semiconductor device 200B according to embodiments of the inventive concept.

The semiconductor device 200B has substantially the same configuration as the semiconductor device 200A illustrated in FIGS. 3A to 3C, except that it includes two semiconductor pins 204. Although two semiconductor pins 204 are illustrated in FIG. 6, three or more semiconductor pins 204 may be included as required in design.

7A and 7B are diagrams for explaining a main configuration of a semiconductor device 300A according to embodiments of the inventive concept, and FIG. 7A is a partial perspective view of the semiconductor device 300A, and FIG. 7B is a view. It is a vertical section along the 7B-7B 'line of 7a. 7A and 7B illustrate a semiconductor device 300A made of a finFET manufactured from a bulk substrate.

The semiconductor device 300A includes a semiconductor layer 304 extending in one direction (X direction in FIGS. 7A and 7B). The semiconductor layer 304 includes an active region 304X made of a semiconductor fin protruding from the substrate 302 and extending in a first direction. In this example, a configuration in which only one semiconductor layer 304 is formed is illustrated, but the technical spirit of the present invention is not limited thereto. The case where a plurality of semiconductor layers 304 are formed on the substrate 302 is also included in the scope of the technical idea of the present invention.

The semiconductor layer 304 further includes an epitaxy semiconductor layer 304EP covering a portion of the top surface and both sidewalls of the active region 304X.

In some embodiments, the substrate 302 may include semiconductors such as Si and Ge. In some other embodiments, the substrate 302 may include a compound semiconductor such as Ge, SiGe, SiC, GaAs, InAs, or InP. In some embodiments, the substrate 302 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities.

The active region 304X extends along one direction (X direction in FIGS. 7A and 7B). A device isolation layer 306 is formed around the active region 304X on the substrate 302. The active region 304X protrudes in a pin shape over the device isolation layer 306.

The semiconductor fin 304 includes a channel region 312 extending between a pair of source / drain regions 310 and the pair of source / drain regions 310.

A gate 320 extends on the device isolation layer 306 on the substrate 302. The gate 320 extends in a direction (Y direction in FIGS. 7A and 7B) that intersects the active region 304X while covering the top and both sides of the active region 304X. The gate 320 constitutes a MOS transistor TR2. The MOS transistor TR2 is formed of a MOS transistor having a three-dimensional structure in which channels are formed on the top and both sides of the active region 304X.

The gate 320 has a sidewall 320S extending from the device isolation layer 306 to a predetermined height (HCG) in a vertical direction (Z direction in FIG. 7A).

In some embodiments, the gate 320 may be made of doped polysilicon, metal, conductive metal nitride, metal silicide, alloy, or a combination thereof. For example, the gate 320 may include at least one metal selected from Al, Ti, Ta, W, Ru, Nb, Mo, or Hf, or a nitride thereof.

The upper surface of the gate 320 is covered by an insulating capping layer 322. In some embodiments, the insulating capping layer 322 may be formed of a silicon nitride film, a silicon oxide film, or a combination thereof.

A gate dielectric layer 324 is interposed between the channel region 312 and the gate 320. The gate dielectric layer 324 may be formed of a silicon oxide layer or a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer.

Corner insulating spacers 330 extending along side surfaces 320S of the gate 320 and upper surfaces of the device isolation layer 306 are formed on both sides of the gate 320, respectively.

The corner insulating spacer 330 is provided with the gate at the concave corner portion C3 (see FIGS. 8C and 8D) formed between the gate 320, the active region 304X, and the device isolation layer 306. It extends along the sidewall 320S of 320).

The corner insulating spacer 330 includes a first surface 332 covering at least a portion of the sidewall 320S of the gate 320 from one side of the gate dielectric layer 324 adjacent to the sidewall 320S of the gate 320, It has a second surface 334 (see FIG. 8D) covering a portion of the active region 304X. The first surface 332 of the corner insulating spacer 330 may directly contact at least a portion of the sidewall 320S of the gate 320. The second surface 334 may directly contact a portion of the active region 304X.

The first surface 332 of the corner insulating spacer 330 covers the sidewall 320S of the gate 320 to a first height HC1 smaller than the height HCG of the sidewall 320S. However, the technical spirit of the present invention is not limited to this. For example, the first surface 332 of the corner insulating spacer 330 covers the side walls 320S at various heights within a range not exceeding the height HCG of the side walls 320S of the gate 320. Can be.

An outer insulating spacer 340 is formed on the corner insulating spacer 330. The outer insulating spacer 340 may extend on the device isolation layer 306 to a second height HC2 greater than the first height HC1. 7A and 7B illustrate that the second height HC2 of the outer insulating spacer 340 is higher than the upper surface of the gate 320 and reaches a level lower than the upper surface of the insulating capping layer 322. The technical idea is not limited to this. For example, the second height HC2 of the outer insulating spacer 340 is necessary within a range between the first height HC1 of the corner insulating spacer 330 and the height of the top surface of the insulating capping layer 322. It can be selected accordingly.

The outer insulating spacer 340 may cover a portion of the sidewalls 320S of the gate 320 that are not covered by the corner insulating spacer 330. The outer insulating spacer 340 may have a surface that directly contacts a portion of the sidewalls 320S of the gate 320 that is not covered by the corner insulating spacer 330. In some embodiments, when the sidewall 320S of the gate 320 is completely covered by a corner insulating spacer 330, the outer insulating spacer 340 is an insulating capping layer above the corner insulating spacer 330 ( 322) may be covered.

The outer insulating spacer 340 has a dielectric constant smaller than that of the corner insulating spacer 330.

For more details of the corner insulating spacer 330 and the outer insulating spacer 340, refer to the description of the corner insulating spacer 130 and the outer insulating spacer 140 with reference to FIG. 1.

Each of the corner insulating spacers 330 has a horizontal separation distance L3 (see FIG. 7B) from the sidewall 320S of the gate 320 to the outer wall of the outer insulating spacer 340 along the sidewall of the active region 304X. It has a small width (CW3) (see Fig. 7A). The corner insulating spacer 330 covers the device isolation layer 306 by a width CW3 within a distance corresponding to the horizontal separation distance L3 from the sidewall 320S of the gate 320.

In some embodiments, the horizontal width CW3 of the corner insulating spacer 330 is within a range from the sidewall 320S of the gate 320 to a distance of 1/2 of the horizontal separation distance L3. Can be selected.

In FIG. 7B, the source / drain region 310 is illustrated as extending to the epitaxy semiconductor layer 304EP and the lower portion and the lower portion of the outer insulating spacer 330, but the technical spirit of the present invention is limited to the illustrated example. It is not.

In the semiconductor device 300A illustrated in FIGS. 7A and 7B, the active area 304X, the gate 320, and the device isolation layer 306 among the insulating spacer regions extending along the sidewalls 320S of the gate 320 A corner insulating spacer 330 made of an insulating material having a relatively high dielectric constant is disposed in the inner portion of the concave corner portion C3 formed between the. Therefore, it is possible to suppress the occurrence of fringing capacitance in the semiconductor device 300A, improve the "ON" current characteristic and the "OFF" current characteristic of the transistor, and prevent the performance of the transistor from deteriorating. can do. In addition, an outer insulating spacer 340 made of an insulating material having a smaller dielectric constant than the corner insulating spacer 330 is formed on an outer portion of the insulating spacer region formed in the concave corner portion C3. Therefore, parasitic capacitance is reduced in the semiconductor device 300A, thereby improving the operation speed of the transistor and reducing power consumption.

8A to 8G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept according to a process sequence. In this example, a process for manufacturing the semiconductor device 300A illustrated in FIGS. 7A and 7B will be described as an example. 8A to 8G, the same reference numerals as in FIGS. 7A and 7B denote the same members, and thus detailed descriptions thereof will be omitted here.

Referring to FIG. 8A, a trench 303 for device isolation is formed on the substrate 302, and a plurality of pins protruding upward from the substrate 302 and extending in one direction (eg, Z direction in FIG. 8A) The active region 304X is formed. The plurality of fin-type active regions 304X may include P-type or N-type impurity diffusion regions.

Thereafter, after filling the plurality of device isolation trenches 303 and forming an insulating layer covering the plurality of active regions 304X, the insulating layer remains only below the plurality of device isolation trenches 303. The insulating film is etched back to form a plurality of device isolation films 306 filling a part of the plurality of device isolation trenches 303. As a result, the plurality of active regions 304X protrude above the upper surfaces of the plurality of device isolation layers 306 and are exposed outside the device isolation layer 306.

The plurality of device isolation layers 306 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, or a combination thereof. The plurality of device isolation layers 306 may include an insulating liner (not shown) made of a thermal oxide film and a buried insulating layer (not shown) filling the lower portion of the trench 303 on the insulating liner.

Referring to FIG. 8B, a dielectric layer 324L covering the device isolation layer 306 and the active region 304X is formed on the substrate 302, and a conductive layer 320L having a planarized top surface is formed on the dielectric layer 324L. To form.

Details of the dielectric layer 324L and the conductive layer 320L are as described for the dielectric layer 224L and the conductive layer 220L with reference to FIG. 5B.

Thereafter, an insulating capping layer 322 is formed on the conductive layer 320L using a photolithography process. The insulating capping layer 322 is formed to cover an area on which the gate 320 (see FIG. 8C) is to be formed on the top surface of the conductive layer 320L.

Referring to FIG. 8C, the gate layer 320 and the gate dielectric layer 324 are etched by sequentially etching the conductive layer 320L and the dielectric layer 324L illustrated in FIG. 8B using the insulating capping layer 322 as an etching mask. To form.

The gate 320 extends in a direction intersecting with the extending direction of the active region 304X (Y direction in FIG. 8C). In some embodiments, the gate 320 may be formed to have a line width WL3 of about 10 to 30 nm, but is not limited thereto.

Concave corners C3 are provided on both sides of the gate 320 between the sidewall of the gate 320, the active region 304X, and the device isolation layer 306, respectively. The gate dielectric layer 324 is exposed in the concave corner portion C3.

Referring to FIG. 8D, in a similar manner as described with reference to FIG. 5E, a corner insulating spacer 330 covering a portion of the sidewall 320S of the gate 320 is formed in the concave corner portion C3.

The corner insulating spacer 330 may be selected to have a width (CW3) selected within a range of about 1 to 20 nm, and a height (CH3) selected within a range of about 3 to 60 nm, but is not limited thereto. It does not work. The height CH3 of the corner insulating spacer 330 may correspond to the first height HC1 illustrated in FIG. 7A.

Referring to FIG. 8E, in an analogous manner to that described with reference to FIG. 5F, an outer insulating spacer 340 covering the corner insulating spacer 330 is formed in a concave corner portion C3.

The outer insulating spacer 340 is made of a material having a dielectric constant smaller than that of the constituent material of the corner insulating spacer 330.

The width OW3 of the outer insulating spacer 340 is greater than the width CW3 of the corner insulating spacer 330, and the height OH3 of the outer insulating spacer 340 is the height of the corner insulating spacer 330. Higher than (CH3). The height OH3 of the outer insulating spacer 340 may correspond to the second height HC2 illustrated in FIG. 7A.

Referring to FIG. 8F, an epitaxial semiconductor layer 304EP is formed on an exposed surface of the active region 304X illustrated in FIG. 8E to form a semiconductor fin (consisting of the active region 304X and the epitaxial semiconductor layer 304EP) 304).

More details of the epitaxial semiconductor layer 304EP and its formation method are substantially the same as described for the epitaxial semiconductor layer 310EP with reference to FIG. 5G.

Since the semiconductor fin 304 includes an epitaxial semiconductor layer 304EP, a source / drain region formed in the semiconductor fin 304 may have a raised source / drain (RSD) structure.

Referring to FIG. 8G, impurity ions (IIP3) are injected into the semiconductor fin 304 using the insulating capping layer 322 and the outer insulating spacer 340 as an ion implantation mask, so that semiconductors are formed on both sides of the gate 320. A source / drain region 310 is formed in the fin 304.

Although not shown, in order to reduce the resistance in the source / drain region 310, similar to that described with reference to FIG. 5H, a salicide process is performed on the surface of the source / drain region 310 to form a metal silicide film. You can.

Subsequently, the corner insulating spacer 330, the outer insulating spacer 340, and the pair of source / drain regions 310 are processed using processes similar to those described with reference to FIGS. 5I to 5K. The formed result may be covered with an interlayer insulating film to perform a conventional contact forming process.

9 is a perspective view illustrating a main configuration of a semiconductor device 300B according to embodiments of the inventive concept.

The semiconductor device 300B has substantially the same configuration as the semiconductor device 300A illustrated in FIGS. 7A and 7B, except that it includes two semiconductor pins 304. Although two semiconductor fins 304 are illustrated in FIG. 9, three or more semiconductor fins 304 may be included as required in the design.

10 is a plan view of the memory module 400 according to the technical spirit of the present invention.

The memory module 400 includes a module substrate 410 and a plurality of semiconductor chips 420 attached to the module substrate 410.

The semiconductor chip 420 includes a semiconductor device according to the technical idea of the present invention. The semiconductor chip 420 includes at least one semiconductor device among the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

One side of the module substrate 410 is provided with a connection portion 430 that can be fitted into a socket of the motherboard. A ceramic decoupling capacitor 440 is disposed on the module substrate 410. The memory module 400 according to the present invention is not limited to the configuration illustrated in FIG. 10 and may be manufactured in various forms.

11 is a schematic block diagram of a display driver IC (DDI) 500 and a display device 520 including the DDI 500 according to embodiments of the inventive concept.

Referring to FIG. 11, the DDI 500 includes a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508 ). The control unit 502 receives and decodes an instruction applied from the main processing unit (MPU) 522, and controls each block of the DDI 500 to implement an operation according to the instruction. The power supply circuit unit 504 generates a driving voltage in response to the control of the control unit 502. The driver block 506 drives the display panel 524 using the driving voltage generated by the power supply circuit unit 504 in response to control of the control unit 502. The display panel 524 may be a liquid crystal display panel or a plasma display panel. The memory block 508 is a block that temporarily stores commands input to the control unit 502 or control signals output from the control unit 502 or stores necessary data, and may include memory such as RAM and ROM. At least one of the power supply circuit portion 504 and the driver block 506 includes at least one semiconductor element among the semiconductor elements 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

12 is a circuit diagram of a CMOS inverter 600 according to embodiments of the inventive concept.

The CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a PMOS transistor 620 and an NMOS transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 includes at least one of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

13 is a circuit diagram of a CMOS SRAM device 700 according to embodiments of the inventive concept.

The CMOS SRAM device 700 includes a pair of driving transistors 710. Each of the pair of driving transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power terminal Vdd and a ground terminal. The CMOS SRAM device 700 further includes a pair of transfer transistors 740. The source of the transfer transistor 740 is cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 constituting the driving transistor 710. A power terminal Vdd is connected to the source of the PMOS transistor 720, and a ground terminal is connected to the source of the NMOS transistor 730. A word line WL is connected to a gate of the pair of transfer transistors 740, and a bit line BL and an inverted bit line are connected to drains of each of the pair of transfer transistors 740.

At least one of the driving transistor 710 and the transmission transistor 740 of the CMOS SRAM device 700 is at least one of the semiconductor devices 100A, 100B, 200A, 200B, 300A, 300B illustrated in FIGS. 1 to 9. And semiconductor devices.

14 is a circuit diagram of a CMOS NAND circuit 800 according to embodiments of the inventive concept.

The CMOS NAND circuit 800 includes a pair of CMOS transistors through which different input signals are transmitted. The CMOS NAND circuit 800 includes at least one of the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

15 is a block diagram illustrating an electronic system 900 according to embodiments of the inventive concept.

The electronic system 900 includes a memory 910 and a memory controller 920. The memory controller 920 controls the memory 910 to read data from the memory 910 and / or write data to the memory 910 in response to a request from the host 930. At least one of the memory 910 and the memory controller 920 includes at least one semiconductor element among the semiconductor elements 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

16 is a block diagram of an electronic system 1000 according to embodiments of the inventive concept.

The electronic system 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and an interface 1040, each of which is interconnected through a bus 1050.

The controller 1010 may include at least one of a microprocessor, a digital signal processor, or similar processing devices. The input / output device 1020 may include at least one of a keypad, a keyboard, or a display. The memory 1030 may be used to store instructions executed by the controller 1010. For example, the memory 1030 may be used to store user data.

The electronic system 1000 may configure a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. In order to transmit / receive data through the wireless communication network in the electronic system 1000, the interface 1040 may be configured as a wireless interface. The interface 1040 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic system 1000 is a third generation communication system, such as code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), E-TDMA (extended-time division multiple access), and / or wide band code division multiple access (WCDMA). The electronic system 1000 includes at least one semiconductor device among the semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B illustrated in FIGS. 1 to 9.

As described above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention This is possible.

102: semiconductor substrate, 106: active region, 110: source / drain region, 112: channel region, 120: gate, 120S: sidewall, 122: insulating capping layer, 124: gate dielectric film, 130: corner insulating spacer, 140: outer Insulation spacer, 202: substrate, 204: semiconductor fin, 206: buried insulating layer, 208: SOI wafer, 210: source / drain region, 212: channel region, 220: gate, 220S: sidewall, 222: insulating capping layer, 224 : Gate dielectric film, 230: corner insulating spacer, 240: outer insulating spacer, 302: substrate, 304: semiconductor layer, 306: device isolation film, 310: source / drain region, 312: channel region, 320: gate, 320S: sidewall, 322: insulating capping layer, 324: gate dielectric film, 330: corner insulating spacer, 340: outer insulating spacer.

Claims (10)

A semiconductor layer extending in a first direction with a pair of source / drain regions and a channel region extending between the pair of source / drain regions;
A gate extending in a second direction on the semiconductor layer to cover the channel region;
A gate dielectric layer interposed between the channel region and the gate,
An insulating capping layer covering the top surface of the gate,
A corner insulation spacer extending in the second direction along the sidewall of the gate and having a first surface covering at least a portion of the sidewall of the gate from one side of the gate dielectric film and a second surface covering a portion of the semiconductor layer;
A sidewall of the gate over the corner insulating spacer, and including an outer insulating spacer having a dielectric constant smaller than that of the corner insulating spacer,
The pair of source / drain regions each include a source / drain extension region having a first impurity doping concentration, and a deep source / drain region having a second impurity doping concentration higher than the first impurity doping concentration,
The outer insulating spacer has a surface contacting a sidewall of the insulating capping layer and a surface contacting the source / drain extension region. According to claim 1,
The sidewall of the gate has a first height,
And a first surface of the corner insulating spacer covers a sidewall of the gate to a second height smaller than the first height. According to claim 1,
The semiconductor layer is part of the bulk semiconductor substrate,
The corner insulating spacer extends along a sidewall of the gate at a reentrant corner portion formed between the gate and the pair of source / drain regions. According to claim 1,
Further comprising a semiconductor substrate disposed under the gate,
The semiconductor layer includes a semiconductor fin protruding from the semiconductor substrate and extending in a first direction. The method of claim 4,
On the semiconductor substrate further comprises a device isolation layer that contacts both sidewalls of the semiconductor fin and has an upper surface with a lower level than the upper surface of the semiconductor fin,
The gate extends in the second direction on the semiconductor fin and the device isolation layer,
The corner insulating spacer extends along the sidewall of the gate from the semiconductor fin at a concave corner formed between the gate, the semiconductor fin, and the device isolation layer. According to claim 1,
A substrate disposed under the gate,
Further comprising a buried insulating layer interposed between the substrate and the gate,
The semiconductor layer comprises a semiconductor fin extending in the first direction on the buried insulating layer and having a base portion contacting the buried insulating layer. The method of claim 6,
The gate extends in the second direction on the semiconductor fin and the buried insulating layer,
The corner insulation spacer extends along the sidewall of the gate from the semiconductor fin at a concave corner portion formed between the gate, the semiconductor fin, and the buried insulation layer. According to claim 1,
And the corner insulating spacer covers the source / drain extension region by a width smaller than a horizontal separation distance between the gate and the deep source / drain region from the sidewall of the gate. A semiconductor layer extending in a first direction with a pair of source / drain regions and a channel region extending between the pair of source / drain regions;
An insulating layer covering at least a portion of the semiconductor layer,
A gate extending in a second direction crossing the semiconductor layer on the channel region and the insulating layer;
A gate dielectric layer interposed between the channel region and the gate,
An insulating capping layer covering the top surface of the gate,
A corner insulating spacer extending from the semiconductor layer along a sidewall of the gate and having a first surface covering at least a portion of the sidewall of the gate and a second surface covering a portion of the semiconductor layer;
A sidewall of the gate over the corner insulating spacer, and including an outer insulating spacer having a dielectric constant smaller than that of the corner insulating spacer,
The pair of source / drain regions each include a source / drain extension region having a first impurity doping concentration, and a deep source / drain region having a second impurity doping concentration higher than the first impurity doping concentration,
The outer insulating spacer has a surface contacting a sidewall of the insulating capping layer and a surface contacting the source / drain extension region. The method of claim 9,
The corner insulating spacer has a width smaller than a horizontal separation distance from the side wall of the gate to the outer wall of the outer insulating spacer along the first direction.

Images