KR20170103657A - Systems and methods for using one or more fixtures and efficiency to determine parameters of a match network model - Google Patents

Abstract

Disclosed are systems and methods for using at least one fixture and efficiency to determine parameters of a matching network model. The methods comprises: comparing a value of efficiency measured by using a network analyzer with a predicted value of efficiency determined by using a matching network model; and performing a comparison to determine whether fixed parameters are assigned to the matching network model.

Description

FIELD OF THE INVENTION The present invention relates to systems and methods for using one or more fixtures and efficiencies to determine parameters of a matching network model. ≪ RTI ID = 0.0 > [0001] < / RTI >

The embodiments relate to systems and methods for using one or more fixtures and efficiencies to determine parameters of a matching network model.

Plasma systems are used to control plasma processes. The plasma system includes a plurality of radio frequency (RF) sources, impedance matching, and a plasma reactor. The workpiece is positioned within the plasma chamber and the plasma is generated in the plasma chamber to process the product. It is important that the workpiece is processed in a similar or uniform manner independently of the replacement or use of a portion of the plasma system with other portions of the plasma system. For example, if a portion of the plasma system is replaced with another portion, the workpiece is processed differently.

The embodiments described in this disclosure appear in this context.

The disclosed embodiments provide apparatus, methods and computer programs for using one or more fixtures and efficiencies to determine parameters of a matching network model. It should be appreciated that the embodiments may be implemented in numerous ways, for example, in a process, an apparatus, a system, a portion of hardware, or a method on a computer-readable medium. Some embodiments are described below.

A radio frequency (RF) matching network model is a computer representation or mathematical representation of a physical impedance matching network and is used to derive RF characteristics at the output of the impedance matching network from measurements of RF characteristics at the input of the impedance matching network, And phase of the signal. As a starting point, the matching network model has a modular form including various modules. Examples of modules are provided in a patent application having Application Serial No. 14 / 245,803. Each of the modules includes one or more circuit elements. The values of the circuit elements in the modules are based on known values of the capacitance and inductance from the schematic of the impedance matching network and are based on approximations of some physical quantities such as the inductance of the connection straps that are not included in the conceptual diagram . The starting point of the matching network model is improved by adjusting the values of the circuit elements to create a set of experimental measurements and to provide a fit between the predictions and measurements of the matching network model. One way to obtain experimental measurements is to use wafers in a plasma tool. During on-tool measurements, a high-accuracy RF voltage and current probe is used to perform various plasma recipes and to measure the RF voltage and current measured at the output of the impedance matching network for each of the recipes And is temporarily installed at the output of the impedance matching network implemented in the plasma tool to vary the values of the circuit elements in the modules of the matching network model to provide fitting between predictions and measurements.

However, on-tool measurements where tool time is occupied using plasma tools are time consuming. By using high-accurate RF voltage and current probes, the reference values of the matching network model are generated for each of the impedance matching networks. However, each individual matching network having a particular serial number and model number is slightly different from any other individual matching network having another serial number and the same model number. The use of high-accuracy RF voltage and current probes is performed on approximately six individual matching networks that take several weeks.

When a criterion matching model is present, more accurate models for individual matching networks are created using bench network analyzer measurements obtained for each matching network. Measurements are sometimes obtained by attaching a physical test fixture, referred to herein as a load impedance fixture, to the output of the impedance matching network under test and by using a network analyzer to obtain measurements at the input of the impedance matching network . The load impedance fixture is designed to have the same impedance as one of the plurality of plasma conditions so that the measurements by the network analyzer mimics the measurements of many on-tool tests. The matching network model is adjusted for the impedance matching network based on the measurements obtained using the load impedance fixture to produce a more accurate result when the reference model is applied to the impedance matching network.

It should be noted that the plasma impedance varies with various RF generators, such as 2 MHz, 27 MHz, 60 MHz, 400 KHz, and the like. That is, in some embodiments, for multi-frequency plasma systems where more than two of the 400 kHz, 2 MHz, 27 MHz and 60 MHz RF generators are used, the impedances of the plasma at different frequencies of the RF generators are different.

In various embodiments, different load impedance fixtures are used for different frequencies. For example, a first load impedance fixture is used for 2 MHz, a second load impedance fixture is used for 27 MHz, and a third load impedance fixture is used for 60 MHz.

In some embodiments, a plurality of sets of bench-top fixtures, sometimes referred to herein as load impedance fixtures, are used to resemble a plurality of on-tool plasma conditions to obtain a plurality of network analyzer measurements. do. A plurality of network analyzer measurements using a plurality of bench-top fixtures are used to generate reference values of the matching network model without having to run on the wafers on the plasma tool with the plasma, which is the on- - saves time associated with line tool resources. Multiple bench-top fixtures are not expensive. The plurality of bench-top fixtures are made from resistors, or capacitors, or inductors, or cables, or a combination of two or more thereof. For example, one of the fixtures includes a resistor and a variable length coaxial cable. Each of the plurality of bench-top fixtures is connected in series with the output of the impedance matching network and one or more values of the combined variable capacitance of the impedance matching network and network analyzer measurements associated with the input of the matching network at the RF frequency are obtained. The values of the circuit elements of the matching network model are optimized to obtain an agreement between the network analyzer measurements and the predicted values generated from the network analyzer measurements without using the plasma.

In various embodiments, the efficiency is measured using a load impedance fixture and network analyzer, the efficiency is predicted using a matching network model, the agreement is made between the predicted efficiency and the measured efficiency to determine the parameters of the matching network model . The use of efficiencies provides an accurate determination of the parameters. In addition, as described above, plasma tools, e.g., plasma chambers, etc., are not used to calculate efficiencies. Unprecedented use of such a plasma tool saves tool time.

In some embodiments, a match between the predicted impedances and the measured impedances using the plurality of bench-top fixtures using the matching network model, and the agreement between the predicted and measured efficiencies, . The use of efficiencies and impedances results in an accurate determination of the parameters.

Some of the advantages of the systems and methods described herein include that the matching network model is created and identified on a test bench without having to use wafers and tool time. Additional advantages of the systems and methods described herein include covering a wide range of plasma conditions using a plurality of fixtures over a range covered using actual different recipes in a plasma tool. The matching network model is accurate for the range of RF frequencies and impedance tuning network variable capacitances that the test wafers are to be processed, when generated using a plasma tool. If the future new process uses different variable capacitances or different RF frequencies, the matching network model will not be as accurate for different variable capacitances and different RF frequencies as well. By using a plurality of fixtures, a wide range of plasma conditions are resembled so that the matching network model is created to be used with wide-bladed plasma conditions. Also, a plurality of fixtures are relatively inexpensive to manufacture.

An additional benefit includes using the measured efficiency and the predicted efficiency to determine the parameters of the matching network model. The use of efficiencies results in a precise determination of the parameters.

Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

The embodiments are understood with reference to the following description taken in conjunction with the accompanying drawings.
Figure 1a illustrates the determination of one or more variable capacitances of an impedance matching network for use of one or more variable capacitances and one or more variable frequencies in a matching network model and the determination of one or more variable frequencies of a network analyzer connected to load impedance fixture 1 It is leading.
1B illustrates the determination of one or more variable capacitances of an impedance matching network for use of one or more variable capacitances and one or more variable frequencies in a matching network model and the determination of one or more variable frequencies of a network analyzer connected to the load impedance fixture N It is leading.
2A is a diagram illustrating various embodiments of a load impedance fixture.
2B is an example graph illustrating the achievement of various plasma conditions with the use of a load impedance fixture 1 through a load impedance fixture N. FIG.
Figure 3 is a diagram of an embodiment of a host computer system for illustrating determination of fixed parameters of a matching network model.
4 is a diagram of an embodiment of a system for illustrating determination of measured efficiency of an impedance matching network.
5 is a diagram of an embodiment of a host computer system illustrating the determination of the values of fixed parameters based on the measured efficiency when the predicted efficiency and impedance matching network is connected to the load impedance fixture 1. [
6 is a flowchart of an embodiment of a method for determining fixed parameters by using impedances and efficiencies.
7 is a diagram of an embodiment of a system for illustrating the determination of measured efficiency of an impedance matching network when an impedance matching network is connected to a load impedance fixture N. Fig.
8 is a diagram illustrating a method performed by the host computer system to determine the values of the fixed parameters based on the measured efficiency when the predicted efficiency and impedance matching network is connected to the load impedance fixture N. [
9 is a flowchart of an embodiment of a method for determining fixed parameters by using impedances and efficiencies.
10 is a diagram of an embodiment of a plasma system for illustrating the use of a matching network model in a plasma system.
11 is a block diagram of an embodiment of a matching network model.

The following embodiments describe systems and methods for using one or more fixtures and efficiencies to determine parameters of a matching network model. It will be apparent that the embodiments may be practiced without some or all of the specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the embodiments.

In various embodiments, the efficiency is measured using a network analyzer and the efficiency is predicted using a matching network model. It is determined whether there is a level of agreement between the measured efficiency and the predicted efficiency. When it is determined that there is a match, the parameters determined based on the predicted efficiency are assigned to the matching network model. Otherwise, the parameters change until a match is reached. The changed parameters are then assigned to the matching network model.

FIG. 1A illustrates the determination of one or more variable capacitances of the impedance matching network 1 for use of one or more variable capacitances and one or more variable frequencies in a matching network model and the determination of one or more variable frequencies of the network analyzer 102 connected to the load impedance fixture 1 It is a diagram illustrating the decision. In some embodiments, the network analyzer 102 is a measurement device for measuring s-parameters of electrical networks coupled to the network analyzer 102. For example, the network analyzer 102 measures the transmission parameters of the reflective and electrical networks, e.g., impedance, reflection coefficient, voltage standing wave ratio, and the like.

In some embodiments, the network analyzer includes a signal generator, one or more sensors, and a display screen, as used herein. The signal generator generates the RF signal, one or more sensors sense the s-parameter, and the display screen displays the s-parameter.

The network analyzer 102 is connected from the output 113 of the network analyzer to the input 1111 of the load impedance fixture 1 via the RF cable 104. The load impedance fixture 1 has an impedance representing a plasma condition, for example, an impedance in a plasma chamber, and the like. The network analyzer 102 generates an RF signal having a frequency f11 and provides an RF signal to the load impedance fixture 1 through an output unit 113, an RF cable 104, and an input unit 1111. [ When an RF signal having a frequency f11 is provided to the load impedance fixture 1, the load impedance Zo1m is measured at the input 1111 of the load impedance fixture 1.

The network analyzer 102 is disconnected from the load impedance fixture 1 and then is connected to the input of the branch circuit of the impedance matching network 1 at the output 113 of the network analyzer 102 via the RF cable 106 (Not shown). For example, the branch circuit is connected to the x ㎒ RF generator or to the y ㎒ RF generator or to the z ㎒ RF generator during the processing of the wafer. The branch circuit is one of a plurality of branch circuits when a plurality of RF generators are used. For example, when x MHz and y MHz RF generators are used, two branch circuits are implemented in the impedance matching network 1. One of the two branch circuits is connected to the output of the x ㎒ RF generator and the other of the two branch circuits is connected to the output of the y ㎒ RF generator. The outputs of the two branch circuits are connected together and connected to an RF transmission line or load impedance fixture. In some embodiments, an example of an x MHz RF generator includes a 2 MHz RF generator, an example of a y MHz RF generator includes a 27 MHz RF generator, and an example of a z MHz RF generator includes a 60 MHz RF generator do. In various embodiments, an example of an x MHz RF generator includes a 400 MHz RF generator, an example of a y MHz RF generator includes a 27 MHz RF generator, and an example of a z MHz RF generator includes a 60 MHz RF generator do.

Each of the branch circuits of the impedance matching network 1 includes one or more inductors, or one or more capacitors, or one or more resistors, or a combination thereof. For example, the branch circuit of the impedance matching network 1 includes a series circuit including an inductor coupled in series with a capacitor. The branch circuit of the impedance matching network 1 further includes a shunt circuit connected to the series circuit. The shunt circuit includes a capacitor connected in series with the inductor. The branch circuit of the impedance matching network 1 comprises one or more capacitors and the corresponding capacitances of the one or more capacitors are variable during the processing of the wafer, for example using a drive assembly or the like. For example, the processor of the host computer system 112 may determine the location of one or both plates of the variable capacitor of the impedance matching network 1 so as to vary the area between the two plates to further vary the capacitance of the variable capacitor to achieve a certain capacitance To the drive assembly. The combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to a value C11. For example, the positions of corresponding oppositely-located plates of one or more variable capacitors are adjusted to be set to variable capacitance C11. For purposes of illustration, the combined capacitance of two or more capacitors connected in parallel is the sum of the capacitances of the capacitors. As another example, the combined capacitance of two or more capacitors connected in series is the reciprocal of the sum of the reciprocals of the capacitances of the capacitors. As another example, the processor of the host computer system 112 controls the drive assembly to move the plates of the variable capacitor of the impedance matching network 1 to achieve the capacitance C11, as described further below. An example of an impedance matching network 1 is provided in a patent application having application Ser. No. 14 / 716,797.

The impedance matching network 1 is also connected to the input 1111 of the load impedance fixture 1 at the output 109 of the impedance matching network 1, which is the output of the branch circuit via the RF cable 108. The branching circuit is connected from the input section 107 to the output section 113. In addition, the combined variable capacitance of the impedance matching network 1 is set to the value C11. The load impedance fixture 1 has an impedance representing a plasma condition, for example, an impedance in the plasma chamber. The network analyzer 102 generates an RF signal having a frequency f11 and provides an RF signal to the impedance matching network 1 through an output unit 113, an RF cable 106, and an input unit 107. [ The impedance matching network 1 matches the impedance of the load connected to the impedance matching network 1 to the impedance of the source connected to the impedance matching network 1 to generate a modified signal which is an RF signal. Examples of loads include a load impedance fixture 1 and an RF cable 108, and examples of sources include a network analyzer 102 and an RF cable 106. The changed signal is supplied from the impedance matching network 1 to the load impedance fixture 1 through the output unit 109 and the input unit 1111. [ When supplied by the network analyzer 102 via the RF cable 106 to the impedance matching network 1 having the variable capacitance C11 coupled with the RF signal, the input impedance Zi1m at the input 107 of the impedance matching network 1 ) Is measured by the network analyzer 102. The impedance used herein is a complex value. For example, the impedance Z is a complex value R + jX where R is resistance, X is reactance, and j is a complex number.

The network analyzer 102 is coupled to the host computer system 112 via a network cable 110, including a processor and a memory device. Examples of the host computer system 112 include a laptop computer or a desktop computer or a tablet or smart phone. As used herein, a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), or a programmable logic device (PLD) is used in place of the processor and these terms are used interchangeably herein do. Examples of memory devices include read-only memory (ROM), random access memory (RAM), hard disk, volatile memory, non-volatile memory, redundant arrays of storage disks, And the like. Examples of network cables used herein are cables used to transfer data in a serial manner, in a parallel manner, or using a Universal Serial Bus (USB) protocol or the like.

The processor of the host computer system 112 receives the measured input impedance Zi1m from the network analyzer 102 via the network cable 110. [ The processor may determine that at operation 132 of method 130 the measured input impedance Zi1m is less than a predetermined threshold of pre-determined impedance, e.g., 50, 55, 60, Ω and the like. In some embodiments, the pre-determined threshold and the pre-determined impedance are received as input by a processor from a user via an input device, as described further below, and within a memory device of the host computer system 112, Lt; / RTI > In some embodiments, the pre-determined threshold and the pre-determined impedance are received by the processor before the time measured by the network analyzer 102, such as input impedance, e.g., Zi1m. If the measured input impedance Zi1m is within a pre-determined threshold of the pre-determined impedance, the processor determines at operation 134 of method 130 whether the frequency f11 and / And stores the variable capacitance C11.

If, on the other hand, the measured input impedance Zi1m is not within a pre-determined threshold of the pre-determined impedance, the processor determines, at operation 136 of method 130, a pre-determined weight for frequency f11 And decides to assign a pre-determined weight to the variable capacitance C11. For example, the pre-determined weight is assigned by the processor at frequency f11 to produce the weighted frequency fw11 and the pre-determined weight is applied to the processor at variable capacitance C11 to produce a weighted capacitance Cw11 And the sum of the weighted frequency fw11 and the sum of other weighted frequencies fww11 and the weighted capacitance Cw11 and the sum of the weighted capacitances Cww11 and Scw1 is calculated by the following processor Generated and used. A lower weight than the other capacitance Co11 is assigned to the capacitance C11 and a lower weight is assigned to the frequency f11 in comparison with the other frequency fo11. Another weighted capacitance Cww11 is generated by the processor by assigning a weight to the other capacitance Co11 and another weighted frequency fww11 is generated by the processor by assigning a weight to the other frequency fo11. The other frequency fo11 and the other capacitance Co11 are those whose impedance measured at the input 107 of the impedance matching network 1 is within the threshold of a pre-determined impedance. As another example, a weight of 0 is assigned to the variable capacitance C11 and a weight of 0 is assigned to the frequency f11. As another example, variable capacitance C11 and frequency f11 are not stored in the memory device of host computer system 112 for later use.

When assigning a pre-determined weight to frequency f11 and assigning a pre-determined weight to variable capacitance C11, operation 138 of method 130 is performed. For example, if the network analyzer 102 determines that Q is an integer greater than 0 and the input impedance Zi1Qm measured at the input 107 of the impedance matching network 1 is within a pre-determined threshold of the pre-determined impedance The frequency of the generated RF signal is changed from, for example, f11 to f12, f12 to f13, and / or the combined variable capacitance of the impedance matching network 1 is changed from, for example, C11 to C12, And so on. For example, the network analyzer 102 changes the frequency of the RF signal from f11 to f12, and the variable capacitance C11 is not changed. The input impedance Zi1Qm measured by the network analyzer 102 is within a pre-determined threshold of a pre-determined impedance. The processor stores frequency (f12) and variable capacitance (C11) in the memory device. As another example, the variable capacitance C11 of the impedance matching network 1 changes from C11 to C12. For example, the drive assembly controls the plates of the variable capacitors of the impedance matching network 1 to change the variable capacitance of the variable capacitors so that the combined variable capacitance of all the variable capacitors of the impedance matching network 1 is C12. When the network analyzer supplies an RF signal having a frequency f11 to the impedance matching network 1, the network analyzer measures the impedance Zi1Qm at the input 107 of the impedance matching network 1 and the processor determines that the impedance Zi1Qm is pre- Is determined to be within a pre-determined threshold value from the determined impedance. The frequency f11 and the variable capacitance C12 are stored in the memory device. In this manner, a plurality of frequencies f1n and a plurality of capacitances C1n, whose impedances Zi1Qm are within a pre-determined threshold and n is an integer greater than zero, and a plurality of capacitances C1n are calculated and stored in the memory device.

1B illustrates the determination of one or more variable frequencies of a network analyzer 102 coupled to a load impedance fix N that is an integer greater than one and an impedance matching network 1 for use of one or more variable capacitances and one or more variable frequencies in a matching network model. Lt; RTI ID = 0.0 > of < / RTI > one or more variable capacitances. The network analyzer 102 is disconnected from the load impedance fixture 1 and connected to the input 111N of the load impedance fixture N via the RF cable 104 at the output 113 of the network analyzer 102. [ The load impedance fixture N has an impedance representing the plasma condition, which is different from the plasma condition exhibited by the load impedance fixture 1. For example, the load impedance fixture N has an impedance that is different from the impedance of the load impedance fixture 1. The network analyzer 102 generates an RF signal having a frequency fN1 and provides an RF signal to the load impedance fix N through the output 113, the RF cable 104, and the input 111N. When an RF signal is provided to the load impedance fixture N, the load impedance ZoNm is measured at the input 111N of the load impedance fixture N. [

It should be noted that the values (Zo1m and ZoNm) are not constant values. For example, the value Zo1m varies with the RF frequency of the operation of the load impedance fixture 1 and the value ZoNm varies with the RF frequency of the operation of the load impedance fixture N. [

The network analyzer 102 is disconnected from the load impedance fixture 1 and connected to the input 107 of the branch circuit of the impedance matching network 1 via the RF cable 106 and the output 109 of the branch circuit is connected to the RF cable 108 to the input 111N of the load impedance fixture N. [ The load impedance fixture N has an impedance representing the plasma condition, which is different from the plasma condition exhibited by the load impedance fixture 1. For example, the load impedance fixture N has an impedance that is different from the impedance of the load impedance fixture 1.

The combined variable capacitance of the one or more variable capacitors of the impedance matching network 1 is adjusted through the drive assembly to achieve the value CNl. The network analyzer 102 generates an RF signal having a frequency fN1 and supplies an RF signal to the impedance matching network 1 through an output unit 113, an RF cable 106, and an input unit 107. [ The impedance matching network 1 matches the impedance of the load connected to the impedance matching network 1 to the impedance of the source connected to the impedance matching network 1 to generate a modified signal which is an RF signal. Examples of loads include a load impedance fixture N and an RF cable 108, and examples of sources include a network analyzer 102 and an RF cable 106. The changed signal is provided from the impedance matching network 1 to the load impedance fixture N via the output unit 109, the RF cable 108, and the input unit 111N. When the RF signal having the frequency fN1 is supplied to the branch circuit of the impedance matching network 1 through the RF cable 106 and the combined variable capacitance of the impedance matching network 1 is CN1, the input impedance ZiNm is supplied to the impedance matching network 1 In the input unit 107 of FIG.

The processor of the host computer system 112 receives the measured input impedance ZiNm from the network analyzer 102 via the network cable 110. [ The processor determines at operation 152 of method 150 whether the measured input impedance ZiNm is within a pre-determined threshold of a pre-determined impedance. If the measured input impedance ZiNm is determined to be within a pre-determined threshold of the pre-determined impedance, then at step 154 of the method 150, the processor determines whether the frequency fN1 and / And stores the variable capacitance CN1.

If, on the other hand, it is determined that the measured input impedance ZiNm is not within a pre-determined threshold of the pre-determined impedance, the processor determines in operation 156 of method 150 that the pre- And assigns a pre-determined weight to the variable capacitance CN1. For example, the processor may assign a pre-determined weight to the variable capacitance CN1 to assign a pre-determined weight to the frequency fN1 to produce a weighted frequency fwN1 and to produce a weighted capacitance CwNl, And the sum of the weighted frequency fwN1 and another weighted frequency fwwN1 and the sum of the weighted capacitance CwN1 and another weighted capacitance CwwN1 are generated by the following processors Is used. A lower weight than the other capacitance CoN1 is assigned to the capacitance CN1 and a lower weight is assigned to the frequency fN1 as compared to the other frequency foNl. The other weighted capacitance CwwN1 is generated by the processor by assigning weights to the other capacitances CoN1 and the other weighted frequency fwwN1 is generated by the processor by assigning weights to the other frequency foNl. The other frequency foN1 and the other capacitance CoN1 are those whose impedances measured at the input 107 of the impedance matching network 1 are within the threshold of a pre-determined impedance. As another example, a weight of 0 is assigned to the variable capacitance CN1 and a weight of 0 is assigned to the frequency fN1. As another example, the variable capacitance CN1 and the frequency fN1 are not stored in the memory device of the host computer system 112 for later use.

If the pre-determined weight is assigned to frequency fN1 and the pre-determined weight is assigned to variable capacitance CN1, then operation 158 of method 150 is performed. For example, the frequency of the RF signal generated by the network analyzer 102, such that the input impedance ZiNQm measured at the input 107 of the impedance matching network 1 is within a pre-determined threshold of a pre-determined impedance, For example, from fN1 to fN2, from fN2 to fN3, and / or the combined variable capacitance of the impedance matching network 1 is changed from CN1 to CN2, CN2 to CN3, and so on. For example, the network analyzer 102 changes the frequency of the RF signal from fN1 to fN2, and the variable capacitance CN1 is not changed. The input impedance ZiNQm measured by the network analyzer 102 is within a pre-determined threshold of a pre-determined impedance. The processor stores frequency (fN2) and variable capacitance (CN1) in the memory device. As another example, the variable capacitance CN1 of the impedance matching network 1 changes from CN1 to CN2. For example, the drive assembly controls the plates of the variable capacitor of the impedance matching network 1 to change the variable capacitance of the variable capacitor such that the combined variable capacitance of all the variable capacitors of the impedance matching network 1 is CN2. When the network analyzer 102 supplies the RF signal having the frequency fN1 to the impedance matching network 1, the network analyzer 102 measures the impedance ZiNQm at the input 107 of the impedance matching network 1, (ZiNQm) is within a pre-determined threshold from a pre-determined impedance. The frequency fN1 and the variable capacitance CN2 are stored in the memory device. In this manner, a plurality of frequencies fNn and a plurality of capacitances CNn whose impedances ZiNQm are within a pre-determined threshold are calculated and stored in the memory device.

In some embodiments, any number of load impedance fixes, such as load impedance fixtures N, such as 10, 15, 20, 100, 200, 300, 1000, 10000, 100000, 1000000, The impedance at the input 107 of the branch circuit of the matching network 1 is used to determine the frequencies of the network analyzer 102 and the variable capacitances of the impedance matching network 1 that are within a pre-determined threshold of the pre-determined impedance. Each of the load impedance fixtures N resembles the different conditions of the plasma within the plasma chamber.

It should be noted that, in some embodiments, when the impedance matching network 1 is connected to the network analyzer described herein, the impedance matching network 1 is not connected to the plasma chamber, which is described further below. Moreover, in various embodiments, there is no processing of the wafers in the plasma processing chamber when the impedance matching network 1 is connected to the network analyzer described herein. This saves on-tool time using the plasma processing chamber.

2A is a diagram illustrating various embodiments of a load impedance fixture. The load impedance fixture includes a cable CB1 of length 11, a resistor R1, an inductor L1, and a capacitor C1. The resistor R1 has a resistance R1, the capacitor C1 has a capacitance C1 and the inductor L1 has an inductance L1. In some embodiments, the load impedance fixture 1 includes at least one of a cable CB1, a resistor R1, an inductor L1, and a capacitor C1. For example, the load impedance fixture 1 includes the cable CB1 and excludes the resistor R1, the inductor L1, and the capacitor C1. As another example, the load impedance fixture 1 includes an inductor L1 and a capacitor C1, and does not include a cable CB1 and a resistor R1.

The load impedance fixture N includes a cable CBN, a resistor RN, an inductor LN, and a capacitor CN of length lN. The resistor RN has a resistance RN, the capacitor CN has a capacitance CN and the inductor LN has an inductance LN. In some embodiments, the load impedance fixture N includes at least one of a cable CBN, a resistor RN, an inductor LN, and a capacitor CN. For example, the load impedance fixture N includes a cable CBN and excludes the resistor RN, the inductor LN, and the capacitor CN. As another example, the load impedance fixture N includes the inductor LN and the capacitor CN, and does not include the cable CBN and the resistor RN. As another example, the load impedance fixture N includes the inductor LN and excludes the capacitor CN, the cable CBN, and the resistor RN.

The load impedance fixture N is different from the corresponding one of the cable length l1, resistance R1, capacitance C1 and inductance L1 of the load impedance fixture 1, the cable length lN, the resistance RN, CN), and inductance (LN). For example, the resistance R1 is equal to the resistance RN, the capacitance C1 is equal to the capacitance CN, the inductance L1 is equal to the inductance LN, and the cable length L1 is equal to the cable length (LN). As another example, the resistance R1 is equal to the resistance RN, the capacitance C1 is equal to the capacitance CN, the cable length 11 is different from the cable length lN and the inductance L1 is equal to the inductance (LN). As another example, the load impedance fixture 1 includes the register R1, and the load impedance fixture N includes the register RN. As another example, the load impedance fixture 1 includes the cable CB1, and the load impedance fixture N includes the cable CBN. As another example, the resistance R1 is equal to the resistance RN, the capacitance C1 is different from the capacitance CN, the cable length 11 is equal to the cable length lN, and the inductance L1 is And is different from the inductance LN.

In some embodiments, the plasma condition is indicated using a power reflection ratio or gamma instead of an impedance. Gamma is the voltage reflection coefficient, which is the ratio of the reflected voltage to the applied voltage. Gamma is a complex number because the reflected voltage has a phase and an amplitude with respect to the supplied voltage. When the impedance matching network 1 is connected to the RF generator via an RF cable and is connected to the plasma chamber via an RF transmission line, the reflected voltage is the voltage reflected from the plasma chamber towards the RF generator, and the supplied voltage is fed from the RF generator to the impedance matching network 1 Supplied voltage. The power reflection ratio is the square of gamma. There is a one-to-one relationship between the gamma at the input of the impedance matching network 1 and the impedance at the input of the impedance matching network 1 for a 50 ohm RF cable connected to the input of the impedance matching network 1 so that the use of impedance or gamma In reality, it is a matter of convenience.

In some embodiments, the values of the registers used in the plurality of load impedance fixtures 1 through N are in the range of 0.4 OMEGA to 2 OMEGA. Note that the range of 0.4 Ω to 2 Ω is the range for the frequency of 60 ㎒. If 2 ㎒ or 27 ㎒ frequencies are used, the range will vary. In various embodiments, the coaxial cable used in load impedance fixture 1 or N is a 50 ohm cable.

2B is an example graph 250 illustrating the achievement of various plasma conditions using a load impedance fixture 1 to a load impedance fixture N. FIG. Graph 250 shows the real part of the reflection coefficient represented by gamma on the x-axis and the imaginary part of the reflection coefficient on the y-axis indicated by gamma. The top line 252 of the graph 250 shows the different frequencies of the RF signals generated by the network analyzer 102 when coupled to the load impedance fixtures 1 through N having variable length coaxial cables and resistors having a first value. And to the points measured by the network analyzer 102 for the variable capacitance C1. In addition, the bottom line 254 of the graph 250 represents the different (or substantially identical) values of the RF signals generated by the network analyzer 102 coupled to the load impedance fixtures 1 through N having variable length coaxial cables and resistors having a second value And is fitted to the points measured by network analyzer 102 for frequency and variable capacitance (CN). All points between the top line 252 and the bottom line 254 correspond to different frequencies of the RF signal generated by the network analyzer 102 coupled to the load impedance fixtures 1 through N and to the variable capacitances C1 and & And is measured by network analyzer 102 for variable capacitances between variable capacitances (CN).

3 is a diagram of an embodiment of a host computer system 112 for illustrating the determination of parameters of the matching network model 302. As shown in FIG. An example of matching network model 302 is illustrated below with reference to FIG. Matching network model 302 includes a number of modules 1 to P, where P is an integer greater than zero. Module 1 includes a fixed serial resistor R1s, a fixed series inductor L1s, and a fixed series capacitor C1s. Module 1 further includes a fixed shunt resistor R1p, a fixed shunt inductor L1p, and a fixed shunt capacitor C1p. In addition, the module 2 includes a fixed serial resistor R2s, a fixed series inductor L2s, and a fixed series capacitor C2s. Module 2 further includes a fixed shunt resistor R2p, a fixed shunt inductor L2p, and a fixed shunt capacitor C2p. Furthermore, the module 3 includes a fixed serial resistor R3s, a fixed series inductor L3s, and a fixed series capacitor C3s. Module 3 further includes a fixed shunt resistor R3p, a fixed shunt inductor L3p, and a fixed shunt capacitor C3p. The matching network model 302 is a computer-generated model of a portion of the impedance matching network 1. For example, the matching network model 302 is a computer-generated model of an x ㎒ RF generator, or a y ㎒ RF generator, or a branch circuit of an impedance matching network 1 coupled to a z ㎒ RF generator. The matching network model 302 is generated by the processor of the host computer system 112.

The matching network model 302 is derived from a branch circuit that is part of the impedance matching network 1 and represents, for example, a branch circuit of the portion of the impedance matching network 1. For example, if the x MHz RF generator is connected to a branch circuit that is part of the impedance matching network 1, the matching network model 302 represents the circuit of the impedance matching network 1, And the generated model. As another example, the matching network model 302 does not have the same number of circuit components as the circuit components of the impedance matching network 1. The matching network model 302 has fewer circuit elements than the number of circuit components of the branch circuit of the impedance matching network 1.

In some embodiments, the matching network model 302 is a simplified form of a portion of the impedance matching network 1. For example, the variable capacitances of the plurality of variable capacitors of the branch circuit of the impedance matching network 1 may be combined into a combined variable capacitance represented by one or more variable capacitive elements of the impedance matching model and / The fixed inductances of the plurality of fixed inductors of the branch circuit of the network 1 are coupled to the combined fixed inductance represented by one or more fixed inductive elements of the impedance matching model and / The fixed resistances of the plurality of fixed resistors are combined into a combined fixed resistance represented by one or more fixed resistive elements of the impedance matching model 302. For purposes of illustration, the capacitances of the capacitors in series are determined by inverting each of the capacitances to produce a plurality of inverted capacitances, adding the inverted capacitances to produce the inverted combined capacitances, and generating the combined capacitances Lt; RTI ID = 0.0 > inverted < / RTI > As another example, the inductances of a plurality of inductors coupled in series are added to produce a combined inductance, and the resistances of the plurality of resistors in series are combined to produce a combined resistance. The total fixed capacitance of all the fixed capacitors of a portion of the impedance matching network 1 is coupled to the combined fixed capacitance of one or more fixed capacitive elements of the matching network model 302. [ Other examples of matching network model 302 are provided in a patent application having application number 14 / 716,797 and in a patent application having application number 14 / 245,803. A method for generating a matching network model from an impedance matching network is also described in a patent application having Application Serial No. 14 / 245,803.

It should be noted that in some embodiments, the fixed parameters, e.g., resistances, capacitances, inductances, etc., are not variable. For example, the fixed parameters can not be varied using the drive assembly during processing of the wafer. In comparison, the value of the variable parameter is changed during processing of the wafer.

In various embodiments, the matching network model 302 has the same topology, e.g., connections between circuit elements, number of circuit elements, etc., such as the topology of a portion of the impedance matching network 1. For example, if the branch circuit of the impedance matching network 1 includes a capacitor coupled in series with the inductor, the matching network model 302 includes a capacitor coupled in series with the inductor. In this example, the branch circuits of the impedance matching network 1 and the inductors of the matching network model 302 have the same value, and the branch circuits of the impedance matching network 1 and the capacitors of the matching network model 302 have the same value. In another example, if a portion of the impedance matching network 1 includes a capacitor coupled in parallel with the inductor, the matching network model 302 includes a capacitor coupled in parallel with the inductor. In this example, the branch circuits of the impedance matching network 1 and the inductors of the matching network model 302 have the same value, and the branch circuits of the impedance matching network 1 and the capacitors of the matching network model 302 have the same value. In another example, the matching network model 302 may have the same number and type of circuit components as the number and type of circuit components of the impedance matching network 1, and between the circuit elements of the same type as the types of connections between the circuit components. Connections. Examples of types of circuit elements include resistors, inductors, and capacitors, and examples of types of connections include series, parallel, and the like.

The method 303 is executed by a processor of the host computer system 112. The processor receives the measured load impedance Zo1m and the measured load impedance ZoNm from network analyzer 102 over a network cable. The processor has a frequency f11, a combined variable capacitance C11, fixed inductances L1s, L1p, L2s, L2p, fixed resistances R1s, R1p, R2s, R2p, and fixed capacitances C1s, C1p, RTI ID = 0.0 > C2s, C2p). ≪ / RTI > For purposes of describing FIG. 3, a matching network model 302 with module 1 and module 2 is used without all of the remaining modules 3 - P. In some embodiments, instead of the combined variable capacitance C11, the matching network model 302 is initialized to have a sum Sc1, and instead of the frequency f11, the matching network model 302 is summed Sf1).

By way of example, the parameters C11 and f11 applied to the matching network model 302 are such that the RF signal having the frequency f11 is supplied by the network analyzer 102 after the impedance matching network 1 is connected to the load impedance fixture 1 , One or more fixed capacitors having one or more fixed capacitors having a combined fixed capacitance of Cs and one or more motor-driven capacitors having a combined variable capacitance of C11, with one or more fixed capacitors having a combined fixed capacitance of Cs, With one or more fixed capacitors having a combined fixed capacitance of Cp, with one or more fixed capacitors having a combined fixed capacitance of Cp, with one or more fixed resistors having a combined fixed resistance of Rs, Having at least one fixed resistance With one or more fixed inductors having a combined fixed resistance of R1p and one or more fixed resistors with a combined fixed resistance of R2p and having one or more fixed inductors with a combined fixed inductance of L1s , One or more fixed inductors having a combined fixed inductance of L2p and one or more fixed inductors having a combined fixed inductance of L1p and one or more fixed inductors having a combined fixed inductance of L2p, 1.

In some embodiments, the fixed parameter values of many elements of the matching network model 302 are zero or the matching network model 302 is not sensitive to the fixed parameter values of the elements. For example, a large change in the value of a non-sensitive fixed element of the matching network model 302 does not produce a large change in the impedance of the matching network model 302. [

In some embodiments, the fixed element, e.g., an inductor, a resistor, a capacitor, etc., has a fixed parameter value that does not change using, for example, a motor or the like.

The processor back propagates the measured load impedance Zo1m through the matching network model 302 and calculates the measured load impedance Zo1m and the parameters f11, C11, L1s, L1p, L2s, L2p, Which is an impedance at the input of the matching network model 302, from the input impedance Rs, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p. For example, the processor may calculate the impedance ZC11 of one or more capacitive elements having a variable capacitance C11 from the frequency f11 and from the capacitance C11, and calculate the impedance ZC11 from the frequency f11 and from the inductance Lls, The impedance ZL11s of the inductor L2s is calculated from the frequency f11 and from the inductance L2s and the impedance ZL21s of the inductor L1s is calculated from the frequency f11 and from the inductance L1p, And calculates the impedance ZL21p of the inductor L2p from the frequency f11 and from the inductance L2p to calculate the impedance ZL21p of the capacitor C1s from the frequency f11 and from the capacitance C1s The impedance ZC11s is calculated and the impedance ZC21s of the capacitor C2s is calculated from the frequency f11 and from the capacitance C2s, The impedance ZC11p of the capacitor C1p is calculated from the capacitance C1p and the impedance ZC21p of the capacitor C2p is calculated from the frequency f11 and from the capacitance C2p, The impedance ZR1s to be the resistor R1s is calculated and the impedance ZR2s to be the resistance R2s of the resistor R2s is calculated to calculate the impedance ZR1p to be the resistance R1p of the resistor R1p And the impedance ZR2p which becomes the resistance R2p of the resistor R2p is calculated. To illustrate, the processor computes the impedance of a capacitor with ω equal to 2πf11, (1 / jωC), and calculates the impedance of the inductor to be jωL. The processor combines, for example, adds the measured load impedance (Zo1m) and impedances (ZC11, ZC11s, ZC21s, ZC11p, ZC21p, ZL11s, ZL21s ZL11p, ZL21p, ZR1s, ZR2s, ZR1p, and ZR2p) And calculates a predicted input impedance Zi1p by generating a directional sum. For example, if matching network model 302 includes module 1 without modules 2 through P, then the directional sum of the impedances ZC11p, ZL11p, and ZR1p is the sum of the impedances ZC11p, ZL11p, and ZR1p to be. In this example, the sum of the impedances is added to the sum of the impedances ZR1s, ZL11s, and ZC11s to produce the direction sum of the impedances ZC11p, ZL11p, ZR1p, ZR1s, ZL11s, and ZC11s.

Similarly, the processor may determine from the parameters of the matching network model 302 by inverse propagating the measured load impedance ZoNm applied to the output 304 and the measured load impedance ZoNm through the matching network model 302 The input impedance ZiNp predicted at the input 306 of the matching network model 302 is calculated. For example, the processor may change the parameters of the matching network model 302 from f11 to fN1, from C11 to CN1, but may also include fixed parameters such as L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p , C1s, C1p, C2s, and C2p remain unchanged. In embodiments where weighted capacitances and weighted frequencies are used, the processor changes the parameters of the matching network model 302 from Sf1 to SfN, Sc1 to ScN.

The parameters fN1 and CN1 applied to the matching network model 302 are supplied to the network analyzer 102 after the impedance matching network 1 is connected to the load impedance fixture N and an RF signal having a frequency fN1 is supplied, Having one or more fixed capacitors having a combined fixed capacitance of C2s, one or more fixed capacitors having a combined fixed capacitance of C1s, one or more motor-driven capacitors having a combined variable capacitance, With one or more fixed capacitors having a combined fixed resistance of Rs and one or more fixed capacitors having a combined fixed capacitance of Rs, with one or more fixed capacitors having a combined fixed capacitance of Rs, One or more resistances With one or more fixed inductors having a combined fixed resistance of R1p and one or more fixed resistors having a combined fixed resistance of R2p and having a fixed fixed inductance of L1s, With one or more fixed inductors having a combined fixed inductance of L2p and one or more fixed inductors with a combined fixed inductance of L1p and having one or more fixed inductances with a combined fixed inductance of L2p, . The processor calculates the impedance ZCN1 of the at least one capacitive element having a variable capacitance CN1 from the frequency fN1 and from the capacitance CN1 and calculates the impedance ZCN1 of the inductor L1s from the frequency fNl and from the inductance Lls. The impedance ZL1Ns is calculated from the frequency fN1 and the inductance L2Ls of the inductor L2s from the inductance L2s and the impedance ZL2Ns of the inductor L1p is calculated from the frequency fNl and from the inductance L1p ZL1Np of the capacitor C1s and calculates the impedance ZL2Np of the inductor L2p from the frequency fN1 and from the inductance L2p and calculates the impedance ZC1Ns of the capacitor C1s from the frequency fN1 and from the capacitance C1s, And calculates the impedance ZC2Ns of the capacitor C2s from the frequency fN1 and from the capacitance C2s to calculate the impedance ZC2Ns from the frequency fN1 The impedance ZC1Np of the capacitor C1p is calculated from the capacitance C1p and the impedance ZC2Np of the capacitor C2p is calculated from the frequency fN1 and from the capacitance C2p and the impedances ZR1s, ZR2s, ZR1p And the impedance ZR2p. To illustrate, the processor computes the impedance of a capacitor, where ω is equal to 2πfN1, (1 / jωC), and calculates the impedance of the inductor to be jωL. The processor calculates the predicted input impedance Zi1p by combining the output measured load Zo1m with the impedances ZC11, ZC11s, ZC21s, ZC11p, ZC21p, ZL11s, ZL21s ZL11p, ZL21p, ZR1s, ZR2s, ZR1p, (ZCN1, ZC1Ns, ZC2Ns, ZC1Np, ZC2Np, ZL1Ns, ZL2Ns ZL1Np, ZL2Np, ZL1Np, ZL2Np, ZR1s, ZR2s, ZR1p, and ZR2p) are combined, for example, added, and the predicted input impedance ZiNp is calculated.

In operation 308 of method 303, the processor of the host computer system 112 determines whether the predicted input impedance Zi1p is within a pre-determined range from the measured input impedance Zi1m and the predicted input impedance ZiNp, Is within a pre-determined range from the measured input impedance ZiNm. For example, if the predicted input impedance Zi1p is within a pre-determined range from the measured input impedance Zi1m and if the predicted input impedance ZiNp is within a pre-determined range from the measured input impedance ZiNm The decisions are performed simultaneously by the processor, e.g., at the same time, during the same clock cycle, and so on. Operation 308 is performed for all load impedance fixtures. For example, if three load impedance fixtures 1, 2, and 3 are used in the manner described above in which the load impedance fixtures 1 and 2 are used, the processor determines that the predicted input impedance Zi1p is equal to the measured input impedance Zi1m is within a pre-determined range and the predicted input impedance Zi2p is within a pre-determined range from the measured input impedance Zi2m and the predicted input impedance ZiNp is within a predetermined range from the measured input impedance ZiNm And determines whether it is within a pre-determined range. The measured input impedance Zi2m is determined such that the load impedance fixture 2 is connected to the impedance matching network 1 via the RF cable 108 (Fig. 1B) and the impedance matching network 1 is also connected to the network 10 via the RF cable 106 When connected to the analyzer 102, it is measured by the network analyzer 102. In addition, the predicted input impedance Zi2p is calculated by the processor in a similar manner as the predicted input impedances Zi1p and ZiNp are calculated by the processor.

When determining that the predicted input impedance Zi1p is within a pre-determined range from the measured input impedance Zi1m and the predicted input impedance ZiNp is within a pre-determined range from the measured input impedance ZiNm, the method 303 L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p for use with the impedance matching network 1, To the model 302. For example, the processor may set the fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) to the identification number of the impedance matching network 1, Maps, and stores mappings, parameters, and identification numbers in the memory device of the host computer system 112. [ On the other hand, if the predicted input impedance Zi1p is not within the pre-determined range from the measured input impedance Zi1m or the predicted input impedance ZiNp is not within the pre-determined range from the measured input impedance ZiNm L2p, R1s, R1p, R2s, R2p, C1s, C1p, C1p, C1p, C1p, C1p, C1p, C1p, C2s, and C2p.

In various embodiments, the processor is operable, by the user, to pre-register one or more parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) The determined range is provided and the one or more parameters are changed to be within a pre-determined range. For example, the user indicates to the processor that the parameter Lls is also changed by 5% from the value provided by the user to the processor via the input device. During operation 312, the processor changes the value of parameter L1s by 5%. As another example, the user indicates to the processor that the parameter C1s also changes by 2% from the value provided to the processor by the user via the input device. During operation 312, the processor changes the value of parameter Cls by 2%. As another example, the user indicates to the processor that the parameter C1s also changes by 0% from the value provided to the processor by the user via the input device. During operation 312, the processor changes the value of parameter Cls by 0%.

In some embodiments, in addition to or instead of changing one or more fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) At operation 312, changes the capacitance C11. For example, the capacitance C11 is the variable capacitance of one of the modules of the matching network model 302 and the variable capacitance represents the motor-driven capacitor of the impedance matching network 1. [ In this example, the capacitance C11 is represented by an equation that is a sum of a constant term, a linear term, and a quadratic term. The first term is the product of the first order coefficient and the variable, eg the position in the motor shaft revolution. The second term is the product of the second order coefficient and the square of the variable. The processor changes the value of the constant, and / or the first order coefficient, and / or the second order coefficient to change the variable capacitance C11, at operation 312.

The processor determines whether the predicted input impedance Zi1p for the changed parameters is within a pre-determined range from the measured input impedance Zi1m and the predicted input impedance ZiNp for the changed parameters is the measured input impedance ZiNm, (308) using one or more of the changed parameters to determine if it is within a pre-determined range. In this manner, the processor may determine that the predicted input impedance Zi1p to find one or more values of one or more corresponding changed parameters for the matching network model 302 is within a pre-determined range from the measured input impedance Zi1m, Operation 308 is repeated until the predicted input impedance ZiNp is within a pre-determined range from the measured input impedance ZiNm. One or more values of one or more corresponding changed parameters are then assigned to the matching network model 302. For example, the processor maps the changed parameters to the identification number of the impedance matching network 1 and stores the mapping, changed parameters, and identification number in the memory device of the host computer system 112.

It should be noted that, in some embodiments, the value of the parameter is the same as the parameter. For example, each of the parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) is a value. Thus, when the value changes, the parameter changes.

If the measured input impedance Zi1m is not within a pre-determined threshold of a pre-determined impedance as determined by operation 132 in FIG. 1A and the measured input impedance ZiNm is determined by operation 152 of FIG. In embodiments that are not within a pre-determined threshold of a pre-determined impedance, such as operation 308, operation 308 is performed on the measured input impedances Zi1Qm and ZiNQm (see Figures Ia and Ib). For example, if the predicted input impedance Zi1p obtained for the measured input impedance Zi1Qm is within a pre-determined range of the measured input impedance Zi1Qm and the predicted input obtained for the measured input impedance ZiNQm It is determined at operation 308 whether the impedance ZiNp is within a pre-determined range of the measured input impedance ZiNQm. When determining that the predicted input impedance Zi1p is within a pre-determined range of the measured input impedance Zi1Qm and that the predicted input impedance ZiNp is within a pre-determined range of the measured input impedance ZiNQm, 310) is performed. On the other hand, if the predicted input impedance Zi1p is not within a pre-determined range of the measured input impedance Zi1Qm and the predicted input impedance ZiNp is within a pre-determined range of the measured input impedance ZiNQm If not, then operation 312 is performed.

4 is a diagram of an embodiment of a system 400 for illustrating the determination of the efficiency of the impedance matching network 1. The system 400 includes a network analyzer 402, an impedance matching network 1, a load impedance fixture 1, and a host computer system 112. The host computer system 112 is connected to the network analyzer 402 via a network cable 404.

The network analyzer 402 has a port S1 and another port S2. In various embodiments, port S2 is an input port and port S1 is an output port. The port S1 is connected to the input 107 of the impedance matching network 1 via the RF cable 106 and the port S2 is connected to the output 406 of the load impedance fixture 1 via the RF cable 408 . The output 109 of the impedance matching network 1 is coupled to a combined load fixture 410 including the inductance and / or capacitance of the load impedance fixture 1 and the resistance of the port S2, e.g., 50 OMEGA, 49 OMEGA to 51 OMEGA, ). ≪ / RTI > In some embodiments, the impedance of the combined load fixture 410 resembles the plasma condition A, e.g., some impedance of the plasma, a pre-determined range of impedances of the plasma, and the like.

When the combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to a value C11, the network analyzer 402 operates at frequency f11. For example, the network analyzer 402 generates an RF signal having a frequency f11 and sends the RF signal from the port S1 via the RF cable 106 to the input 107 of the impedance matching network 1. [ In some embodiments, the combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to a value different than the value C11, and the network analyzer 402 operates at a frequency different from the frequency f11. The impedance matching network 1 receives an RF signal to generate a modified RF signal and transmits the impedance of a load, e.g., an RF cable 108, and a combined load fixture 410, to a source, e.g., an RF cable 106 ), And the port (S1). The modified RF signal is provided to the combined load fixture 410. For example, the modified RF signal is delivered to the port S2 of the network analyzer 402 via the load impedance fixture 1.

When the modified RF signal is provided to the combined load fixture 410, the network analyzer 402 measures the S21 parameter, the S11 parameter, and the amount of power Po1m output by the RF signal at the S1 port. For example, the network analyzer 402 measures the power Po1m supplied by the RF signal sent to the impedance matching network 1 through the RF cable 106 at port S1. The parameters S11 and S12 are scattering parameters. The scattering parameters S11 and S12 are voltage parameters and the associated powers are squares of the scattering parameters. For example, the ratio of the power input to the port S1 to the power from the port S1 is S11 ² and the ratio of the power input to the port S2 to the power from the port S1 is S21 ² . The network analyzer 402 sends the amount of power Po1m, the S11 parameter, and the S21 parameter to the processor of the host computer system 112 via the network cable 404. If the combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to a value C11 and the network analyzer 402 is operating at a frequency f11 then the processor will calculate the square of the S21 parameter and the square of the 1 and S11 parameters The efficiency? 1m of the impedance matching network 1 is calculated. The ratio is expressed as follows.

........ Equation (1)

It should be noted that, in some embodiments, the measured efficiency of the impedance matching network 1 is not a simple number, but instead depends on the impedance of the load connected to the impedance matching network 1.

In some embodiments, efficiency < RTI ID = 0.0 > 1m < / RTI > may be chosen such that the load impedance fixture 1 is lossless or has a minimal loss of power, for example power lost in the load impedance fixture 1 is substantially equal to impedance matching network 1 Less than the power lost in the power supply, etc., is measured using Equation (1). The efficiency [epsilon] lm is the efficiency of the combined load fixture 410. In some embodiments, the ratio is changed when the load impedance fixture 1 has a small amount of power loss. In some embodiments, the efficiency (ε1m) are termed decision on all values of the combined variable-capacitance of the RF frequency and the impedance matching network 1 of the network analyzer 402, the efficiency (ε1m) is accurate for the S11 ² of a value As S11 ² increases, it becomes inaccurate. In various embodiments, efficiency < RTI ID = 0.0 > 1m < / RTI > may be used when impedance matching network 1 is tuned or nearly tuned, for example when the combined variable capacitance of impedance matching network 1 and the RF frequency of network analyzer 402 are S11 ² is tuned close to zero. The efficiency ([epsilon] 1m) is sometimes referred to herein as the measured efficiency.

In some embodiments, instead of the load impedance fixture 1, another load impedance fixture A is connected to the impedance matching network 1 and port S2 of the network analyzer 402. The load impedance fixture A has the same structure as the structure of the load impedance fixture 1 except that the load impedance fixture A includes one or more lossless capacitors, and / or one or more lossless inductors, and does not include any resistors . For example, the load impedance fixture A includes one or more lossless capacitors coupled in series with one or more lossless inductors. One or more lossless capacitors are coupled to input 1111 and one or more lossless inductors are coupled to output 406. As another example, the load impedance fixture A may include one or more lossless capacitors coupled in series with one or more lossless inductors. One or more lossless inductors are coupled to input 1111 and one or more lossless capacitors are coupled to output 406.

In some embodiments, a lossless circuit component, e.g., an inductor, capacitor, resistor, etc., is a circuit component that is less than a pre-determined amount of power loss when current passes through the circuit component.

5 is a diagrammatic representation of the embodiment of the host computer system 112 for illustrating the determination of the values of the fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) to be. The matching network model 302 includes a radio frequency f11, a capacitance C11 and fixed parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p . For example, the user may enter fixed values (f11, C11, L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p). In some embodiments, instead of the combined variable capacitance C11, the matching network model 302 is started to have a sum Sc1, and instead of the frequency f11, the matching network model 302 is summed Sf1, Lt; / RTI >

The processor receives the measured output power Po1m from network analyzer 402 over network cable 404. So that the matching network model 302 has the radio frequency f11, the capacitance C11 and the parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p. During the initialized time period, the processor applies the input power Pi1p at the input 306 of the matching network model 302 to calculate the predicted output power Po1p at the output 304 of the matching network model 302 Propagates the input power Pi1p in the forward direction through the circuit elements of the matching network model 302. [ For example, when the matching network model 302 includes a series combination of circuit elements R1s, C1s, L1s, and C11, a significant amount of current flows through the power PRs consumed by the resistor R1s, (PCs) consumed by the capacitor C1s, the power PLs consumed by the inductor Ls, and the power PCs consumed by the capacitor C11. The processor calculates the directional sum of the input power Pi1p, the power PRs, the power PCs, the power PLs, and the power PC1s to calculate the predicted output power Po1p.

In some embodiments, the input power Pi1p is equal to the power Po1m. In various embodiments, the input power Pi1p is randomly selected by the processor of the host computer system 112. [ In various embodiments, input power Pi1p is received from a user via an input device coupled to the processor.

The processor calculates the predicted efficiency [epsilon] p of the matching network model 302 by the ratio of the predicted output power Po1p to the input power Pi1p. The processor may change one or more fixed values of one or more corresponding fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) of the matching network model 302 Method 500 is applied to determine. For example, in operation 502, the processor determines that the predicted efficiency, [epsilon] lp, is within a pre-determined limit of the measured efficiency [epsilon] 1m. The pre-determined limit is provided as input to the processor via the input device. For example, a pre-determined limit is provided to the processor before action 502 or before method 500 is performed. When the predicted efficiency? 1p is determined to be within a pre-determined limit of the measured efficiency? 1m, the processor determines at operation 310 that the matching network model 302 for use with the impedance matching network 1 includes parameters L1s , L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p. On the other hand, when determining that the predicted efficiency? 1p is not within a pre-determined limit of the measured efficiency? 1m, the processor, in operation 312, L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p. To illustrate, the processor changes the value of inductor Lls from V1 to V2 to produce one or more changed parameters. As another example, the processor changes the value of inductor L1s from V1 to V2 and the value of capacitor C1s from W1 to W2 to produce one or more changed parameters.

The processor repeats operation 502 using one or more changed parameters to determine whether the predicted efficiency [epsilon] p for the changed parameters is within a pre-determined limit from the measured efficiency [epsilon] 1m. In this manner, until the predicted efficiency [epsilon] lp to find one or more values of one or more corresponding changed parameters for the matching network model 302 is within a pre-determined limit from the measured efficiency [epsilon] 502). One or more values of one or more corresponding changed parameters are then assigned to the matching network model 302. For example, the processor may map one or more changed parameters to an identification number of the impedance matching network 1, and provide a mapping, one or more changed parameters, and an identification number of the matching network model 302 to a memory device Lt; / RTI >

In some embodiments, instead of or in addition to changing one or more fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) In operation 312 of method 500, the variable capacitance C11 is changed in the same manner as described above.

Fig. 6 is a graph showing the relationship between the fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s) using the impedances (Zi1p, Zi1m, ZiNp, ZiNm) and efficiencies 0.0 > C2p < / RTI > The method 600 is executed by a processor of the host computer system 112. In operation 602 of method 600, if the predicted input impedance Zi1p is within a pre-determined range of input impedance Zi1m and the predicted input impedance ZiNp is within a pre-determined range of input impedance ZiNm And whether the predicted efficiency? 1p is within a pre-determined limit from the measured efficiency? 1m is determined by the processor.

If the predicted input impedance Zi1p is within a pre-determined range of the input impedance Zi1m and the predicted input impedance ZiNp is within a pre-determined range of the input impedance ZiNm and the predicted efficiency? When determining that it is within a pre-determined limit from the measured efficiency ([epsilon] 1m), operation 310 is performed by the processor. On the other hand, if the predicted input impedance Zi1p is not within a pre-determined range of the input impedance Zi1m, or if the predicted input impedance ZiNp is not within a pre-determined range of the input impedance ZiNm, When it is determined that the predicted efficiency [epsilon] lp is not within a pre-determined limit from the measured efficiency [epsilon] 1m, the processor performs an operation 312. [

In some embodiments, if the predicted input impedance Zi1p is not within a pre-determined range of input impedance Zi1m, or if the predicted input impedance ZiNp is not within a pre-determined range of input impedance ZiNm Or when the predicted efficiency? 1p is not within a pre-determined limit from the measured efficiency? 1m, or a combination of two or more thereof, the processor performs an operation 312. For example, if the predicted input impedance Zi1p is not within a pre-determined range of the input impedance Zi1m and the predicted input impedance ZiNp is not within a pre-determined range of the input impedance ZiNm, When it is determined that the efficiency [epsilon] lp is not within the pre-determined limit from the measured efficiency [epsilon] lm, the processor performs an operation 312. [

The processor determines if the predicted input impedance Zi1p is within a pre-determined range of the input impedance Zi1m, if the predicted input impedance ZiNp is within a pre-determined range of the input impedance ZiNm, ) Is determined to be within a pre-determined limit from the measured efficiency ([epsilon] 1m) using the one or more changed parameters. In this manner, the input impedance Zi1p predicted to look for one or more values of one or more corresponding changed parameters for the matching network model 302 is within a pre-determined range of input impedance Zi1m, The processor repeats operation 602 until ZiNp is within a pre-determined range of input impedance ZiNm and the predicted efficiency? 1p is within a pre-determined limit from the measured efficiency? 1m. One or more values of one or more corresponding changed parameters are then assigned to the matching network model 302. For example, the processor assigns the changed parameters to the identification number of the impedance matching network 1 and stores the mapping, identification number, and one or more changed parameters in the memory device of the host computer system 112.

In some embodiments, in addition to or instead of changing one or more fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) At operation 312 of method 600, changes the variable capacitance C11 in the same manner as described above.

7 is a diagram of an embodiment of a system 700 for illustrating the determination of the efficiency of the impedance matching network 1 when the impedance matching network 1 is connected to a load impedance fixture N. Fig. The system 700 includes a network analyzer 402, an impedance matching network 1, a load impedance fixture N, and a host computer system 112.

The port S2 is connected to the output 702 of the load impedance fixture N via the RF cable 408. The output 109 of the impedance matching network 1 is connected via an RF cable 108 to a combined load fixture 704 comprising the inductances and / or capacitances of the load impedance fixture N and the resistance of the port S2 Be careful. In some embodiments, the impedance of the combined load fixture 704 resembles the plasma condition B, e.g., one impedance of the plasma, a pre-determined range of impedances of the plasma, and the like, Is different from the condition (A). For example, the impedance exhibited by the combined load fixture 704 is different from the impedance exhibited by the combined load fixture 410 (FIG. 4). As another example, a pre-determined range of impedances exhibited by the combined load fixture 704 excludes a pre-determined range of impedances exhibited by the combined load fixture 410.

When the combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to the value CN1, the network analyzer 402 operates at the frequency fN1. For example, the network analyzer 402 generates an RF signal having a frequency fN1 and sends an RF signal from the port S1 to the input 107 of the impedance matching network 1 via the RF cable 106. [ In some embodiments, the combined variable capacitance of one or more variable capacitors of the impedance matching network 1 is set to a value different than the value CN1, and the network analyzer 402 operates at a frequency different from the frequency fN1. The impedance matching network 1 receives the RF signal to generate a modified RF signal and provides a load, e.g., RF cable 108, load impedance fixture N, and port S2, coupled to the output 109 of the impedance matching network 1, Such as the RF cable 106, and the port S1, which are connected to the input section 107 of the impedance matching network 1, are matched. The modified RF signal is provided to a combined load fixture 704. For example, the modified RF signal is delivered to port S2 of network analyzer 402 via load impedance fixture N. [

If a modified RF signal is provided to the combined load fixture 704, the network analyzer 402 measures the S21 parameter, the S11 parameter, and the power PoNm of the RF signal output at the S1 port. For example, the network analyzer 402 measures, at port S1, the power PoNm supplied by the RF signal sent to the impedance matching network 1 via the RF cable 106. Network analyzer 402 sends S11 parameters, and S21 parameters, and power (PoNm) to the processor of host computer system 112 over network cable 404. The processor calculates the efficiency ([epsilon] Nm) of the impedance matching network 1 by the ratio of the square of the S21 parameter and the square of the 1 and S11 parameters.

The ratio is expressed as follows.

.......... Equation (2)

The efficiency? Nm is the efficiency of the combined load fixture 704. In some embodiments, efficiency < RTI ID = 0.0 > (Nm) < / RTI > may be chosen so that the load impedance fixture N is lossless or has a minimum loss of power, for example power lost in the load impedance fixture N is substantially lost in the impedance matching network 1 Power, etc., is measured using Equation (2). In some embodiments, the ratio is changed when the load impedance fixture N has a small amount of power loss. In some embodiments, the efficiency? Nm is determined at all values of the RF frequency of the network analyzer 402 and the combined variable capacitance of the impedance matching network 1, but the efficiency? Nm is accurate for a small value of S11 ² As S11 ² increases, it becomes inaccurate. In various embodiments, efficiency < RTI ID = 0.0 > (Nm) < / RTI > is a function of impedance matching network 1 when the impedance matching network 1 is tuned or nearly tuned, for example when the combined variable capacitance of impedance matching network 1 and the RF frequency of network analyzer 402 are S11 ² is tuned close to zero.

In some embodiments, instead of load impedance fixture N, another load impedance fixture B is connected to impedance matching network 1 and port S2 of network analyzer 402. [ The load impedance fixture B has the same structure as the structure of the load impedance fixture N except that the load impedance fixture B includes one or more lossless capacitors, and / or one or more lossless inductors, and does not include any resistors . For example, the load impedance fixture B includes one or more lossless capacitors coupled in series with one or more lossless inductors. One or more lossless capacitors are coupled to input 111N and one or more lossless inductors are coupled to output 702. As another example, the load impedance fixture B includes one or more lossless capacitors coupled in series with one or more lossless inductors. One or more lossless inductors are coupled to input 111N and one or more lossless capacitors are coupled to output 702.

8 illustrates a method 800 executed by the host computer system 112 to determine values of fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) ). ≪ / RTI > The predicted efficiency? 1p is determined using the matching network model 302 as described above with reference to FIG. In addition, the matching network model 302 includes a radio frequency fN1, a capacitance CN1 and fixed parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, Lt; / RTI > For example, the user may enter values (fN1, CN1, L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p , C1s, C1p, C2s, and C2p). In embodiments in which weighted capacitances and weighted frequencies are used, the processor changes the parameters of the matching network model 302 from Sf1 to SfN and from Sc1 to ScN. For example, instead of the capacitance CN1, the value ScN is used and, instead of the value fN1, the value SfN is used.

The processor receives the measured output power PoNm from network analyzer 402 over network cable 404. The matching network model 302 has a radio frequency fN1, a capacitance CN1 and fixed parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p The processor applies the input power PiNp at the input 306 of the matching network model 302 to calculate the predicted output power PoNp at the output 304 of the matching network model 302 And propagates the input power PiNp in the forward direction through the circuit elements of the matching network model 302. For example, when the matching network model 302 includes a series combination of circuit elements R1s, C1s, L1s, and C11, a significant amount of current flows through the power PRs consumed by the resistor R1s, (PCs) consumed by the capacitor C1s, the power PLs consumed by the inductor Ls, and the power PCs consumed by the capacitor C11. The processor calculates the directional sum of the input power PiNp, the power PRs, the power PCs, the power PLs, and the power PCs to calculate the predicted output power PoNp. In some embodiments, the input power PiNp is equal to the power PoNm. In various embodiments, the input power PiNp is randomly selected by the processor of the host computer system 112. In various embodiments, input power PiNp is received from a user via an input device coupled to the processor.

The processor computes the predicted efficiency [epsilon] Np of the matching network model 302 as the ratio of the predicted output power PoNp to the input power PiNp. The processor determines the method 800 to determine whether to change one or more parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) of the matching network model 302 To be applied. For example, at operation 802, the processor determines whether the predicted efficiency, epsilon 1p, is within a pre-determined limit of the measured efficiency, epsilon 1m, and if the predicted efficiency, epsilon NP, Within the limit. When the predicted efficiency? 1p is determined to be within a pre-determined limit of the measured efficiency? 1m and the predicted efficiency? Np is within a pre-determined limit of the measured efficiency? Nm, (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) to the matching network model 302 for use with the impedance matching network 1. On the other hand, when it is determined that the predicted efficiency? 1p is not within a pre-determined limit of the measured efficiency? 1m or the predicted efficiency? Np is not within a pre-determined limit of the measured efficiency? Nm, At operation 312, one or more parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) to produce one or more changed parameters.

The processor determines whether the predicted efficiency [epsilon] lp for the changed parameters is within a pre-determined limit from the measured efficiency [epsilon] m and the predicted efficiency [epsilon] Np for the changed parameters is determined from the measured efficiency [ And then repeats operation 802 using one or more changed parameters to determine if it is within a limit. In this manner, the predicted efficiency [epsilon] lp to find one or more values of one or more corresponding changed parameters for the matching network model 302 is determined for the parameters that are within the pre-determined limit from the measured efficiency [ The processor repeats operation 802 until the predicted efficiency? Np is within a pre-determined limit from the measured efficiency? Nm. One or more values of one or more corresponding changed parameters are then assigned to the matching network model 302. For example, the processor maps one or more changed parameters to an identification number of the impedance matching network 1, and stores the mapping, identification number, and one or more changed parameters in the memory device of the host computer system 112.

In some embodiments, instead of or in addition to changing one or more fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) At operation 312 of method 800, the capacitance C11 is changed in the same manner as described above.

In various embodiments, it is determined that the predicted efficiency? 1p is not within a pre-determined limit from the measured efficiency? 1m and the predicted efficiency? Np is not within a pre-determined limit from the measured efficiency? Nm At step 312, the processor, in operation 312, changes one or more parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) .

L1p, L2s, L2p, R1s, R1p, and R2s () are calculated using the impedances Zi1p, Zi1m, ZiNp, ZiNm, efficiencies? 1m and? 1p, and efficiencies? , R2p, C1s, C1p, C2s, and C2p). ≪ / RTI > The method 900 is executed by a processor of the host computer system 112. In operation 902 of method 900, if the predicted input impedance Zi1p is within a pre-determined range of input impedance Zi1m and the predicted input impedance ZiNp is within a pre-determined range of input impedance ZiNm Whether or not the predicted efficiency? 1p is within a pre-determined limit from the measured efficiency? 1m and whether the predicted efficiency? Np is within a pre-determined limit from the measured efficiency? Nm is determined by the processor do.

If the predicted input impedance Zi1p is within a pre-determined range of the input impedance Zi1m and the predicted input impedance ZiNp is within a pre-determined range of the input impedance ZiNm and the predicted efficiency? Operation 310 is within a pre-determined limit from the calculated efficiency? 1m and the predicted efficiency? Np is within a pre-determined limit from the measured efficiency? Nm. On the other hand, if the predicted input impedance Zi1p is not within a pre-determined range of the input impedance Zi1m, or if the predicted input impedance ZiNp is not within a pre-determined range of the input impedance ZiNm, When the determined efficiency ε1p is not within a pre-determined limit from the measured efficiency ε1m or the predicted efficiency εNp is not within a pre-determined limit from the measured efficiency εNm, (312).

In some embodiments, if the predicted input impedance Zi1p is not within a pre-determined range of input impedance Zi1m, or if the predicted input impedance ZiNp is not within a pre-determined range of input impedance ZiNm Or the predicted efficiency ε1p is not within the pre-determined limit from the measured efficiency ε1m or the predicted efficiency εNp is not within the pre-determined limit from the measured efficiency εNm, , The processor performs an operation 312. In operation 312, For example, if the predicted input impedance Zi1p is not within a pre-determined range of the input impedance Zi1m, the predicted input impedance ZiNp is not within a pre-determined range of the input impedance ZiNm, When the determined efficiency ε1p is not within a pre-determined limit from the measured efficiency ε1m and the predicted efficiency εNp is not within a pre-determined limit from the measured efficiency εNm, 312). As another example, when it is determined that the predicted input impedance ZiNp is not within a pre-determined range of the input impedance ZiNm and the predicted efficiency? Np is not within a pre-determined limit from the measured efficiency? Nm, (312). ≪ / RTI >

The processor determines whether the predicted input impedance Zi1p is within a pre-determined range of the input impedance Zi1m and whether the predicted input impedance ZiNp is within a pre-determined range of the input impedance ZiNm, (902) using one or more of the changed parameters to determine whether the estimated efficiency (εNp) is within a pre-determined limit from the measured efficiency (ε1m) and whether the predicted efficiency (εNp) . In this manner, the input impedance Zi1p predicted to look for one or more values of the corresponding one or more changed parameters of the matching network model 302 is within a pre-determined range of the input impedance Zi1m and the predicted input impedance Determined range of the input impedance ZiNm and the predicted efficiency? 1p is within a pre-determined limit from the measured efficiency? 1m and the predicted efficiency? Np is within the pre-determined range of the measured efficiency? The processor repeats operation 902 until it is within a pre-determined limit. The one or more changed parameters are then assigned to the matching network model 302. For example, the processor maps one or more changed parameters to an identification number of the impedance matching network 1 and stores the mapping, one or more changed parameters, and an identification number in the memory device of the host computer system 112.

In some embodiments, instead of or in addition to changing one or more fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) At operation 312 of method 900, the variable capacitance C11 is changed in the same manner as described above.

10 is a diagram of an embodiment of a plasma system 1000 for illustrating the use of a matching network model 302 within a plasma system 1000. The system 1000 includes an RF generator 1002, an impedance matching network 1, a plasma chamber 1004, and a host computer system 112. The RF generator 1002 is an x ㎒ RF generator, a y ㎒ RF generator, or a z ㎒ RF generator. RF generator 1002 operates at frequency fRF1. The plasma chamber 1004 is connected to the output 109 of the impedance matching network 1 via the RF transmission line 1006 and the input 107 of the branch circuit of the impedance matching network 1 is connected to the RF generator 1002 ).

RF generator 1002 includes an RF power supply 1010 and a sensor 1012, e.g., a complex voltage and current sensor, a complex impedance sensor, a complex voltage sensor, a complex current sensor, and the like. The sensor 1012 is connected to the host computer system 112 via a network cable 1014, for example, a serial transfer cable, a parallel transfer cable, a USB cable, or the like. Examples of the sensor 1012 include a voltage sensor, a current sensor, an impedance sensor, a complex voltage and current sensor, a power sensor, and the like. The host computer system 112 includes a memory device 1018 that stores a matching network model 302 for access by a processor 1016 and a processor 1016.

The plasma chamber 1004 includes an upper electrode 1020, a chuck 1022, and a wafer W. [ The upper electrode 1020 faces the chuck 1022 and faces the ground, e. G., Reference voltage and coupling, zero voltage and coupling, negative voltage and coupling, and so on. Examples of the chuck 1022 include an ESC (electrostatic chuck) and a magnetic chuck. The lower electrode of the chuck 1022 is made of a metal, for example, anodized aluminum, an aluminum alloy, or the like. Further, the upper electrode 1020 is made of a metal, for example, aluminum, an aluminum alloy, or the like. The upper electrode 1020 is located on the opposite side of the lower electrode of the chuck 1022 and confronts it.

In some embodiments, the plasma chamber 1004 includes additional components, such as an upper electrode extension surrounding the upper electrode 1020, a lower electrode extension surrounding the lower electrode of the chuck 1022, A dielectric ring between the electrode 1020 and the upper electrode extension, a dielectric ring between the lower electrode extension and the lower electrode extension, a chuck 1022 and an upper electrode 1020 to surround the region in the plasma chamber 1004 in which the plasma is formed Or confinement rings located at the edges of the substrate.

The wafer W may be processed by, for example, depositing materials on the wafer W, cleaning the wafer W, etching the deposited layers on the wafer W, The ion implantation on the wafer W or the photolithographic pattern on the wafer W or the etching of the wafer W or the sputtering of the wafer W, Is placed on top surface 1024 of chuck 1022 for combination.

The processor 1016 of the host computer system 112 may determine the frequency fRF1 of the RF signal to be generated by the recipe, e.g., the RF generator 1002, from the memory device 1018 of the host computer system 112, The amount of power of the RF signal to be generated by the RF generator 1002, and the like, and provides a recipe to the RF generator 1002 via the network cable 1026. [

The recipe also includes the combined variable capacitance of the impedance matching network 1 to be achieved. The processor is coupled to the drive assembly 1040, which is coupled to one or more variable capacitors of the impedance matching network 1 via a connection mechanism 1042. Examples of drive assembly 1040 include one or more drivers, e.g., one or more transistors, coupled to each of the one or more motors. One or more motors are connected to each of one or more rods of the connection mechanism 1042. The processor 1016 controls the drive assembly 1040 to control one or more variable capacitors of the impedance matching network 1 via the connection mechanism 1042 to achieve corresponding one or more capacitance values to further achieve the combined variable capacitance . For example, the processor 1016 sends a signal to one of one or more drivers coupled to one of the one or more motors. When receiving a signal, the driver generates a current signal provided to the stator of the motor. The rotor in communication with the stator rotates to rotate one or more loads of the connection mechanism 1042 connected to the rotor. The rotation of one or more loads changes the position of one of the one or more variable capacitors of the impedance matching network 1 to change the combined variable capacitance of the impedance matching network 1. Similarly, other ones of the one or more variable capacitors of the impedance matching network 1 are controlled by the processor 1016 to achieve a combined variable capacitance. The combined capacitance of all the variable capacitors of the impedance matching network 1 to be achieved is represented by the combined variable capacitance C11.

RF generator 1002 receives the recipe and generates an RF signal with power and frequency fRF1 in the recipe. The branch circuit of the impedance matching network 1 having the combined variable capacitance C11 is connected to the RF generator 100 via the output unit 1030, the RF cable 1008 and the input unit 107 of the impedance matching network 1 to generate a modified RF signal. 1002 to match the impedance of the load connected to the output 109 of the impedance matching network 1 and the impedance of the source connected to the input 107 of the impedance matching network 1. Examples of the source include an RF cable 1008 and an RF generator 1002 coupling the RF generator 1002 to the impedance matching network 1. Examples of loads include an RF transmission line 1006 and a plasma chamber 1004. The RF transmission line 1006 connects the lower electrode of the chuck 1022 to the impedance matching network 1. The modified RF signal is provided to the chuck 1022 by the impedance matching network 1 through the output 109 and RF transmission line 1006.

The chuck 1022 receives the modified RF signal and when the process gas enters the plasma chamber 1004, the plasma strikes or remains within the plasma chamber 1004. Examples of the process gas include an oxygen-containing gas or a fluorine-containing gas, and the process gas is provided in a gap between the upper electrode 1020 and the chuck 1022.

The matching network model 302 is stored in the memory device 1018 of the host computer system 112. In addition, the memory device 1018 includes an identification of the impedance matching network 1, values of the parameters of the matching network model 302, the frequency fRF1 of the RF signal generated by the RF generator 1002, And an associated variable capacitance C11. For example, the database 1028 includes an identification number of the impedance matching network 1, for example, ID1, and the like, and ID1 and fixed parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s and C2p) or the method 300 (FIG. 3) or the method 500 (FIG. 5) or the method 600 (FIG. 6) or the method 800 (FIG. 8) or the method 900 And stores the mapping between one or more changed parameters, determined using the < RTI ID = 0.0 > Examples of the identification number of the impedance matching network include the serial number of the impedance matching network. In addition, in this example, the memory device 1018 stores a mapping between the ID2 of the other impedance matching network 2, and the parameters of the impedance matching network 2 and ID2. The parameters of the impedance matching network 2 are determined in a manner similar to the manner of determining the parameters of the illustrated impedance matching network 1 using FIG. 3, FIG. 6, FIG. 8, or FIG.

In some embodiments, the fixed parameters of the impedance matching network 2 are equal to the fixed parameters of the impedance matching network 1. For example, the fixed parameters of the impedance matching network 2 are L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p or one or more changed parameters.

In various embodiments, the parameters of the impedance matching network 2 are the same as those of the impedance matching network 1. For example, the parameters of the impedance matching network 2 are L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, C2p, and C11 or one or more changed parameters.

The impedance matching network 1 is assigned a serial number different from the serial number assigned to the impedance matching network 2, and both the impedance matching network 1 and the impedance matching network 2 have the same model number. In some embodiments, the serial number is on the housing of the impedance matching network and the model number is on the housing of the impedance matching network. In various embodiments, the identification number includes letters, numbers, symbols, or a combination of two or more letters, numbers, and symbols.

The processor 1016 of the host computer system 112 may be connected to input devices connected to the host computer system 112 connected to the impedance matching network 1 with the RF generator 1002 having ID1 such as a stylus, , A touch screen, a button, a mouse, and the like. The processor 1016 determines whether the ID1 of the impedance matching network 1 is equal to or greater than one of the parameters L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p or the matching network model 302 From the memory device 1018 associated with the changed parameters. Processor 1016 accesses, e.g., reads, and reads parameters (e.g., L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) from memory device 1018 Of the matching network model 302 so as to have one or more changed parameters associated with the impedance matching network 1 so as to have the same value (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, Adjust the parameters.

The sensor 1012 is connected to the output 1030 to measure the variable at the output 1030. For example, the sensor 1012 may determine the impedance at the output 1030 or the complex voltage and current of the RF signal supplied by the RF generator 1002, or the complex voltage of the RF signal delivered by the RF generator 1002 And the amount of current. In some embodiments, the RF signal delivered by the RF generator 1002 is coupled to the impedance matching network 1 via the RF cable 1008 and the RF signal supplied by the RF generator 1002 via the impedance matching network 1, Is the difference between the RF signal reflected back from the RF generator 1004 to the RF generator 1002.

When the measured variables, such as complex voltage, complex current, complex impedance, complex power, complex voltage and current, are received by the processor 1016 from the sensor 1012 through the network cable 1014, 1016 may be configured to have one or more parameters associated with ID1 or one or more changed parameters associated with ID1 to generate a predicted variable at output 304 of the matching network model 302 The measured variable is applied to the input unit 306. The measured variable is propagated from the input 306 to the output 304 in a forward direction by the processor 1016 via the matching network model 302 to produce an output variable at the output 304 of the matching network model 302 do. For example, the processor 416 may determine the complex voltage received at the input 306 of the matching network model 302, the complex voltage across the resistive element with the resistance R1s in the matching network model 302, A complex voltage across the inductive element having an inductance L1s in the matching network model 302, a complex voltage across the capacitive element having the fixed capacitance C1s, a resistive element with resistance R2s in the matching network model 302, A complex voltage across the capacitive element having a fixed capacitance C 2s and a complex voltage across the inductive element having inductance L 2 s in the matching network model 302, To calculate the directional sum of the complex voltage across the capacitive element having the variable capacitance C11.

To a capacitive element having a fixed capacitance C1s over an inductive element having an inductance Lls in the matching network model 302 over a resistive element having resistance R1s in the matching network model 302 (C2s) across the inductive element having inductance (L2s) within the matching network model 302 over the resistive element having resistance (R2s) within the matched network model 302, The complex voltages received at the input of the matching network model 302 across the capacitive element across the element and across the capacitive element having the variable capacitance C11 within the matching network model 302 are provided to the output 304 of the matching network model 302 ) Has a frequency of fRF1 to produce a complex value. In this example, the matching network model 302 includes a register R1s, an inductor L1s, a capacitor C1s, a resistor R2s, an inductor L2s, a capacitor C2s, and a capacitor C11) and any other circuit elements. The complex voltage received at the input 306 of the matching network model 302 is measured by the sensor 1012 connected to the output 1030 of the RF generator 1002 and received by the processor 1016 from the sensor 1012 do. Accordingly, a sensor, for example, a voltage sensor, a current sensor, a complex impedance sensor, a complex voltage sensor (not shown) may be provided between the impedance matching network 1 and the plasma chamber 1004 to determine the value of the variable at the output 109 of the impedance matching network 1. [ And a current sensor need not be used. These sensors are expensive to use. By comparison, the sensor 1012 is already part of the RF generator 1002 and is ready for use.

In some embodiments, the fixed values (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) apply to all impedance matching networks of the same model. For example, the fixed values (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) By the processor 1016 to calculate a variable at the output 304 of the matching network model 302 based on the value of the parameter obtained from the sensor 1012 when connected continuously to the output 1030 of the matching network 1002 . As another example, the parameters, for example, the fixed parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, 1 < / RTI > This saves time in initializing the matching network model 302 when the impedance matching network 1 is replaced with the impedance matching network 2 or when the impedance matching network 2 is replaced with the impedance matching network 1.

In some embodiments, the parameters (L1s, L1p, L2s, L2p, R1s, R1p, R2s, R2p, C1s, C1p, C2s, and C2p) are fixed during processing of the wafer W, Assembly 1040, and coupling mechanism 1042, etc. < / RTI >

FIG. 11 is a block diagram of an embodiment of a matching network model 302. The series circuit including the resistor R1s, the inductor L1s and the capacitors C1s is connected to the shunt circuit including the resistor R1p, the inductor L1p, and the capacitors C1p. In addition, the series circuit including the resistor R2s, the inductor L2s, and the capacitors C2s is connected to the shunt circuit including the resistor R2p, the inductor L2p, and the capacitors C2p. In addition, the series circuit including the resistor R3s, the inductor L3s, and the capacitors C3s is connected to the shunt circuit including the resistor R3p, the inductor L3p, and the capacitors C3p.

It should be noted that in some of the embodiments described above, the RF signal is applied to the lower electrode of the chuck 1022 and the upper electrode 1020 is grounded. In various embodiments, the RF signal is applied to the top electrode 1020 and the bottom electrode of the chuck 1022 is grounded.

The embodiments described herein may be practiced with a variety of computer system configurations, including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, have. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units linked through a computer network.

In some embodiments, the controller is part of a system that may be part of the examples described above. The system includes semiconductor processing equipment, including processing tools or tools, chambers or chambers, processing platforms or platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.). The system is incorporated into an electronic device for controlling its operation prior to, during, and after the processing of a semiconductor wafer or substrate. An electronic device is referred to as a "controller" that may control various components or sub-components of the system. The controller may control the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator And / or < / RTI > coupled to or interfaced with load locks, such as, for example, RF settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, location and operation settings, Including, but not limited to, transmissions.

Generally speaking, in various embodiments, the controller may be implemented with various integrated circuits, logic, memory, memory, etc. that receive instructions and issue instructions, control operations, enable cleaning operations, enable end point measurements, And / or software. The integrated circuits may include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors executing program instructions (e.g., software) Or microcontrollers. The program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define operating parameters for executing a process on a semiconductor wafer or a semiconductor wafer. In some embodiments, the operating parameters may be varied to achieve one or more processing steps during fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / It is part of the recipe specified by the engineer.

The controller is, in some embodiments, coupled to or part of a computer that is integrated into the system, coupled to the system, or otherwise networked to the system, or a combination thereof. For example, the controller is in all or part of a fab host computer system or "cloud" that enables remote access of wafer processing. The controller may enable remote access to the system to change the parameters of the current processing, to set the processing steps following the current processing, or to monitor the current progress of manufacturing operations to start a new process, Review the history and review trends or performance metrics from a plurality of manufacturing operations.

In some embodiments, a remote computer (e.g., a server) provides process recipes to the system via a local network or a computer network including the Internet. The remote computer may include a user interface for enabling entry or programming of parameters and / or settings, and parameters and / or settings are then communicated from the remote computer to the system. In some instances, the controller receives instructions in the form of settings for processing wafers. It should be understood that these settings are specific to the type of tool that the controller will control or interfere with and the type of process to be performed on the wafer. Thus, as described above, the controller may be distributed, such as by including one or more separate controllers that are networked and operated together for common purposes, such as the processes and controls described herein. Examples of distributed controllers for these purposes include one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely located (such as at the platform level or as part of a remote computer) .

Without limitation, in various embodiments, the system may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel bevel edge etching chambers or modules, PVD chambers or modules, CVD (chemical vapor deposition) chambers or modules, ALD (atomic layer deposition) chambers or modules, ALE (atomic layer etch) chambers or modules, A chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated with or used in the fabrication and / or fabrication of semiconductor wafers.

Although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, etc., in some embodiments, the operations described above may be applied to other types of plasma chambers, , Inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, plasma chambers including dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, and the like. For example, the x ㎒ RF generator, the y ㎒ RF generator, and the z ㎒ RF generator are coupled to the inductor in the ICP plasma chamber. Examples of shapes of inductors include solenoids, dome-shaped coils, and the like.

As mentioned above, in accordance with the process operations to be performed by the tool, the controller may be implemented in one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, Communicate with the tools used to transport the materials to or from the tool locations and / or load ports in the semiconductor fabrication plant, the tools, the main computer, another controller, or the containers of the wafers.

In view of the above embodiments, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are operations that manipulate physical quantities.

Some of the embodiments also relate to a hardware unit or apparatus for performing these operations. The device is specially configured as a special purpose computer. When specified as a special purpose computer, the computer performs other processing, program executions or routines that are not part of a special purpose, but may still operate for a special purpose.

In some embodiments, the operations described herein may be performed by an optionally activated computer, or by one or more computer programs stored in a computer memory, or obtained over a network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, for example, by a cloud of computing resources.

One or more embodiments described herein may also be manufactured with computer-readable code on non-volatile computer-readable media. The non-volatile computer-readable medium is any data storage hardware unit, such as a memory device, that stores data that is thereafter read by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), read-only memory (ROM), random access memory (RAM), compact disc-ROMs, CD- rewritables, magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable media includes computer-readable media distributed over network-coupled computer systems in which the computer-readable code is stored and executed in a distributed manner .

While some of the method operations described above are presented in a particular order, in various embodiments, other housekeeping operations may be performed between method operations, or method operations may be adjusted such that method operations occur at slightly different times , Distributed in a system that allows the generation of method operations at various intervals, or performed in a different order than described above.

It should be noted that in one embodiment, one or more features from any of the embodiments described above are combined with one or more features of any other embodiment without departing from the scope of the various embodiments described in this disclosure do.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the embodiments are to be considered as illustrative rather than restrictive, and the embodiments are not intended to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims (23)

A method for determining fixed parameters of a matching network model,
Measuring the efficiency of the impedance matching network;
Applying input power at an input of the matching network model to calculate the predicted output power at an output of the matching network model when a fixed inductance, a fixed capacitance, and a fixed resistance are assigned to the matching network model;
Calculating a predicted efficiency of the impedance matching model from the predicted output power and the input power;
Determining if the predicted efficiency is within a predetermined limit from the measured efficiency; And
Assigning the fixed inductance, the fixed capacitance, and the fixed resistance to the matching network model after determining that the predicted efficiency is within the predetermined limit from the measured efficiency. Method for determining. The method according to claim 1,
Wherein the measured efficiency is measured when the impedance matching network is connected to a network analyzer and a load impedance fixture, the network analyzer having an input port and an output port, the load impedance fixture and the input Wherein the combined impedance of the port is indicative of a plasma condition. The method according to claim 1,
Further comprising modifying the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof, when determining that the predicted efficiency is not within the predetermined limit from the measured efficiency. A method for determining fixed parameters of a model. The method according to claim 1,
Wherein the measured efficiency is measured when a first port of the network analyzer is connected to the input of the impedance matching network,
Receiving the S21 parameter from the network analyzer when the second port of the network analyzer is connected to the output of the fixture and when the fixture is connected to the output of the impedance matching circuit; And
Further comprising calculating a ratio of a difference between a square of the S21 parameter and a square of the S11 parameter to determine the measured efficiency. The method according to claim 1,
The measured efficiency is calculated when the impedance matching network is controlled to have a pre-determined combined variable capacitance and the network analyzer is operated at a pre-determined RF frequency, and the network analyzer calculates the impedance matching network To the input of the matching network model. The method according to claim 1,
Associating the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof with an identity of the impedance matching network;
Storing the association between the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of the two or more, and the identity in a memory device;
Receiving the identity of the impedance matching network; And
Further comprising initializing the matching network model to have the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof upon receiving the identity, determining fixed parameters of the matching network model Way. The method according to claim 1,
Wherein the measured efficiency is measured when a network analyzer is connected to the input of the impedance matching network and the output of the impedance matching network is connected to a load fixture. The method according to claim 1,
Wherein the step of applying the measured output power to the input of the matching network model is performed when the matching network model is initialized to have a combined capacitance value and RF, Way. 9. The method of claim 8,
Wherein the combined capacitance value is equal to the combined capacitance value of the impedance matching network and the RF is used to measure the measured efficiency. The method according to claim 1,
Wherein the fixed inductance, the fixed capacitance, and the fixed resistance are not changed during processing of the substrate. The method according to claim 1,
Wherein calculating the predicted efficiency of the impedance matching model from the predicted output power and the input power is performed by calculating a ratio of the predicted output power and the input power to determine the fixed parameters of the matching network model Way. A system for determining fixed parameters of a matching network model,
A processor configured to receive input power,
Wherein the processor is configured to apply the input power at the input of the matching network model to calculate the predicted output power at the output of the matching network model when the matching inductance, Lt; / RTI >
Wherein the processor is configured to calculate a predicted efficiency of the impedance matching model from the predicted output power and the input power,
Wherein the processor is configured to determine if the predicted efficiency is within a predetermined limit from the measured efficiency, and
Wherein the processor assigns the fixed inductance, the fixed capacitance, and the fixed resistance to the matching network model after determining that the predicted efficiency is within the predetermined limit from the measured efficiency. And
And a memory device coupled to the processor, the memory device configured to store the matching network model, wherein the memory device is configured to store the matching network model. 13. The method of claim 12,
Wherein the measured efficiency is measured when the impedance matching network is connected to a network analyzer and connected to a load impedance fixture, the network analyzer having an input port and an output port, wherein the load impedance fixture and the input port of the network analyzer Wherein the combined impedance is indicative of a plasma condition. 13. The method of claim 12,
Wherein the processor is configured to modify the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof, when determining that the predicted efficiency is not within the predetermined limit from the measured efficiency. Of the fixed parameters. 13. The method of claim 12,
Wherein the measured efficiency is measured when a first port of the network analyzer is connected to the input of the impedance matching network,
Wherein the processor is configured to receive the S21 parameter from the network analyzer when the second port of the network analyzer is connected to the output of the fixture and when the fixture is connected to the output of the impedance matching circuit,
Wherein the processor is configured to calculate a ratio of the difference between the squares of the S21 parameters and the squares of the 1 and S11 parameters to determine the measured efficiency. 13. The method of claim 12,
Wherein the measured efficiency is measured when the impedance matching network is controlled to have a pre-determined combined variable capacitance and when the network analyzer is operated at a pre-determined radio frequency, To determine the fixed parameters of the matching network model. 13. The method of claim 12,
Wherein the processor is configured to associate the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof with an identity of the impedance matching network,
Wherein the processor is configured to store in the memory device an association between the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof,
Wherein the processor is configured to receive the identity of the impedance matching network, and
Wherein the processor is configured to initialize the matching network model to have the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more of the fixed inductances upon receiving the identity, For the system. 13. The method of claim 12,
To calculate the predicted efficiency of the impedance matching model from the predicted output power and the input power, the processor is configured to calculate the fixed parameters of the matching network model, which are configured to calculate the ratio of the predicted output power to the input power A system for determining. A system for determining fixed parameters of a matching network model,
An RF generator configured to generate an RF signal;
An impedance matching network having an input coupled to the RF generator;
A plasma chamber coupled to the impedance matching network output;
A host computer system coupled to the RF generator, the host computer system including a processor and a memory device, the memory device including the host computer system coupled to the processor,
Wherein the processor is configured to receive input power,
Wherein the processor is configured to apply the input power to the input of the matching network model to calculate the predicted output power at the output of the matching network model when the matching inductance, fixed capacitance, and fixed resistance are assigned to the matching network model,
Wherein the processor is configured to calculate a predicted efficiency of the impedance matching model from the predicted output power and the input power,
Wherein the processor is configured to determine if the predicted efficiency is within a predetermined limit from the measured efficiency, and
Wherein the processor is configured to allocate the fixed inductance, the fixed capacitance, and the fixed resistance to the matching network model after determining that the predicted efficiency is within the predetermined limit from the measured efficiency,
Wherein the memory device is configured to store the matching network model. 20. The method of claim 19,
Wherein the measured efficiency is measured when the impedance matching network is connected to a network analyzer and connected to a load impedance fixture, the network analyzer having an input port and an output port, wherein the load impedance fixture and the input port of the network analyzer Wherein the combined impedance is indicative of a plasma condition of the plasma chamber. 20. The method of claim 19,
Wherein the processor is configured to modify the fixed inductance, or the fixed capacitance, or the fixed resistance, or a combination of two or more thereof, when determining that the predicted efficiency is not within the predetermined limit from the measured efficiency. Of the fixed parameters. 20. The method of claim 19,
Wherein the measured efficiency is determined such that a first port of the network analyzer is coupled to the input of the impedance matching network,
Wherein the processor is configured to receive the S21 parameter from the network analyzer when the second port of the network analyzer is connected to the output of the fixture and when the fixture is connected to the output of the impedance matching circuit,
Wherein the processor is configured to calculate a ratio of the difference between the squares of the S21 parameters and the squares of the 1 and S11 parameters to determine the measured efficiency. 20. The method of claim 19,
Wherein the measured efficiency is calculated when the impedance matching network is controlled to have a pre-determined combined variable capacitance and the network analyzer is operated in a pre-determined RF.

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