KR20170081110A - Display pannel and display device having the same - Google Patents

Abstract

The display panel of the present invention includes a substrate having a plurality of sub-pixel regions divided into a light emitting region and a non-light emitting region, an organic light emitting diode, a transistor, and a storage capacitor, wherein the first electrode of the organic light emitting diode, And the source electrode or the first electrode is overlapped with a part of the contact hole, thereby maximizing the aperture ratio of the sub-pixel and increasing the lifetime of the organic light emitting diode.
The organic light emitting diode display according to the present invention includes a display panel, a source driver, a scan driver, and a controller, wherein a contact hole for electrically connecting the first electrode of the organic light emitting diode and the source electrode of the transistor is formed, The electrode or the first electrode is overlapped with a part of the contact hole, thereby maximizing the aperture ratio of the sub-pixel and increasing the lifetime of the organic light emitting diode.

Description

DISPLAY PANEL AND DISPLAY DEVICE HAVING THE SAME [0002]

The present invention relates to a display panel and a display device having the same.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. Recently, a liquid crystal display device, a plasma display device, an organic light emitting display device Organic Light Emitting Display Device) are being utilized.

Such a display device includes a lower substrate having a structure in which a conductive layer made of a conductive material and insulating layers made of an insulating material are stacked, and an upper substrate arranged opposite to the lower substrate.

Particularly, a plurality of sub-pixels are arranged on a lower substrate of an organic light emitting diode (OLED) display device, and each sub-pixel includes an emission area (EA) composed of an organic light emitting diode (OLED) And a non-emission area (NEA).

As described above, a plurality of transistors and a storage capacitor are disposed in each sub-pixel of the organic light emitting display, and they are electrically connected to the electrodes and wirings located in the upper and lower layers through the contact holes.

Therefore, the contact holes for the transistors disposed in the non-emission region of each subpixel are closely related to the aperture ratio of the emission region.

For example, when the size of the contact holes disposed in the non-emission region is increased, the area of the non-emission region is widened, thereby reducing the area of the emission region. If the area of the light emitting region of the subpixel is reduced, the area of the organic light emitting diode is reduced and the aperture ratio of the subpixel is reduced as a whole.

Also, if the aperture ratio of the subpixel is reduced, the lifetime of the organic light emitting diode is shortened.

The present invention prevents the aperture ratio of the light emitting region (EA) from being reduced even when the position of the contact hole disposed in the non-emitting region of the subpixel divided by the light emitting region (EA) and the non-emitting region (NEA) And an organic light emitting diode (OLED) display device capable of maximizing the aperture ratio of the subpixel and increasing the lifetime of the organic light emitting diode.

According to an aspect of the present invention, there is provided a display panel including a substrate having a plurality of sub-pixel regions divided into a light emitting region and a non-emitting region, an organic light emitting diode disposed in a light emitting region of the sub- And a transistor and a storage capacitor disposed in the non-emission region of the subpixel.

In addition, a contact hole for electrically connecting the first electrode of the organic light emitting diode and the source electrode of the transistor is formed in the non-emission region, the source electrode and the first electrode are disposed on the lower side and the upper side of the contact hole, The first electrode overlaps with a part of the contact hole, and the source electrode and the first electrode are electrically connected through the contact hole, thereby maximizing the aperture ratio of the subpixel and increasing the lifetime of the organic light emitting diode.

In addition, the organic light emitting diode display of the present invention includes a display panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of sub-pixels are arranged, a source driver for driving a plurality of data lines, A scan driver, a source driver, and a controller for controlling the scan driver.

In addition, the subpixel includes an organic light emitting diode disposed in a light emitting region of a subpixel, a transistor disposed in a non-emitting region, and a storage capacitor, the light emitting region being divided into a light emitting region and a non- A source electrode and a first electrode are disposed on the lower and upper sides of the contact hole, the source electrode or the first electrode is overlapped with a part of the contact hole, The source electrode and the first electrode are electrically connected to each other through the contact hole, thereby maximizing the aperture ratio of the subpixel and increasing the lifetime of the organic light emitting diode.

The display panel and the organic light emitting diode display according to the present invention are capable of reducing the size of the contact hole and the size of the contact hole disposed in the non-emission region of the subpixel divided by the emission region EA and the non- The aperture ratio of the organic light emitting diodes (EA) is not reduced, thereby maximizing the aperture ratio of the subpixel and increasing the lifetime of the organic light emitting diode.

1 is a schematic system configuration diagram of an organic light emitting diode display according to the present invention.
FIGS. 2A and 2B are exemplary views illustrating an organic light emitting display sub-pixel structure according to embodiments of the present invention. Referring to FIG.
3A is a plan view showing a sub-pixel structure of an organic light emitting diode display.
FIG. 3B is a view for explaining a problem that occurs when a contact hole is formed in a source electrode region of a driving transistor disposed in each sub-pixel of the organic light emitting display device.
4 is a view showing a state where the aperture ratio of the organic light emitting diode is reduced when the contact hole of the source electrode region of the driving transistor of the organic light emitting display device is extended.
5 is a view illustrating a sub-pixel structure of an OLED display according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a driving transistor and an organic light emitting diode region of an OLED display according to the present invention.
7 is an enlarged view of the area A in Fig.
8 is a cross-sectional view taken along the line II-II 'of FIG.
9 is a view illustrating a sub-pixel structure of an OLED display according to another embodiment of the present invention.
10 is an enlarged view of the area B in Fig.
11 is a cross-sectional view taken along line III-III 'of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

FIG. 1 is a schematic system configuration diagram of an organic light emitting display according to the present invention, and FIGS. 2A and 2B are exemplary views of a subpixel structure of an organic light emitting display according to embodiments of the present invention.

1, a plurality of data lines DL and a plurality of gate lines GL are arranged, and a plurality of sub pixels (SPs) are arranged A source driver 120 driving a plurality of data lines DL, a scan driver 130 driving a plurality of gate lines GL, a source driver 120, A timing controller 140 for controlling the controller 130, and the like.

The timing controller 140 supplies various control signals to the source driver 120 and the scan driver 130 to control the source driver 120 and the scan driver 130.

The timing controller 140 starts scanning according to the timing implemented in each frame and switches the input image data inputted from the outside according to the data signal format used by the source driver 120, ), And controls the display driving data at an appropriate time in accordance with the scan signal.

The source driver 120 drives the plurality of data lines DL by supplying the driving data voltage Vdata to the plurality of data lines DL. Here, the source driver 120 is also referred to as a " data driver ".

The scan driver 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the scan driver 130 is also referred to as a 'gate driver'.

The scan driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the plurality of gate lines GL under the control of the timing controller 140.

When the specific gate line is opened by the scan driver 130, the source driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the source driver 120 is located only on one side (e.g., on the upper side or the lower side) of the display panel 110 but may be disposed on both sides of the display panel 110 ). ≪ / RTI >

1, the scan driver 130 is disposed on only one side (e.g., the left side or the right side) of the display panel 110, The right side).

The timing controller 140 described above includes the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the input data enable signal DE, the clock signal CLK, and the like in addition to the input video data And receives various timing signals from the outside (e.g., the host system).

The timing controller 140 may control the source driver 120 and the scan driver 130 in addition to outputting the converted video data by switching the input video data inputted from the outside according to the data signal format used by the source driver 120 A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the source driver 120 and the scan driver 130 .

For example, in order to control the scan driver 130, the timing controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver ICs constituting the scan driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In addition, the timing controller 140 controls the source driver 120 such that a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, Output enable (DCS) data control signals.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver ICs constituting the source driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the source driver 120. [

The source driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) includes a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, a gamma voltage generator, and the like can do.

Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The scan driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

Each subpixel SP disposed on the display panel 110 may include a circuit element such as a transistor.

For example, in the display panel 110, each sub-pixel SP is composed of an organic light emitting diode (OLED) and a circuit element such as a driving transistor (DT) for driving the organic light emitting diode .

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

2A and 2B, in the organic light emitting diode display 100 according to the present invention, each of the sub pixels includes an organic light emitting diode (OLED), a driving circuit for driving the organic light emitting diode (OLED) And a reference voltage line RVL (reference voltage line) for supplying a reference voltage Vref to the first node N1 of the driving transistor DT, A second transistor T2 electrically connected between a second node N2 of the driving transistor DT and a data line DL supplying a data voltage Vdata; And a storage capacitor Cst (storage capacitor) electrically connected between the first node N1 and the second node N2 of the data driver DT.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

The driving transistor DT supplies driving current to the organic light emitting diode OLED to drive (emit) the organic light emitting diode OLED.

The first node N1 of the driving transistor DT may be electrically connected to the first electrode of the organic light emitting diode OLED and may be a source node or a drain node. The second node N2 of the driving transistor DT may be electrically connected to the source node or the drain node of the second transistor T2 and may be a gate node. The third node N3 of the driving transistor DT may be electrically connected to a driving voltage line (DVL) for supplying a driving voltage EVDD, and may be a drain node or a source node. The gate node, the drain node, and the source node refer to a gate electrode, a drain electrode, and a source electrode.

2A, the first transistor T1 is turned on by the first scan signal SCAN1 to apply a reference voltage Vref to the first node N1 of the driving transistor DT .

In addition, the first transistor T1 may be utilized as a voltage sensing path to the first node N1 of the driving transistor DT when turned on.

The second transistor T2 transfers the data voltage Vdata supplied through the data line DL to the second node N2 of the driving transistor DT when the second transistor T2 is turned on by the second scan signal SCAN2 It does.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DT so that the data voltage corresponding to the video signal voltage or the voltage corresponding thereto is applied for one frame time I can keep it.

The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DT, And is an external capacitor intentionally designed outside the driving transistor DT.

On the other hand, as shown in FIG. 2B, the first transistor T1 and the second transistor T2 may be controlled together by a single scan signal SCAN.

That is, the first transistor T1 and the second transistor T2 are connected to the same gate line GL, and the same scan signal SCAN can be supplied to both the first transistor T1 and the second transistor T2.

The reference voltage line RVL electrically connected to the drain node or the source node of the first transistor T1 may be arranged one for each sub pixel column or two or more sub pixel columns And may be arranged one by one.

For example, when one pixel is composed of four subpixels (red subpixel, white subpixel, blue subpixel, green subpixel), the reference voltage line RVL is divided into four subpixel columns , A white subpixel column, a blue subpixel column, and a green subpixel column).

In the case of the organic light emitting diode display 100 according to the present invention, as the driving time of each sub-pixel SP becomes long, the deterioration of circuit elements such as the organic light emitting diode OLED and the driving transistor DT Degradation can proceed.

Accordingly, inherent characteristic values (e.g., threshold voltage, mobility, etc.) of the circuit elements such as the organic light emitting diode OLED and the driving transistor DT can be changed.

Such a change in the characteristic value of the circuit element causes the luminance change of the corresponding subpixel.

Here, the characteristic value of a circuit element (hereinafter also referred to as a " subpixel characteristic value ") may include, for example, a threshold voltage and mobility of the driving transistor DT, May include the threshold voltage of the transistor.

The organic light emitting diode display 100 according to the present invention includes a sensing function for sensing a characteristic value variation of a subpixel or a characteristic value deviation between subpixels and a compensation function for compensating a subpixel characteristic value using a sensing result can do.

Accordingly, the organic light emitting diode display 100 of the present invention is provided with a subpixel structure (FIG. 2A or 2B) corresponding thereto, and a compensation including a sensing and compensation structure, in order to provide a sensing and compensation function for the subpixel characteristic value. Circuit.

Particularly, in the organic light emitting diode display of the present invention, the area of the light emitting area EA is not reduced even if the positions of the contact holes provided in the non-emitting area NEA of the sub pixel are changed or the size of the contact hole is greatly changed, The aperture ratio of the pixel is secured to prevent the shortening of the lifetime of the organic light emitting diode.

FIG. 3A is a plan view showing a subpixel structure of the organic light emitting display device, FIG. 3B is a view explaining a problem that occurs when a contact hole formed in a source electrode region of a driving transistor disposed in each subpixel of the organic light emitting diode And FIG. 4 is a view showing a state where the aperture ratio of the organic light emitting diode is reduced when the contact hole of the source electrode region of the driving transistor of the organic light emitting display device is extended.

3A and 3B, each subpixel SP of the organic light emitting diode display 100 is defined by intersecting the gate line 300 and the data line 310. The subpixel SP may be divided into a light emitting region EA where the organic light emitting diode OLED is disposed and a non-light emitting region NEA where the transistors are disposed.

 The subpixel SP may include a driving transistor DT, a first transistor T1, a second transistor T2, a storage capacitor Cst, and an organic light emitting diode (OLED).

2B, a one-scan line structure in which the first transistor T1 and the second transistor T2 operate in one gate line 300 is mainly described. However, as shown in FIG. 2A, The same can be applied to the case of two scan lines of two individuals.

More specifically, the second transistor T2 is controlled by a scan signal supplied from the gate line 300, receives a data voltage from the data line 310, and stores the data voltage in the storage capacitor Cst.

The first transistor T1 is controlled by a scan signal supplied from the gate line 300 and supplies a reference voltage Vref through the first connection pattern 340 electrically connected to the reference voltage line RVL to the driving transistor DT to the source electrode 270 of the TFT.

The storage capacitor Cst is disposed such that the first storage electrode CE1 and the second storage electrode CE2 overlap each other. The first storage electrode CE1 is connected to the gate electrode 430 of the driving transistor DT, 1 contact holes C1.

The second storage electrode CE2 is electrically connected to the source electrode 270 of the driving transistor DT so that the source electrode 270 is electrically connected to the first electrode of the organic light emitting diode OLED, And the first node N1 to which the first node 211 is connected. The first electrode 211 is extended from the light emitting region EA to overlap the driving transistor DT and the storage capacitor Cst in the non-light emitting region NEA.

The source electrode 270 of the driving transistor DT is electrically connected to the first electrode 211 of the organic light emitting diode OLED through the second contact hole C2. The first electrode 211 is disposed in the bank layer open region 200 and the organic light emitting layer OLED is formed on the first electrode 211 by stacking the organic light emitting layer and the second electrode. do.

Although not shown in the figure, reference numeral 330 denotes a driving voltage line (DVL), and reference numeral 190 denotes a second connection pattern, which functions to connect the driving voltage line 330 to driving transistors of adjacent subpixels. A light blocking layer 290 is disposed in the region of the driving transistor DT and the storage capacitor Cst in the non-emission region NEA of the subpixel SP.

The redundancy pattern 370 may be formed of the same material as that of the first electrode 211 and may not be connected to other wirings They are placed in isolation.

The redundancy pattern 370 is used when the defective sub-pixel SP is electrically connected to the first electrode of the adjacent normal sub-pixel to repair the defective sub-pixel.

Therefore, the redundancy pattern 370 must be spaced a certain distance D from the first electrode 211 of the organic light emitting diode OLED, since the redundancy pattern 370 is a pattern used when repairing a sub-pixel is required.

This is because if the first electrode 211 and the redundancy pattern 370 are adjacent to each other by a certain distance D or less, there is a problem that the redundancy pattern 370 and the first electrode 211 are electrically short-circuited .

3A, when the position of the second contact hole C2 is moved in the direction of the redundancy pattern 370, the electrical connection between the source electrode 270 and the first electrode 211 of the driving transistor DT The first electrode 211 also moves in the direction of the redundancy pattern 370 and the distance between the first electrode 211 and the redundancy pattern 370 is narrowed to D1.

3A and 3B, the second contact hole C2 is moved in the direction of the redundancy pattern 370, and correspondingly, the first electrode 211 is extended to cover the second contact hole C2 The distance D1 between the first electrode 211 and the redundancy pattern 370 becomes closer (FIG. 3 (a)).

3B, a light blocking layer 290 is disposed on the substrate 400 in the second contact hole C2 region, a buffer layer 402 is formed on the light blocking layer 290, Respectively. An active layer 404 of the driving transistor DT is disposed on the buffer layer 402. The active layer 404 is electrically connected to the source electrode 270 through the exposed region of the interlayer insulating layer 407 have.

The first electrode 211 and the source electrode 270 are electrically connected to each other through the second contact hole C2 formed on the protective layer 408. The protective layer 408 is formed on the source electrode 270, do.

However, since the source electrode 270 disposed on the lower side with respect to the second contact hole C2 and the first electrode 211 disposed on the upper side are formed to cover the entire second contact hole C2, The distance between the redundancy pattern 211 and the redundancy pattern 370 becomes closer. In the figure, reference numeral 420 denotes a bank layer 420.

Therefore, in order to secure the design distance D between the first electrode 211 and the redundancy pattern 370 in the movement of the contact hole disposed in the sub-pixel, the area of the non-emission area NEA must be increased. The aperture ratio of the aperture stop EA is reduced.

4, when the size of the second contact hole C2 of the driving transistor DT is increased, the source electrode 270 disposed under the second contact hole C2 must be formed to be large. 2 contact hole C2 can be positioned on the source electrode 270. [

When the source electrode 270 is formed to be large, the first storage electrode CE1 of the storage capacitor Cst, the drain electrode connected to the gate electrode 430 of the driving transistor DT and the driving voltage line 330, There arises a problem that the opening area of the light emitting area EA is reduced because the position of the light emitting area 280 must be moved toward the light emitting area EA.

The display panel and the organic light emitting display according to the present invention are characterized in that when a position of a contact hole formed in a non-emission region of a subpixel moves, a portion of the first electrode formed in the contact hole region is overlapped, And the design distance between the first electrode and the redundancy pattern is maintained.

When the size of the contact hole formed in the non-emission region of the subpixel is enlarged, a portion of the source electrode disposed below the contact hole and the contact hole are overlapped with each other to secure the aperture ratio of the emission region, To prevent shortening.

6 is a cross-sectional view illustrating a driving transistor and an organic light emitting diode region of an OLED display according to an exemplary embodiment of the present invention. FIG. 7 is a cross- 5 is an enlarged view of the region A, and Fig. 8 is a cross-sectional view taken along a line II-II 'in Fig.

Referring to FIG. 2B together with FIGS. 5 to 8, a display panel and an OLED display 100 according to the present invention define a subpixel by intersecting a gate line 300 and a data line 310.

Each subpixel SP is divided into a light emitting region EA and a non-light emitting region NEA and an organic light emitting diode OLED is disposed in the light emitting region EA. The organic light emitting diode OLED may have a structure in which an organic light emitting layer 212 and a second electrode (not shown) are stacked on the first electrode 211 and the first electrode 211.

Driving elements composed of the driving transistor DT, the first transistor T1, the second transistor T2 and the one storage capacitor Cst are arranged in the non-emission region NEA.

The driving transistor DT includes a drain electrode 280 connected to the driving voltage line 330, a gate electrode 430 disposed adjacent to the drain electrode 280, and an active layer disposed across the storage capacitor Cst And a source electrode 270 connected to the second storage electrode CE2 of the storage capacitor. The gate electrode 430 is electrically connected to the first storage electrode CE1 of the storage capacitor Cst through the first contact hole C1.

The first storage electrode CE1 and the second storage electrode CE2 of the storage capacitor Cst are overlapped with each other.

The second storage electrode CE2 may be formed by conducting a plasma treatment on a part of the active layer 404 overlapping the first storage electrode CE1 or by forming an electrode pattern As shown in FIG.

The first electrode 211 of the organic light emitting diode is disposed in the emission region EA and extends along the non-emission region NEA to overlap the driving transistor DT and the storage capacitor Cst. Also, the first electrode 211 is electrically connected to the source electrode 270 through the second contact hole C2.

That is, the source electrode 270 and the first electrode 211 of the driving transistor DT are electrically connected to each other at the position of the first node N1 of FIG. 2B.

As shown in the figure, when the position of the second contact hole C2 is moved below the non-emission region NEA, the source electrode 270 disposed below the second contact hole C2, And the first electrode 211 covering the second contact hole C2 is disposed so as to partially overlap the second contact hole C2.

More specifically, although the source electrode 270 disposed on the lower side of the second contact hole C2 is reduced in size, the source electrode 270 is overlapped with the second contact hole C2 in the entire region, and on the upper side of the second contact hole C2 The first electrode 211 and the source electrode 270 are electrically connected to each other while overlapping the first electrode 211 and the second contact hole C2.

Therefore, even if the position of the second contact hole C2 moves in the direction of the redundancy pattern 370, the first electrode 211 does not extend, and the source electrode 270 ).

That is, the distance between the edge of the first electrode 211 and the edge of the redundancy pattern 370 intersecting with the gate line 300 maintains the design distance D before the second contact hole C2 is moved.

As described above, the display panel and the organic light emitting diode display according to the present invention are capable of changing the position of the second contact hole C2 formed in the non-emission region of the subpixel, Emitting region NEA can be maximized without enlarging the area of the non-emission region NEA by overlapping only a portion of the second contact hole C2 with the second contact hole C2.

6 and 7, in the sub-pixel structure of the present invention, the driving transistor DT includes a gate electrode 430, a gate pattern 403, an interlayer insulating layer 407, an active layer 404, a drain electrode 280, and a source electrode 270.

A light blocking layer 290 and a buffer layer 402 are stacked and arranged between the driving transistor DT and the substrate 400.

A protective layer 408 is disposed on the driving transistor DT and a second contact hole C2 for exposing a part of the source electrode 270 is formed on the protective layer 408. [

The source electrode 270 is connected to the first electrode 211 disposed in the organic light emitting diode OLED region in the second contact hole C2 region.

That is, although the second contact hole C2 moves in the direction of the redundancy pattern 370, since the first electrode 211 of the organic light emitting diode OLED is not extended, Only a part of the electrode 211 overlaps the second contact hole C2. Therefore, a part of the first electrode 211 is electrically connected to the source electrode 270 in the second contact hole C2 region.

In addition, since the bank layer 420 is filled in the second contact hole C2 region, even if a part of the first electrode 211 is connected to the source electrode 270, the device characteristics are not affected.

The organic light emitting diode OLED is disposed in the emission region of the subpixel. The first electrode 211 is formed on the passivation layer 408 and the organic emission layer 212 is disposed on the first electrode 211. Although not shown in the drawing, a second electrode may be disposed on the organic light emitting layer 212.

Although not shown in the drawing, an organic layer or an overcoat layer may be additionally formed between the protective layer 408 and the organic light emitting diode OLED.

8, the active layer 404 and the source electrode 270 are electrically connected to each other in the second contact hole C2 region, and the passivation layer 408 is formed on the source electrode 270. Referring to FIG. The protective layer 408 is partially removed to form the second contact hole C2 and the first electrode 211 is disposed on the protective layer 408. The first electrode 211 is electrically connected to the second contact hole C2 are overlapped with the source electrode 270 under the second contact hole C2.

As described above, in the present invention, even if the position of the second contact hole C2 formed in the non-emission region is moved, the first electrode 211 is not extended and the first electrode 211 is formed in the second contact hole C2 region 211 are partially connected to the source electrode 270 so that the aperture ratio of the light emitting region can be maximized while maintaining the design distance between the first electrode 211 and the redundancy pattern 370.

In addition, since the bank layer 420 made of an insulating material is filled in the second contact hole C2 region, deterioration of device performance is prevented.

In addition, even if the position of the contact hole formed in the non-emission region of the subpixel is shifted, the aperture ratio of the emission region is not reduced, thereby reducing the lifetime of the organic light emitting diode.

FIG. 9 is a view showing a sub-pixel structure of an organic light emitting diode display according to another embodiment of the present invention, FIG. 10 is an enlarged view of a region B in FIG. 9, and FIG. 11 is a sectional view taken along the line III- Sectional view.

Referring to FIG. 2B and FIGS. 9 to 11, a display panel and an organic light emitting diode display 100 according to the present invention include a driving transistor DT and a first electrode 211 of an organic light emitting diode, (C2).

4, when the source electrode 270 disposed under the second contact hole C2 is extended to form the source electrode 270 (see FIG. 4) The first storage electrode CE1 of the storage capacitor Cst and the drain electrode 280 and the gate electrode 430 of the driving transistor DT arranged between the light emitting regions are moved in the light emitting region direction, There arises a problem that the aperture ratio of the diode is reduced.

According to the present invention, when the second contact hole C2 is formed to be large, the size of the source electrode 270 disposed below the second contact hole C2 is not enlarged, So that the aperture ratio of the light emitting region EA is prevented from decreasing.

10 and 11, in the region B, a light blocking layer 290 and a buffer layer 402 are stacked on a substrate 400, and an active layer 404 is formed on the buffer layer 402 Respectively.

A second contact hole C2 in which a part of the interlayer insulating layer 407 and the protective layer 408 are removed is formed on the active layer 404 and the source electrode 270 is formed in the second contact hole C2 Only a part thereof is formed.

More specifically, the source electrode 270 disposed on the lower side of the second contact hole C2 overlaps with a part of the second contact hole C2 and is electrically connected to the first electrode (not shown) disposed on the upper side of the second contact hole C2 211 are electrically connected to the first electrode 211 and the source electrode 270 while being overlapped in the entire region of the second contact hole C2.

The first electrode 211 formed on the protective layer 408 covers the entire second contact hole C2 and the bank layer 420 completely covers the second contact hole C2 region.

As described above, even if the second contact hole C2 is extended, the source electrode 270 is connected to the active layer 404 (second story electrode) while overlapping only a part of the second contact hole C2.

In addition, since the bank layer 420 is disposed in the second contact hole C2 in which the first electrode 211 is disposed, deterioration of device performance can be prevented.

That is, in the present invention, even if the size of the second contact hole C2 is increased, the source electrode 270 disposed under the second contact hole C2 is not extended, thereby preventing the aperture ratio of the light emitting region from being lowered.

In the present invention, since the size of the first electrode 211 is not changed, the design distance with respect to the redundancy pattern 370 can be maintained at D, and the short circuit between the first electrode 211 and the redundancy pattern 370 Defects can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
120: Source driver
130: scan driver
140: Tie network controller
270: source electrode
280: drain electrode
430: gate electrode
C1: first contact hole
C2: second contact hole

Claims (10)

A substrate having a plurality of sub-pixel regions divided into a light emitting region and a non-light emitting region;
An organic light emitting diode disposed in a light emitting region of the subpixel; And
A transistor and a storage capacitor disposed in a non-emission region of the subpixel,
A contact hole for electrically connecting the first electrode of the organic light emitting diode and the source electrode of the transistor is formed in the non-emission region,
The source electrode and the first electrode are disposed on the lower side and the upper side of the contact hole,
Wherein the source electrode or the first electrode overlaps with a part of the contact hole,
And the source electrode and the first electrode are electrically connected through the contact hole. The method according to claim 1,
Wherein the first electrode overlaps with the entire region of the contact hole on the contact hole when the source electrode and the contact hole partially overlap each other. The method according to claim 1,
Wherein the source electrode overlaps the entire region of the contact hole from the lower side of the contact hole when the first electrode overlaps with a part of the contact hole. The method according to claim 1,
And a first electrode of the organic light emitting diode disposed in the light emitting region is extended to the non-emitting region to be electrically connected to the source electrode of the transistor. The method according to claim 1,
And a bank layer disposed in the entire region of the contact hole in which the source electrode and the first electrode are disposed. A display panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of subpixels are arranged;
A source driver for driving the plurality of data lines;
A scan driver for driving the plurality of gate lines; And
And a controller for controlling the source driver and the scan driver,
The subpixel is divided into a light emitting region and a non-emitting region, and includes an organic light emitting diode disposed in a light emitting region of the subpixel, a transistor disposed in the non-emitting region, and a storage capacitor,
A contact hole for electrically connecting the first electrode of the organic light emitting diode and the source electrode of the transistor is formed in the non-emission region,
The source electrode and the first electrode are disposed on the lower side and the upper side of the contact hole,
Wherein the source electrode or the first electrode overlaps with a part of the contact hole,
And the source electrode and the first electrode are electrically connected through the contact hole. The method according to claim 6,
Wherein the first electrode overlaps with the entire region of the contact hole on the contact hole when the source electrode and the contact hole partially overlap each other. The method according to claim 6,
Wherein the source electrode overlaps the entire region of the contact hole from the lower side of the contact hole when the first electrode overlaps with a part of the contact hole. The method according to claim 6,
And a first electrode of the organic light emitting diode disposed in the light emitting region is extended to the non-emitting region to be electrically connected to the source electrode of the transistor. The method according to claim 6,
And a bank layer disposed in the entire region of the contact hole in which the source electrode and the first electrode are disposed.

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