KR20170081109A - Array substrate and organic light-emitting display device having the same - Google Patents

Abstract

An array substrate of the present invention includes a substrate on which first and second non-display regions arranged so as to face each other with a display region in which a plurality of sub-pixels are arranged and a display region are partitioned, The first pad region in which the reference voltage pads are arranged and the second pad region in which the second reference voltage pads are arranged, thereby preventing a minute short circuit or damage of the reference voltage line due to foreign matter after the substrate is cut.
The first non-display region of the display panel includes data pads formed integrally with the data lines, and a plurality of data lines formed integrally with the reference voltage lines. The first pad region in which the first reference voltage pads are formed and the second non-display region includes the second pad region in which the second reference voltage pads formed integrally with the reference voltage line are disposed, It is possible to prevent the degradation of the compensation characteristic due to the influence of the external force.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display, and an organic light emitting diode (OLED)

The present invention relates to an array substrate and an organic light emitting display having the same.

2. Description of the Related Art [0002] In recent years, an organic light emitting diode (OLED) display device that has been spotlighted as a display device has advantages of high response speed, high luminous efficiency, high luminance and wide viewing angle by using an organic light emitting diode (OLED)

Such an organic light emitting display device arranges subpixels including organic light emitting diodes in a matrix form and controls the brightness of subpixels selected by the scan signals according to the gradation of data.

Such an organic light emitting display device includes a display area A / A in which subpixels are arranged and an image is displayed, and pads Pad for connection to an external driving IC along the periphery of the display area A / A And has a non-display area N / A (Non Active Area).

In the non-display area N / A, gate pads and data pads for connection with the external driver are arranged side by side. In addition, the gate pads and data pads are connected to each other by shorting bars for anti-static and auto-probing.

Also, in the final step of the organic light emitting diode display, the pad region in which the gate pads and the data pads are arranged and the sho tting bar region in which the shorting bars are disposed are cut off, thereby separating the display region from the display panel at all times.

Such an organic light emitting display may further include transistors corresponding thereto for further performing various functions in each subpixel, thereby further arranging signal lines for supplying various signals to the transistors.

For example, when an internal or external compensation circuit is applied to a subpixel to improve the luminance unevenness between subpixels, a transistor involved in the sensing operation for compensation must be added, and a signal line connected thereto must be added.

A reference voltage line, also referred to as a " sensing line " is disposed in the signal lines. In order to compensate for internal or external signals, an initialization signal or the like must be supplied to the subpixel through the reference voltage line. And a shorting bar for connecting them is added.

Since the reference voltage pads, the connection lines extending from the pads, and the shorting bars must be disposed in the non-display area N / A, short failures with existing data pads due to spatial restrictions There is a problem that it becomes vulnerable to line damage.

In the present invention, the first non-display area and the second display area are disposed facing each other with the display area (A / A) therebetween, data pads and the shorting bars connected to the data pads are arranged in the first non- , And a reference voltage pad and a shorting bar connected to the reference voltage pads are disposed in the second non-display area to prevent damage to the reference voltage line due to foreign matter after cutting the substrate, and an organic light emitting display device having the same .

Further, according to the present invention, by disposing a second pad region in which reference voltage pads are arranged to face a first pad region in which data pads are disposed with a display region (A / A) therebetween, And an organic light emitting diode (OLED) display device including the same.

According to an aspect of the present invention, there is provided an array substrate comprising: a display region in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged; Wherein the first non-display region includes a data pad formed integrally with the data line and a first non-display region formed integrally with the reference voltage line arranged in the display region, wherein the first and second non- The first non-display region includes a first pad region in which reference voltage pads are disposed, and a first shorting bar region including a plurality of shorting bars electrically connected to data pads in the first pad region, And a shorting bar electrically connected to the second reference voltage pads of the second pad region, wherein the second reference voltage pads 2 shows the substrate after cutting, by including tingba area has a short circuit or prevent the fine reference voltage line damaging effects caused by foreign substances.

Further, the organic light emitting diode display of the present invention includes a display region in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged, and a plurality of subpixels arranged in the display region, A source driver for driving the plurality of data lines, a scan driver for driving the plurality of gate lines, a controller for controlling the source driver and the scan driver, Wherein the first non-display region of the first non-display region includes data pads formed integrally with the data line and a first pad region in which first reference voltage pads formed integrally with a reference voltage line disposed in the display region are disposed, Region includes a second pad region in which second reference voltage pads formed integrally with the reference voltage line are arranged, It has the effect of preventing the characteristic degradation due to poor compensation.

The array substrate and the organic light emitting display device having the same according to the present invention are arranged such that the first non-display region and the second display region are opposed to each other with the display region (A / A) therebetween, Data pads and shorting bars connected to the data pads are disposed in the first non-display region, and shorting bars connected to the first and second non-display regions are disposed in the second non-display region to prevent a micro short- .

The array substrate according to the present invention and the organic light emitting diode display device having the array substrate according to the present invention may further include a second pad having reference voltage pads disposed to face the first pad region in which data pads are disposed with a display region A / By arranging the regions, it is possible to prevent the degradation of the compensation characteristic due to the short-circuit failure of the reference voltage line.

1 is a schematic system configuration diagram of an organic light emitting diode display according to the present invention.
2 is an exemplary view illustrating an organic light emitting display sub-pixel structure according to embodiments of the present invention.
3 is a plan view schematically showing a part of a display panel of an organic light emitting display according to the present invention.
4A is a view showing a structure of pads and shorting bars disposed on an array substrate of an organic light emitting display device.
FIG. 4B is a view showing a short circuit failure occurring on a cut surface when shorting bars disposed on the array substrate of the organic light emitting display device are removed.
5 is a diagram showing the structure of a display region and a non-display region of an array substrate of an organic light emitting diode display of the present invention.
6 is a cross-sectional view of the subpixel region, I-I 'and II-II' in FIG.
FIG. 7 is an enlarged view of the area X in FIG.
8 is an enlarged view of the Y area in Fig.
FIGS. 9A and 9B are diagrams comparing a compensation value variation in the case where a short circuit defect occurs in a reference voltage line of the organic light emitting display device of the present invention and a case in which a short circuit defect does not occur. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a schematic system configuration diagram of an OLED display 100 according to the present invention.

1, a plurality of data lines DL and a plurality of gate lines GL are arranged, and a plurality of sub pixels (SPs) are arranged A source driver 120 driving a plurality of data lines DL, a scan driver 130 driving a plurality of gate lines GL, a source driver 120, A timing controller 140 for controlling the controller 130, and the like.

The timing controller 140 supplies various control signals to the source driver 120 and the scan driver 130 to control the source driver 120 and the scan driver 130.

The timing controller 140 starts scanning according to the timing implemented in each frame and switches the input image data inputted from the outside according to the data signal format used by the source driver 120, ), And controls the display driving data at an appropriate time in accordance with the scan signal.

The source driver 120 drives the plurality of data lines DL by supplying the driving data voltage Vdata to the plurality of data lines DL. Here, the source driver 120 is also referred to as a " data driver ".

The scan driver 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the scan driver 130 is also referred to as a 'gate driver'.

The scan driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the plurality of gate lines GL under the control of the timing controller 140.

When the specific gate line is opened by the scan driver 130, the source driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the source driver 120 is located only on one side (e.g., on the upper side or the lower side) of the display panel 110 but may be disposed on both sides of the display panel 110 ). ≪ / RTI >

1, the scan driver 130 is disposed on only one side (e.g., the left side or the right side) of the display panel 110, The right side).

The timing controller 140 described above includes the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the input data enable signal DE, the clock signal CLK, and the like in addition to the input video data And receives various timing signals from the outside (e.g., the host system).

The timing controller 140 may control the source driver 120 and the scan driver 130 in addition to outputting the converted video data by switching the input video data inputted from the outside according to the data signal format used by the source driver 120 A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the source driver 120 and the scan driver 130 .

For example, in order to control the scan driver 130, the timing controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver ICs constituting the scan driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In addition, the timing controller 140 controls the source driver 120 such that a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, Output enable (DCS) data control signals.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver ICs constituting the source driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the source driver 120. [

The source driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) includes a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, a gamma voltage generator, and the like can do.

Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The scan driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

Each subpixel SP disposed on the display panel 110 may include a circuit element such as a transistor.

For example, in the display panel 110, each sub-pixel SP is composed of an organic light emitting diode (OLED) and a circuit element such as a driving transistor for driving the organic light emitting diode (OLED).

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

FIG. 2 is a view illustrating an example of a sub-pixel structure of an organic light emitting display according to embodiments of the present invention, and FIG. 3 is a plan view of a part of a display panel of an OLED display according to the present invention

Referring to FIG. 2, the OLED display 100 according to the present invention may include a compensation structure for compensating a characteristic value of a sub-pixel in each sub-pixel.

 The driving circuit in the sub-pixel having the compensation structure includes, for example, three transistors (a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, and a capacitor Cstg) Lt; / RTI >

Thus, a subpixel including three transistors (DRT, SWT, SENT) and one capacitor (Cstg) has a "3T1C structure".

Referring to FIG. 2, the driving transistor DRT is a transistor for driving the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

In the driving transistor DRT, the node N1 may be electrically connected to the first electrode or the second electrode of the organic light emitting diode OLED, and the node N2 may be electrically connected to the source node or the drain node of the switching transistor SWT. And the N3 node may be electrically connected to the driving voltage line DVL for supplying the driving voltage EVDD.

The switching transistor SWT is a transistor for transferring the data voltage Vdata to the N2 node corresponding to the gate node of the driving transistor DRT.

This switching transistor SWT is controlled by the scan signals SCAN (gate high voltage VGH and gate low voltage VGL) applied to the gate node and is supplied to the N2 node of the driving transistor DRT and the data line DL As shown in Fig.

Referring to FIG. 2, a sensing transistor SENT is newly added to a sub-pixel of a general OLED display. The added sensing transistor SENT is controlled by a sense signal SENSE which is a type of a scan signal applied to the gate node and is connected between the reference voltage line RVL and the node N1 of the drive transistor DRT And can be electrically connected.

This sensing transistor SENT is turned on to apply the reference voltage Vref supplied through the reference voltage line RVL to the N1 node (e.g., the source node or the drain node) of the driving transistor DRT .

The sensing transistor SENT serves to allow the voltage of the node N1 of the driving transistor DRT to be sensed by an analog-to-digital converter (ADC) electrically connected to the reference voltage line RVL.

The role of the sensing transistor SETN is related to the compensation function for the characteristic value of the driving transistor DRT. Here, the inherent characteristic value of the driving transistor DRT may include, for example, a threshold voltage (Vth), a mobility, and the like.

The reference voltage line RVL electrically connected to the drain node or the source node of the first transistor T1 may be arranged one for each sub pixel column or two or more sub pixel columns And may be arranged one by one.

For example, referring to FIG. 3, when one pixel is composed of four subpixels (red subpixel SP1, white subpixel SP2, green subpixel SP3, and blue subpixel SP4) , And the reference voltage line RVL may be arranged for each of four sub-pixel columns (a red sub-pixel column, a white sub-pixel column, a green sub-pixel column, and a blue sub-pixel column).

In the case of the organic light emitting diode display 100 according to the present invention, as the driving time of each sub-pixel SP increases, deterioration of circuit elements such as the organic light emitting diode OLED and the driving transistor DRT Degradation can proceed.

Accordingly, inherent characteristic values (e.g., threshold voltage, mobility, etc.) of the circuit elements such as the organic light emitting diode OLED and the driving transistor DRT can be changed.

Such a change in the characteristic value of the circuit element causes the luminance change of the corresponding subpixel.

Here, the characteristic value of a circuit element (hereinafter also referred to as a " subpixel characteristic value ") may include, for example, a threshold voltage and a mobility of a driving transistor DRT, May include the threshold voltage of the transistor.

The organic light emitting diode display 100 according to the present invention includes a sensing function for sensing a characteristic value variation of a subpixel or a characteristic value deviation between subpixels and a compensation function for compensating a subpixel characteristic value using a sensing result can do.

As shown in FIG. 3, the four sub-pixels SP1 to SP4 connected to the reference voltage line RVL are arranged symmetrically with respect to the reference voltage line RVL.

For example, the reference voltage line RVL and the second and third subpixels SP2 and SP3 are directly connected to the reference voltage line RVL and connected to the first and fourth subpixels SP1 and SP4 Pattern (CP).

According to this reference voltage line connection structure, each of the sub-pixels SP1 to SP4 receives the reference voltage Vref from the reference voltage line RVL to the node N1, the sensing transistor SENT arranged in each of the sub-pixels SP1 to SP4, .

As described above, when the compensation circuit is disposed in each subpixel of the OLED display device, each of the subpixels SP1 to SP4 can operate in a display mode or a sensing mode. In the sensing mode, when the characteristic values of the subpixels are changed, such as when deterioration occurs in the display mode of each of the subpixels SP1 to SP4, the changed characteristic value is sensed and the compensated data voltage is provided in the display mode.

Since the reference voltage line RVL is added based on the four subpixels when the compensation circuit is disposed in each subpixel of the organic light emitting diode display device, So that the spacing between the pads is narrowed.

The array substrate of the present invention and the organic light emitting diode display device having the array substrate of the present invention are arranged such that the reference voltage pads of the reference voltage lines to be added are arranged in different regions from the data pads to prevent the short circuit failure and compensation errors of the reference voltage lines.

FIG. 4A is a view showing the structure of pads and shorting bars disposed on the array substrate of the organic light emitting diode display device, FIG. 4B is a diagram illustrating a state where shorting bars disposed on the array substrate of the OLED display device are removed, FIG.

Referring to FIGS. 4A and 4B, as shown in FIGS. 2 and 3, each of the sub-pixels SP1 to SP4 includes a compensation circuit for compensating sub-pixel property values. As a result, the reference voltage line RVL is additionally disposed in the basic organic light emitting display.

The display panel 110 may include an array substrate on which transistors and an organic light emitting diode (OLED) are formed, and an upper substrate (encapsulation substrate) on an array substrate. The display panel can be realized by disposing the upper substrate on the array substrate and then removing the shorting bars formed on the array substrate.

3, when one reference voltage line RVL is arranged in the four sub-pixels SP1 to SP4, the display region A / A of the array substrate is provided with a reference Voltage lines RVL are arranged.

Thus, in the non-display area N / A disposed on the array substrate of the display panel 110, a pad area PA composed of pads PD, a plurality of extended signal lines ESL And a plurality of shorting bars SB1 to SB5 connected to the extended signal lines ESL via the contact holes C. The shorting bar area SBP includes a plurality of shorting bars SB1 to SB5.

The pads PD include data pads DPD and reference voltage pads RVPD connected to the data lines DL and the reference voltage line RVL, (ESL) are formed integrally with each other.

The first shorting bar SB1 disposed in the shorting bar area SBP may be a shorting bar connected to the reference voltage line RVL and the second through fifth shorting bars SB2 to SB5 may be shorting bars connected to the data line DL. Lt; RTI ID = 0.0 &

The array substrate of the organic light emitting diode display having the above structure cuts the grinding region (GDA) when the auto probe inspection process such as lighting test is completed through the shorting bars SB1 to SB5 to complete the display panel.

Thus, as shown in FIG. 4B, when the array substrate is cut along the grinding region GDA, extended signal lines ESL extending from the pad region PA are exposed to the grinding end face.

In particular, since the reference voltage line RVL is added, the interval between the extended signal lines ESL becomes narrow, and a short failure occurs due to foreign matter or the like between the extended signal lines ESL.

When the reference voltage line RVL is short-circuited to the adjacent other data line DL, when the organic light emitting display device operates in the sensing mode, the voltage of the reference voltage line RVL is affected, There is a problem that arises.

The array substrate and the organic light emitting diode display of the present invention are arranged such that the reference voltage pads of the reference voltage line arranged to sense the deterioration of the driving transistor or the organic light emitting diode arranged in the subpixels SP1 to SP4, Area and the other pad area, it is possible to prevent short-circuit failure between the reference voltage line and the data line due to the grinding process for separating the shorting bars.

That is, the array substrate according to the present invention and the organic light emitting display device having the array substrate according to the present invention are arranged such that the first non-display region and the second display region overlap each other with the display region A / A in between, The data pads and the shorting bars connected to the data pads are arranged in the second non-display region, and the shorting bars connected to the reference pads and the shorting bars connected to the data pads are arranged in the second non-display region. .

The array substrate according to the present invention and the organic light emitting diode display device having the array substrate according to the present invention may further include a second pad having reference voltage pads disposed to face the first pad region in which data pads are disposed with a display region A / By arranging the regions, it is possible to prevent the degradation of the compensation characteristic due to the short-circuit failure of the reference voltage line.

5 is a diagram showing the structure of a display region and a non-display region of an array substrate of an organic light emitting diode display of the present invention.

5, the OLED display 100 includes a display area A / A in which a plurality of subpixels SP are arranged to display an image, a display area A / And a non-display area N / A disposed along the periphery.

The non-display area N / A disposed on the display panel 110 of the present invention includes a first non-display area N / A_1 including a first pad area PA1 formed of data pads DPD, And a second non-display area N / A_2 facing the first non-display area N / A_1 with the display area A / A therebetween. Although not shown in the figure, the region constituted by the gate pads GPD may include a third non-display region (not shown).

A first non-display area N / A_1 arranged on the array substrate of the display panel 110 is connected to data pads DPD connected to a plurality of data lines and a first reference voltage Vdd connected to a plurality of reference voltage lines RVL. The first pad region PA1 in which the pads Vref_PD1 are arranged and the second to fifth shorting bars SB2 to SB5 electrically connected to the data pads DPD in the first pad region PA1, A first grating region SBP1 in which a first extended signal line ESL1 for connecting the data pads DPD and second to fifth shorting bars SB2 to SB5 is disposed, GDA1).

The first extended signal line ESL1 is formed integrally with the data pads DPD and is connected to the second through fifth shorting bars SB2 through SB5 by the first contact hole C1.

The second non-display region of the array substrate includes a second pad region PA2 in which second reference voltage pads Vref_PD2 connected to a plurality of reference voltage lines RVL are arranged in a (N / A_2) A second shorting bar region SBP2 including a first shorting bar SB1 electrically connected to the second voltage pads Vref_PD2 and a first shorting bar SB1 electrically connected to the voltage pads Vref_PD2, And a second grating region GDA2 having a second extended signal line ESL2 connected thereto.

The second extended signal line ESL2 is formed integrally with the second reference voltage pads Vref_PD2 and is connected to the first shorting bar SB1 by the second contact hole C2.

In the present invention, the first reference voltage pads Vref_PD1 are disposed between the data pads DPD in the first pad area PA1 of the array substrate, but the edges of the first reference voltage pads Vref_PD1 are And are spaced apart from the first cutting line CL1 by a certain distance in the direction of the display area.

That is, the data pads DPD are disposed up to the first cutting line CL1 region, and they are integrally connected to the first extended signal lines ESL1, but the first reference voltage pads Vref_PD1 Only the inside of the first cutting line CL1 is disposed.

Therefore, when the substrate is cut along the first cutting line CL1, the first reference voltage pads Vref_PD1 are not exposed to the cut surface and the adjacent data pads DPD or the first extended signal lines ESL1 Can be prevented from being short-circuited.

In addition, the second reference voltage pads Vref_PD2 are disposed in the second pad area PA1, and data pads connected to the data lines are not present in a region adjacent to the second reference voltage pads Vref_PD2.

Therefore, when the substrate is cut along the second cutting line CL2, only the second reference voltage pads Vref_PD2 or the second extended signal lines ESL2 connected to the second reference voltage pads Vref_PD2 are exposed to the cut end face.

Particularly, in the present invention, since the second reference voltage pads Vref_PD2 formed integrally with the reference voltage line RVL are spaced apart from each other by four data lines (data pads or extension signal lines) There is an effect that the short circuit failure between the second reference voltage pads Vref_PD2 can be reduced.

That is, in the present invention, in the first non-display area N / A_1 of the array substrate, the first reference voltage pads Vref_PD1, which are formed integrally with the reference voltage line RVL, So that it is possible to fundamentally prevent the short circuit failure.

In the second non-display area N / A_2, the second reference voltage pads Vref_PD2 formed integrally with the reference voltage line RVL are exposed on the cut surface. However, since the intervals between the pads are wide, RVL) can be prevented from being short-circuited.

FIG. 6 is a cross-sectional view of the subpixel region, I-I 'line and II-II' line of FIG. 5, FIG. 7 is an enlarged view of the X region of FIG. 5, Fig.

Referring to FIG. 6 together with FIG. 5, an organic light emitting display 100 according to the present invention includes a display area A / A in which subpixels SP are arranged in a matrix, (N / A) disposed around the non-display region N / A. The non-display area N / A includes first and second non-display areas N / A_1 and N / A_2. Although not shown in the figure, the non-display area N / A may include a third non-display area in which the pad area where the gate pads are arranged.

The driving transistor and the organic light emitting diode disposed in the sub pixel area of the display area A / A and the lines I-I 'and II-II' of FIG. 5 are as follows.

In the organic light emitting diode display of the present invention, an organic light emitting diode 614 is disposed on a driving transistor DRT and a driving transistor on a substrate 600.

The driving transistor DRT is composed of an active layer 604, a gate pattern 603, a gate electrode 605, an interlayer insulating film 624, and drain and source electrodes 607a and 607b. Here, the drain electrode 607a corresponds to a third node N3 drawn from the driving voltage line DVL of FIG. 2, and the source electrode 607b corresponds to the first electrode 611 of the organic light emitting diode 614 And a second node N2 connected to the second node N2.

The active layer 304 is formed of a semiconductor layer and includes a drain region 304b and a source region 304b doped with impurities at high concentration on both sides of the active region 304a and the active region 304a. do.

The semiconductor layer may be formed of a silicon-based material or an oxide semiconductor material containing zinc (Zn), for example, zinc oxide (ZnO), indium gallium gallium oxide (InGaZnO 4) It is not.

The organic light emitting display of the present invention may be a top emission type or a bottom emission type.

The organic light emitting diode 614 includes a passivation layer 626 stacked on the driving transistor DRT and a first electrode 611 formed on the planarization layer 618 and formed of a transparent conductive material, And a second electrode 613. On the organic light emitting diode 614, a passivation layer, an organic film including a polymer, an adhesive layer, and protective films may be further stacked.

A first electrode 611 of the organic light emitting diode 614 is disposed in the sub pixel region where the bank layer 616 is opened.

The organic light emitting layer 612 of the organic light emitting diode 614 may be a light emitting layer for emitting white light and the corresponding sub pixel may be a red (R), green (G), or blue (B) The color filter CF may be disposed between the interlayer insulating layer 624 and the passivation layer 626 corresponding to the organic light emitting diode 614 or between the passivation layer 626 and the planarization layer 618. [

The color filter CF is constituted by a red (R), green (G) or blue (B) color filter, and a separate color filter is not arranged in a white (W) subpixel.

The first electrode 611 of the organic light emitting diode 614 may be formed of a metal, an alloy thereof, a combination of a metal and an oxide metal. Preferably, the metal is a transparent conductive material because of the bottom emission method. The first electrode 611 may be formed of one of ITO, IZO, ITO / APC / ITO, AlNd / ITO, Ag / ITO or ITO / APC / ITO.

The organic light emitting layer 612 may include a hole injection layer, a hole transport layer, an emission material layer, an electron transport layer, and an electron injection layer, injection layer.

The hole transport layer HTL may further include an electron blocking layer EBL and the electron transport layer ETL may be formed using a low molecular material such as PBD, TAZ, Alq3, BAlq, TPBI or Bepp2. have.

The second electrode 613 may be formed of a material having high reflectivity and being opaque, such as aluminum (Al), silver (Ag), or an alloy thereof.

The first extended signal lines ESL1 are arranged on the interlayer insulating film 624 in the first grinding region GDA1 of the first non-display region N / A_1. The first extended signal line ESL1 may be composed of two metal patterns 603a and 603b.

The first extended signal lines ESL1 are signal lines connected to the data pads DPD of the first pad area PA1 as described with reference to FIG. Therefore, there is no signal line connected to the reference voltage pads in the first extended signal lines ESL1.

The second extended signal line ESL2 is disposed in the interlayer insulating film 624 in the second grinding area GDA2 of the second non-display area N / A_2. The second extended signal line ESL2 may also be composed of two metal patterns 640a and 640b.

Since the second extended signal line ESL2 is formed integrally with the second reference voltage pads Vref_PD2 of the reference voltage line as described with reference to FIG. 5, There is no signal line connected to them, and the separation distance is wide.

As described above, the array substrate and the organic light emitting display according to the present invention have the extended signal line integrally connected to the first reference voltage pad Vref_PD1 in the first grinding region GDA1 in the first non-display region N / A_1 So that the short circuit failure due to the substrate cutting is fundamentally prevented.

Since the second extended signal line ESL2 corresponding to the reference voltage line RVL exists in the second non-display area N / A_2, the interval of the second extended signal line ESL2 exposed on the substrate cut surface is So that short-circuit failure of the reference voltage line (RVL) is prevented.

Referring to FIG. 7, the data pad DPD and the first reference voltage pads Vref_PD1 are arranged in the first pad region PD1 of the array substrate (X region) It can be seen that the pad Vref_PD1 is spaced apart from the first cutting line CL1 by L1 in the inner side (display region direction) unlike the data pads DPD.

Therefore, even if the substrate is cut along the first cutting line, the first reference voltage pad Vref_PD1 formed integrally with the reference voltage line RVL at the cut end face is not exposed to the outside, thereby preventing a short circuit failure.

In the Y region of the array substrate, only the second reference voltage pad Vref_PD2, which is formed integrally with the reference voltage line RVL, is disposed in the second pad region PA2. Even if the substrate is cut, only the second reference voltage pads Vref_PD2 are exposed to the cut end face.

In particular, the second reference voltage pads Vref_PD2 are spaced apart from each other by a distance L2 corresponding to a region where the four data pads DPD are disposed, thereby preventing short-circuit failure of the reference voltage pads due to foreign matter. Dotted DPD refers to impersonate data pads (DPD).

As described above, the array substrate and the organic light emitting display device having the same according to the present invention are arranged such that the first non-display region and the second display region overlap each other with the display region (A / A) therebetween, The data pads and the shorting bars connected to the data pads are disposed in the display area, and the reference voltage pads and the shorting bars connected to the data pads are disposed in the second non-display area to prevent a minute short circuit or damage of the reference voltage line It is effective.

The array substrate according to the present invention and the organic light emitting diode display device having the array substrate according to the present invention may further include a second pad having reference voltage pads disposed to face the first pad region in which data pads are disposed with a display region A / By arranging the regions, it is possible to prevent the degradation of the compensation characteristic due to the short-circuit failure of the reference voltage line.

FIGS. 9A and 9B are diagrams comparing a compensation value variation in the case where a short circuit defect occurs in a reference voltage line of the organic light emitting display device of the present invention and a case in which a short circuit defect does not occur. FIG.

FIGS. 9A and 9B are diagrams for explaining the occurrence of an error when calculating the compensation value for compensating the deterioration of the sub-pixel characteristic value when the reference voltage line is short-circuited.

Referring to FIG. 9A together with FIG. 3, subpixels SP1 to SP4 connected in common with a reference voltage line RVL are referred to as red subpixel SP1, white subpixel SP2, green subpixel SP3, And the blue subpixel SP4. In the A region, the data lines of the reference voltage line and the white subpixel SP2 are shorted to each other. In the region B, the data lines of the reference voltage line and the red subpixel SP1 are connected to each other It is a case of short circuit.

In the case where the subpixel characteristic value sensing is performed for the white subpixel SP2 in the A region, the reference voltage line is equivalent to the sensing data voltage supplied to the white subpixel SP2 (in short) And the compensation value does not increase.

However, when sensing is performed for the other sub-pixels SP1, SP3 and SP4 except for the white sub-pixel SP2, since the sensing black data is supplied to the white sub-pixel SP2, The sensing value is sensed.

When the underflow sensing value is sensed, the compensating unit determines that the characteristic value change of the subpixel is large (it is determined that the degradation is severe) A high over-compensation value is set.

This overcorrection is detected as a bright line defect when the organic light emitting display device operates in the display mode.

On the same principle, there is no large fluctuation in the compensation value for the red subpixel SP1 in which a short circuit occurs in the B region. However, in the shorted subpixels SP2 to SP4, the underflow sensing value is sensed, Respectively. This causes a bright line defect in the display mode thereafter.

However, as shown in FIG. 5 of the present invention, when the short-circuit failure of the reference voltage line RVL is originally cut off, there is no region in which the compensation value is rapidly set in the entire region of the display panel as shown in FIG. 9B .

Therefore, the compensation data voltage for compensating the characteristic value of each subpixel is not supplied abnormally high, so that a bright line defect caused by shorting of the reference voltage line is not generated.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
120: Source driver
130: scan driver
140: Timing controller
110: Display panel
A / A: display area
N / A: Non-display area

Claims (9)

A substrate having a display region in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged and a first and a second non-display regions arranged to face each other with the display region interposed therebetween; ,
The first non-display region includes a first pad region in which first reference voltage pads formed integrally with data pads formed integrally with a data line and a reference voltage line disposed in a display region are disposed,
And a plurality of shorting bars electrically connected to the data pads of the first pad region,
The second non-display region includes a second pad region in which second reference voltage pads formed integrally with the reference voltage line are disposed,
And a second shorting bar region including a shorting bar electrically connected to second reference voltage pads of the second pad region. The method according to claim 1,
Further comprising first extended signal lines for electrically connecting data pads of the first pad region to shorting bars of the first shorting bar region. The method according to claim 1,
And second extending signal lines electrically connecting the second reference voltage pads of the second pad region to a shorting bar of the second shorting bar region. The method according to claim 1,
Wherein the first reference voltage pads disposed in the first pad region are spaced apart from the first cut line by a predetermined distance in the display region direction. The method according to claim 1,
And second reference voltage pads disposed in the second pad region are spaced apart from each other with an area where four data pads among the data pads disposed in the first pad region are arranged. A display panel including a display region in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged, and first and second non-display regions arranged to face each other with the display region interposed therebetween;
A source driver for driving the plurality of data lines;
A scan driver for driving the plurality of gate lines; And
And a controller for controlling the source driver and the scan driver,
Wherein the first non-display region of the display panel includes data pads formed integrally with the data lines and a first pad region having first reference voltage pads formed integrally with a reference voltage line arranged in the display region,
And the second non-display region includes a second pad region in which second reference voltage pads formed integrally with the reference voltage line are disposed. The method according to claim 6,
Wherein the first reference voltage pads disposed in the first pad region are spaced apart from the cut end surface of the first cut line at a predetermined distance in the display region direction. 8. The method of claim 7,
And the data pads disposed in the first pad region are partially exposed on a cut surface of the first cut line at the edge of the display panel. The method according to claim 6,
And the second reference voltage pads disposed in the second pad region are spaced apart from each other with an area where four data pads among the data pads disposed in the first pad region are disposed.

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