KR102458853B1 - Array substrate and organic light-emitting display device having the same - Google Patents

Abstract

The array substrate of the present invention includes a display area in which a plurality of subpixels are disposed, and a substrate in which first and second non-display areas disposed to face each other with the display area therebetween are partitioned, the data pads and the first By including the first pad area in which the reference voltage pads are disposed and the second pad area in which the second reference voltage pads are disposed, there is an effect of preventing a minute short circuit or damage to the reference voltage line due to a foreign material after cutting the substrate.
In addition, the organic light emitting display device of the present invention includes a display panel, a source driver, a scan driver, and a controller, and the first non-display area of the display panel is integrally formed with data pads and a reference voltage line. The first pad area in which the formed first reference voltage pads are disposed and the second non-display area include the second pad area in which the second reference voltage pads formed integrally with the reference voltage line are disposed, thereby preventing a short circuit of the reference voltage line. There is an effect that can prevent the deterioration of the compensation characteristics due to this.

Description

Array substrate and organic light emitting display device having same

The present invention relates to an array substrate and an organic light emitting display device having the same.

Recently, an organic light-emitting display device, which has been in the spotlight as a display device, has advantages of fast response speed, high luminous efficiency, luminance, and viewing angle by using an organic light-emitting diode (OLED) that emits light by itself.

In such an organic light emitting display device, sub-pixels including organic light emitting diodes are arranged in a matrix form, and the brightness of the sub-pixels selected by a scan signal is controlled according to a gray level of data.

In such an organic light emitting display device, an active area (A/A) in which sub-pixels are disposed to display an image, and pads (Pad) for connection with an external driving IC along the periphery of the display area (A/A) are provided. It has an arranged non-display area (N/A: Non Active Area).

In the non-display area N/A, gate pads for connection to an external driving driver and data pads are arranged side by side. In addition, the gate pads and the data pads are connected to each other by shorting bars to prevent static electricity and to perform an auto probe.

In addition, in the final process of the organic light emitting diode display, the shorting bar area is always separated from the display panel by cutting between the pad area where the gate pads and data pads are disposed and the shorting bar area where the shorting bars are disposed.

Such an organic light emitting display device may further include a transistor suitable for performing various functions in each sub-pixel. Accordingly, signal lines for supplying various signals to the transistors are further disposed.

For example, when an internal or external compensation circuit is applied to a sub-pixel to improve luminance non-uniformity between sub-pixels, a transistor involved in a sensing operation for compensation must be added, and a signal line connected thereto must also be added.

A reference voltage line, also called a “sensing line,” is disposed among the signal lines. Since an initialization signal, etc. must be supplied to the sub-pixel through the reference voltage line for internal or external compensation, reference voltage pads are disposed at the end of the reference voltage line. and a shorting bar for connecting them is also added.

As described above, since reference voltage pads, connection lines extending from the pads, and shorting bars must be additionally disposed in the non-display area N/A, a short circuit defect with existing data pads due to space restrictions, etc. There is a problem of being vulnerable to line damage.

According to the present invention, the first non-display area and the second display area are disposed to face each other with the display area A/A interposed therebetween, and data pads and shorting bars connected thereto are disposed in the first non-display area, , To provide an array substrate and an organic light emitting diode display having the same, in which reference voltage pads and a shorting bar connected thereto are disposed in the second non-display area to prevent micro-short circuit or damage to the reference voltage line due to foreign matter after cutting the substrate There is this.

Further, according to the present invention, by arranging the second pad area in which the reference voltage pads are disposed so as to face the first pad area in which the data pads are disposed with the display area A/A interposed therebetween, a short circuit failure of the reference voltage line is prevented. Another object of the present invention is to provide an array substrate capable of preventing deterioration of compensation characteristics and an organic light emitting display device having the same.

In order to solve the problems of the prior art, the array substrate of the present invention provides a display area in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are disposed and facing each other with the display area interposed therebetween. and a substrate in which first and second non-display areas arranged so as to be separated from each other, wherein the first non-display area includes data pads integrally formed with a data line and a first non-display area integrally formed with a reference voltage line disposed in the display area a first pad region in which reference voltage pads are disposed, and a first shorting bar region including a plurality of shorting bars electrically connected to the data pads of the first pad region, wherein the second non-display region includes a reference voltage A substrate comprising: a second pad region on which second reference voltage pads formed integrally with a line are disposed; and a second shorting bar region including a shorting bar electrically connected to the second reference voltage pads of the second pad region; After cutting, it has the effect of preventing micro-short circuit or damage to the reference voltage line due to foreign substances.

Also, in the organic light emitting display device of the present invention, a display area in which a plurality of sub-pixels defined by a plurality of data lines and a plurality of gate lines are disposed, and first and second pixels disposed to face each other with the display area interposed therebetween A display panel comprising two non-display areas, a source driver driving the plurality of data lines, a scan driver driving the plurality of gate lines, and a controller controlling the source driver and the scan driver, the display panel comprising: The first non-display area of ' includes a first pad area on which data pads integrally formed with the data line and first reference voltage pads integrally formed with the reference voltage line disposed on the display area are disposed, and the second non-display area includes: Since the region includes a second pad region in which second reference voltage pads formed integrally with the reference voltage line are disposed, it is possible to prevent deterioration of compensation characteristics due to a short circuit failure of the reference voltage line.

According to the present invention, an array substrate and an organic light emitting display having the same include a first non-display area and a second display area facing each other with a display area A/A interposed therebetween, and the first non-display area By arranging the data pads and the shorting bars connected to them, and disposing the reference voltage pads and the shorting bars connected thereto in the second non-display area, there is an effect of preventing a micro short circuit or damage to the reference voltage line due to foreign matter after cutting the substrate. .

In addition, in the array substrate and the organic light emitting display device having the same according to the present invention, a second pad having reference voltage pads disposed to face the first pad area having data pads disposed therebetween with the display area A/A interposed therebetween. By disposing the region, it is possible to prevent deterioration of compensation characteristics due to a short circuit failure of the reference voltage line.

1 is a schematic system configuration diagram of an organic light emitting display device according to the present invention.
2 is an exemplary diagram of a subpixel structure of an organic light emitting diode display according to embodiments of the present invention.
3 is a schematic plan view illustrating a part of a display panel of an organic light emitting display device according to the present invention.
4A is a diagram illustrating a structure of pads and shorting bars disposed on an array substrate of an organic light emitting diode display.
FIG. 4B is a diagram illustrating a short circuit defect occurring in a cut surface when shorting bars disposed on an array substrate of an organic light emitting display device are removed.
5 is a diagram illustrating structures of a display area and a non-display area of an array substrate of an organic light emitting diode display according to the present invention.
FIG. 6 is a cross-sectional view illustrating the sub-pixel region of FIG. 5, along lines I-I' and II-II'.
FIG. 7 is an enlarged view of region X of FIG. 5 .
FIG. 8 is an enlarged view of the Y region of FIG. 5 .
9A and 9B are diagrams comparing compensation value fluctuations when a short-circuit failure occurs in a reference voltage line of an organic light emitting diode display according to the present invention and when a short-circuit failure does not occur.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, when the temporal relationship is described as 'after', 'following', 'after', 'before', etc., 'immediately' or 'directly' Unless ' is used, cases that are not continuous may be included.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals refer to like elements throughout.

1 is a schematic system configuration diagram of an organic light emitting display device 100 according to the present invention.

Referring to FIG. 1 , in the organic light emitting diode display 100 according to the present invention, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of sub-pixels (SP) are disposed. display panel 110 , a source driver 120 driving a plurality of data lines DL, a scan driver 130 driving a plurality of gate lines GL, a source driver 120 , and a scan driver and a timing controller 140 for controlling 130 and the like.

The timing controller 140 supplies various control signals to the source driver 120 and the scan driver 130 to control the source driver 120 and the scan driver 130 .

The timing controller 140 starts a scan according to the timing implemented in each frame, and converts the input image data input from the outside according to the data signal format used by the source driver 120 to match the converted driving data DATA. ) and control the display driving data at an appropriate time according to the scan signal.

The source driver 120 drives the plurality of data lines DL by supplying the driving data voltage Vdata to the plurality of data lines DL. Here, the source driver 120 is also referred to as a 'data driver'.

The scan driver 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the scan driver 130 is also referred to as a 'gate driver'.

The scan driver 130 sequentially supplies a scan signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the timing controller 140 .

When a specific gate line is opened by the scan driver 130 , the source driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies it to the plurality of data lines DL.

Although the source driver 120 is located only on one side (eg, upper or lower side) of the display panel 110 in FIG. 1 , the source driver 120 is located on both sides (eg, upper and lower sides) of the display panel 110 according to a driving method and a panel design method. ) may be located in

Although the scan driver 130 is located only on one side (eg, left or right) of the display panel 110 in FIG. 1 , the scan driver 130 is located on both sides (eg, left and right side) of the display panel 110 according to a driving method, a panel design method, etc. may be located on the right).

The above-described timing controller 140 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), etc. together with the input image data. It receives various timing signals from the outside (eg, host system).

The timing controller 140 converts the input image data input from the outside to match the data signal format used by the source driver 120 and outputs the converted image data, as well as the source driver 120 and the scan driver 130 . ), the source driver 120 and the scan driver 130 receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal to generate various control signals. ) is output.

For example, the timing controller 140 controls the scan driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable).

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver ICs constituting the scan driver 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the timing controller 140 controls the source driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Output Enable) and output various data control signals (DCS: Data Control Signal).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver ICs constituting the source driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the source driver 120 .

The source driver 120 may include at least one source driver integrated circuit (SDIC) to drive a plurality of data lines.

Each source driver integrated circuit (SDIC) includes a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and a gamma voltage generator. can do.

Each source driver integrated circuit SDIC may further include an analog-to-digital converter (ADC) in some cases.

The scan driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver integrated circuit GDIC may include a shift register, a level shifter, and the like.

Each subpixel SP disposed on the display panel 110 may include a circuit element such as a transistor.

For example, in the display panel 110 , each sub-pixel SP includes an organic light emitting diode (OLED) and circuit elements such as a driving transistor for driving the organic light emitting diode (OLED).

The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to a provided function and a design method.

FIG. 2 is an exemplary diagram of a sub-pixel structure of an organic light emitting diode display according to embodiments of the present invention, and FIG. 3 is a schematic plan view of a part of a display panel of an organic light emitting display according to the present invention.

Referring to FIG. 2 , in the organic light emitting diode display 100 according to the present invention, a compensation structure for compensating a characteristic value of a sub-pixel may be disposed in each sub-pixel.

A driving circuit in a subpixel having a compensation structure includes, for example, three transistors (a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT)) and one capacitor (storage capacitor (Cstg)). can be configured.

As described above, a sub-pixel including three transistors DRT, SWT, and SENT and one capacitor Cstg is said to have a “3T1C structure”.

Referring to FIG. 2 , the driving transistor DRT is a transistor that supplies a driving current to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

In the driving transistor DRT, the N1 node may be electrically connected to the first electrode or the second electrode of the organic light emitting diode OLED, and the N2 node may be electrically connected to the source node or the drain node of the switching transistor SWT. and the N3 node may be electrically connected to the driving voltage line DVL supplying the driving voltage EVDD.

The switching transistor SWT is a transistor that transfers the data voltage Vdata to the N2 node corresponding to the gate node of the driving transistor DRT.

The switching transistor SWT is controlled by a scan signal SCAN (gate high voltage VGH and gate low voltage VGL) applied to the gate node, and the N2 node of the driving transistor DRT and the data line DL ) are electrically connected between

Meanwhile, referring to FIG. 2 , a sensing transistor SENT is newly added to a subpixel of a general organic light emitting diode display. The added sensing transistor SENT is controlled by a sense signal SENSE, which is a type of scan signal applied to the gate node, and is located between the reference voltage line (RVL) and the N1 node of the driving transistor DRT. can be electrically connected.

The sensing transistor SENT is turned on to apply the reference voltage Vref supplied through the reference voltage line RVL to the N1 node (eg, a source node or a drain node) of the driving transistor DRT. .

In addition, the sensing transistor SENT serves to sense the voltage of the N1 node of the driving transistor DRT by the analog-to-digital converter ADC electrically connected to the reference voltage line RVL.

The role of the sensing transistor SETN is related to a compensation function for the intrinsic characteristic value of the driving transistor DRT. Here, the intrinsic characteristic value of the driving transistor DRT may include, for example, a threshold voltage (Vth), mobility, and the like.

Meanwhile, one reference voltage line RVL electrically connected to the drain node or the source node of the first transistor T1 may be disposed in one sub-pixel column, or two or more sub-pixel columns. One of each may be arranged.

For example, referring to FIG. 3 , when one pixel consists of four subpixels (a red subpixel SP1 , a white subpixel SP2 , a green subpixel SP3 , and a blue subpixel SP4 ). , one reference voltage line RVL may be disposed for every four sub-pixel columns (a red sub-pixel column, a white sub-pixel column, a green sub-pixel column, and a blue sub-pixel column).

On the other hand, in the case of the organic light emitting diode display 100 according to the present invention, as the driving time of each sub-pixel SP increases, circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT) are deteriorated ( Degradation) may proceed.

Accordingly, unique characteristic values (eg, threshold voltage, mobility, etc.) of circuit elements such as organic light emitting diodes (OLEDs) and driving transistors (DRTs) may change.

A change in the characteristic value of such a circuit element causes a change in luminance of a corresponding sub-pixel.

Here, the characteristic value of the circuit element (hereinafter also referred to as “sub-pixel characteristic value”) may include, for example, the threshold voltage and mobility of the driving transistor DRT, and in some cases, the organic light emitting diode (OLED). may include a threshold voltage of

The organic light emitting display device 100 according to the present invention provides a sensing function for sensing (measuring) a change in a characteristic value of a sub-pixel or a characteristic value deviation between each sub-pixel, and a compensation function for compensating for a characteristic value of a sub-pixel using the sensing result. can do.

As shown in FIG. 3 , the four sub-pixels SP1 to SP4 connected to the reference voltage line RVL are symmetrically disposed with respect to the reference voltage line RVL.

For example, the reference voltage line RVL and the second and third subpixels SP2 and SP3 are directly connected to the reference voltage line RVL and connected to the first and fourth subpixels SP1 and SP4. It is connected through a pattern (CP).

According to this reference voltage line connection structure, each sub-pixel SP1 to SP4 connects the sensing transistor SENT disposed in each sub-pixel SP1 to SP4 from the reference voltage line RVL to the N1 node with the reference voltage Vref. to supply

As described above, when the compensation circuit is disposed in each sub-pixel of the organic light emitting diode display, each of the sub-pixels SP1 to SP4 may operate in a display mode or a sensing mode. In the sensing mode, when a characteristic value of each sub-pixel SP1 to SP4 is changed such as deterioration occurs in the display mode, the changed characteristic value is sensed and a compensated data voltage is provided in the display mode.

As described above, when the compensation circuit is disposed in each subpixel of the organic light emitting display device, one reference voltage line RVL is added based on the four subpixels, so that reference voltage pads are also provided in the pad area of the display panel 100 . It is disposed so that the gap between the pads is narrowed.

In the array substrate and the organic light emitting diode display having the same according to the present invention, a short circuit defect and a compensation error of the reference voltage line are prevented by disposing the reference voltage pads of the additional reference voltage line in a region different from that of the data pads.

4A is a diagram illustrating a structure of pads and shorting bars disposed on an array substrate of an organic light emitting display device, and FIG. 4B is a diagram illustrating a short circuit occurring in a cut surface when the shorting bars disposed on the array substrate of the organic light emitting diode display device are removed. It is a drawing showing a defect.

Referring to FIGS. 4A and 4B , as shown in FIGS. 2 and 3 , each sub-pixel SP1 to SP4 includes a compensation circuit for compensating the characteristic value of the sub-pixel. For this reason, the reference voltage line RVL is additionally disposed in the basic organic light emitting diode display.

The display panel 110 may be configured by disposing an array substrate on which transistors and organic light emitting diodes (OLED) are formed, and an upper substrate (encapsulation substrate) on the array substrate. A display panel may be realized by disposing the upper substrate on the array substrate and then removing the shorting bars formed on the array substrate.

As described in FIG. 3 , when one reference voltage line RVL is disposed in the four subpixels SP1 to SP4 , the reference voltage line RVL is disposed between the data lines DL in the display area A/A of the array substrate. Voltage lines RVL are disposed.

Accordingly, in the non-display area N/A disposed on the array substrate of the display panel 110 , a pad area PA composed of pads PD and a plurality of extension signal lines ESL extending from the pads PD are provided. .

The pads PD include data pads DPD and reference voltage pads RVPD respectively connected to data lines DL and reference voltage line RVL, and pads PD and an extension signal line. (ESL) are formed integrally with each other.

Also, the first shorting bar SB1 disposed in the shorting bar area SBP may be a shorting bar connected to the reference voltage line RVL, and the second to fifth shorting bars SB2 to SB5 are the data line DL. It may be a shorting bar connected to

The array substrate of the organic light emitting diode display having the above structure completes the display panel by cutting the grinding area GDA when the auto probe inspection process such as lighting inspection is completed through the shorting bars SB1 to SB5.

Accordingly, as shown in FIG. 4B , when the array substrate is cut along the grinding area GDA, the extension signal lines ESL extending from the pad area PA are exposed on the grinding end surface.

In particular, as the reference voltage line RVL is added, the gap between the extension signal lines ESL is narrowed, and a short defect occurs due to a foreign material between the extension signal lines ESL.

When the reference voltage line RVL is short-circuited with another adjacent data line DL, when the organic light emitting diode display operates in the sensing mode, the voltage of the reference voltage line RVL is affected and an error occurs in the sensed value Vsen. There is a problem that arises.

In the array substrate and organic light emitting display device of the present invention, reference voltage pads of a reference voltage line arranged to sense deterioration of driving transistors or organic light emitting diodes arranged in sub-pixels SP1 to SP4 are pads on which data pads are arranged. By disposing the pad area in a different pad area from the area, a short circuit failure between the reference voltage line and the data line due to the grinding process for separating the shorting bars is prevented.

That is, in the array substrate according to the present invention and the organic light emitting display device having the same, the first non-display area and the second display area face each other with the display area A/A interposed therebetween, and the first non-display area is disposed. By arranging data pads and shorting bars connected to them in the area, and disposing reference voltage pads and shorting bars connected thereto in the second non-display area, a micro-short circuit or damage to the reference voltage line due to foreign matter after cutting the substrate is prevented. there is

In addition, in the array substrate and the organic light emitting display device having the same according to the present invention, a second pad having reference voltage pads disposed to face the first pad area having data pads disposed therebetween with the display area A/A interposed therebetween. By disposing the region, it is possible to prevent deterioration of compensation characteristics due to a short circuit failure of the reference voltage line.

5 is a diagram illustrating structures of a display area and a non-display area of an array substrate of an organic light emitting diode display according to the present invention.

Referring to FIG. 5 , the organic light emitting diode display 100 of the present invention includes a display area A/A in which a plurality of sub-pixels SP are disposed to display an image, and the display area A/A. and a non-display area N/A disposed along the circumference.

The non-display area N/A disposed on the display panel 110 of the present invention includes a first non-display area N/A_1 including a first pad area PA1 composed of data pads DPD; , and a second non-display area N/A_2 facing the first non-display area N/A_1 with the display area A/A interposed therebetween. Although not shown in the drawing, the region including the gate pads GPD may include a third non-display region (not shown).

The first non-display area N/A_1 disposed on the array substrate of the display panel 110 includes data pads DPD connected to a plurality of data lines and a first reference voltage connected to a plurality of reference voltage lines RVL. and a first pad area PA1 in which the pads Vref_PD1 are disposed, and second to fifth shorting bars SB2 to SB5 electrically connected to the data pads DPD of the first pad area PA1. A first grinding area ( SBP1 ) in which a first extension signal line ( ESL1 ) connecting the data pads ( DPD ) and the second to fifth shorting bars ( SB2 to SB5 ) is disposed. GDA1).

The first extension signal line ESL1 is integrally formed with the data pads DPD and is respectively connected to the second to fifth shorting bars SB2 to SB5 by the first contact hole C1 .

In addition, the second non-display area of the array substrate (N/A_2) includes a second pad area PA2 in which second reference voltage pads Vref_PD2 connected to the plurality of reference voltage lines RVL are disposed, and a second reference voltage line RVL. The second shorting bar region SBP2 including the first shorting bar SB1 electrically connected to the voltage pads Vref_PD2, and the first shorting bar SB1 extending from the second reference voltage pads Vref_PD2 and a second grinding area GDA2 in which a second extension signal line ESL2 connected to .

The second extension signal line ESL2 is integrally formed with the second reference voltage pads Vref_PD2 and is connected to the first shorting bar SB1 by the second contact hole C2 .

Also, in the present invention, although the first reference voltage pads Vref_PD1 are disposed between the data pads DPD in the first pad area PA1 of the array substrate, the edges of the first reference voltage pads Vref_PD1 are They are disposed to be spaced apart from the first cutting line CL1 by a predetermined distance in the direction of the display area.

That is, the data pads DPD are disposed up to the area of the first cutting line CL1 , and they are again integrally connected to the first extension signal lines ESL1 , but the first reference voltage pads Vref_PD1 are It is disposed only to the inner side of the first cutting line CL1 .

Accordingly, when the substrate is cut along the first cutting line CL1 , the first reference voltage pads Vref_PD1 are not exposed to the cut end surface, so that the adjacent data pads DPD or the first extension signal lines ESL1 are not exposed. ) to prevent short circuit faults.

In addition, second reference voltage pads Vref_PD2 are disposed in the second pad area PA1 , but data pads connected to data lines do not exist in an area adjacent to the second reference voltage pads Vref_PD2 .

Accordingly, when the substrate is cut along the second cutting line CL2 , only the second reference voltage pads Vref_PD2 or the second extension signal lines ESL2 connected thereto are exposed at the cut end surface.

In particular, in the present invention, since the second reference voltage pads Vref_PD2 integrally formed with the reference voltage line RVL are disposed at intervals at which four data lines (data pads or extended signal lines) are to be disposed. There is an effect that a short circuit defect between the second reference voltage pads Vref_PD2 can be reduced.

That is, in the present invention, in the first non-display area N/A_1 of the array substrate, the first reference voltage pads Vref_PD1 integrally formed with the reference voltage line RVL are not exposed to the cut end of the adjacent data pads. It was designed to fundamentally prevent short circuit defects.

Also, in the second non-display area N/A_2 , the second reference voltage pads Vref_PD2 integrally formed with the reference voltage line RVL are exposed to the cut end surface, but since the pads have a wide interval, the reference voltage line ( RVL) to prevent short circuit failure.

FIG. 6 is a cross-sectional view illustrating the sub-pixel area, line I-I' and line II-II' of FIG. 5, FIG. 7 is an enlarged view of area X of FIG. 5, and FIG. 8 is area Y of FIG. It is an enlarged drawing.

Referring to FIG. 6 together with FIG. 5 , the organic light emitting diode display 100 of the present invention includes a display area A/A in which sub-pixels SP are arranged in a matrix form, and the display area A/A ) and a non-display area N/A disposed on the periphery. The non-display area N/A includes first and second non-display areas N/A_1 and N/A_2. Although not shown in the drawing, the non-display area N/A may include a pad area in which gate pads are disposed and may include a third non-display area.

The driving transistor and the organic light emitting diode disposed in the sub-pixel area of the display area A/A and lines I-I' and II-II' of FIG. 5 are as follows.

In the array substrate of the organic light emitting diode display according to the present invention, a driving transistor DRT is disposed on a substrate 600 and an organic light emitting diode 614 is disposed on the driving transistor.

The driving transistor DRT includes an active layer 604 , a gate pattern 603 , a gate electrode 605 , an interlayer insulating film 624 , and drain and source electrodes 607a and 607b . Here, the drain electrode 607a corresponds to the third node N3 drawn from the driving voltage line DVL of FIG. 2 , and the source electrode 607b is the first electrode 611 of the organic light emitting diode 614 . ) corresponds to the second node (N2) connected to.

In addition, the active layer 304 is made of a semiconductor layer, the central portion of which is composed of an active region 304a forming a channel, and drain and source regions 304b and 304c doped with a high concentration of impurities on both sides of the active region 304a. do.

The semiconductor layer may be formed of a silicon-based material or an oxide semiconductor material containing zinc (Zn), for example, zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO4), etc. may be used, but is limited thereto. it is not

The organic light emitting display device of the present invention may be a top emission type or a bottom emission type.

The organic light emitting diode 614 is disposed on a passivation layer 626 and a planarization layer 618 stacked on the driving transistor DRT, a first electrode 611 formed of a transparent conductive material, and an organic light emitting layer 612 . ) and a second electrode 613 . A passivation layer, an organic film including a polymer, an adhesive layer, and a protective film may be further stacked on the organic light emitting diode 614 .

Although shown in the drawings, 616, which is not described, is a bank layer, and the first electrode 611 of the organic light emitting diode 614 is disposed in the sub-pixel area where the bank layer 616 is open, respectively.

In addition, the organic light emitting layer 612 of the organic light emitting diode 614 may be a light emitting layer emitting white (W) light, and the corresponding sub-pixel is a red (R), green (G) or blue (B) sub-pixel. When used, the color filter CF may be disposed between the interlayer insulating layer 624 and the passivation layer 626 corresponding to the organic light emitting diode 614 , or between the passivation layer 626 and the planarization layer 618 .

The color filter CF includes a red (R), green (G), or blue (B) color filter, and a separate color filter is not disposed in the white (W) sub-pixel.

The first electrode 611 of the organic light emitting diode 614 may be formed of a metal, an alloy thereof, or a combination of a metal and an oxide metal. Since it is a bottom light emitting method, the metal is preferably a transparent conductive material. The first electrode 611 may be formed of one of ITO, IZO, ITO/APC/ITO, AlNd/ITO, Ag/ITO, or ITO/APC/ITO.

The organic light emitting layer 612 includes a hole injection layer, a hole transport layer, an emitting material layer, an electron transport layer, and an electron injection layer to increase luminous efficiency. It can be composed of multiple layers of injection layers).

In addition, the hole transport layer (HTL) may further include an electron blocking layer (EBL), the electron transport layer (ETL) may be formed using a low molecular weight material such as PBD, TAZ, Alq3, BAlq, TPBI, Bepp2. have.

The second electrode 613 may be formed of an opaque material having high reflectance, such as aluminum (Al), silver (Ag), or an alloy thereof.

Also, looking at the first grinding area GDA1 of the first non-display area N/A_1 , the first extension signal lines ESL1 are disposed on the interlayer insulating layer 624 . The first extension signal line ESL1 may include two metal patterns 603a and 603b.

As described with reference to FIG. 5 , the first extended signal lines ESL1 are signal lines connected to the data pads DPD of the first pad area PA1 . Accordingly, signal lines connected to the reference voltage pads do not exist in the first extended signal lines ESL1 .

Also, in the second grinding area GDA2 of the second non-display area N/A_2 , the second extension signal line ESL2 is disposed on the interlayer insulating layer 624 . The second extended signal line ESL2 may also include two metal patterns 640a and 640b.

As described with reference to FIG. 5 , the second extended signal line ESL2 is a signal line integrally formed with the second reference voltage pads Vref_PD2 of the reference voltage line, and thus a data pad is disposed between the second extended signal line ESL2 . Since there is no signal line connected to each other, the separation distance is wide.

As described above, in the array substrate and the organic light emitting display device of the present invention, the extended signal line integrally connected to the first non-display area N/A_1 and the first grinding area GDA1 and the first reference voltage pad Vref_PD1 is provided. Because it does not exist, it fundamentally prevents short circuit defects caused by cutting the substrate.

In addition, since only the second extension signal line ESL2 corresponding to the reference voltage line RVL exists in the second non-display area N/A_2, the interval between the second extension signal lines ESL2 exposed to the cut surface of the substrate is increased. It is wide to prevent short circuit failure of the reference voltage line (RVL).

Referring to FIG. 7 , looking at the structure of the first pad region PD1 of the array substrate (region X), although the data pads DPD and the first reference voltage pads Vref_PD1 are disposed, the first reference voltage It can be seen that the pad Vref_PD1 is spaced apart from the first cutting line CL1 inward (in the display area direction) by L1 unlike the data pads DPD.

Accordingly, even when the substrate is cut along the first cutting line, the first reference voltage pad Vref_PD1 integrally formed with the reference voltage line RVL on the cut end surface is not exposed to the outside, thereby preventing a short circuit failure.

In addition, when looking at the Y region of the array substrate, only the second reference voltage pad Vref_PD2 integrally formed with the reference voltage line RVL is disposed in the second pad area PA2 , and thus, along the second cutting line CL2 . Even when the substrate is cut, only the second reference voltage pads Vref_PD2 are exposed on the cut end surface.

In particular, since the second reference voltage pads Vref_PD2 are spaced apart by a distance L2 corresponding to the region in which the four data pads DPD are disposed, a short circuit defect of the reference voltage pads due to a foreign material may be prevented. DPDs processed by dotted lines mean disguised data pads DPD.

As described above, in the array substrate according to the present invention and the organic light emitting display device having the same, the first non-display area and the second display area face each other with the display area A/A interposed therebetween, and the first ratio Data pads and shorting bars connected thereto are arranged in the display area, and reference voltage pads and shorting bars connected thereto are arranged in the second non-display area to prevent micro short circuit or damage to the reference voltage line due to foreign matter after cutting the substrate. It works.

In addition, in the array substrate and the organic light emitting display device having the same according to the present invention, a second pad having reference voltage pads disposed to face the first pad area having data pads disposed therebetween with the display area A/A interposed therebetween. By disposing the region, it is possible to prevent deterioration of compensation characteristics due to a short circuit failure of the reference voltage line.

9A and 9B are diagrams comparing compensation value fluctuations when a short-circuit failure occurs in a reference voltage line of an organic light emitting diode display according to the present invention and when a short-circuit failure does not occur.

9A and 9B compare and explain that an error occurs when calculating a compensation value for compensating for deterioration of a characteristic value of a sub-pixel when a reference voltage line is short-circuited.

Referring to FIG. 9A together with FIG. 3 , the subpixels SP1 to SP4 commonly connected to the reference voltage line RVL are respectively a red subpixel SP1 , a white subpixel SP2 , and a green subpixel SP3 . and blue sub-pixel SP4. In area A, the reference voltage line and the data line of the white sub-pixel SP2 are shorted to each other, and in area B, the reference voltage line and the data line of the red sub-pixel SP1 are connected to each other. in case of short circuit.

When the sub-pixel characteristic value is sensed with respect to the white sub-pixel SP2 in the region A, the reference voltage line is equalized to the sensing data voltage supplied to the white sub-pixel SP2 (short-circuited) so that the sensed value is a constant voltage level appears and the compensation value does not increase.

However, when sensing is performed on the sub-pixels SP1, SP3, and SP4 other than the white sub-pixel SP2, since black data for sensing is supplied to the white sub-pixel SP2, the reference voltage line has an underflow shape. The sensed value is sensed with

When the underflow sensing value is sensed in this way, the compensator determines that the characteristic value change of the sub-pixel is large (determined that deterioration is severe), and the sub-pixels SP1, SP3, and SP4 are not shorted because the compensation value is set high. It can be seen that a high overcompensation value is set.

Such overcompensation is detected as a bright line defect when the organic light emitting diode display operates in the display mode.

According to the same principle, there is no significant change in the compensation value for the short-circuited red sub-pixel SP1 in the B region, but the underflow sensing value is sensed in the non-shorted sub-pixels SP2 to SP4 to increase the overcompensation value. is set This causes a bright line defect in the subsequent display mode.

However, as shown in FIG. 5 of the present invention, when the short circuit failure of the reference voltage line RVL is fundamentally blocked, there is no region in which the compensation value is abruptly set high in the entire region of the display panel as shown in FIG. 9B . .

Accordingly, the compensation data voltage for compensating the characteristic value of each sub-pixel is not supplied abnormally high, so that a bright line defect caused by a short circuit of the reference voltage line does not occur.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device
120: source driver
130: scan driver
140: timing controller
110: display panel
A/A: display area
N/A: non-display area

Claims (10)

A substrate comprising: a display area having a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines disposed therebetween; and first and second non-display areas disposed to face each other with the display area interposed therebetween; ,
The first non-display area includes a first pad area in which data pads integrally formed with the data line and first reference voltage pads integrally formed with a reference voltage line disposed in the display area are disposed, and a data pad in the first pad area. a first shorting bar region including a plurality of shorting bars electrically connected to the ?rst; and a first grinding region in which a first extension signal line connecting the data pads and the plurality of shorting bars is disposed;
The second non-display area includes a second pad area in which second reference voltage pads formed integrally with a reference voltage line are disposed, and a shorting bar electrically connected to the second reference voltage pads of the second pad area. a shorting bar area, and a second grinding area in which a second extension signal line connecting the second reference voltage pads and the shorting bar is disposed;
and edges of the first reference voltage pads are spaced apart from the first grinding area by a predetermined distance. According to claim 1,
The first grinding area is
An array substrate in which an extension signal line for connecting the first reference voltage pads to the plurality of shorting bars included in the first shorting bar region does not exist. According to claim 1,
The second grinding area is
and second extension signal lines electrically connecting the second reference voltage pads and the shorting bar of the second shorting bar area;
An array substrate having no data pads and no extension signal lines connected thereto. delete According to claim 1,
The second reference voltage pads disposed in the second pad area are spaced apart from each other with an area in which four data pads are to be disposed among the data pads disposed in the first pad area. a display panel comprising: a display panel including a display area in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are disposed, and first and second non-display areas disposed to face each other with the display area interposed therebetween;
a source driver driving the plurality of data lines;
a scan driver driving the plurality of gate lines; and
A controller for controlling the source driver and the scan driver,
The first non-display area of the display panel includes a first pad area on which data pads integrally formed with a data line and first reference voltage pads integrally formed with a reference voltage line disposed on the display area are disposed;
The second non-display area includes a second pad area on which second reference voltage pads formed integrally with the reference voltage line are disposed,
The first reference voltage pads are disposed to be spaced apart from the cut end of the first cutting line at the edge of the display panel by a predetermined distance in the direction of the display area, and there is an extension signal line for connecting the first reference voltage pads and the plurality of shorting bars. An organic light emitting display device that does not do this. delete 7. The method of claim 6,
the data pads disposed in the first pad area are partially exposed to the cut end surface of the first cutting line at the edge of the display panel;
The first reference voltage pads are not exposed to the cut end of the first cutting line. 7. The method of claim 6,
The second reference voltage pads disposed in the second pad area are spaced apart from each other with an area in which four data pads are to be disposed among the data pads disposed in the first pad area. According to claim 1,
The first reference voltage pads are
When the substrate is cut along a first cutting line adjacent to the first pad area and the first grinding area, the cut end surface is not exposed.

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