KR20170081002A - Array substrate with enhanced thermal resistance and display device having thereof - Google Patents

Abstract

The present invention relates to an array substrate and a display device having a planarization layer in which porous copper particles are dispersed in a binder resin having excellent heat resistance between a touch panel and a display panel. The planarization layer is not deteriorated even by the manufacturing process of the high temperature thin film transistor by applying the planarization layer in which the porous copper particles having excellent heat resistance are dispersed between the touch panel and the display panel. In addition, when the flattening layer of the present invention is applied, it is possible to stably adhere the display panel and the touch panel with excellent adhesion properties, anti-cracking property, and anti-electrostatic property, And it is possible to quickly discharge the static electricity to prevent the defective device.

Description

TECHNICAL FIELD [0001] The present invention relates to an array substrate having improved heat resistance and a display device including the array substrate.

The present invention relates to an array substrate, and more particularly, to an array substrate for a display device having improved heat resistance, which is applied to an in-cell type display device and a display device including the same.

As smart devices have become widespread, touch screen panels have been applied to flat panel display devices such as liquid crystal display devices (LCDs) and organic light emitting diode display devices (OLED display devices). A touch screen panel refers to an input device that recognizes a position of a screen or touches the screen with a finger or a pen or the like and transmits the touch screen to the system.

The touch screen panel consists of a touch panel, a controller IC, and driver software. The touch panel is composed of a substrate on which a transparent electrode is deposited. The touch panel detects a position where a contact occurs or a signal generation position due to a change in electric capacity, and transmits the signal to the controller IC. The controller IC converts the analog signal transmitted from the touch panel to a digital signal, The driver software receives the digital signal transmitted from the controller IC and controls the touch panel to be implemented in each operating system.

According to the application method of the touch panel, two substrates in which a transparent electrode layer such as indium-tin-oxide (ITO) is coated are bonded together such that a transparent electrode layer faces each other with a dot space therebetween (Resistive Touch Type) which recognizes the pressure applied to the upper substrate, a transparent electrode is formed by coating a conductive metal on both sides of a substrate constituting a touch screen sensor, and a certain amount of current is caused to flow on the surface of the substrate Capacitive touch type which recognizes a portion where the amount of electric current is changed by subtracting the capacitance in the human body through the potential difference between the two conductors is typically used. In addition, an ultrasonic method (Surface Acoustic Wave Touch Type) that recognizes a user or an area contacted by a pen using sound propagation characteristics, or an infrared touch type that uses an attribute that is blocked when an infrared ray hits an obstacle It was proposed.

On the other hand, according to the stacked-up structure of the touch panel and the display panel, an external type (Add-on Type) in which the touch panel is interposed between the outside of the substrate constituting the display panel and the cover glass, (Embedded Type). The built-in touch panel also includes an on-cell type in which a touch panel is mounted on the top of a display panel and an in-cell type in which a touch panel is mounted in a display panel (for example, . Compared to the external touch panel, the built-in touch panel does not require a separate substrate for the touch sensor, so it can be made thinner and lighter. In addition, since the built-in type reduces the light-reflection on the surface of the touch panel, the power consumption required for the display device is also reduced.

1 is a cross-sectional view schematically showing a display device to which an in-cell type touch panel is applied. 1, a display device 1 to which a conventional in-cell type touch panel is applied includes a lower substrate 11, an upper substrate 12 facing the lower substrate 11, And a touch panel 30 positioned between the lower substrate 11 and the display panel 20. The display panel 20 includes a display panel 20,

The display panel 20 includes a thin film transistor (TFT) 22 for driving the display panel 20. The thin film transistor 22 includes an inorganic insulating film laminated by a silicon material, and the inorganic insulating film is deposited at a high temperature, for example, at 350 DEG C or higher. The touch panel 30 positioned directly on the upper surface of the lower substrate 11 includes a first touch electrode 32 and a second touch electrode 34 made of a transparent metal such as ITO. Since the touch panel 30 and the display panel 20 can not be directly attached due to the touch electrodes 32 and 34, the touch panel 30 and the thin film transistors 22 located below the display panel 20 A flattening film 36 of an insulating material is interposed.

Conventionally, an acrylate resin has been generally employed as an insulating material for forming the planarization film 36 located between the display panel 20 and the touch panel 30. [ However, the acrylate resin has a good processability, but is poor in heat resistance. Therefore, the flattening film 36 made of an acrylate resin easily deteriorates under high-temperature processing conditions for forming the thin film transistor 22 constituting the display panel 20 located thereon. As the flattening film 36 deteriorates, lifting occurs at the interface between the display panel 20 and the touch panel 30, cracks occur in the flattening film 36, (Yellow mura) occurs in the photoreceptor (1).

Therefore, it is necessary to develop a planarizing film having excellent adhesion to these display panels while suppressing lifting and cracking at the interface between the touch panel and the display panel and ensuring sufficient heat resistance properties and not deteriorating even under high-temperature process conditions.

DISCLOSURE OF THE INVENTION The present invention has been proposed in order to solve the above problems of the prior art, and an object of the present invention is to provide an array substrate for a display device which is excellent in heat resistance and does not deteriorate even by a high temperature process for manufacturing a thin film transistor, .

It is another object of the present invention to provide an array substrate for a display device having a bonding property to a substrate, an anti-crack property, and an anti-scratch property, and a display device including the same.

Another object of the present invention is to provide an array substrate for a display device having a light transmitting property and an excellent electrostatic discharge characteristic, and a display device including the same.

According to an aspect of the present invention, there is provided an array substrate for a display device having a flattening film in which porous copper particles are dispersed in a binder resin having excellent heat resistance between a touch panel and thin film transistors constituting a display panel, And a display device including the same.

In an exemplary embodiment, a buffer layer may further be interposed between the planarization film and the touch panel and the thin film transistor, respectively.

The porous copper particles may be mesoporous copper particles, for example, mesoporous copper particles impregnated into the inner walls of porous silicate particles.

According to the present invention, there is proposed an array substrate for a display device in which a planarizing film in which porous copper particles are dispersed in a heat-resistant binder resin is disposed between a touch panel and a thin film transistor or a display panel located on an upper portion of the substrate, and a display device including the same .

The planarizing film of the present invention is excellent in heat resistance and is not deteriorated by a high-temperature process for manufacturing a thin film transistor to be applied to a display panel.

Particularly, by adopting the pore structure, a passage for dispersing the heat generated in the array panel to the touch panel is formed. Thereby lowering the coefficient of thermal expansion (CTE) of these panels, thereby making the thermal stresses applied to these panels similar. Therefore, the flattening film of the present invention is excellent in adhesion properties to a substrate even at a high temperature, and is excellent in anti-cracking property and scratch resistance, so that the touch panel and the display panel are not peeled off even under external shocks or severe process conditions They can be adhered well.

Since the light-transmitting property of the planarizing film of the present invention does not deteriorate even by the curing process, good luminance can be obtained even in a display device to which the planarizing film is applied. In addition, since the planarizing film of the present invention can reduce the parasitic capacitance by adopting a low dielectric constant material, power consumption can be reduced.

In addition, since the planarizing film of the present invention can quickly attenuate static electricity, it is possible to prevent degradation of the driving performance of the display panel or the touch panel due to the generation of static electricity.

1 is a cross-sectional view schematically showing a display device having a touch panel according to a related art.
2 is a schematic cross-sectional view of a planarizing film applied between a touch panel and a display panel in accordance with an exemplary embodiment of the present invention.
Figure 3a is a schematic illustration of a process for making MCM-41 used as a template for making mesoporous copper particles in accordance with an exemplary embodiment of the present invention.
3B is a schematic view illustrating a process for producing mesoporous copper particles from MCM-41 used as a mold.
4 is a cross-sectional view schematically illustrating a display device to which a high-temperature-resistant flattening film is applied between a touch panel and a liquid crystal display panel according to an exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view schematically illustrating a display device to which a high-temperature-resistant flattening film is applied between a touch panel and a light-emitting diode display panel according to an exemplary embodiment of the present invention.
FIGS. 6A to 6F show the results of analysis of synthesized mesoporous copper particles, respectively, according to an exemplary embodiment of the present invention.
FIG. 6A is a graph showing an X-ray diffraction (XRD) analysis result of mesoporous copper particles, and FIG. 6B is a graph showing FTIR spectroscopy (Fourier transform infrared spectroscopy) analysis results of mesoporous copper particles. It is a graph.
FIG. 6C is a graph showing the results of BET (Brunauer-Emmett-Teller) analysis for mesoporous copper particles, and FIG. 6D is a graph showing NMR spectrum analysis results for mesoporous copper particles. In FIG. 6C, A shows the analysis results for copper-impregnated mesoporous particles, and B shows the analysis results for the porous silicates before copper impregnation.
6E and 6F are SEM and TEM photographs of mesoporous copper particles, respectively.
FIG. 7A is a pattern photograph according to an adhesion test of a planarizing film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention. FIG.
Figs. 7B and 7C are photographs of a pattern of a polyacrylate binder resin in which mesoporous particles are not dispersed and a planarizing film composed of polysiloxane resin alone, respectively, as a comparative example.
Figs. 7D and 7E are photographs of a pattern according to an adhesion test of a planarizing film in which mesoporous aluminum particles and mesoporous chrome particles are dispersed in a polysiloxane resin as comparative examples.
FIG. 8A is a photograph of a crack characteristic of a planarizing film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention. FIG.
FIGS. 8B and 8C are photographs showing crack characteristics of a polyacrylate binder resin in which mesoporous particles are not dispersed and a planarization insulating film composed of only a polysiloxane resin, as comparative examples.
8D and 8E are photographs showing crack characteristics of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as comparative examples.
9A is a photograph of peel strength analysis of a planarization insulating film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention.
FIGS. 9B and 9C are photographs showing a peel strength analysis of a polyacrylate binder resin in which mesoporous particles are not dispersed and a planarization insulating film composed solely of polysiloxane resin, as comparative examples.
9D and 9E are photographs showing crack characteristics of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as comparative examples.
FIG. 10A is a photograph of a crack analysis characteristic of a planarization insulating film in which mesoporous copper particles are dispersed in a polysiloxane resin according to stress, according to an exemplary embodiment of the present invention. FIG.
FIGS. 10B and 10C are photographs showing crack characteristics of a polyacrylate binder resin in which mesoporous particles are not dispersed and a planarizing insulating film composed of polysiloxane resin only, according to stress, respectively, as comparative examples.
FIGS. 10D and 10E are photographs showing crack characteristics according to stress of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as comparative examples.

According to an aspect of the present invention, there is provided a touch panel including: a touch panel disposed on a substrate; A thin film transistor positioned apart from the touch panel; And a planarization layer interposed between the touch panel and the thin film transistor, wherein the planarization layer includes porous copper particles dispersed in a binder resin.

A first buffer layer positioned between the touch panel and the planarization layer, and a second buffer layer positioned between the planarization layer and the thin film transistor.

The porous copper particles may include mesoporous copper particles, and the binder resin may be selected from the group consisting of a polysiloxane-based resin, a polyimide-based resin, and a combination thereof.

For example, the porous copper particles may be dispersed in the binder resin in a proportion of 0.5 to 10 parts by weight to the binder resin, and the porous copper particles are impregnated with porous silicate particles.

According to another aspect of the present invention, there is provided a plasma display panel comprising: a first substrate; A touch panel positioned on the first substrate; A display panel spaced apart from the touch panel; And a planarization layer interposed between the touch panel and the display panel, wherein the planarization layer includes porous copper particles dispersed in a binder resin.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings where necessary.

Fig. 2 is a plan view of a planarizing film applied between a touch panel TP (see Fig. 4) and a display panel DP (see Fig. 4), for example an array panel AP (see Fig. 4), according to an exemplary embodiment of the present invention Fig. The planarization layer 300 includes a planarization layer 310 in which porous copper particles 320 are dispersed in a binder resin 312 and a first buffer layer 332 located in a lower portion and an upper portion of the planarization layer 310, And a second buffer layer 334.

In one exemplary embodiment, the binder resin 312 constituting the planarization layer 310 may be a binder resin having excellent heat resistance. For example, the binder resin 312 may be a polysiloxane-based resin and / or a polyimide-based (PI) resin. The polysiloxane-based resin and the polyimide-based resin basically have an advantage that they are not deteriorated even under high-temperature conditions because they have good heat-resistant properties. The planarization layer 310 may be coated and laminated on the touch panel TP (see FIG. 4) through the first buffer layer 332.

In order to form the planarization layer 310 composed of the binder resin 312 in which the porous copper particles 320 are dispersed on the first buffer layer 332, a reactive component that can be cured with the binder resin, an organic solvent, And other additives are coated on the upper portion of the first buffer layer 332, and the binder composition is cured.

In one exemplary embodiment, to obtain a polysiloxane-based resin as the binder resin 312, a silane monomer or siloxane monomer having at least one silanol group and / or siloxane group may be used as a heat-reactive component. When these suitable silane monomers and / or siloxane monomers are heat-treated, cross-linking is formed between these monomers to obtain a polysiloxane-based resin. Examples of the monomer compound having a silanol group according to the present invention include silanol group-containing monomers obtained by hydrolyzing silyl group-containing unsaturated monomers such as ethylenically unsaturated alkoxysilanes and ethylenically unsaturated acyloxysilanes .

Examples of the ethylenically unsaturated alkoxysilane compounds include acrylate-based alkoxysilanes such as? -Acryloxypropyl-trimethoxysilane and? -Acryloxypropyl-triethoxysilane, 2)? -Methacryloxypropyltrimethoxysilane Methacrylate-based alkoxysilanes such as? -Methoxypropyltrimethoxysilane,? -Methacryloxypropyltriethoxysilane,? -Methacryloxypropyl-tris (2-methoxyethoxy) silane. On the other hand, examples of the ethylenically unsaturated acyloxysilane compounds include acrylate-based acetoxysilane, methacrylate-based acetoxysilane and ethylenically-unsaturated acetoxysilane (for example, acrylatepropyltriacetoxysilane, methacrylate Propyltriacetoxysilane) and the like.

Examples of the silyl group-containing unsaturated compound capable of obtaining a monomer having a silanol group through hydrolysis or the like include chlorodimethylvinylsilane, 5-trimethylsilyl-1,3-cyclopentadiene, 3-trimethylsilylallyl alcohol, But are not limited to, trimethylsilyl methacrylate, 1-trimethylsilyloxy-1,3-butadiene, 1-trimethylsilyloxycyclopentene, 2-trimethylsilyloxyethyl methacrylate, 2-trimethylsilyloxyfuran, , Allyloxy-t-butyldimethylsilane, and trisalkoxyvinylsilane such as allyloxytrimethylsilane, trimethoxyvinylsilane, triethoxyvinylsilane, and tris (methoxyethoxy) vinylsilane. The above-mentioned silanol group-containing monomers may be used singly or in combination of two or more.

On the other hand, as the reactive component for obtaining the polysiloxane-based resin, a monomer having a siloxane group can also be used. As such a monomer having a siloxane group, a compound having a linear siloxane group, a compound having a cyclic siloxane group, a compound having a siloxane group having a tetrahedral structure, and silsesquioxane can be used.

A monomer compound having a linear siloxane is C ₁ -C ₁₀ alkyl and / or C ₁ -C ₁₀ alkoxy group of 4-8 is an alkyl siloxane, an alkoxy siloxane, alkoxy alkyl siloxanes, vinyl alkoxy substituted with siloxane, N- ( Aminoethyl) -3-aminopropylmethyldimethoxysilane, N- (2-aminoethyl) -3-aminopropylmethyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3- glycidoxypropyl tri But are not limited to, ethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 2- (3,4-ethoxycyclohexyl) ethyltrimethoxysilane, 3-chloropropylmethyldimethoxysilane, 3-chloropropyltrimethoxysilane , 3-methacryloxypropyltrimethoxysilane, 3-mercaptopropyltrimethoxysilane, and the like, or a mixture of two or more selected from them may be used, but the present invention is not limited thereto . For example, a linear siloxane group containing an alkoxy group such as TMOS, TEOS, MTMS, vinyltris (2-methoxyethoxy) -silane, N- (2-aminoethyl) -3-aminopropylmethyldimethoxysilane, The monomers may be used singly or in combination of two or more.

On the other hand, non-limiting examples of cyclic siloxane include cyclotrisiloxane such as methylhydro-cyclosiloxane, hexamethyl-cyclotrisiloxane, hexaethyl-cyclotrisiloxane; Cyclotetrasiloxanes such as tetraoctyl-cyclotetrasiloxane, hexamethyl-cyclotetrasiloxane, octamethyl-cyclotetrasiloxane; Tetra- and penta-methylcyclotetrasiloxanes; Tetra-, penta-, hexa- and hepta-methyl cyclopentasiloxanes; Tetra-, penta- and hexamethyl-cyclohexasiloxane, tetraethyl-cyclotetrasiloxane, and tetraphenylcyclotetrasiloxane; Decamethylcyclopentasiloxane, dodecamethylcyclosiloxane, 1,3,5,7-tetramethyl-cyclotetrasiloxane, 1,3,5,7,9-pentamethyl-cyclopentasiloxane, and 1,3, 5,7,9,11-hexamethylcyclohexasiloxane may be used in particular, but the present invention is not limited thereto.

Further, non-limiting examples of the monomer having a tetrahedral siloxane group include tetrakisdimethylsiloxysilane, tetrakis diphenylsiloxysilane and tetrakisdiethylsiloxysilane, and mixtures thereof.

In addition to the linear, cyclic and tetrahedral siloxanes, silsesquioxane (SSQ), which can be synthesized by, for example, reaction of methyltrichlorosiloxane with dimethylchlorosiloxane, is also used as a reactive material for synthesizing polysiloxane . Silsesquioxane can be synthesized by crosslinking with polysilsesquioxane having a ladder structure or a cage structure. For example, by hydrolysis of organotrichlorosilane, a heptamer type siloxane having a partial cage structure, a heptamer form of a cage structure, and an octamer type siloxane can be obtained. By using the difference in solubility, Silsesquioxane monomer can be obtained by the condensation reaction of organotrialkoxysilane or organotrichlorosilane. The silsesquioxane monomer can be obtained by condensation reaction of organotrialkoxysilane or organotrichlorosilane. Silsesquioxane may have a chemical structure of approximately RSiO _3/2 (R is hydrogen, an alkyl group having 1-10 carbon atoms, an alkenyl group having 2-10 carbon atoms, an aryl group such as phenyl, an arylene group) The silsesquioxane that can be used is not limited thereto.

Meanwhile, the reactive material for synthesizing the polyimide that can be used as the binder resin 312 may include an amine compound and an anhydride. The polyimide may include, for example, an aromatic polyimide (PI) and a colorless polyimide (CPI). For example, the CPI introduces an element having relatively high electronegativity such as trifluoromethyl (-CF ₃ ), sulfone (-SO ₂ ), and ether (-O-) in the main chain of PI, A method of reducing the density of the [pi] electrons present in the main chain by introducing a cyclic olefin structure which is limited or not benzene can be used. The polyimide may be obtained by synthesizing a polyamic acid by adding a diamine and a dianhydride to an appropriate solvent, and reacting the obtained polyamic acid through a suitable imidization process, for example, a thermal imidization process or a catalytic / chemical imidization process Can be obtained.

Transparency Dielectric and Transparent Diamine for Producing Transparent Polyimide (CPI) The following transparent dianhydrides and transparent diamines can be used.

The transparency dianhydride can be prepared by reacting 4,4 '- (hexafluoroisopropylidene) diphthalic anhydride (4,4' - (Hexafluoroisopropylidene) diphthalic anhydride, 6FDA), 1,2,4,5-cyclobutanetetracarboxylic dianhydride 1,2,4,5-cyclobutane tetracarboxylic dianhydride (CBDA), 1,2,4,5-cyclohexane tetracarboxylic dianhydride (CHDA), 4,4'- Oxydiphthalic anhydride (ODPA), 3,3 ', 4,4'-diphenylsulfone tetracarboxylic dianhydride (DSDA), 3,3', 4,4'-diphenylsulfone tetracarboxylic dianhydride , 3,3 ', 4,4'-benzophenone tetracarboxylic dianhydride (BPDA or BTDA), 2,2-Bis [4- (3,4- Dicarboxyphenoxy) phenol]] propane dianhydride (BPADA), and combinations thereof. However, in the present invention The present invention is not limited thereto.

On the other hand, the transparent diamine is 4,4'-oxydianiline (ODA), 2,2-Bis [4- (4-aminophenoxy) phenyl] propane - (4-aminophenoxy) phenyl] propane, BAPP), 2,2'-bis (trifluoromethyl) -4,4'-biphenyldiamine biphenyldiamine, TFMB or TFB), 4,4'-Bis (4-aminophenoxy) biphenyl, BAPB, cyclohexyl diamine Diaminobenzene cyanide (DABN), 2,2-bis [4- (4-aminophenoxy) phenyl] hexafluoropropane, 2,2- 6FBAPP), bis [4- (4-aminophenoxy) phenyl] sulfone, BAPS), and combinations thereof. But is not limited thereto.

The silanol / siloxane monomer or the dianhydride / diamine, which is a reactive component of the binder resin 312, is used in an amount of about 5 to 40 parts by weight, preferably 10 to 30 parts by weight, in the binder composition for synthesizing the binder resin 312 ≪ / RTI > Unless otherwise stated herein, parts by weight refers to the weight ratio between the components being compounded.

The porous copper particles 320 dispersed in the binder resin 312 may be any porous particles having a pore structure. For example, the porous copper particles 320 include microporous copper particles, mesoporous copper particles, and macroporous copper particles. In the present specification, the microporous particles mean porous particles having an average pore diameter of less than 2 nm. The mesoporous particles mean porous particles having an average pore diameter of 2 nm or more and less than 50 nm. The macroporous particles have an average diameter Means a porous particle of 50 nm or more. In one exemplary embodiment, the porous copper particles are mesoporous particles. The mesoporous copper particles have a pore size sufficient to release heat generated from the array panel AP (see FIG. 4) located on top of the planarization layer 310 of the present invention to the outside, and the uniform pore size and pore distribution Has an advantage of being easy to manufacture.

Mesoporous silicate can be used as a template to obtain mesoporous copper particles, and mesoporous silicate can be synthesized by various methods. In one exemplary embodiment, the mesoporous copper particles 320 can be synthesized using mesoporous silicates, which are porous molecular sieve materials, as a template. The mesoporous silicate of the porous molecular sieve material may be suitable for use as a template for the porous copper particles 320 of the present invention because of its uniform pore size and excellent non-surface area.

The mesoporous silicate that can be used as a template for synthesizing the porous copper particles 320 can be prepared by using a surfactant such as cetyltrimethyl ammonium bromide (CTAB) as a structure directing material , A mobile composition of matter (MCM) series using tetramethyl orthosilicate (TMOS), tetraethyl orthosilicate (TEOS) or sodium methasilicate as a silica introduction material . Alternatively, a non-ionic surfactant such as a pluronic surfactant or a pore polymer such as poly (ethylene oxide) -poly (ethylene oxide) -poly (ethylene oxide) PEO-PPO- SBA (Santa Barbara Amorphous) series using a non-ionic triblock copolymer as a structure-inducing material and using TMOS, TEOS as a silica-introducing material can be applied as a mesoporous silicate. These mesoporous silicates have various structures depending on the silica introduced component, the kind of the surfactant, the content thereof, the charge density at the interface between the surfactant and the silica-introduced component, and the like.

For example, MCM-41, SBA-3, and SBA-15 are regular hexagonal arrangements of one-dimensional nanopores, while MCM-48 is a two- Structure (cubic Ia3d). MCM-50 is a layered structure, SBA-1 and SBA-6 are spherical mesopores with three-dimensionally connected cubic Pm3n lattice structures, and SBA-16 are three-dimensional porous materials with cubic Im3m lattice structures . In addition to these, the KIT-1 (Korea Advanced Institute of Science and Technology-1) and MSU-X (Michigan State University-Institute of Science and Technology-1), a structure in which mesoporous materials are regularly arranged and SBA- X), and hexagonal mesoporous silica (HMS).

The case where MCM-41 is used as a template for the process of synthesizing the porous copper particles 320 dispersed in the binder resin 312 constituting the planarization layer 310 will be described by way of example. Figure 3a is a schematic illustration of a process for making MCM-41 used as a template for making mesoporous copper particles in accordance with an exemplary embodiment of the present invention.

3A, a surfactant 322 such as CTAB is used as a structure-inducing material and a silica-introduced material such as TEOS, TMOS, sodium metasilicate, fumed silica, Ludox (for example, Ludox HS40) Or under a catalyst such as a base. In this process, the surfactant 322 is arranged in a micelle structure. The silicate formed by the hydrolysis and condensation of the silica-introduced components around the surfactant 322 arranged in a micelle structure is a self- - Self-assembled to form a supra-molecule. Specifically, an inorganic material such as a silicate interacts with a hydrophilic moiety located on the surface of a self-aligned surfactant in a micelle structure to form an organic-inorganic complex in the form of a solid powder or film. Then, the organic-inorganic hybrid material is calcined at a temperature of 500 ° C or higher to remove organic molecules such as the surfactant 322 and the mesoporous silicate 324 having mesopores 326 is arranged in hexagonal order to form MCM-41 Structure.

Subsequently, FIG. 3B is a view schematically showing a process for producing mesoporous copper particles from MCM-41 used as a mold. (CuNO ₃ ) hydrate, CuCOOH hydrate, CuCl hydrate, Cu (II) acetylacetonate, etc., to the hexagonal mesoporous silicate 324 from which the surfactant 322 The copper particles 328 from the copper precursor material are impregnated into the inner walls of the pores 326 of the mesoporous silicate 324 to obtain mesoporous copper particles have. Thus, according to an exemplary embodiment of the present invention, the porous copper particles 320 (see FIG. 2) may be impregnated with the porous silicate particles, but the present invention is not limited thereto.

For example, the porous copper particles 320 may be dispersed in the binder resin 312 at a ratio of about 0.5 to 10 parts by weight. If the content of the porous copper particles 320 is less than this, improvement in physical properties such as improvement in heat resistance characteristics is difficult to expect. On the other hand, even if the content of the porous copper particles 320 is larger than that, the physical properties do not increase in proportion to the added amount, and the light-transmittance may be lowered.

On the other hand, the solvent used in the binder composition is not particularly limited, and examples thereof include alcohol solvents such as methanol and ethanol; Ethylene glycol monoethyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, diethylene glycol monomethyl ether, diethylene glycol monomethyl ether, Ether solvents selected from one or more selected from the group consisting of ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol propyl ether and propylene glycol butyl ether; Propylene glycol monomethyl ether acetate, ethylene glycol monoethyl ester, methyl lactate, ethyl lactate, ethyl acetate, propyl acetate, ethyl 2-hydroxypropionate, methyl 2-hydroxy- Ester solvents selected from the group consisting of methylhydroxyacetate, ethylhydroxyacetate, propyleneglycol methylethylpropionate, propyleneglycol ethylether propionate, and the like; An acetate solvent selected from the group consisting of ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate and propylene glycol monoethyl ether acetate; An aromatic hydrocarbon solvent selected from at least one of toluene, xylene, cresol and the like; A ketone-based solvent selected from one or more of acetone, methyl ethyl ketone, cyclopentanone, cyclohexanone, 2-heptanone, and 4-hydroxy-4-methyl-2-pentanone; An amide selected from at least one of N-methylpyrrolidone (NMP), N-methylacetamide, N, N-dimethylacetamide (DMAc), N-methylformamide and N, N-dimethylformamide Based solvent; a lactone-based solvent which can be? -butyrolactone, and a combination thereof. These solvents may be blended in the binder composition at a ratio of 40 to 100 parts by weight, preferably 50 to 90 parts by weight, more preferably 60 to 80 parts by weight.

If necessary, the binder composition may further comprise a functional additive. The functional additive may include a coupling agent, a surfactant, a crosslinking accelerator, and the like. The coupling agent is used for improving the bonding property between the binder resin 312 and the substrate, and may be selected from at least one of a silane coupling agent, an aluminum coupling agent, a titanium coupling agent, and a zirconium coupling agent, Is a silane coupling agent. These coupling agents are not particularly limited so long as they can improve the adhesion to the substrate by the surface treatment of the binder resin (312), but may be blended in a proportion of preferably 1 to 10 parts by weight in the binder composition.

In addition, anionic surfactant, cationic surfactant, amphoteric surfactant, and nonionic surfactant may be used as the surfactant for inducing dispersion of the thermoreactive component. Examples of the anionic surfactant include alkylsulfonic acid (sulfonate), alkylsulfuric acid (sulfate), aralkyl and alkaryl anionic surfactants, alkylsuccinic acid (succinate), and alkylsulfosuccinate (sulfosuccinate) have. Particularly preferred are sodium, magnesium, ammonium and monoethanolamine, diethanolamine and triethanolamine salts of alkarylsulfonic acid, alkylsulfuric acid and alkarylsulfuric acid. The content of the surfactant may vary depending on the type of the solvent used, the content of the reactive component, and the like, but the content thereof may be approximately 0.01 to 1.0 part by weight in the binder composition.

Further, a crosslinking accelerator for promoting crosslinking of the silanol / siloxane monomer or the like used as the reactive component may be used in the binder composition. Crosslinking accelerators that can be used include dimethylaniline, 1,1'-methylenebis (3-methylpiperidine) (MBMP), dimethylbenzylamine (DMBA), tris (dimethylaminomethyl) phenol (TDMAMP), hexamethylenetetramine And monoethylamine such as 1,6-bis- (dimethylamino) hexane, tertiary amines such as trimethylamine and octyldimethylamine; N ', N'-dimethylurea, N-4-methylphenyl-N', N'-dimethylurea, N- (2-hydroxyphenyl) -N ' - urea derivatives such as dimethylurea; For example, imidazole, benzimidazole, 1-methylimidazole, 3-methylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, , 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1- (2,6-dichlorobenzoyl) -2-phenylimidazole and 1- , 6-trimethylbenzoyl) -2-phenylimidazole; substituted or unsubstituted imidazoles; Organic phosphines such as triphenylphosphine; Silsesquioxanes, and the like, or a mixture of two or more thereof.

Particularly, the siloxane-based reactive component may be deteriorated in heat resistance as a crosslinking accelerator is added. Therefore, it may be preferable to use a crosslinking accelerator which does not affect the heat resistance of the flattening layer 310 composed of the binder resin 312 finally produced. An example of such a crosslinking accelerator is polyhedral oligomeric silsesquioxane (POSS) which is a silsesquioxane having a cage structure among polysilsesquioxanes. The content of the crosslinking accelerator may vary depending on the type and content of the solvent and the solvent to be contained in the binder composition, but the content thereof may be approximately 0.01 to 0.1 part by weight in the binder composition.

A binder composition containing the above-described reactive component, porous copper particles, solvent, other additives, and the like is coated on a suitable substrate, and then the resultant is cured to form a planarizing layer (binder layer) 312 composed of a binder resin 312 in which porous copper particles 320 are dispersed 320 can be obtained. The coating method is not limited, and a slit coating method using a slit nozzle such as spin coating, roll coating, spray coating, bar coating, discharge nozzle coating and the like can be used, and two or more coating methods can be combined and coated have. The thickness of the coated film may vary depending on the coating method, the concentration of the solid content in the binder composition, the viscosity, and the like. However, the thickness of the flattening layer 310 may be 0.1 to 2.0 μm after drying.

Concretely, the curing process for the binder composition described above is performed to evaporate the solvent, and finally the binder resin 312 in which the porous copper particles 320 are dispersed can be formed on the substrate. This process can be generally used as a method of volatilizing the solvent by applying appropriate heat. For example, when a polysiloxane resin is to be used as the binder resin 312, it is preheated (prebaked) at a temperature of 80 to 120 ° C for 0.1 to 5 minutes, then at a temperature of 150 to 400 ° C for 5 to 200 (Post-baking) for 10 minutes to 10 minutes, preferably 10 to 100 minutes.

On the other hand, in order to produce the binder resin 312 in which the porous copper particles 320 are dispersed in the polyimide, the binder composition comprising the amine compound, the anhydride and the porous copper particles 320 described above is coated on the substrate, An imidation thermal imidization process in which a polyamic acid obtained by reaction of a compound and an anhydride is heated at 140 to 300 ° C, a chemical imidization process in which a chemical imidization reaction is performed using a dehydration catalyst such as acetic anhydride / pyridine May be used alone or in combination.

Referring back to FIG. 2, the first and second buffer layers 332 and 334 located at the lower and upper portions of the planarization layer 310 constituting the planarization layer 300 are located. As described above, porous copper particles 320, which are metal components, are dispersed in the binder resin 312 in the planarization layer 310. When the planarization layer 310 is directly interposed between the touch panel TP (see FIG. 4) and the array panel AP, a large number of metallic electrodes or wiring constituting the touch panel and the array panel, and a plurality of porous copper particles 320 An electrical short may occur. In order to prevent this, a first buffer layer 332 and a second buffer layer 334, which are made of an insulating material, are disposed on the lower and upper portions of the planarization layer 310, respectively.

In one exemplary embodiment, the first buffer layer 332 and the second buffer layer 334 may be laminated using an inorganic material. For example, such as the first buffer layer 332 and the second buffer layer 334 is a silicon oxide (SiO ₂₎ and / or may be prepared using silicon nitride (SiNx), PECVD (plasma enhanced chemical vapor deposition) Method. ≪ / RTI > In this case, the first buffer layer 332 and the second buffer layer 334 may each be laminated to a thickness of 500 to 2000, but the present invention is not limited thereto.

The planarization layer 310 as an insulating film in which the porous copper particles 320 are dispersed in the binder resin 312 according to the present invention has excellent heat resistance characteristics. When the planarization layer 310 is used as the planarization film 300 between the touch panel TP (see FIG. 4) and the array panel AP (see FIG. 4) constituting the display panel DP No deterioration such as destruction of the structure of the planarization layer 310 is caused by the high-temperature process at 350 DEG C or more for manufacturing the thin film transistor Tr (see Fig. 4) constituting the panel.

That is, the planarization layer 300 including the planarization layer 310 manufactured according to the present invention employs the binder resin 310 having excellent heat resistance characteristics, while using the porous copper particles 320, Since the passage is formed, the heat dispersion property is good. Accordingly, the thermal stress between the array panel AP (see FIG. 4) located on the planarizing film 300 and the touch panel TP (see FIG.

Therefore, it is possible to maintain excellent adhesion to the touch panel or substrate and the array panel, which are located at the upper and lower portions, respectively, even under high temperature conditions (see FIG. 7A). In addition, cracking does not occur (see FIGS. 8A and 10A) because peeling does not occur at the interface with the substrate, and the peel strength is excellent (see FIG. 9A). Furthermore, since the light-transmittance property is not lowered even by the high-temperature treatment, it can be applied to a display device to obtain a satisfactory brightness, and since it includes the particles 320 having a porous structure, The driving voltage can be lowered. In addition, since the porous copper particles 320 having a low dielectric constant structure are dispersed to reduce the resistance of the planarization layer 310 used as an insulating layer, the static electricity that can be caused in the driving process can be rapidly attenuated, .

Subsequently, an array substrate for a display device and a display device to which a planarization layer 310 composed of a binder resin 312 in which the porous copper particles 320 are dispersed can be applied will be described. 4 is a cross-sectional view schematically illustrating a display device to which a high-temperature-resistant flattening film is applied between a touch panel and a liquid crystal display panel according to an exemplary embodiment of the present invention. The in-cell touch type liquid crystal display device 100 according to the second embodiment of the present invention includes a touch panel TP positioned on the first substrate 101 and an array panel AP). ≪ / RTI > A second substrate 102 facing the first substrate 101 is positioned at the upper end of the display panel DP and a liquid crystal layer 180 is interposed between the first substrate 101 and the second substrate 102 have. The first substrate 101 and the second substrate 102 may be made of a plastic material such as polyimide (PI) as well as glass.

The touch panel TP senses a user's touch. The touch panel TP includes a plurality of first touch electrodes 112 arranged along a first direction and a plurality of first touch electrodes 112 arranged along a second direction different from the first direction. And a plurality of second electrodes 114 which are connected to the second electrodes 114. For example, the first direction may be parallel to a data line (not shown), and the second direction may be parallel to a gate line (not shown), but is not limited thereto.

The first touch electrode 112 and the second touch electrode 114 are spaced apart from each other. For example, the plurality of first touch electrodes 112 may be integrally formed on the first substrate 101 along a first direction, and may have an island shape spaced apart from each other along the second direction A plurality of second touch electrodes 114 may be formed. In one exemplary embodiment, the first touch electrode 112 may be a transmit (Tx) electrode and the second touch electrode 114 may be a receive (Rx) electrode.

The touch panel TP may include a driving line connected to the first touch electrode 112, a second touch electrode 114 connected to the first touch electrode 112, A sensing line and a touch pad (not shown) are formed. The touch pad (not shown) is electrically connected to a plurality of transmission lines (not shown) or reception lines (not shown), and is connected to a display pad (not shown) through a connection means (not shown), for example an anisotropic conductive film. (Not shown).

A first buffer layer 332 covering the first and second touch electrodes 112 and 124 is formed on the touch panel TP. A first buffer layer 332 may be composed of an inorganic insulating material such as silicon oxide (SiO ₂₎ or silicon nitride (SiNx). The first buffer layer 332 is interposed between the touch panel TP and the planarization layer 310 and is disposed between the first and second touch electrodes 112 and 114 and the porous copper particles dispersed in the planarization layer 310 Prevents electrical shorts.

A planarization layer 310 in which porous copper particles are dispersed in a binder resin is disposed on the upper surface of the first buffer layer 332. For example, porous copper particles are mesoporous porous copper particles. A second buffer layer 334 composed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is disposed on the planarization layer 310, and the porous copper particles dispersed in the planarization layer 330 The gate electrode 132, and / or the data line 170, which are included in the array panel AP.

An array panel AP constituting the display panel DP is formed on the second buffer layer 334. The array panel AP is composed of a plurality of electrodes and wires so as to control the operation of a backlight unit (not shown).

The electrodes and wiring constituting the array panel AP will be described in detail. A plurality of gate lines (not shown) extend in one direction on the upper portion of the second buffer layer 334 and intersect the plurality of gate lines (not shown) to define a plurality of pixel regions P, A plurality of data lines 170 are formed. A gate pad (not shown) is formed in the non-display region and connected to one end of the data line 170 to form a data pad (not shown) in the non-display region .

Each of the plurality of pixel regions P includes a semiconductor layer 140 including a gate electrode 132, a gate insulating film 136, an active layer 142a and an ohmic contact layer 142b, and source and drain electrodes 152 And 154 are formed on the substrate. The gate electrode 132 is connected to a gate wiring (not shown) and is formed on the second buffer layer 334. On the gate wiring (not shown) and the gate electrode 132, a gate insulating film 136 made of an inorganic insulating material, for example, an inorganic insulating material which may be silicon oxide or silicon nitride, is formed.

An active layer 142a made of pure amorphous silicon and an ohmic contact layer 142b formed on the active layer 142a and exposing the center of the active layer 142a and made of impurity amorphous silicon are formed on the gate insulating film 136 . The active layer 142a and the ohmic contact layer 142b constitute the semiconductor layer 140. [

A source electrode 152 and a drain electrode 154 are formed on the semiconductor layer 140 to expose the center of the active layer 142a. The source electrode 152 is located on the semiconductor layer 140 and extends in the data line 170 while the drain electrode 154 is located on the semiconductor layer 140 and away from the source electrode 152. The thin film transistor Tr is located in the switching region TrA.

On the gate insulating film 136, a data line 170 extending along the second direction is formed so as to intersect the gate line (not shown). The data line 170 extends from the source electrode 152 of the thin film transistor Tr located in the pixel region P. [ Although not shown in the figure, in one exemplary embodiment, a common wiring (not shown) is formed along the second direction parallel to the data wiring 170 on the gate insulating film 136, ). In an alternative embodiment, the common wiring (not shown) may be formed in the same layer as the gate wiring (not shown) in parallel with the gate wiring (not shown).

On the other hand, the first passivation layer 160 that covers the data line 170, the source electrode 152, the drain electrode 154, and the common line (not shown) is formed as a first interlayer insulating film. A drain contact hole 164 is formed in the first passivation layer 160 to expose the drain electrode 154 of the thin film transistor Tr. The first passivation layer 160 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or an organic insulating material such as benzocyclobutene or photo acryl . The first passivation layer 160 prevents the ohmic contact layer 142b from being damaged in the process of forming the pixel electrode 176. [

A pixel electrode 176 as a first electrode which is in contact with and electrically connected to the drain electrode 174 of the thin film transistor Tr through the drain contact hole 164 is formed in each pixel region P, (Not shown). The pixel electrode 176 is made of a transparent conductive material and may have a plate shape in each pixel region P. [ For example, the transparent conductive material may be indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Although not shown, a gate pad electrode and a data pad electrode made of the same transparent conductive material as the pixel electrode 176 are formed in the non-display region of the upper portion of the first passivation layer 160, And is electrically connected to the gate pad through a pad contact hole (not shown), and the data pad electrode is electrically connected to the data pad through a data pad contact hole (not shown).

A second passivation layer 178, which is a second interlayer insulating film, is formed on the pixel electrode 176. The second protective layer 178 may be formed of an organic insulating material such as silicon oxide (SiO ₂₎ or silicon nitride (SiNx) and the inorganic insulating material or benzocyclobutene (benzocyclobutene) or the picture acrylate (photo acryl) of .

On the other hand, a common electrode 190 having a plurality of slit-shaped holes (openings 192) is formed on the second passivation layer 178 to overlap with the plate-shaped pixel electrode 176. Like the pixel electrode 176, the common electrode 190 as the second electrode may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The common electrode 190 is formed on the entire surface of the display region where a plurality of pixel regions P are formed. When a voltage is applied between the pixel electrode 176, which may be a first electrode in the form of a plate, and the common electrode 190, which may be a second electrode having the opening 192, a fringe field is formed, By driving, the transmission efficiency is improved and a high-quality image is displayed.

Although not shown in the drawings, a black matrix, which is a light shielding member having openings corresponding to the respective pixel regions P, is formed under the second substrate 102, and the lower portion of the black matrix and the exposed portion of the black matrix, 2, a color filter layer is formed on the lower side of the substrate 102. The color filter layer (not shown) includes red, green, and blue color filters corresponding to the pixel regions P. An overcoat layer (not shown) of a material such as polyimide, polyacrylate, or polyurethane is formed between the color filter layer (not shown) and the liquid crystal layer 180 in order to protect the color filter layer (not shown) Can be formed. In addition, although not shown, a polarizing plate may be disposed on the second substrate 102, and a cover window may be disposed on the polarizing plate (not shown) through an optically clear adhesive (OCA).

The display device 100 according to the first embodiment of the present invention includes a planarizing layer having porous copper particles dispersed in a high heat-resistant binder resin between an array panel AP constituting a display panel DP and a touch panel TP, (310). Therefore, the planarization layer 310 is not deteriorated even by the high-temperature process of 350 DEG C or more for fabricating the thin film transistor Tr constituting the array panel AP. The planarization layer 310 is firmly adhered to the touch panel TP and the array panel AP even after the array panel AP is finally manufactured so that the touch panel TP and the array panel AP) can be firmly maintained.

In addition, since the planarization layer 310 according to the present invention can maintain its characteristics even by a high-temperature process, cracking and / or peeling due to a high-temperature process does not occur. Since the light-transmittance is not lowered even by the high-temperature process, good luminance can be obtained, and since the porous copper particles having the pore structure are dispersed, the low-permittivity can be ensured and the driving voltage can be lowered. In addition, since the pore structure can rapidly attenuate and remove the static electricity that may be caused in the operation of the device, it is advantageous in that defective operation of the device due to static electricity or decrease in yield can be prevented.

FIG. 4 illustrates an in-cell type display device using a liquid crystal display device 100 as a display device as a display device. However, the planarizing film of the present invention is an in-cell type display device using an organic light emitting diode as a display device . ≪ / RTI > 5 is a cross-sectional view schematically illustrating a display device to which a high-temperature-resistant flattening film is applied between a touch panel and a light-emitting diode display panel according to a second exemplary embodiment of the present invention. The in-cell touch type organic light emitting diode display device 200 according to the second embodiment of the present invention includes a touch panel TP located on a substrate 201 and an array panel AP), and a light emitting diode (E) on the array panel (AP). The touch panel TP senses a user's touch. The light emitting diode E serves as a light source. The array panel AP controls the operation of the light emitting diode E. The substrate 201 is made of glass or a plastic material.

The touch panel TP includes a plurality of first touch electrodes 212 arranged along a first direction and a plurality of second electrodes 214 arranged along a second direction different from the first direction. For example, the first direction may be parallel to a data line (not shown), and the second direction may be parallel to a gate line (not shown), but is not limited thereto.

The first touch electrode 212 and the second touch electrode 214 are spaced apart from each other. For example, the plurality of first touch electrodes 212 may be formed integrally with each other along a first direction on a substrate 201, and a plurality of island-shaped The second touch electrode 214 may be formed. In one exemplary embodiment, the first touch electrode 212 may be a transmit (Tx) electrode and the second touch electrode 214 may be a receive (Rx) electrode.

The touch panel TP may include a driving line connected to the first touch electrode 212 and a second touch electrode 214 connected to the first touch electrode 212 and the second touch electrode 212. In addition to the first and second touch electrodes 212 and 214, A sensing line and a touch pad (not shown) are formed. The touch pad (not shown) is electrically connected to a plurality of transmission lines (not shown) or reception lines (not shown), and is connected to a display pad (not shown) through a connection means (not shown), for example an anisotropic conductive film. (Not shown).

A first buffer layer 332 covering the first and second touch electrodes 112 and 124 is formed on the touch panel TP. A first buffer layer 332 may be composed of an inorganic insulating material such as silicon oxide (SiO ₂₎ or silicon nitride (SiNx). The first buffer layer 332 is interposed between the touch panel TP and the planarization layer 310 and is disposed between the first and second touch electrodes 112 and 114 and the porous copper particles dispersed in the planarization layer 310 Prevents electrical shorts.

A planarization layer 310 in which porous copper particles are dispersed in a binder resin is disposed on the upper surface of the first buffer layer 332. For example, porous copper particles are mesoporous porous copper particles. A second buffer layer 334 composed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is disposed on the planarization layer 310, and the porous copper particles dispersed in the planarization layer 330 And the gate electrode 232, and between the wiring and the wiring.

The array panel AP is located above the touch panel TP and includes a driving thin film transistor Tr for controlling the operation of the light emitting diode E, a switching thin film transistor (not shown), a gate wiring (not shown) Wiring (not shown), and power supply wiring (not shown).

Although not shown, the data wiring extends along the second direction and intersects with the gate wiring to define the pixel region P, and the power supply wiring for supplying the high potential voltage is located apart from the data wiring. The switching thin film transistor is connected to the gate wiring and the data wiring. The driving thin film transistor Tr is connected to the switching thin film transistor and the power supply wiring, and the voltage of the power supply wiring is applied to the light emitting diode E by the operation of the switching thin film transistor.

Each of the switching thin film transistor and the driving thin film transistor Tr may include a gate electrode 232, a gate insulating film 236, a semiconductor layer 240, a source electrode 252, and a drain electrode 254. For example, the gate electrode 232 is formed on the second buffer layer 334 formed on the planarization layer 310. A gate insulating layer 236 covers the gate electrode 232 and the semiconductor layer 240 can overlap the gate electrode 232 on the gate insulating layer 236. The source electrode 252 and the drain electrode 254 are spaced apart from each other on the semiconductor layer 240.

For example, the gate line, the gate electrode 232, the data line, the source electrode 252, and the drain electrode 254 may be formed of a metal such as aluminum, aluminum alloy, copper, copper alloy, molybdenum , And chromium.

2, the semiconductor layer 240 of the driving thin film transistor Tr is formed of an oxide semiconductor layer. The structure in which the etch stopper 242 is formed for protecting the semiconductor layer 240 made of an oxide semiconductor material Respectively. However, it is apparent that the above-mentioned etch-stopper 242 can be omitted. It is not limited to the structure of the driving thin film transistor Tr shown in Fig. For example, instead of the semiconductor layer 240 made of an oxide semiconductor material, the semiconductor layer 240 may include a semiconductor layer composed of an active layer of pure amorphous silicon and an ohmic contact layer of impurity amorphous silicon. Further, a top gate type thin film transistor using a semiconductor layer made of polysilicon may be included.

A first passivation layer 260 covering the driving thin film transistor Tr is formed and a second passivation layer 262 covering the first passivation layer 260 and providing a flat top surface is formed. The passivation layers 260 and 262 include a drain contact hole 264 exposing the drain electrode 254 of the driving thin film transistor Tr.

The first passivation layer 260 is made of an inorganic insulating material such as silicon oxide or silicon nitride for improving the contact property with the semiconductor layer 240. The first passivation layer 260 made of an inorganic insulating material, It is possible to have a concavo-convex shape by the step of the lower component of Fig. When the light emitting diode (E) is formed on the first passivation layer 260, the characteristics of the organic light emitting layer 274 may be degraded. Thus, the second passivation layer 262 having a planar upper surface is formed on the first passivation layer 260 by an organic insulating material such as photo-acryl. However, it goes without saying that either the first protective layer 260 or the second protective layer 262 may be omitted.

On the second passivation layer 262, a light emitting diode E is formed corresponding to the pixel region P. The light emitting diode E includes a first electrode 272 electrically connected to the drain electrode 254 of the driving thin film transistor Tr and a second electrode 276 facing the first electrode 272, 1 and the second electrode 272, 276. The first electrode 272, Although the first electrode 272 is in contact with the drain electrode 254 of the driving TFT Tr through the drain contact hole 264, the first electrode 272 may be connected through a separate connection electrode .

Light is generated by the combination of electrons and holes injected by the first electrode 272 and the second electrode 276 in the organic light emitting layer 274. A bank 277 is located along the boundary of the pixel region P at the edge of the first electrode 272 and the first electrode 272 and the organic light emitting layer 274 are connected to the bank 277. [ The pixel regions P are formed separately. Meanwhile, the second electrode 276 is formed corresponding to the entire substrate 201.

At this time, the first electrode 272 is made of a material having a relatively high work function value as an anode, and may be made of a transparent conductive material such as ITO or IZO. The second electrode 276 may be made of a material having a relatively low work function value as a cathode. In one exemplary embodiment, the light emitted from the organic light emitting layer 274 may be a bottom emission scheme that is displayed externally through the first electrode 272 and the substrate 201. At this time, the second electrode 276 may be made of a reflective metal material such as silver (Ag), aluminum (Al), or aluminum-magnesium alloy (AlMg)

In addition, although not shown, a polarizer may be disposed on the second substrate facing the substrate 201, and a cover window may be disposed on the polarizer (not shown) through an optical clear adhesive (OCA) have.

The display device 200 according to the second embodiment of the present invention is provided with the planarization layer 310 having the porous copper particles dispersed in the high heat-resistant binder resin between the array panel AP and the touch panel TP. Therefore, the planarization layer 310 is not deteriorated even by the high-temperature process of 350 DEG C or more for fabricating the thin film transistor Tr constituting the array panel AP. The planarization layer 310 is firmly adhered to the touch panel TP and the array panel AP even after the array panel AP is finally manufactured so that the touch panel TP and the array panel AP) can be firmly maintained.

In addition, since the planarization layer 310 according to the present invention can maintain its characteristics even by a high-temperature process, cracking and / or peeling due to a high-temperature process does not occur. Since the light-transmittance is not lowered even by the high-temperature process, good luminance can be obtained, and since the porous copper particles having the pore structure are dispersed, the low-permittivity can be ensured and the driving voltage can be lowered. In addition, since the pore structure can rapidly attenuate and remove the static electricity that may be caused in the operation of the device, it is advantageous in that defective operation of the device due to static electricity or decrease in yield can be prevented.

Hereinafter, the present invention will be described in more detail with reference to exemplary embodiments. However, the present invention is not limited to the technical idea described in the following embodiments.

Synthetic Example: Mesoporous Copper Particle Synthesis

This example synthesized mesoporous copper particles employing the MCM-41 structure. In order to synthesize mesoporous silicate (Si-MCM-41), sodium methasilicate was used as a silica-introducing material and cetyltrimethylammonium bromide (CTAB) was used as a surfactant. The size of the pores can be controlled by treating the synthesized MCM-41 with tetraethyl orthosilicate, and the structural properties and physical properties can be controlled by treating Si-MCM-41, which is not baked with a copper precursor . The organic material including the surfactant was removed by baking at a temperature of 500 ° C or higher to synthesize mesoporous silicate. Mesoporous copper particles were synthesized by adding a copper oxide precursor to the Si-MCM-41 thus prepared, and impregnating the copper oxide precursor into the pore openings.

Analysis of synthesized mesoporous copper particles was performed. In the XRD analysis of FIG. 6A, the mesoporous crystallinity was measured in the range of 2 to 3? To confirm the hexagonal structure. The results of the FTIR spectroscopic analysis of FIG. 6 (b) show that the IR peaks exist at 1093 cm ^-1 wavelength and 988 cm ^-1 depending on the type of copper ion. On the other hand, it can be seen from the BET analysis result of FIG. 6C that the synthesized material is a mesoporous material. The results of the analysis of the porous particles using N ₂ adsorption and desorption related to the BET analysis and the Barrett-Joyner-Halenda (BJH) analysis are also shown in Table 1 below.

Table 1: BET analysis results for mesoporous copper particles

In the NMR analysis of FIG. 6 (d), the peaks of the copper atoms were 53 ppm and 0 ppm. As can be seen from the micrographs of FIGS. 6E and 6F, it was confirmed that a hexagonal mesoporous material was synthesized.

Example 1: Planarizing insulating film fabrication

A planarization insulating film in which the porous copper particles obtained in the synthesis example were dispersed was prepared and applied to a bare glass. To prepare the polysiloxane-based binder resin, 5 to 40 parts by weight of a reactive component containing TEOS and silsesquioxane, 40 to 100 parts by weight of a solvent containing PGME (propylene glycol methyl ether) and NMP (N-methylpyrrolidone) 0.5 to 10 parts by weight of the mesoporous copper particles obtained in Synthesis Examples, 0.5 to 5 parts by weight of POSS as a crosslinking accelerator, and 0.5 to 5 parts by weight of a surfactant as an additive were coated on a bare glass. Baked at 110 캜 for 120 seconds, and further post-baked at 350 캜 for 30 minutes to form a planarization insulating film made of a polysiloxane binder in which mesoporous copper particles were dispersed in a bare glass to a thickness of 2.0 nm.

Comparative Example 1: Flattening insulating film fabrication of acrylate resin (Over-coat)

A planarizing insulating film was prepared by forming an over-coat layer obtained by UV curing using an acrylate-based monomer in a bare glass.

Comparative Example 2: Planarizing insulating film fabrication of polysiloxane-based binder resin without porous particles

The procedure of Example 1 was repeated except that the synthesized porous particles were not used in the synthesis example to form a planarization insulating film in a bare glass.

Comparative Example 3: Planarizing insulating film production of polysiloxane-based binder resin in which porous aluminum (Al) particles were dispersed

The procedure of Example 1 was repeated except that the mesoporous aluminum particles were used instead of the mesoporous copper particles synthesized in the synthesis example to form a planarization insulating film in a bare glass.

Comparative Example 4: Planarizing insulating film production of polysiloxane-based binder resin in which porous chromium (Cr) particles were dispersed

The procedure of Example 1 was repeated except that the mesoporous chromium particles were used instead of the mesoporous porous copper particles synthesized in the synthesis example to form a planarization insulating film in a bare glass.

Example 2: Evaluation of adhesion of planarization insulating film

The adhesive strength to the planarization insulating films prepared in Example 1 and Comparative Example 1-4 was analyzed. The planarizing insulating film using mesoporous copper particles had no problem with the adhesion to the substrate (Fig. 7A), but all of the planarizing insulating films prepared in the comparative example had problems in adhesion (Figs. 7B to 7E). Therefore, the planarization insulating film of the present invention is excellent in the processability of the material, and the production yield can be improved, and the production time and the product cost can be reduced.

Example 3: Evaluation of crack property of planarization insulating film

The cracking characteristics of the planarizing insulating film in the form of the insulating film prepared in Example 1 and Comparative Example 1-4 were analyzed. The planarizing insulating film using mesoporous copper particles did not crack (Fig. 8A), but all the planarizing insulating films produced in the comparative example were cracked (Figs. 8B to 8E). As in Example 2, the planarizing insulating film of the present invention was evaluated to be excellent in material processability and superior in production yield and the like.

Example 4 Measurement of Peel Strength of Planarizing Insulating Film

The peel strengths of the planarization insulating films prepared in Example 1 and Comparative Example 1-4 were measured. The measurement mode was a constant - load mode, the horizontal velocity was 1,000 ㎚ / sec, the vertical velocity was 5 ㎚ / sec, the vertical load was 0.2 N, and the blade was a diamond cutter 0.3 ㎜. The measurement results are shown in Figs. 9A to 9E, and are also shown in Table 2 below. It can be seen that the planarizing insulating film manufactured according to the present invention has a low sensitivity to heat stress and thus has a very high peel strength.

Table 2: Peel strength of planarization insulating film

Example 5: Measurement of transmittance of a planarization insulating film

The planarization insulating films prepared in Example 1 and Comparative Example 1-4 were allowed to stand at a high temperature for a long period of time, and the transmittance was measured. The measurement results are shown in Tables 3 to 7 below.

As can be seen from these results, the planarization insulating film in which the mesoporous copper particles are dispersed according to the present invention can minimize the reaction of the non-reactant remaining in the thin film with heat, while easily discharging the heat without being trapped in the thin film. (350 ° C), and the permeation change rate was 1.3%. From the viewpoint of smearing, the rate of change in transmittance according to the high temperature (350 ° C) process is changed by about 3.0%. In the case of the planarized insulating film of the comparative example, It shows the lack of heat resistance.

Table 3: Transmittance of planarization insulating film in which mesoporous copper particles are dispersed

Table 4: Transmittance of the acrylate binder planarization insulating film

Table 5: Transmittance of planarization insulating film without mesoporous particles

Table 6: Transmittance of planarizing film in which mesoporous aluminum particles are dispersed

Table 7: Transmittance of planarization insulating film in which mesoporous chromium particles are dispersed

Example 6: Measurement of dielectric constant

The dielectric constant of the planarization insulating film prepared in each of Example 1 and Comparative Example 1-4 was measured. The insulating film prepared in Example 1 and Comparative Example 1-4 was coated on the lower electrode of the dot pattern, and an upper electrode (Al square pattern) was deposited on the dot pattern. The tip contact portion insulator for the lower electrode measurement was removed, and the permittivity between the upper and lower electrodes was measured (based on 100 kHz). Each dielectric film sample was fabricated and measured by time difference. At least 5 points were measured at each measurement. Table 8 shows the standard deviation of the dielectric constant according to the measured value average and thickness.

In the case of the planarization insulating film made of the binder resin in which the mesoporous copper particles were dispersed according to the present invention, the bulkiness characteristic was secured by the influence of the pore size in the particle, and the packing density was lowered and the dielectric constant was relatively low at 3.02. Therefore, it is estimated that the parasitic current is not generated and the driving voltage can be lowered.

Table 8: Permittivity of planarization insulating film

Example 7: Measurement of electrostatic damping effect of a planarization insulating film

The degree of static attenuation of the planarization insulating films prepared in Example 1 and Comparative Example 1-4 was measured. When static electricity is generated in the conductive film after the voltage is applied, the voltage is increased and a saturation voltage is generated. The time required for attenuation of the saturated voltage to 1/2 level is measured. The decay time (50%) is measured from 70 ms to 23 hrs (0.001 second display is possible) (STATIC HONESTMETER, model: H-0110). The measurement results are shown in Table 9.

According to the present invention, the electrostatic decay time of the insulating film in which the mesoporous copper particles are dispersed was rapidly discharged within 1 sec. However, the static decay time of the insulating film prepared in the comparative example was more than 5 sec, and the electrostatic discharge was delayed. That is, the planarization insulating film of the comparative example is vulnerable to static electricity, and it is evaluated that when the static electricity occurs, there arises a problem in the driving of the panel, which may affect the yield.

Table 9: Electrostatic decay time of the planarization insulating film

Example 8: Evaluation of crack property of bottom metal-based planarizing film production

Cu was deposited as a metal electrode on the glass substrate to a thickness of 5000, and silicon nitride was deposited thereon as a first buffer layer to a thickness of 1000 nm. The planarization insulating film prepared in each of Example 1 and Comparative Example 1-4 was coated on the first buffer layer to a thickness of 2-4 mu m and then silicon nitride was further deposited to a thickness of 1000 nm on the planarization insulating film as a second buffer layer . The upper portion of the second buffer layer was left at a high temperature of 350 DEG C or higher, and cracking or buckling between the planarization insulating film and the buffer layer was evaluated according to whether the thermal expansion coefficient was adjusted or not. According to the present invention, the planarization insulating film on which the mesoporous copper particles were injected did not crack or lift off (FIG. 10A), but cracks occurred in the planarization insulating film produced in the comparative example (FIGS. 10B to 10E). That is, the insulating film produced according to the present invention has an excellent thermal expansion coefficient, which is good in thermal stress matching that relaxes lifting and cracking between the upper and lower layers in a high-temperature process.

Although the present invention has been described based on the exemplary embodiments and examples of the present invention, the present invention is not limited to the technical ideas described in the above embodiments and examples. On the contrary, those skilled in the art will appreciate that various modifications and changes may be made without departing from the scope of the present invention. It will be apparent, however, that such modifications and variations are all within the scope of the present invention.

100, 200: display device 101, 201: first substrate
102, 202: second substrate 300: planarization film
310: planarization layer 312: binder resin
320: porous copper particles 332, 334: buffer layer
AP: Array panel DP: Display panel
TP: touch panel Tr: thin film transistor
E: organic light emitting diode P: display area

Claims (12)

A touch panel positioned on the substrate;
A thin film transistor positioned apart from the touch panel;
And a planarization layer interposed between the touch panel and the thin film transistor,
Wherein the planarization layer comprises porous copper particles dispersed in a binder resin.
The method according to claim 1,
A first buffer layer positioned between the touch panel and the planarization layer, and a second buffer layer positioned between the planarization layer and the thin film transistor.
The method according to claim 1,
Wherein the porous copper particles comprise mesoporous copper particles.
The method according to claim 1,
Wherein the binder resin is selected from the group consisting of a polysiloxane-based resin, a polyimide-based resin, and a combination thereof.
The method according to claim 1,
Wherein the porous copper particles are dispersed in the binder resin in a proportion of 0.5 to 10 parts by weight to the binder resin.
The method according to claim 1,
Wherein the porous copper particles are impregnated with porous silicate particles.
A first substrate;
A touch panel positioned on the first substrate;
A display panel spaced apart from the touch panel;
And a planarization layer interposed between the touch panel and the display panel,
Wherein the planarizing layer comprises porous copper particles dispersed in a binder resin.
8. The method of claim 7,
A first buffer layer positioned between the touch panel and the planarization layer, and a second buffer layer positioned between the planarization layer and the display panel.
8. The method of claim 7,
Wherein the porous copper particles comprise mesoporous copper particles.
8. The method of claim 7,
Wherein the binder resin is selected from the group consisting of a polysiloxane resin, a polyimide resin, and a combination thereof.
8. The method of claim 7,
Wherein the porous copper particles are dispersed in the binder resin in a proportion of 0.5 to 10 parts by weight to the binder resin.
8. The method of claim 7,
Wherein the porous copper particles are impregnated with porous silicate particles.

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