KR20170041312A - Liquid crystal display device - Google Patents

Abstract

The present invention provides a DRD type liquid crystal display device capable of preventing deterioration of display quality. The liquid crystal display device includes: a pair of n^th (where n is an integer of 1 or more) gate lines arranged between first and second subpixels arranged in first row and third and fourth subpixels arranged in second row; an (n+1)^th gate line arranged between the pair of the n-^h gate lines; and first and second data lines crossing the n^th and (n+1)^th gate lines and each disposed at a left side of the first and third subpixels arranged in first row and at a right side of the second and fourth subpixels arranged in second row. Second and fourth thin film transistors are connected to the n^th gate line, and first and third thin film transistors are connected to the (n+1)^th gate line. The first and second thin film transistors are connected to a first data line and the third and fourth thin film transistors are connected to a second data line, or the first and second thin film transistors are connected to the second data line and the third and fourth thin film transistors are connected to the first data line.

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a DRD type liquid crystal display device capable of preventing deterioration of display quality and reducing power consumption.

The liquid crystal display device includes a liquid crystal display panel in which an image is displayed. In order to prevent deterioration of the liquid crystal when driving the liquid crystal display panel and to improve the display quality of an image, an inversion driving method Is generally used.

The inversion driving method is classified into a frame inversion method, a column inversion method, and a dot inversion method according to a unit in which the polarity is inverted.

The liquid crystal display includes a gate driver for driving gate wirings and a data driver for driving data lines. As the liquid crystal display becomes larger and higher in resolution, the number of data driver ICs included in the data driver increases.

However, since data driving ICs are relatively more expensive than other devices, various methods for reducing the number of data driving ICs have been researched and developed. In one of them, the number of gate wirings is doubled, A DRD (Double Rate Driving) method which realizes the same resolution as the conventional one while reducing the number of required data driving ICs by half is proposed.

FIG. 1 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a column-inversion method, and FIG. 2 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a 4-dot version.

As shown in FIGS. 1 and 2, a conventional DRD type liquid crystal display device includes first to 32.sup.th sub-pixels SP1 to T32 each including first to 32th thin film transistors T1 to T32 and arranged in 4 rows and 8 columns, To SP32, first to eighth gate lines GL1 to GL8, and first to fifth data lines DL1 to DL5.

The first to 32nd sub-pixels SP1 to SP32 display any one of red (R), green (G), blue (B) and white (W) Four subpixels representing green (G), blue (B) and white (W) are gathered to form one unit pixel.

Meanwhile, although the first to 32nd subpixels (SP1 to SP32) are shown as being arranged in 4 rows and 8 columns, a larger number of subpixels may be arranged in a plurality of rows and columns.

The first and second gate lines GL1 and GL2 are arranged on the upper side and the lower side of the subpixels SP1 to SP8 arranged in one row and the third and fourth gate lines GL3 and GL4 The fifth and sixth gate lines GL5 and GL6 are arranged on the upper side and the lower side of the subpixels SP9 to SP16 arranged in the second row and the fifth and sixth gate lines GL5 and GL6 are arranged on the upper side of the subpixels SP17 to SP24 arranged in three rows, And the seventh and eighth gate lines GL7 and GL8 are respectively disposed on the upper and lower sides of the subpixels SP25 to SP32 arranged in four rows.

The first to fifth data lines DL1 to DL5 intersect with the first to eighth gate lines GL1 to GL8. The first data line DL1 includes subpixels SP1 and SP9 SP17 and SP25 and the second data line DL2 is arranged on the left side of the subpixels SP2, SP10, SP18 and SP26 arranged in two columns and the subpixels SP3, SP11, SP19, The third data line DL3 is disposed between the subpixels SP5, SP13, SP21 and SP29 arranged in the fifth column, and the subpixels SP5, SP13, SP21 and SP29 arranged in the fifth column, The fourth data line DL4 is arranged between the subpixels SP6, SP14, SP22 and SP30 arranged in the sixth column and the subpixels SP7, SP15, SP23 and SP31 arranged in the seventh column, The fifth data line DL5 is arranged on the right side of the subpixels SP8, SP16, SP24 and SP32 arranged in the eight columns.

The first gate wiring GL1 is connected to the first, third, fifth and seventh thin film transistors T1, T3, T5 and T7 and the second gate wiring GL2 is connected to the second, T11, T13, and T15 are connected to the first, sixth, and eighth thin film transistors T2, T4, T6, and T8, and the third gate wiring GL3 is connected to the ninth, The fourth gate wiring GL4 is connected to the tenth, twelfth, fourteenth and sixteenth thin film transistors T10, T12, T14 and T16, the fifth gate wiring GL5 is connected to the seventeenth, Twenty-second, twenty-second, and twenty-third thin film transistors T18, T20, T22, and T23, and the sixth gate wiring GL6 is connected to the seventeenth, twentieth, twenty- The seventh gate line GL7 is connected to the 25th, 27th, 29th and 31st thin film transistors T25, T27, T29 and T31, the eighth gate line GL8 is connected to the 26th, , 28th, 30th and 32th thin film transistors (T26, T28, T30, T32).

The first data line DL1 is connected to the first, ninth, seventeenth and twenty-fifth TFTs T1, T9, T17 and T25 and the second data line DL2 is connected to the second, third, T3, T10, T11, T18, T19, T26, and T27, and the third data line DL3 is connected to the fourth, sixth, seventh, T4, T5, T12, T13, T20, T21, T28, and T29, and the fourth data line DL4 Is connected to the sixth, seventh, fourteenth, fifteenth, twenty second, thirtieth, thirtieth and thirty th thin film transistors T6, T7, T14, T15, T22, T23, T30, T31, The data line DL5 is connected to the eighth, 16th, 24th and 32th thin film transistors T8, T16, T24 and T32.

When a conventional DRD type liquid crystal display device is driven by a column-version method, odd-numbered data lines and even-numbered data lines supply data voltages of different polarities for one frame.

For example, as shown in FIG. 1, the first, third and fifth data lines DL1, DL3 and DL5 supply a positive data voltage and the second, fourth and sixth The data lines DL2, DL4, and DL6 can supply a negative data voltage for one frame.

(SP1, SP9, SP17, SP25), (SP4, SP12, SP20, SP28), (SP5, SP13, SP21, SP29) (SP2, SP10, SP18, SP26) arranged in the second column, the third column, the sixth column and the seventh column are supplied with data voltages of positive polarity, (-) data voltages are supplied to the data lines (SP3, SP11, SP19, SP27), (SP6, SP14, SP22, SP30), (SP7, SP15, SP23, SP31) And the display quality is deteriorated.

In order to prevent the flicker phenomenon between the vertical lines, as shown in FIG. 2, the conventional DRD type liquid crystal display device is driven by the version with the 4-dot version.

In this way, when driven by the 4-dot inversion method, the polarity of the data voltage supplied from each data line is inverted every four horizontal periods.

For example, as shown in Fig. 2, the first data line DL1 is connected to the negative (-) data line during the four horizontal periods in which the gate signal is supplied through the third to sixth gate lines GL3 to GL6 And supplies a positive (+) data voltage whose polarity is inverted during the next four horizontal periods after supplying the voltage.

The second data line DL2 supplies a positive data voltage during four horizontal periods in which the gate signal is supplied through the fourth to seventh gate lines GL4 to GL7, (-) data voltage whose polarity is inverted for a predetermined period of time.

Likewise, the third to fifth data lines DL3 to DL5 supply a data voltage whose polarity is inverted every four horizontal periods.

As described above, the conventional DRD type liquid crystal display device is driven by a version method with four dots, thereby minimizing the flicker between the vertical lines, thereby preventing display quality deterioration.

However, the 4-dot-inversion method has a problem in that power consumption is increased and reliability is lowered due to heat generation of the data-driving IC because the polarity must be inverted every four horizontal periods unlike the column-inversion method.

In particular, since the number of data driving ICs increases as the size and resolution of the liquid crystal display device increases, such a problem becomes even more serious.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of reducing power consumption and preventing deterioration of display quality.

According to an aspect of the present invention, there is provided a liquid crystal display device including first to fourth sub-pixels each including first to fourth thin film transistors and arranged in two rows and two columns in a display region and first to fourth sub- And a pair of nth (n is an integer of 1 or more) gate wiring arranged between the second subpixel and the third and fourth subpixels arranged in the second row, and a pair of n- (n + 1) -th gate wiring, the first and third subpixels arranged in one column and the second and fourth subpixels arranged in two columns intersect with the (n + 1) The first and third thin film transistors are connected to the (n + 1) -th gate wiring, the first and third thin film transistors are connected to the (n + 1) -th gate wiring, The first and second thin film transistors are connected to the first data line and the third and fourth thin film transistors are connected to the second data line First and second thin film transistor is connected to the second data line, the third and the fourth thin film transistor is a liquid crystal display device that is connected to the first data line.

Further, among the pair of n-th gate wirings, the n-th gate wiring arranged on the (n + 1) -th gate wiring is connected to the second thin film transistor, and the n-th gate wiring arranged on the The gate wiring is connected to the fourth thin film transistor.

The n-th gate wiring connected to the second thin film transistor surrounds the gate electrode of the first thin film transistor, and the n-th gate wiring connected to the fourth thin film transistor surrounds the gate electrode of the third thin film transistor.

The n-th gate wiring connected to the second thin film transistor is overlapped with the active layer of the first thin film transistor, and the n-th gate wiring connected to the fourth thin film transistor is overlapped with the active layer of the third thin film transistor.

The present invention has the effect of minimizing the flicker phenomenon and preventing display quality degradation.

Further, power consumption can be reduced by driving in a column-version manner, and reliability can be prevented from deteriorating due to heat generation of the data driving IC.

1 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a column inversion method.
FIG. 2 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a 4-dot version system.
3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.
FIGS. 4 and 5 are plan views illustrating first to fourth sub-pixels of the DRD type liquid crystal display device according to the exemplary embodiment of the present invention, and a data line and a gate line connected to the first to fourth sub-pixels.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.

As shown in the drawing, a DRD type liquid crystal display device according to an embodiment of the present invention includes first through 32 th sub-pixels (first through 32 th TFTs) each including first through 32 th thin film transistors T 1 through T 32, SP1 to SP32, first to tenth gate lines GL1 to GL10, and first to fifth data lines DL1 to DL5.

The first to 32nd sub-pixels SP1 to SP32 display any one of red (R), green (G), blue (B) and white (W) Four subpixels representing green (G), blue (B) and white (W) are gathered to form one unit pixel.

Meanwhile, although the first to 32nd subpixels (SP1 to SP32) are shown as being arranged in 4 rows and 8 columns, a larger number of subpixels may be arranged in a plurality of rows and columns.

The first gate line GL1 is disposed on the upper side of the subpixels SP1, SP2, SP9, SP10, SP17, SP18, SP25, and SP26 arranged in one row, Two gate wirings GL2 are arranged.

(SP1, SP2, SP9, SP10, SP17, SP18, SP25 and SP26), (SP3, SP4, SP11, SP12, SP19, SP20, SP27 and SP28) arranged in the first row and the second row, And a fourth gate wiring GL4 is disposed between the pair of third gate wiring GL3.

(SP3, SP4, SP11, SP12, SP19, SP20, SP27 and SP28), (SP5, SP6, SP13, SP14, SP21, SP22, SP29 and SP30) arranged in the second row and the third row, A fifth gate wiring GL5 is disposed between the pair of fifth gate wiring GL5 and a sixth gate wiring GL6 is disposed between the pair of fifth gate wiring GL5.

(SP5, SP6, SP13, SP14, SP21, SP22, SP29 and SP30), (SP7, SP8, SP15, SP16, SP23, SP24, SP31 and SP32) arranged in the third row and the fourth row, A seventh gate wiring GL7 is disposed between the pair of seventh gate wiring GL7 and an eighth gate wiring GL8 is disposed between the pair of seventh gate wiring GL7.

A ninth gate wiring GL9 is disposed below the subpixels SP7, SP8, SP15, SP16, SP23, SP24, SP31, and SP32 arranged in the fourth row. 10 gate wirings GL10 are arranged.

The first to fifth data lines DL1 to DL5 intersect with the first to tenth gate lines GL1 to GL10 while the first data line DL1 includes subpixels SP1 and SP3 SP5 and SP7 and the second data line DL2 is arranged on the left side of the subpixels SP9, SP11, SP13, SP13, The third data line DL3 is arranged between the subpixels SP10, SP12, SP14 and SP16 arranged in the fourth column and the subpixels SP17, SP19, SP21 and SP23 arranged in the fifth column, The fourth data line DL4 is arranged between the subpixels SP18, SP20, SP22 and SP24 arranged in the sixth column and the subpixels SP25, SP27, SP29 and SP31 arranged in the seventh column, The fifth data line DL5 is arranged on the right side of the subpixels SP26, SP28, SP30 and SP32 arranged in the eight columns.

The first gate line GL1 is connected to the ninth and twenty fifth TFTs T9 and T25 and the second gate line GL2 is connected to the tenth and twenty sixth TFTs T10 and T26.

The third gate wiring GL3 disposed on the fourth gate wiring GL4 of the pair of third gate wiring GL3 is connected to the first and seventeenth thin film transistors T1 and T17, The third gate wiring GL3 disposed under the gate wiring GL4 is connected to the third and the nineteenth thin film transistors T3 and T19 and the fourth gate wiring GL4 is connected to the second, And connected to the twentieth thin film transistors T2, T4, T18, and T20.

The fifth gate wiring GL5 disposed on the sixth gate wiring GL6 of the pair of fifth gate wiring GL5 is connected to the eleventh and thirtieth thin film transistors T11 and T27, The fifth gate wiring GL5 disposed under the gate wiring GL6 is connected to the thirteenth and twenty-ninth thin film transistors T13 and T29, the sixth gate wiring GL6 is connected to the twelfth, fourteenth, And connected to the thirtieth thin film transistors T12, T14, T28, and T30.

The seventh gate wiring GL7 disposed on the eighth gate wiring GL8 of the pair of seventh gate wiring GL7 is connected to the fifth and twentieth thin film transistors T5 and T21, The seventh gate wiring GL7 disposed under the gate wiring GL8 is connected to the seventh and thirtieth thin film transistors T7 and T23 and the eighth gate wiring GL8 is connected to the sixth, And is connected to the twenty-fourth thin film transistors T6, T8, T22, and T24.

The ninth gate line GL9 is connected to the fifteenth and thirty-first thin film transistors T15 and T31 and the tenth gate line GL10 is connected to the sixteenth and thirty-second thin film transistors T16 and T32.

The first data line DL1 is connected to the first, second, seventh and eighth thin film transistors T1, T2, T7 and T8, the second data line DL2 is connected to the third, The third data line DL3 is connected to the thirteenth through sixteenth and the nineteenth through twenty-second thin film transistors T13 through T16 and T19 through T22, and the third data line DL3 is connected to the ninth through twelfth thin film transistors T3 through T6 and T9 through T12. The fourth data line DL4 is connected to the 17th, 18th, 23rd, 24th and 29th to 32th thin film transistors T17, T18, T23, T24, T29 to T32, The data line DL5 is connected to the 25th to 28th thin film transistors T25 to T28.

The DRD type liquid crystal display device according to the embodiment of the present invention is driven by a column inversion method in which odd data lines and even data lines are supplied with data voltages of different polarities for one frame.

For example, as shown in the figure, the first, third and fifth data lines DL1, DL3 and DL5 supply a data voltage of positive polarity and the second, fourth and sixth data The wirings DL2, DL4, and DL6 can supply the data voltage of negative polarity for one frame.

Hereinafter, the polarity arrangement of the data voltages applied to the respective sub-pixels of the DRD type liquid crystal display device according to the embodiment of the present invention will be described.

First, when the ninth and twenty-fifth thin film transistors T9 and T25 are turned on by the gate signal supplied from the first gate wiring GL1, a negative data voltage (-) is applied from the second data wiring DL2, Is supplied to the ninth subpixel SP9 and a positive data voltage is supplied to the twenty-fifth subpixel SP25 from the fifth data line DL5.

Next, when the tenth and the twentieth thin film transistors T10 and T26 are turned on by the gate signal supplied from the second gate wiring GL2, the data voltage of negative polarity (-) from the second data wiring DL2 Is supplied to the tenth subpixel SP10 and a positive data voltage is supplied to the twenty-sixth subpixel SP26 from the fifth data line DL5.

Next, when the first, third, seventeenth and nineteenth thin film transistors T1, T3, T17 and T19 are turned on by the gate signal supplied from the pair of third gate lines GL3, A data voltage of positive polarity is supplied to the first subpixel SP1 from the wiring DL1 and a data voltage of negative polarity is supplied from the second data line DL2 to the third subpixel SP3 A positive data voltage is supplied to the nineteenth subpixel SP19 from the third data line DL3 and a negative data voltage is supplied from the fourth data line DL4 to the seventeenth subpixel SP19, And supplied to the sub-pixel SP17.

Next, when the second, fourth, eighth and twentieth thin film transistors T2, T4, T18 and T20 are turned on by the gate signal supplied from the fourth gate wiring GL4, the first data line DL1 The data voltage of positive polarity is supplied to the second subpixel SP2 from the data line DL2 and the data voltage of negative polarity is supplied to the fourth subpixel SP4 from the second data line DL2, A positive data voltage is supplied to the 20th subpixel SP20 from the third data line DL3 and a data voltage of negative polarity is supplied from the fourth data line DL4 to the 18th subpixel SP20 SP18.

Next, when the 11th, 13th, 27th and 29th thin film transistors T11, T13, T27, and T29 are turned on by the gate signal supplied from the pair of fifth gate lines GL5, The data voltage of negative polarity is supplied from the wiring DL2 to the eleventh subpixel SP11 and the data voltage of positive polarity is supplied from the third data line DL3 to the thirteenth subpixel SP13 A negative data voltage is supplied to the 29th subpixel SP29 from the fourth data line DL4 and a positive data voltage is supplied from the fifth data line DL5 to the 27th subpixel SP29, And supplied to the sub-pixel SP27.

Next, when the twelfth, fourteenth, twenty eighth, and thirtieth thin film transistors T12, T14, T28, and T30 are turned on by the gate signal supplied from the sixth gate wiring GL6, the second data wiring DL2 The data voltage of negative polarity is supplied from the third data line DL3 to the twelfth subpixel SP12 and the data voltage of positive polarity is supplied from the third data line DL3 to the fourteenth subpixel SP14, A negative data voltage is supplied to the 30th subpixel SP30 from the fourth data line DL4 and a positive data voltage is supplied from the fifth data line DL5 to the 28th subpixel SP30 SP28.

Next, when the fifth, seventh, twenty first, and twentieth thin film transistors T5, T7, T21, and T23 are turned on by the gate signal supplied from the pair of seventh gate lines DL7, A data voltage of positive polarity is supplied to the seventh subpixel SP7 from the wiring DL1 and a data voltage of negative polarity is supplied from the second data line DL2 to the fifth subpixel SP5 (+) Data voltage is supplied to the twenty-first sub-pixel SP21 from the third data line DL3 and a negative (-) data voltage is supplied from the fourth data line DL4 to the twenty-first sub- And supplied to the sub-pixel SP23.

Next, when the sixth, eighth, twenty second, and twenty fourth TFTs T6, T8, T22 and T24 are turned on by the gate signal supplied from the eighth gate line GL8, the first data line DL1 A data voltage of positive polarity is supplied to the eighth subpixel SP8 from the data line DL2 and a data voltage of negative polarity is supplied to the sixth subpixel SP6 from the second data line DL2, The data voltage of positive polarity is supplied to the twenty-second subpixel SP22 from the third data line DL3 and the data voltage of negative polarity is supplied from the fourth data line DL4 to the twenty- SP24.

Next, when the fifteenth and thirty-first thin film transistors T15 and T31 are turned on by the gate signal supplied from the ninth gate wiring GL9, a positive data voltage (+) from the third data wiring DL3 Is supplied to the fifteenth subpixel SP15 and the data voltage of negative polarity from the fourth data line DL4 is supplied to the thirty-first subpixel SP31.

Finally, when the sixteenth and thirty-second thin film transistors T16 and T32 are turned on by the gate signal supplied from the tenth gate wiring GL10, data of positive polarity (+) from the third data wiring DL3 A voltage is supplied to the 16th subpixel SP16 and a data voltage of negative polarity from the fourth data line DL4 is supplied to the 32nd subpixel SP32.

As described above, in the DRD type liquid crystal display device according to the embodiment of the present invention, the polarity is inverted for every four subpixels in the horizontal direction and the polarity is inverted for each of the two subpixels in the vertical direction. Therefore, flicker between the vertical and horizontal lines It is possible to minimize display quality deterioration.

In addition, since the DRD type liquid crystal display device according to the embodiment of the present invention is driven by the column inversion method, it is possible to reduce the power consumption compared to the 4-dot inversion method and to lower the reliability due to the heat generation of the data driving IC .

FIGS. 4 and 5 are plan views illustrating first to fourth sub-pixels of the DRD type liquid crystal display device according to the exemplary embodiment of the present invention, and a data line and a gate line connected to the first to fourth sub-pixels.

4, a DRD type liquid crystal display device according to an embodiment of the present invention includes first to fourth sub-pixels SP1 to SP4 arranged in two rows and two columns, a pair of n- (n + 1) -th gate wiring GL (n + 1), and first and second data lines DL1 and DL2.

Specifically, the first to fourth sub-pixels SP1 to SP4 include first to fourth thin film transistors T1 to T4, respectively, and red (R), green (G), blue (B) W), respectively.

The first to fourth thin film transistors T1 to T4 may further include first to fourth pixel electrodes 101 to 104 respectively disposed in the first to fourth sub pixels SP1 to SP4, (D) are connected to the first to fourth pixel electrodes 101 to 104 through the drain contact hole DCH, respectively.

The pair of the n-th gate lines GLn are arranged between the first and second subpixels SP1 and SP2 arranged in one row and the third and fourth subpixels SP3 and SP4 arranged in two rows And the (n + 1) -th gate wiring GL (n + 1) is disposed between the pair of the n-th gate wiring GLn.

The n-th gate wiring GLn connected to the second thin film transistor T2 is overlapped with an active layer (not shown) between the source electrode S and the drain electrode D of the first thin film transistor T1 And the nth gate wiring GLn connected to the fourth thin film transistor T4 are overlapped with an active layer (not shown) between the source electrode S and the drain electrode D of the third thin film transistor T3.

The first and second data lines DL1 and DL2 intersect the nth and (n + 1) th gate lines GLn and GL (n + 1) The second data line DL2 is arranged on the right side of the second and fourth subpixels SP2 and SP4 arranged in two columns.

At this time, the n-th gate wiring GLn disposed above the (n + 1) -th gate wiring GL (n + 1) of the pair of the n-th gate wiring GLn is connected to the The n-th gate wiring GLn disposed below the (n + 1) -th gate wiring GL (n + 1) is connected to the gate electrode G of the fourth thin film transistor T4, And the (n + 1) -th gate wiring GL (n + 1) is connected to the gate electrode G of the first and third thin film transistors T1 and T3, respectively.

The first data line DL1 is connected to the source electrode S of the first and second thin film transistors T1 and T2 and the second data line DL2 is connected to the third thin film transistor T3 And T4, respectively.

The first and second data lines DL1 and DL2 supply data voltages of different polarities for one frame and the data voltages supplied by the first and second data lines DL1 and DL2 are inverted every frame do.

Assuming that the first data line DL1 supplies a positive data voltage and the second data line DL2 supplies a negative data voltage, When the second and fourth thin film transistors T2 and T4 are turned on by the gate signal supplied from the n gate wiring GLn, the positive data voltage from the first data line DL1 is applied to the second And the data voltage of negative polarity from the second data line DL2 is supplied to the fourth subpixel SP4.

Next, when the first and third thin film transistors T1 and T3 are turned on by the gate signal supplied from the (n + 1) th gate line GL (n + 1), the first data line DL1 is turned on, A data voltage of positive polarity is supplied to the first subpixel SP1 from the data line DL2 and a data voltage of negative polarity is supplied to the third subpixel SP3 from the second data line DL2.

Meanwhile, in the DRD type liquid crystal display device according to the embodiment of the present invention, the (n + 1) -th gate wiring GL (n + 1) is disposed between a pair of the n-th gate wiring GLn, .

If the nth gate wiring GLn is disposed between a pair of (n + 1) -th gate wirings GL (n + 1) unlike the present invention, the first thin film transistor T1 is connected to the n- The data voltage is supplied to the first subpixel SP1 in the first data line DL1 and the data voltage supplied to the first subpixel SP1 is turned on by the gate signal outputted from the wiring GLn (N + 1) -th gate line GL (n + 1) in which the data voltage is arranged between the first sub-pixel SP1 and the n-th gate wiring GLn in the data voltage holding period It can be influenced by the output gate signal.

That is, the image quality fluctuation of the first sub-pixel SP1 may occur due to the electric field generated by the gate signal output from the (n + 1) th gate line GL (n + 1).

Similarly, by the (n + 1) -th gate wiring GL (n + 1) arranged between the third subpixel SP3 and the nth gate wiring GLn, the image quality fluctuation phenomenon Can occur.

Here, when the (n + 1) -th gate wiring GL (n + 1) is disposed between the pair of the n-th gate wiring GLn as in the present invention, The first thin film transistor T1 is turned on by the gate signal output from the (n + 1) -th gate wiring GL (n + 1) to turn on the data voltage at the first data wiring DL1 The data voltage supplied to the first subpixel SP1 and the data voltage supplied to the first subpixel SP1 are maintained for one frame so that the data voltage is supplied to the first subpixel SP1 and the (n + The gate signal outputted from the n-th gate wiring GLn disposed between the (n + 1) -th gate wiring GL (n + 1).

Likewise, since the n-th gate wiring GLn is disposed between the third sub-pixel SP3 and the (n + 1) -th gate wiring GL (n + 1), the third sub- .

Further, in the DRD type liquid crystal display device according to the embodiment of the present invention, the gate signals supplied from the pair of the n-th gate lines GLn have the same timing.

To this end, a gate driver (not shown) outputs a gate signal having the same timing to each of the pair of n-th gate lines GLn, or a gate driver (not shown) And a pair of n-th gate lines GLn are connected to each other in the non-display region, thereby outputting a gate signal having the same timing to the remaining gate lines.

On the other hand, in order to minimize the decrease of the aperture ratio, the area where the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) are arranged must be minimized. That is, the interval between the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) must be minimized.

To this end, in a state where the interval between the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) is minimized, The gate wiring GLn is arranged to surround the gate electrode G of the first thin film transistor T1 and the nth gate wiring GLn connected to the fourth thin film transistor T4 is arranged in the form of a third thin film transistor T3 of the gate electrode G.

5, the DRD type liquid crystal display device according to the embodiment of the present invention includes fifth through eighth sub-pixels SP5 through SP8 arranged in two rows and two columns, (n + 1) -th gate wiring GL (n + 1), and first and second data lines DL1 and DL2.

Specifically, the fifth to eighth subpixels SP5 to SP8 include the fifth to eighth thin film transistors T5 to T8, respectively, and the red (R), green (G), blue (B) W), respectively.

The fifth to eighth thin film transistors T5 to T8 further include fifth to eighth pixel electrodes 105 to 108 respectively disposed in the fifth to eighth subpixels SP5 to SP8, (D) are connected to the fifth to eighth pixel electrodes 105 to 108 through the drain contact hole DCH, respectively.

The pair of nth gate wirings GLn are arranged between the fifth and sixth subpixels SP5 and SP6 arranged in one row and the seventh and eighth subpixels SP7 and SP8 arranged in two rows And the (n + 1) -th gate wiring GL (n + 1) is disposed between the pair of the n-th gate wiring GLn.

The nth gate wiring GLn connected to the sixth thin film transistor T6 is overlapped with an active layer (not shown) between the source electrode S and the drain electrode D of the fifth thin film transistor T5 And the nth gate wiring GLn connected to the eighth thin film transistor T8 are overlapped with an active layer (not shown) between the source electrode S and the drain electrode D of the seventh thin film transistor T7.

The first and second data lines DL1 and DL2 intersect the nth and (n + 1) th gate lines GLn and GL (n + 1) And the second data line DL2 are arranged on the right side of the sixth and eighth subpixels SP6 and SP8 arranged in two columns.

At this time, the n-th gate wiring GLn disposed above the (n + 1) -th gate wiring GL (n + 1) of the pair of the n-th gate wiring GLn is connected to the n- The n-th gate wiring GLn disposed below the (n + 1) -th gate wiring GL (n + 1) is connected to the gate electrode G of the eighth thin film transistor T8, And the (n + 1) -th gate wiring GL (n + 1) is connected to the gate electrode G of the fifth and seventh thin film transistors T5 and T7, respectively.

The first data line DL1 is connected to the source electrode S of the seventh and eighth thin film transistors T7 and T8 respectively and the second data line DL2 is connected to the fifth and sixth thin film transistors T5 And T6, respectively.

The first and second data lines DL1 and DL2 supply data voltages of different polarities for one frame and the data voltages supplied by the first and second data lines DL1 and DL2 are inverted every frame do.

Assuming that the first data line DL1 supplies a positive data voltage and the second data line DL2 supplies a negative data voltage, When the sixth and eighth thin film transistors T6 and T8 are turned on by the gate signal supplied from the n gate wiring GLn, the positive data voltage from the first data wiring DL1 is applied to the eighth And the data voltage of negative polarity from the second data line DL2 is supplied to the sixth subpixel SP6.

Next, when the fifth and seventh thin film transistors T5 and T7 are turned on by the gate signal supplied from the (n + 1) th gate line GL (n + 1), the first data line DL1 is turned on, The data voltage of positive polarity is supplied to the seventh subpixel SP7 and the data voltage of negative polarity is supplied to the fifth subpixel SP5 from the second data line DL2.

Meanwhile, in the DRD type liquid crystal display device according to the embodiment of the present invention, the (n + 1) -th gate wiring GL (n + 1) is disposed between a pair of the n-th gate wiring GLn, .

If the nth gate wiring GLn is disposed between a pair of (n + 1) -th gate wirings GL (n + 1) unlike the present invention, the fifth thin film transistor T5 is connected to the n- The data voltage is supplied to the fifth subpixel SP5 in the second data line DL2 and the data voltage supplied to the fifth subpixel SP5 is turned on by the gate signal outputted from the wiring GLn (N + 1) th gate line GL (n + 1) in which the data voltage is arranged between the fifth subpixel SP5 and the nth gate wiring GLn in the data voltage holding period It can be influenced by the output gate signal.

That is, the image quality of the fifth subpixel SP5 may occur due to the electric field generated by the gate signal output from the (n + 1) -th gate line GL (n + 1).

Similarly, by the (n + 1) -th gate wiring GL (n + 1) disposed between the seventh sub-pixel SP7 and the n-th gate wiring GLn, Can occur.

Here, when the (n + 1) -th gate wiring GL (n + 1) is disposed between the pair of the n-th gate wiring GLn as in the present invention, The fifth thin film transistor T5 is turned on by the gate signal output from the (n + 1) -th gate line GL (n + 1) to turn on the data voltage in the second data line DL2 The data voltage supplied to the fifth subpixel SP5 and the data voltage supplied to the fifth subpixel SP5 are maintained for one frame so that the data voltage is supplied to the fifth subpixel SP5 and the (n + The gate signal outputted from the n-th gate wiring GLn disposed between the (n + 1) -th gate wiring GL (n + 1).

Similarly, since the n-th gate wiring GLn is disposed between the seventh sub-pixel SP7 and the (n + 1) -th gate wiring GL (n + 1), the seventh sub- .

Further, in the DRD type liquid crystal display device according to the embodiment of the present invention, the gate signals supplied from the pair of the n-th gate lines GLn have the same timing.

To this end, a gate driver (not shown) outputs a gate signal having the same timing to each of the pair of n-th gate lines GLn, or a gate driver (not shown) And a pair of n-th gate lines GLn are connected to each other in the non-display region, thereby outputting a gate signal having the same timing to the remaining gate lines.

On the other hand, in order to minimize the decrease of the aperture ratio, the area where the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) are arranged must be minimized. That is, the interval between the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) must be minimized.

To this end, in a state in which the interval between the pair of the n-th gate wiring GLn and the (n + 1) -th gate wiring GL (n + 1) The gate wiring GLn is arranged to surround the gate electrode G of the fifth thin film transistor T5 and the nth gate wiring GLn connected to the eighth thin film transistor T8 is arranged in the form of a seventh thin film transistor T7 of the gate electrode G.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

GL1 to GL10: gate lines DL1 to DL5: data lines
SP1 to SP32: Subpixels T1 to T32: Thin film transistors

Claims (9)

First to fourth sub-pixels each including first to fourth thin film transistors and arranged in two rows and two columns in a display region;
(N is an integer of 1 or more) gate wiring arranged between the first and second sub-pixels arranged in one row and the third and fourth sub-pixels arranged in two rows, and the pair An (n + 1) -th gate wiring arranged between the n-th gate wiring of the n-th gate wiring; And
(N + 1) -th gate lines, arranged in the first and third subpixels on the left and the second columns arranged in one column, and first and second subpixels arranged on the right side of the second and fourth subpixels, respectively, And a second data line,
The second and fourth thin film transistors are connected to the nth gate wiring, the first and third thin film transistors are connected to the (n + 1) -th gate wiring,
Wherein the first and second thin film transistors are connected to a first data line and the third and fourth thin film transistors are connected to a second data line,
Wherein the first and second thin film transistors are connected to a second data line and the third and fourth thin film transistors are connected to a first data line.
The method according to claim 1,
The n-th gate wiring disposed on the (n + 1) -th gate wiring is connected to the second thin film transistor, and the n-th gate wiring disposed on the (n + And the nth gate wiring is connected to the fourth thin film transistor.
3. The method of claim 2,
Wherein the nth gate wiring connected to the second thin film transistor surrounds the gate electrode of the first thin film transistor and the nth gate wiring connected to the fourth thin film transistor is connected to the gate electrode of the third thin film transistor The liquid crystal display device comprising:
The method of claim 3,
Wherein the nth gate wiring connected to the second thin film transistor overlaps with the active layer of the first thin film transistor and the nth gate wiring connected to the fourth thin film transistor overlaps with the active layer of the third thin film transistor .
5. The method of claim 4,
And the pair of n-th gate wirings are connected to each other in a non-display region.
6. The method of claim 5,
Further comprising first to fourth pixel electrodes arranged in the first to fourth sub-pixels, respectively,
And the drain electrodes of the first to fourth thin film transistors are connected to the first to fourth pixel electrodes through drain contact holes, respectively.
The method according to claim 1,
Wherein the first and second data lines supply data voltages having different polarities for one frame, respectively.
8. The method of claim 7,
Wherein a polarity of a data voltage supplied to each of the first and second data lines is inverted every frame.
9. The method of claim 8,
And the first to fourth sub-pixels display red, green, blue, and white, respectively.

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