KR102439569B1 - Liquid crystal display device - Google Patents

Abstract

The present invention provides a first data extension line extending from a first data line to a first subpixel direction along a second gate line in order to prevent display quality from being deteriorated due to different parasitic capacitances of adjacent subpixels; a second data extension line extending from the second data line to the second sub-pixel direction along the first gate line, and a first thin film transistor in which a gate electrode and a source electrode are respectively connected to the first gate line and the second data extension line and a second thin film transistor in which the gate electrode and the source electrode are respectively connected to the second gate line and the first data extension line, and the drain electrodes of the first and second thin film transistors are respectively connected to the first and second pixel electrodes. Provided is a liquid crystal display connected to or connected to second and first pixel electrodes, respectively.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device, and to a liquid crystal display device capable of preventing display quality from being deteriorated due to different parasitic capacitances of adjacent subpixels.

Recently, with the rapid progress of semiconductor technology, the demand for a flat panel type display device as an electronic display device suitable for a new environment is rapidly increasing in accordance with the trend of miniaturization, thinness, and weight reduction of electronic devices along with low voltage and low power of various electronic devices. is increasing Accordingly, flat panel display devices such as liquid crystal display (LCD), plasma display (PDP), organic EL display (OELD), etc. are being developed, and among these flat panel display devices, it is easy to reduce the size, weight and thickness. , a liquid crystal display device having a low power consumption and a low driving voltage is particularly attracting attention.

In the liquid crystal display device, a liquid crystal material having anisotropic dielectric constant is injected between an upper transparent insulating substrate on which a common electrode, a color filter, a black matrix, etc. are formed and a lower transparent insulating substrate on which a switching element, a pixel electrode, etc. are formed. By applying different potentials to the electrode and the common electrode, the strength of the electric field formed in the liquid crystal material is adjusted to change the molecular arrangement of the liquid crystal material, and through this, the desired image is expressed by controlling the amount of light transmitted through the transparent insulating substrate. display device. As such a liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) element as a switching element is mainly used.

The liquid crystal display device includes a liquid crystal display panel on which an image is displayed. When the liquid crystal display panel is driven, the liquid crystal display panel is driven by inverting the polarity in a certain unit to prevent deterioration of the internal liquid crystal and to improve the display quality of the image. The version driving method is usually used.

The inversion driving method is classified into a frame inversion method, a line inversion method, and a dot inversion method according to a unit in which the polarity is inverted.

The liquid crystal display includes a gate driver for driving gate lines and a data driver for driving data lines, and as liquid crystal displays increase in size and high resolution, the number of ICs constituting the required driver increases.

However, since the IC of the data driver is relatively expensive compared to other devices, various methods are being researched and developed to reduce the number of ICs in order to lower the production cost of liquid crystal display devices. DRD (Double Rate Driving) method has been proposed, which reduces the number of required ICs in half by halving the number of data lines instead of doubling it, while realizing the same resolution as before.

1 is a view showing a conventional DRD type liquid crystal display device.

As shown in the drawing, the conventional DRD type liquid crystal display device includes first to eighteenth sub-pixels SP1 to SP18 arranged in three rows and six columns, first to sixth gate wirings GL1 to GL6; 1 to 4 data lines DL1 to DL4 and first to 18th thin film transistors T1 to T18 are included.

In addition, the first to eighteenth sub-pixels SP1 to SP18 display any one of red (R), green (G), and blue (B), and adjacent to each other red (R), green (G) and Three sub-pixels displaying blue (B) form one unit pixel.

Meanwhile, although the first to eighteenth sub-pixels SP1 to SP18 are illustrated as being arranged in three rows and six columns in the drawing, a larger number of sub-pixels may be arranged in a plurality of rows and columns.

In addition, the first and second gate wirings GL1 and GL2 are respectively disposed above and below the subpixels SP1 to SP6 arranged in one row, and the third and fourth gate wirings GL3 and GL4 are The subpixels SP7 to SP12 arranged in the second row are respectively disposed above and below, and the fifth and sixth gate wirings GL5 and GL6 are arranged above the subpixels SP13 to SP18 arranged in the third row. and disposed on the lower side, respectively.

Also, the first to fourth data lines DL1 to DL4 intersect the first to sixth gate lines GL1 to GL6 , and the first data line DL1 includes the sub-pixels SP1 and SP7 arranged in one column. . , the third data line DL3 is disposed between the subpixels SP4, SP10, and SP16 disposed in the fourth column and the subpixels SP5, SP11, and SP17 disposed in the fifth column, and the fourth data line DL4 ) is disposed on the right side of the sub-pixels SP6, SP12, and SP18 disposed in the sixth column.

In addition, the first thin film transistor T1 is connected to the first gate line GL1, the first data line DL1, and the first sub-pixel SP1, and the second thin film transistor T2 is connected to the second gate line ( GL2) and the first data line DL1, the third thin film transistor T3 is connected to the second gate line GL2 and the second data line DL2, and the fourth thin film transistor T4 is the first Connected to the first gate line GL1 and the second data line DL2, the fifth thin film transistor T5 is connected to the second gate line GL2 and the third data line DL3, and the sixth thin film transistor T5 is connected to the second gate line GL2 and the third data line DL3. T6 is connected to the first gate line GL1 and the third data line DL3.

In addition, the seventh thin film transistor T7 is connected to the third gate line GL3 and the second data line DL2, and the eighth thin film transistor T8 is connected to the fourth gate line GL4 and the second data line DL2. DL2), the ninth thin film transistor T9 is connected to the fourth gate line GL4 and the third data line DL3, and the tenth thin film transistor T10 is connected to the third gate line GL3 and the third data line DL3. It is connected to the third data line DL3, the eleventh thin film transistor T11 is connected to the fourth gate line GL4 and the fourth data line DL4, and the twelfth thin film transistor T12 is connected to the third gate line ( GL3) and the fourth data line DL4.

In addition, the thirteenth thin film transistor T13 is connected to the fifth gate line GL5 and the first data line DL1 , and the 14th thin film transistor T14 is connected to the sixth gate line GL6 and the first data line DL1 . DL1), the fifteenth thin film transistor T15 is connected to the sixth gate line GL6 and the second data line DL2, and the sixteenth thin film transistor T16 is connected to the fifth gate line GL5 and the second data line DL2. It is connected to the second data line DL2, the 17th thin film transistor T17 is connected to the sixth gate line GL6 and the third data line DL3, and the 18th thin film transistor T18 is connected to the fifth gate line ( GL5) and the third data line DL3.

Here, the first and third data lines DL1 and DL3 and the second and fourth data lines DL2 and DL4 supply data voltages having different polarities for one frame without inversion of polarity to form 2 horizontal dots. Power consumption can be reduced because it operates in an inversion method.

However, there is a problem in that the connection structure between the thin film transistor and the pixel electrode is different in driving the conventional DRD type liquid crystal display using the horizontal two-dot inversion method.

In this case, the data voltage is not supplied only to the sub-pixel close to one data line among the sub-pixels located on both sides of the data line or the data voltage is not supplied to only the far sub-pixel, but both the near-side sub-pixel and the far-side sub-pixel This is because the data voltage is supplied to the

FIG. 2 is a plan view illustrating a connection relationship between a first data line of FIG. 1 and first and second sub-pixels;

As shown in the drawing, the conventional DRD type liquid crystal display device includes a first sub-pixel SP1 including a first pixel electrode 11 and a second pixel electrode 12, and includes a first sub-pixel SP1. The second sub-pixel SP2 disposed on the right side, the first and second gate wirings GL1 and GL2 disposed above and below the first and second sub-pixels SP1 and SP2, respectively, and the first and second sub-pixels SP1 and SP2 It includes a first data line DL1 intersecting the second gate lines GL1 and GL2 and disposed on the left side of the first sub-pixel SP1 , and first and second thin film transistors T1 and T2 .

Here, the first thin film transistor T1 is connected to the first gate line GL1 and the first data line DL1, and the second thin film transistor T2 is connected to the second gate line GL2 and the first data line DL1. DL1).

Specifically, the gate electrode 16 of the first thin film transistor T1 is connected to the first gate line GL1, the source electrode 17 is connected to the first data line DL1, and the drain electrode 18 is connected to the first data line DL1. is connected to the first pixel electrode 11 through the drain contact hole DCH1.

In addition, the gate electrode 13 of the second thin film transistor T2 is connected to the second gate line GL2, the source electrode 14 is connected to the first data line DL1, and the drain electrode 15 is It is connected to the second pixel electrode 12 through the drain contact hole DCH2.

In addition, the first data line DL1 supplies a data voltage having the same polarity for one frame without inversion of polarity to drive it in a horizontal two-dot inversion method.

Here, the first data line DL1 supplies a data voltage to a first subpixel SP1 that is a subpixel closer to the first data line DL1 and a second subpixel SP2 that is a subpixel farther from the first data line DL1 , respectively. .

In particular, in the conventional DRD type liquid crystal display device, the first and second thin film transistors T1 and T2 are respectively fixed at positions adjacent to the first data line DL1, and first and second pixel electrodes ( 11 and 12 are extended and connected to the drain electrodes 18 and 15 of the first and second thin film transistors T1 and T2, respectively.

In this case, since the extension lengths of the first and second pixel electrodes 11 and 12 are different, parasitic capacitances of the first and second subpixels SP1 and SP2 are different, and thus display quality is deteriorated. Since the second pixel electrode 12 of the second sub-pixel SP2 , which is a sub-pixel farther from the first data line DL1 , needs to extend relatively longer than the first pixel electrode 11 , the aperture ratio is equal to the extended portion. There is a problem of this deterioration.

An object of the present invention is to provide a liquid crystal display device capable of reducing power consumption, minimizing flicker, and preventing display quality deterioration.

In order to achieve the above object, the present invention provides a first data extension line extending from the first data line along the second gate line in the direction of the first sub-pixel, and a second data line along the first gate line. The second data extension line extending in the second sub-pixel direction, the first thin film transistor having the gate electrode and the source electrode connected to the first gate line and the second data extension line, respectively, and the gate electrode and the source electrode connecting the second gate and second thin film transistors respectively connected to the wiring and the first data extension wiring, and drain electrodes of the first and second thin film transistors are respectively connected to the first and second pixel electrodes, or to the second and first pixel electrodes A liquid crystal display device connected to each other is provided.

According to the present invention, power consumption can be reduced by driving in a one-dot inversion method, and a flicker phenomenon can be further minimized.

In addition, there is an effect of preventing display quality from being deteriorated due to different parasitic capacitances of adjacent subpixels.

1 is a view showing a conventional DRD type liquid crystal display device.
FIG. 2 is a plan view illustrating a connection relationship between a first data line of FIG. 1 and first and second sub-pixels;
3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.
4 is a plan view illustrating a connection relationship between the first and second data lines of FIG. 3 and the first and second sub-pixels.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.

As shown in the drawing, the DRD type liquid crystal display device according to the embodiment of the present invention includes first to eighteenth sub-pixels SP1 to SP18 arranged in three rows and six columns, and first to sixth gate wirings GL1 to GL6), first to fourth data lines DL1 to DL4, and first to 18th thin film transistors T1 to T18.

In addition, the first to eighteenth sub-pixels SP1 to SP18 display any one of red (R), green (G), and blue (B), and adjacent to each other red (R), green (G) and Three sub-pixels displaying blue (B) form one unit pixel.

Meanwhile, although the first to eighteenth sub-pixels SP1 to SP18 are illustrated as being arranged in three rows and six columns in the drawing, a larger number of sub-pixels may be arranged in a plurality of rows and columns.

In addition, the first and second gate wirings GL1 and GL2 are respectively disposed above and below the subpixels SP1 to SP6 arranged in one row, and the third and fourth gate wirings GL3 and GL4 are The subpixels SP7 to SP12 arranged in the second row are respectively disposed above and below, and the fifth and sixth gate wirings GL5 and GL6 are arranged above the subpixels SP13 to SP18 arranged in the third row. and disposed on the lower side, respectively.

Also, the first to fourth data lines DL1 to DL4 intersect the first to sixth gate lines GL1 to GL6 , and the first data line DL1 includes the sub-pixels SP1 and SP7 arranged in one column. . , the third data line DL3 is disposed between the subpixels SP4, SP10, and SP16 disposed in the fourth column and the subpixels SP5, SP11, and SP17 disposed in the fifth column, and the fourth data line DL4 ) is disposed on the right side of the sub-pixels SP6, SP12, and SP18 disposed in the sixth column.

In addition, the first thin film transistor T1 is connected to the first gate line GL1, the second data line DL2, and the first sub-pixel SP1, and the second thin film transistor T2 is connected to the second gate line ( GL2) and the first data line DL1, the third thin film transistor T3 is connected to the second gate line GL2 and the second data line DL2, and the fourth thin film transistor T4 is the first It is connected to the first gate line GL1 and the third data line DL3, the fifth thin film transistor T5 is connected to the first gate line GL1 and the fourth data line DL4, and the sixth thin film transistor T5 is connected to the first gate line GL1 and the fourth data line DL4. T6 is connected to the second gate line GL2 and the third data line DL3.

Also, the seventh thin film transistor T7 is connected to the fourth gate line GL4 and the first data line DL1, and the eighth thin film transistor T8 is connected to the third gate line GL3 and the second data line DL1. DL2), the ninth thin film transistor T9 is connected to the third gate line GL3 and the third data line DL3, and the tenth thin film transistor T10 is connected to the fourth gate line GL4 and the third data line DL3. It is connected to the second data line DL2, the eleventh thin film transistor T11 is connected to the fourth gate line GL4 and the third data line DL3, and the twelfth thin film transistor T12 is connected to the third gate line ( GL3) and the fourth data line DL4.

In addition, the thirteenth thin film transistor T13 is connected to the fifth gate line GL5 and the second data line DL2 , and the 14th thin film transistor T14 is connected to the sixth gate line GL6 and the first data line DL2 . DL1), the fifteenth thin film transistor T15 is connected to the sixth gate line GL6 and the second data line DL2, and the sixteenth thin film transistor T16 is connected to the fifth gate line GL5 and the second data line DL2. The third data line DL3 is connected, the 17th thin film transistor T17 is connected with the fifth gate line GL5 and the fourth data line DL4, and the 18th thin film transistor T18 is connected with the sixth gate line ( GL6) and the third data line DL3.

In this case, the second thin film transistor T2 extends from the first data line DL1 along the second gate line GL2 and has ends corresponding to the positions between the first and second sub-pixels SP1 and SP2. is connected to the first data line DL1 through the first data extension line E1 to The end is connected to the second data line DL2 through the second data extension line E2 positioned correspondingly between the first and second sub-pixels SP1 and SP2.

Similarly, the third to eighteenth thin film transistors T3 to T18 are data wires ( DL1 to DL4) respectively.

Here, the odd-numbered data lines DL1 and DL3 and the even-numbered data lines DL2 and DL4 supply data voltages having different polarities for one frame without polarity inversion, thereby driving the 1-dot inversion method. Therefore, power consumption can be reduced, and the flicker phenomenon can be further minimized compared to the horizontal two-dot inversion method.

In addition, when the DRD type liquid crystal display device according to the embodiment of the present invention is driven in the 1-dot inversion method, data is stored in both the near-side sub-pixel and the far-side sub-pixel among the sub-pixels located on both sides of one data line. Even when voltage is supplied, since each data line and the thin film transistor are connected through the data extension line extended from each data line, the thin film transistor and the pixel electrode can have the same connection structure.

4 is a plan view illustrating a connection relationship between the first and second data lines of FIG. 3 and the first and second sub-pixels.

As shown in the drawing, the DRD type liquid crystal display device according to an embodiment of the present invention includes a first sub-pixel SP1 including a first pixel electrode 111 and a second pixel electrode 112, and includes a first a second sub-pixel SP2 disposed on the right side of the sub-pixel SP1, first and second gate wirings GL1 and GL2 disposed above and below the first and second sub-pixels SP1 and SP2, respectively; , first and second data lines DL1 and DL2 intersecting the first and second gate lines GL1 and GL2 and respectively disposed on the left side of the first sub-pixel SP1 and the right side of the second sub-pixel SP2; , first and second data extension lines E1 and E2, and first and second thin film transistors T1 and T2.

Here, the first data extension line E1 extends from the first data line DL1 in the direction of the first sub-pixel SP1 along the second gate line GL2, and ends of the first and second sub-pixels ( Located between SP1 and SP2, the second data extension line E2 extends from the second data line DL2 along the first gate line GL1 in the direction of the second sub-pixel SP2 to the end thereof. It is positioned correspondingly between the first and second sub-pixels SP1 and SP2.

In addition, the first thin film transistor T1 is connected to the ends of the first gate line GL1 and the second data extension line E2, respectively, and the second thin film transistor T2 is connected to the second gate line GL2 and the first It is connected to the data extension line (E1).

Specifically, the gate electrode 116 of the first thin film transistor T1 is connected to the first gate line GL1 , the source electrode 117 is connected to the second data extension line E2 , and the drain electrode 118 is connected to the second data extension line E2 . ) is connected to the first pixel electrode 111 through the drain contact hole DCH1.

In addition, the gate electrode 113 of the second thin film transistor T2 is connected to the second gate line GL2, the source electrode 114 is connected to the first data extension line E1, and the drain electrode 115 is connected to the first data extension line E1. is connected to the second pixel electrode 112 through the drain contact hole DCH2.

Meanwhile, unlike the drawing, the gate electrode 116 of the first thin film transistor T1 is connected to the first gate line GL1, the source electrode 117 is connected to the second data extension line E2, and the drain The electrode 118 may be connected to the second pixel electrode 112 through a drain contact hole.

At this time, the gate electrode 113 of the second thin film transistor T2 is connected to the second gate line GL2 , the source electrode 114 is connected to the first data extension line E1 , and the drain electrode 115 is connected to the first data extension line E1 . ) is connected to the first pixel electrode 111 through the drain contact hole.

Also, although not shown in the drawing, a third sub-pixel SP3 including a third pixel electrode (not shown) and disposed on the right side of the second sub-pixel SP2 and the second data line DL2, and a fourth pixel The fourth sub-pixel SP4 including an electrode (not shown) and disposed on the right side of the third sub-pixel SP3 intersects the first and second gate lines GL1 and GL2, and the fourth sub-pixel SP4 ) may include a third data line DL3 disposed on the right side.

Here, a third data extension line (not shown) extends from the second data line DL2 in the direction of the third subpixel SP3 along the second gate line GL2 to end the third and fourth subpixels. is positioned between SP3 and SP4, and a fourth data extension line (not shown) extends from the third data line DL3 to the fourth sub-pixel SP4 along the first gate line GL1. Thus, an end thereof may be positioned correspondingly between the third and fourth sub-pixels SP3 and SP4.

In addition, the gate electrode and the source electrode of the third thin film transistor T3 are respectively connected to the ends of the second gate line GL2 and the third data extension line (not shown), and the gate electrode and the source electrode of the fourth thin film transistor T4 The source electrode may be respectively connected to ends of the first gate line GL1 and the fourth data extension line (not shown).

In this case, the drain electrodes of the third and fourth thin film transistors T3 and T4 may be respectively connected to the third and fourth pixel electrodes (not shown) or respectively connected to the fourth and third pixel electrodes (not shown). have.

In addition, the odd-numbered data lines DL1 and DL3 and the even-numbered data lines DL2 and DL4 supply data voltages having different polarities for one frame without polarity inversion to drive them in a 1-dot inversion method.

In particular, in the DRD type liquid crystal display device according to the embodiment of the present invention, the first thin film transistor T1 is connected to the second data line DL2 through the second data extension line E2. by disposing correspondingly between the upper sides of the first and second sub-pixels SP1 and SP2, and connecting the second thin film transistor T2 to the first data line DL1 through the first data extension line E1. The second thin film transistor T2 may be disposed correspondingly between the lower sides of the first and second sub-pixels SP1 and SP2.

At this time, the first and second pixel electrodes 111 and 112 are extended and connected to the drain electrodes 118 and 115 of the first and second thin film transistors T1 and T2, respectively, where the first and second Since the extension lengths of the pixel electrodes 111 and 112 are the same, the parasitic capacitances of the first and second sub-pixels SP1 and SP2 are different, thereby preventing display quality from being deteriorated.

In addition, since the distances to the first and second thin film transistors T1 and T2 and the first and second sub-pixels SP1 and SP2 are the same, which of the first and second thin film transistors T1 and T2 is Since it is not necessary to extend the pixel electrode 111 of one sub-pixel relatively longer, it is possible to prevent a decrease in the aperture ratio by the extended portion.

On the other hand, since the thin film transistors of each of the subpixels sharing one data line are connected to the gate line in opposite directions (up and down), when the mask for forming the gate line and the mask for forming the data line are shifted up and down, They have different magnitudes of parasitic capacitance. As a result, efficiency voltages between adjacent sub-pixels may be different from each other, thereby degrading display quality.

In order to solve this problem, the DRD type liquid crystal display device according to the embodiment of the present invention has a compensation pattern ( 119, 120).

At this time, the compensation patterns 119 and 120 are disposed to overlap the drain electrodes 118 and 115 (not shown), and the drain electrodes 118 and 115 of the first to third thin film transistors T1 to T3 (not shown). each extends in the vertical direction to form a T-shape.

In addition, the compensation patterns 119 and 120 are made of the same material as the gate electrodes 116 and 113 (not shown) of the first to third thin film transistors T1 to T3.

Accordingly, even if the mask for forming the data wiring and the mask for forming the gate wiring are displaced from each other, the overlapping area of the drain electrodes 118 and 115 (not shown) and the compensation patterns 119 and 120 in the subpixel in which the parasitic capacitance is reduced In the sub-pixel in which this area is widened and the parasitic capacitance is increased, the overlapping area of the drain electrodes 118 and 115 (not shown) and the compensation patterns 119 and 120 is narrowed, so that the parasitic capacitance can be compensated.

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

GL1 ~ GL6 : Gate wiring DL1 ~ DL4 : Data wiring
SP1 ~ SP18 : Sub-pixel T1 ~ T18 : Thin film transistor
E1, E2: data extension wiring 119: compensation pattern

Claims (8)

a first sub-pixel including a first pixel electrode and a second sub-pixel including a second pixel electrode and disposed on a right side of the first sub-pixel;
first and second gate wirings respectively disposed above and below the first and second sub-pixels;
first and second data lines intersecting the first and second gate lines and respectively disposed on the left side of the first sub-pixel and on the right side of the second sub-pixel;
a first data extension line extending from the first data line in the direction of the first sub-pixel along the second gate line; and a first data extension line extending from the second data line in the direction of the second sub-pixel along the first gate line a second data extension wiring;
a first thin film transistor in which a gate electrode and a source electrode are respectively connected to the first gate line and a second data extension line, and a second transistor in which the gate electrode and the source electrode are connected to the second gate line and the first data extension line, respectively thin film transistor;
a third sub-pixel including a third pixel electrode, the third sub-pixel disposed on the right side of the second sub-pixel and the second data line, and a fourth sub-pixel disposed on the right side of the third sub-pixel;
a third data line intersecting the first and second gate lines and disposed on a right side of the fourth sub-pixel;
a third data extension line extending from the second data line in the direction of the third sub-pixel along the second gate line, and a third data extension line extending from the third data line in the direction of the fourth sub-pixel along the first gate line a fourth data extension wiring; and
a third thin film transistor in which the gate electrode and the source electrode are respectively connected to the second gate line and the third data extension line, and a fourth transistor in which the gate electrode and the source electrode are respectively connected to the first gate line and the fourth data extension line including a thin film transistor;
The drain electrodes of the first and second thin film transistors are respectively connected to the first and second pixel electrodes or respectively connected to the second and first pixel electrodes,
The drain electrodes of the third and fourth thin film transistors are respectively connected to the third and fourth pixel electrodes or respectively connected to the fourth and third pixel electrodes,
the first thin film transistor is disposed between upper sides of the first and second subpixels, and the second thin film transistor is disposed between lower sides of the first and second subpixels;
The third thin film transistor is disposed between the lower sides of the third and fourth sub-pixels, and the fourth thin film transistor is disposed between the upper sides of the third and fourth sub-pixels.
delete The method of claim 1,
The first to fourth sub-pixels are driven in a one-dot inversion method.
4. The method of claim 3,
The drain electrodes of the first to fourth thin film transistors each extend in a vertical direction to form a T-shape.
5. The method of claim 4,
A compensation pattern disposed under the drain electrode of the first to fourth thin film transistors and overlapping the drain electrode
A liquid crystal display further comprising a.
6. The method of claim 5,
The compensation pattern is made of the same material as the gate electrode of the first to fourth thin film transistors. The method of claim 1,
A distance from the first thin film transistor to the first and second sub-pixels is the same, and a distance from the second thin film transistor to the first and second sub-pixels is equal to each other,
The distance from the third thin film transistor to the third and fourth sub-pixels is the same, and the distance from the fourth thin film transistor to the third and fourth sub-pixels is the same.
7. The method of claim 6,
One end of the drain electrode of the first to fourth thin film transistors overlaps the gate electrode of the first to fourth thin film transistors, and the other end of the drain electrode of the first to fourth thin film transistors overlaps the compensation pattern. display device.

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