CN104062825A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN104062825A CN104062825A CN201410308975.0A CN201410308975A CN104062825A CN 104062825 A CN104062825 A CN 104062825A CN 201410308975 A CN201410308975 A CN 201410308975A CN 104062825 A CN104062825 A CN 104062825A
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Abstract
The invention discloses an array substrate, which comprises a plurality of pixel units, wherein each pixel unit comprises 2*2 sub pixel region matrixes, a first sub pixel region, a second sub pixel region, a third sub pixel region and a fourth sub pixel region are sequentially and clockwise arranged in the 2*2 sub pixel region matrixes, each sub pixel region comprises four sub pixels, the first sub pixel region and the third sub pixel region comprise 2*2 sub pixel matrixes, and the second sub pixel region and the fourth sub pixel region comprise 1*4 sub pixel matrixes. The array substrate as well as a display panel and a display device comprising the array substrate provided by the invention have the advantages that the cost can be reduced, in addition, the wide view angle is realized, and the transmittance is improved.
Description
Technical field
The present invention relates to demonstration field, particularly a kind of array base palte, and the display panel that comprises this array base palte and display device.
Background technology
Display panel is widely used in mobile phone, palm PC (PersonalDigitalAssistant at present, PDA) etc. in portable type electronic product, for example: Thin Film Transistor-LCD (ThinFilmTransistor-LiquidCrystalDisplay, TFT-LCD), organic light emitting diode display (OrganicLightEmittingDiode, OLED), low temperature polycrystalline silicon (LowTemperaturePoly-silicon, LTPS) display and plasma scope (PlasmaDisplayPanel, PDP) etc.Along with showing the flourish of science and technology, consumption is popular also more and more higher for the requirement of display image display quality.Consumption is popular also day by day to improve the requirement of the visual angle of display (viewingangle), color saturation (colorsaturation), display effect and price etc.
In the display panel using at present, there are a variety of Pixel arrangement structures, the modal Pixel arrangement mode that has strip, as shown in Figure 1, the arrangement mode of this pixel, take in Fig. 1 four sub-pixels in pixel cell, in this pixel cell, need 4 data lines,, a gate line, in whole dot structure, the number of data line is many, when display shows, grid drive IC is once opened the transistor of a full line when scanning, when grid drive IC is moved line by line, data line drive IC is responsible in every a line, data voltage being inputted by column, so when data line number increases, can increase the burden of data line drive IC, in order to meet the needs that drive, the number of corresponding data line drive IC also will increase, and the cost of IC is very expensive, and the cost of data line is also more expensive, increasing of data line can cause the cost of whole display device to increase, so just do not meet current consumer for inexpensive consumption demand.
The resolution of liquid crystal display is more and more higher at present, this just means the increase that scans columns, the arrangement mode of this strip dot structure in picture Fig. 1, raising along with resolution, the increase of data line, when showing, needs the columns of scanning to increase, driving time will extend, and does not so just meet the needs of people to the product of high corresponding speed in the market; And the Pixel arrangement of this strip shaped electric poles, can not reach the requirement at wide visual angle.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte, and the display panel that comprises this array base palte and display device.
In view of this, for at least one in addressing the above problem, the embodiment of the present invention provides a kind of array base palte, comprise: a plurality of pixel cells, described pixel cell comprises the first main pixel region and the second main pixel region that level is adjacent, wherein, described the first main pixel region comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the first sub-pixel area and the 4th sub-pixel area; Described the second main pixel region comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the second sub-pixel area and the 3rd sub-pixel area; The setting adjacent with the second sub-pixel area of described the first sub-pixel area, the 3rd sub-pixel area and the 4th adjacent setting in sub-pixel area; Described in each, sub-pixel area comprises four sub-pixels; Wherein, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
The embodiment of the present invention also provides a kind of array base palte, comprise: a plurality of pixel cells, described pixel cell comprises 2 * 2 sub-pixel area matrixes, and described 2 * 2 sub-pixel area matrixes are followed successively by the first sub-pixel area, the second sub-pixel area, the 3rd sub-pixel area and the 4th sub-pixel area according to arranged clockwise; Described in each, sub-pixel area comprises 4 sub-pixels; Described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
Preferably, described the first sub-pixel area comprises and is arranged in order clockwise the first sub-pixel, the second sub-pixel, the 3rd sub-pixel, the 4th sub-pixel; Described the second sub-pixel area comprises the 5th sub-pixel, the 6th sub-pixel, the 7th sub-pixel and the 8th sub-pixel being arranged in order from the direction away from the first sub-pixel area; Described the 3rd sub-pixel area comprises the 9th sub-pixel, the tenth sub-pixel, the 11 sub-pixel and the 12 sub-pixel being arranged in order clockwise; Described the 4th sub-pixel area comprises the 13 sub-pixel, the 14 sub-pixel, the 15 sub-pixel and the 16 sub-pixel being arranged in order from the direction away from the 3rd sub-pixel area.
Preferably, described pixel cell comprises: 16 pixel switches, are arranged at respectively described in each in sub-pixel;
With three gate lines, described gate line is first grid polar curve, second gate line and the 3rd gate line;
With seven data line the first data lines, the second data line, the 3rd data line, the 4th data line, the 5th data line, the 6th data line and the 7th data line;
Described first grid polar curve is electrically connected to described the first sub-pixel, the second sub-pixel, the 5th sub-pixel, the 6th sub-pixel, the 7th sub-pixel and the 8th sub-pixel; Described second gate line is electrically connected to the 3rd sub-pixel, the 4th sub-pixel, the 9th sub-pixel and the tenth sub-pixel; Described the 3rd gate line is electrically connected to the 11 sub-pixel, the 12 sub-pixel, the 13 sub-pixel, the 14 sub-pixel, the 15 sub-pixel and the 16 sub-pixel;
Described the first data line is electrically connected to the 16 sub-pixel; Described the second data line is electrically connected to the first sub-pixel, the 4th sub-pixel, the 15 sub-pixel, described the 3rd data line is electrically connected to the second sub-pixel, the 3rd sub-pixel, the 14 sub-pixel, described the 4th data line is electrically connected to the 5th sub-pixel, the 13 sub-pixel, described the 5th data line is electrically connected to the 6th sub-pixel, the 9th sub-pixel, the 12 sub-pixel, described the 6th data line is electrically connected to the 7th sub-pixel, the tenth sub-pixel, the 11 sub-pixel, and described the 7th data line is electrically connected to the 8th sub-pixel.
Preferably, described the first sub-pixel area and the second sub-pixel area are between first grid polar curve and second gate line; Described the 3rd sub-pixel area and the 4th sub-pixel area are between second gate line and the 3rd gate line; Described gate line and data line are electrically connected to described pixel switch respectively; Wherein, the pixel switch being electrically connected to same gate line in same sub-pixel area, is electrically connected to from different data lines respectively.
Preferably, described pixel switch is thin film transistor (TFT).
Preferably, described pixel cell comprises: 16 pixel switches, are arranged at respectively described in each in sub-pixel;
With four gate lines, described gate line is first grid polar curve, second gate line, the 3rd gate line and the 4th gate line;
With five data line the first data lines, the second data line, the 3rd data line, the 4th data line and the 5th data line;
Described first grid polar curve is electrically connected to the first sub-pixel, the second sub-pixel, the 6th sub-pixel and the 8th sub-pixel; Described second gate line is electrically connected to the 3rd sub-pixel, the 4th sub-pixel, the 5th sub-pixel and the 7th sub-pixel; Described the 3rd gate line is electrically connected to the 9th sub-pixel, the tenth sub-pixel, the 13 sub-pixel and the 15 sub-pixel; Described the 4th gate line is electrically connected to the 11 sub-pixel, the 12 sub-pixel, the 14 sub-pixel and the 16 sub-pixel;
Described the first data line is electrically connected to the 4th sub-pixel, the 16 sub-pixel; Described the second data line is electrically connected to the first sub-pixel, the 3rd sub-pixel, the 14 sub-pixel, the 15 sub-pixel, described the 3rd data line is electrically connected to the second sub-pixel, the 5th sub-pixel, the 12 sub-pixel, the 13 sub-pixel, described the 4th data line is electrically connected to the 6th sub-pixel, the 7th sub-pixel, the 9th sub-pixel, the 11 sub-pixel, and described the 5th data line is electrically connected to the 8th sub-pixel, the tenth sub-pixel.
Preferably, described the first sub-pixel area and the second sub-pixel area are between first grid polar curve and second gate line; Described the 3rd sub-pixel area and the 4th sub-pixel area are between the 3rd gate line and the 4th gate line; Described gate line and data line are electrically connected to described pixel switch respectively; Wherein, the pixel switch being electrically connected to same gate line in same sub-pixel area, is electrically connected to from different data lines respectively.
Preferably, the sub-pixel in described four pixel regions is respectively red sub-pixel, green sub-pixels, blue subpixels and white sub-pixels.
Preferably, described the first sub-pixel area and the 3rd sub-pixel area include two row sub-pixels, and in described two row sub-pixels, every row sub-pixel forms epaulet shape structure; Each sub-pixel in described the second sub-pixel area and the 4th sub-pixel area is epaulet shape structure.
The invention provides a kind of display panel, comprising: first substrate, second substrate and the liquid crystal layer between first substrate and second substrate, wherein, described first substrate comprises array base palte as above.
The present invention also provides a kind of display device, comprises display panel as above.
This array base palte providing in the present invention, and the display panel that comprises this array base palte and display device, can reduce the quantity of data line, thereby can reduce costs, and can shorten driving time, realizes wide visual angle, increases the advantage of transmitance.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram of the strip Pixel arrangement mode that provides of prior art;
Fig. 2 is a kind of structural representation of the pixel cell that provides of the embodiment of the present invention one;
Fig. 3 is a kind of schematic diagram of the arrangement mode of the sub-pixel that provides of the embodiment of the present invention one;
Fig. 4 is the another kind of schematic diagram of the arrangement mode of the sub-pixel that provides of the embodiment of the present invention one;
Fig. 5 is the third schematic diagram of the arrangement mode of the sub-pixel that provides of the embodiment of the present invention one;
Fig. 6 is the 4th kind of schematic diagram of the arrangement mode of the sub-pixel that provides of the embodiment of the present invention one;
Fig. 7 is the 5th kind of schematic diagram of the arrangement mode of the sub-pixel that provides of the embodiment of the present invention one;
Fig. 8 is the another kind of structural representation of the pixel cell that provides of the embodiment of the present invention one;
Fig. 9 is the third structural representation of the pixel cell that provides of the embodiment of the present invention one;
Figure 10 is the 4th kind of structural representation of the pixel cell that provides of the embodiment of the present invention one;
Figure 11 is the 5th kind of structural representation of the pixel cell that provides of the embodiment of the present invention one;
Figure 12 is a kind of structural representation of the pixel cell that provides of the embodiment of the present invention two;
Figure 13 is the another kind of structural representation of the pixel cell that provides of the embodiment of the present invention two.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
The embodiment of the present invention one provides a kind of array base palte, comprise a plurality of pixel cells, as shown in Figure 2, Fig. 2 is a kind of schematic diagram of the pixel cell that provides of the embodiment of the present invention one, as can be seen from Figure 2, described pixel cell comprises the first main pixel region Z1 and the second main pixel region Z3 that level is adjacent, wherein, described the first main pixel region Z1 comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the first sub-pixel area L1 and the 4th sub-pixel area L4; Described the second main pixel region Z2 comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the second sub-pixel area L2 and the 3rd sub-pixel area L3;
Described the first sub-pixel area L1 and the adjacent setting of the second sub-pixel area L2, the 3rd sub-pixel area L3 and the adjacent setting of the 4th sub-pixel area L4;
Be that described pixel cell comprises 2 * 2 sub-pixel area matrixes, described 2 * 2 sub-pixel area matrixes are followed successively by the first sub-pixel area L1, the second sub-pixel area L2, the 3rd sub-pixel area L3 and the 4th sub-pixel area L4 according to arranged clockwise; Described in each, sub-pixel area comprises 4 sub-pixels; Described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
Described four sub-pixels are respectively red sub-pixel (R), green sub-pixels (G), blue subpixels (B) and white sub-pixels (W); Sub-pixel in the first sub-pixel area and the 3rd sub-pixel area is according to being arranged in order clockwise, sub-pixel in the second sub-pixel area is arranged in order according to the direction away from the first sub-pixel area, sub-pixel in the 4th sub-pixel area is arranged in order according to the direction away from the 3rd sub-pixel area, wherein, the arrangement mode of R, G, B, W has multiple, and R, G, B, W can combination in any arrange; In described four sub-pixel area RGBW put in order identical, as shown in Figure 3, each time pixel region comprises red sub-pixel (R), green sub-pixels (G), blue subpixels (B), white sub-pixels (W), and the sub-pixel in each sub-pixel area is arranged according to the order of RGBW; The difference that puts in order of RGBW in the first sub-pixel area, the 3rd sub-pixel area and the second sub-pixel area, the 4th sub-pixel, as shown in Figure 4, arrange according to the order of RGWB respectively the first sub-pixel area and the 3rd sub-pixel area, and arrange according to the order of RGBW respectively the second sub-pixel area and the 4th sub-pixel area; The difference that puts in order of RGBW in the first sub-pixel area, the second sub-pixel area and the 3rd sub-pixel area, the 4th sub-pixel area, as shown in Figure 5, arrange according to the order of RGWB respectively the first sub-pixel area and the second sub-pixel area, and arrange according to the order of RGBW respectively the 3rd sub-pixel area and the 4th sub-pixel area; The difference that puts in order of RGBW in the first sub-pixel area, the 4th sub-pixel area and the second sub-pixel area, the 3rd sub-pixel area, as shown in Figure 6, arrange according to the order of RGWB respectively the first sub-pixel area and the 4th sub-pixel area, and arrange according to the order of RGBW respectively the second sub-pixel area and the 3rd sub-pixel area; All differences that puts in order of RGBW in described four sub-pixel area, as shown in Figure 7, arrange according to the order of RGBW the first sub-pixel area, arrange according to the order of RGWB the second sub-pixel area, and arrange according to the order of RWGB the 3rd sub-pixel area,, arrange according to the order of WRGB the 4th sub-pixel area; This is an embodiment of the present embodiment, the embodiment of the present embodiment can also be, in four pixel regions, there are three sub-pixels identical, all red sub-pixel (R), green sub-pixels (G), blue subpixels (B), another sub-pixel can be any one color in red sub-pixel (R), green sub-pixels (G), blue subpixels (B), white sub-pixels (W), and the color of the sub-pixel in four sub-pixel area can be identical, also can be different, arrange according to the needs of concrete panel designs.
Wherein, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes, and namely the first sub-pixel area and the 3rd sub-pixel area comprise respectively the sub-pixel of two row two row; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix, and namely the second sub-pixel area and the 4th sub-pixel area comprise respectively the sub-pixel of a line four row.Wherein, as shown in Figure 2, described the first sub-pixel area L1 comprises and is arranged in order clockwise the first sub-pixel P1, the second sub-pixel P2, the 3rd sub-pixel P3, the 4th sub-pixel P4; Described the second sub-pixel area L2 comprises the 5th sub-pixel P5, the 6th sub-pixel P6, the 7th sub-pixel P7 and the 8th sub-pixel P8 being arranged in order from the direction away from the first sub-pixel area L1; Described the 3rd sub-pixel area L3 comprises the 9th sub-pixel P9, the tenth sub-pixel P10, the 11 sub-pixel P11 and the 12 sub-pixel P12 being arranged in order clockwise; Described the 4th sub-pixel area L4 comprises the 13 sub-pixel P13, the 14 sub-pixel P14, the 15 sub-pixel P15 and the 16 sub-pixel P16 being arranged in order from the direction away from the 3rd sub-pixel area L3.
This is an embodiment of the present embodiment, the embodiment of the present embodiment can also be, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes, and namely the first sub-pixel area and the 3rd sub-pixel area comprise respectively the sub-pixel of two row two row; Described the second sub-pixel area and the 4th sub-pixel area comprise 4 * 1 sub-pixel matrixes, and namely the second sub-pixel area and the 4th sub-pixel area comprise respectively the sub-pixel of four lines one row.
In the present embodiment, described pixel cell comprises: 16 thin film transistor (TFT)s, be arranged at respectively described in each in sub-pixel, and in each sub-pixel, there is a thin film transistor (TFT), each thin film transistor (TFT) comprises source electrode and drain electrode.As can be seen from Figure 2, these 16 thin film transistor (TFT)s are T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, and are arranged at respectively described in each in sub-pixel.
Described pixel cell also comprises three gate lines and seven data lines, wherein said three gate lines comprise first grid polar curve, second gate line and the 3rd gate line, and described seven data lines comprise the first data line, the second data line, the 3rd data line, the 4th data line, the 5th data line, the 6th data line and the 7th data line.Described gate line and data line are electrically connected to respectively at described thin film transistor (TFT); Wherein, the thin film transistor (TFT) being electrically connected to same gate line in same pixel region, is electrically connected to respectively at different data lines.As shown in Figure 2, described gate line is horizontal direction, and described data line is vertical direction; This pixel cell comprises three row gate lines, respectively first grid polar curve G1, second gate line G2 and the 3rd gate lines G 3, described pixel cell comprises seven data lines on vertical direction, comprise tactic the first data line D1, the second data line D2, the 3rd data line D3, the 4th data line D4, the 5th data line D5, the 6th data line D6, the 7th data line D7, described gate line and data line are electrically connected to described thin film transistor (TFT) respectively.
Wherein, described the first sub-pixel area L1 and the second sub-pixel area L2 are between first grid polar curve G1 and second gate line G2; Described the 3rd sub-pixel area L3 and the 4th sub-pixel area L4 are between second gate line G2 and the 3rd gate lines G 3; Described gate line and data line are electrically connected to described pixel switch respectively; Described pixel switch is thin film transistor (TFT).
Described first grid polar curve G1 is electrically connected to described the first sub-pixel P1, the second sub-pixel P2, the 5th sub-pixel P5, the 6th sub-pixel P6, the 7th sub-pixel P7 and the 8th sub-pixel P8; Described second gate line G2 is electrically connected to the 3rd sub-pixel P3, the 4th sub-pixel P4, the 9th sub-pixel P9 and the tenth sub-pixel P10; Described the 3rd gate lines G 3 is electrically connected to the 11 sub-pixel P11, the 12 sub-pixel P12, the 13 sub-pixel P13, the 14 sub-pixel P14, the 15 sub-pixel P15 and the 16 sub-pixel P16.
Described the first data line D1 is electrically connected to the 16 sub-pixel P16, described the second data line D2 and the first sub-pixel P1, the 4th sub-pixel P4, the 15 sub-pixel P15 is electrically connected to, described the 3rd data line D3 and the second sub-pixel P2, the 3rd sub-pixel P3, the 14 sub-pixel P14 is electrically connected to, described the 4th data line D4 and the 5th sub-pixel P5, the 13 sub-pixel P13 is electrically connected to, described the 5th data line D5 and the 6th sub-pixel P6, the 9th sub-pixel P9, the 12 sub-pixel P12 is electrically connected to, described the 6th data line D6 and the 7th sub-pixel P7, the tenth sub-pixel P10, the 11 sub-pixel P11 is electrically connected to, described the 7th data line D7 is electrically connected to the 8th sub-pixel P8.
Wherein, the thin film transistor (TFT) being electrically connected to same gate line in same pixel region, is electrically connected to respectively at different data lines.First grid polar curve G1 and thin film transistor (TFT) T1, T2, T5, T6, T7, the drain electrode of T8 is electrically connected to, second gate line G2 and thin film transistor (TFT) T3, T4, T9, the drain electrode of T10 is electrically connected to, the 3rd gate lines G 3 and thin film transistor (TFT) T11, T12, T13, T14, T15, the drain electrode of T16 is electrically connected to, the first data line D1 is electrically connected to the source electrode of thin film transistor (TFT) T16, the second data line D2 and thin film transistor (TFT) T1, T4, the source electrode of T15 is electrically connected to, the 3rd data line D3 and thin film transistor (TFT) T2, T3, the source electrode of T14 is electrically connected to, the 4th data line D4 is electrically connected to the source electrode of thin film transistor (TFT) T5 and T13, the 5th data line D5 and thin film transistor (TFT) T6, T9, the source electrode of T12 is electrically connected to, the 6th data line D6 and thin film transistor (TFT) T7, T10, the source electrode of T11 is electrically connected to, the 7th data line D7 is electrically connected to the source electrode of thin film transistor (TFT) T8, wherein, described the first data line D1, the 4th data line D4 and the 7th data line D7 respectively be positioned at data line not the source electrode of two thin film transistor (TFT)s of homonymy be electrically connected to, described data line not homonymy refers to the left and right sides of data line in the horizontal direction, the sub-pixel of the sub-pixel in described pixel cell and surrounding pixel unit shares described the first data line D1 and the 7th data line D7, described the second data line D2, the 3rd data line D3, the 5th data line D5 and the 6th data line D6 are electrically connected to the source electrode that is positioned at three thin film transistor (TFT)s of data line the same side respectively, and described data line the same side refers to left side or the right side of data line in the horizontal direction.
In the present invention, described the first sub-pixel area and the 3rd sub-pixel area include two row sub-pixels, and in described two row sub-pixels, every row sub-pixel forms epaulet shape structure; Each sub-pixel in described the second sub-pixel area and the 4th sub-pixel area is epaulet shape structure.In four sub-pixel area, the sub-pixel of described epaulet shape structure bends to same direction.Pixel in described the first sub-pixel area and the 3rd sub-pixel area is the structure on pseudo-two farmlands, and the pixel in the second sub-pixel area and the 4th sub-pixel area is the structure on two farmlands.Wherein, seven data lines are also arranged to the shape of corresponding broken line.
Be more than one embodiment of the present invention, embodiments of the present invention can also be as shown in Figure 8, in described pixel cell, in the first sub-pixel area L1, the second sub-pixel area L2, the overbending direction of sub-pixel is different from the overbending direction of sub-pixel in the 3rd sub-pixel area L3, the 4th sub-pixel area L4, and data line is straight line in this embodiment; Wherein, seven data lines are also arranged to the shape of corresponding broken line.
In the present invention, in the different subpixel district of pixel cell, the overbending direction of sub-pixel can be identical, also can be different; As shown in Figure 9, different from the overbending direction of sub-pixel in L4 at the overbending direction of sub-pixel area L1, L2 and sub-pixel in L3.The overbending direction of the different subpixel in pixel cell in any sub-pixel area can be identical, also can be different, and as shown in figure 10, in the L3 of sub-pixel area, the bending angle of two different row sub-pixels is different; And data line can be also fold-line-shaped in these embodiments.As shown in figure 11, the sub-pixel in sub-pixel area can be also vertical bar shaped.
A kind of display panel is also provided in the present invention, comprises: first substrate, second substrate and the liquid crystal layer between first substrate and second substrate, wherein, described first substrate comprises array base palte as above.
The present invention also provides a kind of display device, comprises display panel as above.
The array base palte providing in the present embodiment, display panel and display device, can realize all good effects of visual angle and transmitance, can reduce costs, and shorten driving time.
Embodiment bis-
The embodiment of the present invention two provides a kind of array base palte, comprise a plurality of pixel cells, as shown in figure 12, Figure 12 is a kind of structural representation of the pixel cell that provides of the embodiment of the present invention two, as can be seen from Figure 12, described pixel cell comprises the first main pixel region Z1 and the second main pixel region Z3 that level is adjacent, wherein, described the first main pixel region Z1 comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the first sub-pixel area L1 and the 4th sub-pixel area L4; Described the second main pixel region Z2 comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the second sub-pixel area L2 and the 3rd sub-pixel area L3;
Described the first sub-pixel area L1 and the adjacent setting of the second sub-pixel area L2, the 3rd sub-pixel area L3 and the adjacent setting of the 4th sub-pixel area L4;
Be that described pixel cell comprises 2 * 2 sub-pixel area matrixes, described 2 * 2 sub-pixel area matrixes are followed successively by the first sub-pixel area L1, the second sub-pixel area L2, the 3rd sub-pixel area L3 and the 4th sub-pixel area L4 according to arranged clockwise; Described in each, sub-pixel area comprises 4 sub-pixels; Described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
Described four sub-pixels are respectively red sub-pixel (R), green sub-pixels (G), blue subpixels (B) and white sub-pixels (W); Sub-pixel in the first sub-pixel area and the 3rd sub-pixel area is according to being arranged in order clockwise, sub-pixel in the second sub-pixel area is arranged in order according to the direction away from the first sub-pixel area, sub-pixel in the 4th sub-pixel area is arranged in order according to the direction away from the 3rd sub-pixel area, wherein, the arrangement mode of R, G, B, W has multiple, and R, G, B, W can combination in any arrange; In described four sub-pixel area RGBW put in order identical, as shown in Figure 3, each time pixel region comprises red sub-pixel (R), green sub-pixels (G), blue subpixels (B), white sub-pixels (W), and the sub-pixel in each sub-pixel area is arranged according to the order of RGBW; The difference that puts in order of RGBW in the first sub-pixel area, the 3rd sub-pixel area and the second sub-pixel area, the 4th sub-pixel, as shown in Figure 4, arrange according to the order of RGWB respectively the first sub-pixel area and the 3rd sub-pixel area, and arrange according to the order of RGBW respectively the second sub-pixel area and the 4th sub-pixel area; The difference that puts in order of RGBW in the first sub-pixel area, the second sub-pixel area and the 3rd sub-pixel area, the 4th sub-pixel area, as shown in Figure 5, arrange according to the order of RGWB respectively the first sub-pixel area and the second sub-pixel area, and arrange according to the order of RGBW respectively the 3rd sub-pixel area and the 4th sub-pixel area; The difference that puts in order of RGBW in the first sub-pixel area, the 4th sub-pixel area and the second sub-pixel area, the 3rd sub-pixel area, as shown in Figure 6, arrange according to the order of RGWB respectively the first sub-pixel area and the 4th sub-pixel area, and arrange according to the order of RGBW respectively the second sub-pixel area and the 3rd sub-pixel area; All differences that puts in order of RGBW in described four sub-pixel area, as shown in Figure 7, arrange according to the order of RGBW the first sub-pixel area, arrange according to the order of RGWB the second sub-pixel area, and arrange according to the order of RWGB the 3rd sub-pixel area,, arrange according to the order of WRGB the 4th sub-pixel area; This is an embodiment of the present embodiment, the embodiment of the present embodiment can also be, in four pixel regions, there are three sub-pixels identical, all red sub-pixel (R), green sub-pixels (G), blue subpixels (B), another sub-pixel can be any one color in red sub-pixel (R), green sub-pixels (G), blue subpixels (B), white sub-pixels (W), and the color of the sub-pixel in four sub-pixel area can be identical, also can be different, arrange according to the needs of concrete panel designs.
Wherein, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes, and namely the first sub-pixel area and the 3rd sub-pixel area comprise respectively the sub-pixel of two row two row; Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix, and namely the second sub-pixel area and the 4th sub-pixel area comprise respectively the sub-pixel of a line four row.Wherein, as shown in figure 12, described the first sub-pixel area L1 comprises and is arranged in order clockwise the first sub-pixel P1, the second sub-pixel P2, the 3rd sub-pixel P3, the 4th sub-pixel P4; Described the second sub-pixel area L2 comprises the 5th sub-pixel P5, the 6th sub-pixel P6, the 7th sub-pixel P7 and the 8th sub-pixel P8 being arranged in order from the direction away from the first sub-pixel area L1; Described the 3rd sub-pixel area L3 comprises the 9th sub-pixel P9, the tenth sub-pixel P10, the 11 sub-pixel P11 and the 12 sub-pixel P12 being arranged in order clockwise; Described the 4th sub-pixel area L4 comprises the 13 sub-pixel P13, the 14 sub-pixel P14, the 15 sub-pixel P15 and the 16 sub-pixel P16 being arranged in order from the direction away from the 3rd sub-pixel area L3.
This is an embodiment of the present embodiment, the embodiment of the present embodiment can also be, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes, and namely the first sub-pixel area and the 3rd sub-pixel area comprise respectively the sub-pixel of two row two row; Described the second sub-pixel area and the 4th sub-pixel area comprise 4 * 1 sub-pixel matrixes, and namely the second sub-pixel area and the 4th sub-pixel area comprise respectively the sub-pixel of four lines one row.
In the present embodiment, described pixel cell comprises: 16 thin film transistor (TFT)s, be arranged at respectively described in each in sub-pixel, and in each sub-pixel, there is a thin film transistor (TFT), each thin film transistor (TFT) comprises source electrode and drain electrode.As can be seen from Figure 12, these 16 thin film transistor (TFT)s are T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, and are arranged at respectively described in each in sub-pixel.
Described pixel cell also comprises four gate lines and five data lines, wherein said four gate lines comprise first grid polar curve, second gate line, the 3rd gate line and the 4th gate line, and described five data lines comprise the first data line, the second data line, the 3rd data line, the 4th data line and the 5th data line.Described gate line and data line are electrically connected to respectively at described thin film transistor (TFT); Wherein, the thin film transistor (TFT) being electrically connected to same gate line in same pixel region, is electrically connected to respectively at different data lines.As shown in Figure 12, described gate line is horizontal direction, and described data line is vertical direction; This pixel cell comprises four gate lines, respectively first grid polar curve G1, second gate line G2, the 3rd gate lines G 3 and the 4th gate lines G 4, described pixel cell comprises five data lines on vertical direction, comprise tactic the first data line D1, the second data line D2, the 3rd data line D3, the 4th data line D4, the 5th data line D5, described gate line and data line are electrically connected to described thin film transistor (TFT) respectively.
Wherein, described the first sub-pixel area L1 and the second sub-pixel area L2 are between first grid polar curve G1 and second gate line G2; Described the 3rd sub-pixel area L3 and the 4th sub-pixel area L4 are between the 3rd gate lines G 3 and the 4th gate lines G 4; Described gate line and data line are electrically connected to described pixel switch respectively; Described pixel switch is thin film transistor (TFT).
Described first grid polar curve G1 is electrically connected to the first sub-pixel P1, the second sub-pixel P2, the 6th sub-pixel P6 and the 8th sub-pixel P8; Described second gate line G2 is electrically connected to the 3rd sub-pixel P3, the 4th sub-pixel P4, the 5th sub-pixel P5 and the 7th sub-pixel P7; Described the 3rd gate lines G 3 is electrically connected to the 9th sub-pixel P9, the tenth sub-pixel P10, the 13 sub-pixel P13 and the 15 sub-pixel P15; Described the 4th gate lines G 4 is electrically connected to the 11 sub-pixel P11, the 12 sub-pixel P12, the 14 sub-pixel P14 and the 16 sub-pixel P16.
Described the first data line D1 is electrically connected to the 4th sub-pixel P4, the 16 sub-pixel P16; Described the second data line D2 is electrically connected to the first sub-pixel P1, the 3rd sub-pixel P3, the 14 sub-pixel P14, the 15 sub-pixel P15, described the 3rd data line D3 is electrically connected to the second sub-pixel P2, the 5th sub-pixel P5, the 12 sub-pixel P12, the 13 sub-pixel P13, described the 4th data line D4 is electrically connected to the 6th sub-pixel P6, the 7th sub-pixel P7, the 9th sub-pixel P9, the 11 sub-pixel P11, and described the 5th data line D5 is electrically connected to the 8th sub-pixel P8, the tenth sub-pixel P10.
Wherein, the thin film transistor (TFT) being electrically connected to same gate line in same pixel region, is electrically connected to from different data lines respectively.And every data line is electrically connected to the source electrode that is positioned at four thin film transistor (TFT)s of data line both sides.First grid polar curve G1 is electrically connected to the drain electrode of thin film transistor (TFT) T1, T2, T6, T8, second gate line G2 is electrically connected to the drain electrode of thin film transistor (TFT) T3, T4, T5, T7, the 3rd gate lines G 3 is electrically connected to the drain electrode of thin film transistor (TFT) T9, T10, T13, T15, and the 4th gate lines G 4 is electrically connected to the drain electrode of thin film transistor (TFT) T11, T12, T14, T16; The first data line D1 is electrically connected to the source electrode of thin film transistor (TFT) T4 and T16, the second data line D2 is electrically connected to the source electrode of thin film transistor (TFT) T1, T3, T14, T15, the 3rd data line D3 is electrically connected to the source electrode of thin film transistor (TFT) T2, T5, T12, T13, the 4th data line D4 is electrically connected to the source electrode of thin film transistor (TFT) T6, T7, T9, T11, and the 5th data line D5 is electrically connected to the source electrode of thin film transistor (TFT) T8, T10.
In the present invention, described the first sub-pixel area and the 3rd sub-pixel area include two row sub-pixels, and in described two row sub-pixels, every row sub-pixel forms epaulet shape structure; Each sub-pixel in described the second sub-pixel area and the 4th sub-pixel area is epaulet shape structure.In four sub-pixel area, the sub-pixel of described epaulet shape structure bends to same direction.Pixel in described the first sub-pixel area and the 3rd sub-pixel area is the structure on pseudo-two farmlands, and the pixel in the second sub-pixel area and the 4th sub-pixel area is the structure on two farmlands, and seven data lines are linears.Wherein, seven data lines are also arranged to the shape of corresponding broken line.
Be more than one embodiment of the present invention, embodiments of the present invention can also be as shown in figure 13, and the sub-pixel in sub-pixel area can be also vertical bar shaped.
In the present invention, in the different subpixel district of pixel cell, the overbending direction of sub-pixel can be identical, also can be different; And data line can be fold-line-shaped, can be also rectilinear.The multiple bending structure of the sub-pixel of the pixel of these bents in can reference example one.
A kind of display panel is also provided in the present invention, comprises: first substrate, second substrate and the liquid crystal layer between first substrate and second substrate, wherein, described first substrate comprises array base palte as above.
The present invention also provides a kind of display device, comprises display panel as above.
The array base palte providing in the present embodiment, display panel and display device, can realize all good effects of visual angle and transmitance, compares with the pixel of independent list structure, and the decreased number of data line, can reduce costs, and shortens driving time.
The array base palte above embodiment of the present invention being provided, and the display panel that comprises this array base palte and display device are described in detail, applied specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (11)
1. an array base palte, comprise: a plurality of pixel cells, described pixel cell comprises the first main pixel region and the second main pixel region that level is adjacent, wherein, described the first main pixel region comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the first sub-pixel area and the 4th sub-pixel area; Described the second main pixel region comprises vertical two adjacent sub-pixel area, and described two sub-pixel area are the second sub-pixel area and the 3rd sub-pixel area;
The setting adjacent with the second sub-pixel area of described the first sub-pixel area, the 3rd sub-pixel area and the 4th adjacent setting in sub-pixel area;
Described in each, sub-pixel area comprises four sub-pixels;
Wherein, described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes;
Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
2. an array base palte, it is characterized in that, comprise: a plurality of pixel cells, described pixel cell comprises 2 * 2 sub-pixel area matrixes, described 2 * 2 sub-pixel area matrixes are followed successively by the first sub-pixel area, the second sub-pixel area, the 3rd sub-pixel area and the 4th sub-pixel area according to arranged clockwise;
Described in each, sub-pixel area comprises 4 sub-pixels;
Described the first sub-pixel area and the 3rd sub-pixel area comprise 2 * 2 sub-pixel matrixes;
Described the second sub-pixel area and the 4th sub-pixel area comprise 1 * 4 sub-pixel matrix.
3. array base palte according to claim 1 and 2, is characterized in that, described the first sub-pixel area comprises and is arranged in order clockwise the first sub-pixel, the second sub-pixel, the 3rd sub-pixel, the 4th sub-pixel; Described the second sub-pixel area comprises the 5th sub-pixel, the 6th sub-pixel, the 7th sub-pixel and the 8th sub-pixel being arranged in order from the direction away from the first sub-pixel area; Described the 3rd sub-pixel area comprises the 9th sub-pixel, the tenth sub-pixel, the 11 sub-pixel and the 12 sub-pixel being arranged in order clockwise; Described the 4th sub-pixel area comprises the 13 sub-pixel, the 14 sub-pixel, the 15 sub-pixel and the 16 sub-pixel being arranged in order from the direction away from the 3rd sub-pixel area.
4. array base palte according to claim 3, is characterized in that, described pixel cell comprises: 16 pixel switches, are arranged at respectively described in each in sub-pixel;
With three gate lines, described gate line is first grid polar curve, second gate line and the 3rd gate line;
With seven data line the first data lines, the second data line, the 3rd data line, the 4th data line, the 5th data line, the 6th data line and the 7th data line;
Described first grid polar curve is electrically connected to described the first sub-pixel, the second sub-pixel, the 5th sub-pixel, the 6th sub-pixel, the 7th sub-pixel and the 8th sub-pixel; Described second gate line is electrically connected to the 3rd sub-pixel, the 4th sub-pixel, the 9th sub-pixel and the tenth sub-pixel; Described the 3rd gate line is electrically connected to the 11 sub-pixel, the 12 sub-pixel, the 13 sub-pixel, the 14 sub-pixel, the 15 sub-pixel and the 16 sub-pixel;
Described the first data line is electrically connected to the 16 sub-pixel; Described the second data line is electrically connected to the first sub-pixel, the 4th sub-pixel, the 15 sub-pixel, described the 3rd data line is electrically connected to the second sub-pixel, the 3rd sub-pixel, the 14 sub-pixel, described the 4th data line is electrically connected to the 5th sub-pixel, the 13 sub-pixel, described the 5th data line is electrically connected to the 6th sub-pixel, the 9th sub-pixel, the 12 sub-pixel, described the 6th data line is electrically connected to the 7th sub-pixel, the tenth sub-pixel, the 11 sub-pixel, and described the 7th data line is electrically connected to the 8th sub-pixel.
5. array base palte according to claim 4, is characterized in that, described the first sub-pixel area and the second sub-pixel area are between first grid polar curve and second gate line; Described the 3rd sub-pixel area and the 4th sub-pixel area are between second gate line and the 3rd gate line; Described gate line and data line are electrically connected to described pixel switch respectively; Wherein, the pixel switch being electrically connected to same gate line in same sub-pixel area, is electrically connected to from different data lines respectively.
6. array base palte according to claim 3, is characterized in that, described pixel cell comprises: 16 pixel switches, are arranged at respectively described in each in sub-pixel;
With four gate lines, described gate line is first grid polar curve, second gate line, the 3rd gate line and the 4th gate line;
With five data line the first data lines, the second data line, the 3rd data line, the 4th data line and the 5th data line;
Described first grid polar curve is electrically connected to the first sub-pixel, the second sub-pixel, the 6th sub-pixel and the 8th sub-pixel; Described second gate line is electrically connected to the 3rd sub-pixel, the 4th sub-pixel, the 5th sub-pixel and the 7th sub-pixel; Described the 3rd gate line is electrically connected to the 9th sub-pixel, the tenth sub-pixel, the 13 sub-pixel and the 15 sub-pixel; Described the 4th gate line is electrically connected to the 11 sub-pixel, the 12 sub-pixel, the 14 sub-pixel and the 16 sub-pixel;
Described the first data line is electrically connected to the 4th sub-pixel, the 16 sub-pixel; Described the second data line is electrically connected to the first sub-pixel, the 3rd sub-pixel, the 14 sub-pixel, the 15 sub-pixel, described the 3rd data line is electrically connected to the second sub-pixel, the 5th sub-pixel, the 12 sub-pixel, the 13 sub-pixel, described the 4th data line is electrically connected to the 6th sub-pixel, the 7th sub-pixel, the 9th sub-pixel, the 11 sub-pixel, and described the 5th data line is electrically connected to the 8th sub-pixel, the tenth sub-pixel.
7. array base palte according to claim 6, is characterized in that, described the first sub-pixel area and the second sub-pixel area are between first grid polar curve and second gate line; Described the 3rd sub-pixel area and the 4th sub-pixel area are between the 3rd gate line and the 4th gate line; Described gate line and data line are electrically connected to described pixel switch respectively; Wherein, the pixel switch being electrically connected to same gate line in same sub-pixel area, is electrically connected to from different data lines respectively.
8. dot structure according to claim 1, is characterized in that, the sub-pixel in described four pixel regions is respectively red sub-pixel, green sub-pixels, blue subpixels and white sub-pixels.
9. dot structure according to claim 1, is characterized in that, described the first sub-pixel area and the 3rd sub-pixel area include two row sub-pixels, and in described two row sub-pixels, every row sub-pixel forms epaulet shape structure; Each sub-pixel in described the second sub-pixel area and the 4th sub-pixel area is epaulet shape structure.
10. a display panel, is characterized in that, comprising: first substrate, second substrate and the liquid crystal layer between first substrate and second substrate, wherein, described first substrate comprises the array base palte as described in claim 1-9 any one.
11. 1 kinds of display device, is characterized in that, comprise that profit requires the display panel described in 10.
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