CN104777639A - Array substrate and driving method, display panel and display device thereof - Google Patents

Array substrate and driving method, display panel and display device thereof Download PDF

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Publication number
CN104777639A
CN104777639A CN201510227950.2A CN201510227950A CN104777639A CN 104777639 A CN104777639 A CN 104777639A CN 201510227950 A CN201510227950 A CN 201510227950A CN 104777639 A CN104777639 A CN 104777639A
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CN
China
Prior art keywords
sub
line
pix
gate line
array base
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CN201510227950.2A
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Chinese (zh)
Inventor
尹岩岩
吴昊
邢红燕
崔子巍
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to CN201510227950.2A priority Critical patent/CN104777639A/en
Publication of CN104777639A publication Critical patent/CN104777639A/en

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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306Circuit arrangements or driving methods for the control of single liquid crystal cells
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1339Gaskets; Spacers; Sealing of cells
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3603Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals with thermally addressed liquid crystals

Abstract

The invention discloses an array substrate and a driving method, a display panel and a display device thereof, and is used for reducing the occurrence of undesirable cross color and improving the brightness of a product. The array substrate comprises multiple pixel units arranged in arrays, multiple data lines connected with a source driving integrated circuit and multiple gate lines connected with a gate driving integrated circuit; each pixel unit comprises a red pixel, a green pixel, a blue pixel and a fourth pixel besides the color of red, green and blue, and each sub pixel is correspondingly connected with a thin film transistor; in each pixel unit, four kinds of sub pixels are divided into a first sub pixel unit group and a second sub pixel unit group which are arranged in a mirror symmetry mode in the vertical direction, each group comprises two pixels, and the requirement that a corresponding region of the red pixel is not adjacent to a corresponding region of the green pixel is met; one or more the gate lines are distributed between any two adjacent sub pixel groups in the vertical direction.

Description

A kind of array base palte and driving method, display panel, display device

Technical field

The present invention relates to display technique field, particularly relate to a kind of array base palte and driving method, display panel, display device.

Background technology

Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) be at present conventional flat-panel monitor, TFT-LCD display with its low-voltage, low-power consumption, be suitable for that circuit is integrated, the light and handy advantage such as portable and be subject to research and apply widely.

As shown in Figure 1, the array base palte of prior art comprises the pixel cell of some arrayed, the some data line Data1 be connected with source electrode driven integrated circuit, Data2 etc., the some gate lines G ate1 be connected with grid-driving integrated circuit, Gate2 etc., wherein, each pixel cell comprises red (R), green (G) and blue (B) three kinds of sub-pixs, R, G, B sub-pix is horizontal word order, each sub-pix is all corresponding connects a thin film transistor (TFT), the source electrode correspondence of this thin film transistor (TFT) connects data (Data) line, the grid correspondence of this thin film transistor (TFT) connects grid (Gate) line.

When the array base palte shown in Fig. 1 and color membrane substrates being carried out become display panel to box-like, due to the impact on cartridge device etc., can there is skew to a certain degree to array base palte during box and color membrane substrates contraposition, colour contamination phenomenon can be produced when G sub-pix offsets more on R sub-pix direction, when producing colour contamination, display panel yellowing phenomenon is more obvious, and prior art is along with display panel resolution (Pixel Per Inch, PPI) progressively raising, colour contamination becomes one of more and more general bad phenomenon.

In sum, prior art can produce colour contamination phenomenon in various degree due to array base palte and color membrane substrates contraposition skew.

Summary of the invention

Embodiments provide a kind of array base palte and driving method, display panel, display device, in order to reduce the bad generation of colour contamination, improve the brightness of product.

A kind of array base palte that the embodiment of the present invention provides, comprise the pixel cell of some arrayed, the some data lines be connected with source electrode driven integrated circuit and the some gate lines be connected with grid-driving integrated circuit, wherein, pixel cell described in each comprises red, green, blue and except red, green, the 4th kind of sub-pix outside basket, each sub-pix is all corresponding connects a thin film transistor (TFT), in pixel cell described in each: four kinds of sub-pixs are divided into the first sub-pixel unit group and the second sub-pixel unit group of two in the vertical direction specular arrangements, often group comprises two kinds of sub-pixs, and the region meeting region corresponding to red sub-pix corresponding with green sub-pix is non-conterminous,

At least one gate line is distributed with between two described sub-pixel unit groups of in the vertical direction arbitrary neighborhood.

The array base palte provided by the embodiment of the present invention, comprise the pixel cell of some arrayed, the some data lines be connected with source electrode driven integrated circuit and the some gate lines be connected with grid-driving integrated circuit, wherein, pixel cell described in each comprises red, green, blue and except red, green, the 4th kind of sub-pix outside basket, each sub-pix is all corresponding connects a thin film transistor (TFT), in pixel cell described in each: four kinds of sub-pixs are divided into the first sub-pixel unit group and the second sub-pixel unit group of two in the vertical direction specular arrangements, often group comprises two kinds of sub-pixs, and the region meeting region corresponding to red sub-pix corresponding with green sub-pix is non-conterminous, at least one gate line is distributed with between two described sub-pixel unit groups of in the vertical direction arbitrary neighborhood.Due in array base palte design, the region corresponding with green sub-pix, the region that red sub-pix is corresponding is non-conterminous, thus effectively reduce the bad generation of colour contamination, and owing to adding the 4th kind of sub-pix, therefore the transmitance of array base palte can get a promotion, the brightness of the effective improving product of energy while reducing colour contamination.

Preferably, size, the shape of four sub-pixs in pixel cell described in each are identical; The color arrangement of the sub-pix of pixel cell described in each is identical.

Preferably, the shape of sub-pix described in each is triangle.

Preferably, described gate line comprises first grid polar curve and second gate line, and for pixel cell described in every a line, two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect described second gate line, described first grid polar curve and described second gate line are adjacent gate line; Or,

Described gate line comprises first grid polar curve, second gate line and the 3rd gate line, and for pixel cell described in every a line, two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect described second gate line and described 3rd gate line respectively; Or two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve and described second gate line respectively, position under the second sub-pixel unit group in two sub-pixs connect described 3rd gate lines; Described first grid polar curve, described second gate line and described 3rd gate line are adjacent gate line.

Preferably, described 4th kind of sub-pix is white sub-pix or yellow sub-pix.

The embodiment of the present invention additionally provides a kind of display panel, comprises the array base palte and color membrane substrates that are oppositely arranged, and the liquid crystal layer between described array base palte and described color membrane substrates, and wherein, described array base palte is above-mentioned array base palte.

Preferably, also comprise the chock insulator matter be positioned on described array base palte, the region of the orthogonal projection of described chock insulator matter on described array base palte between any two sub-pixs.

The embodiment of the present invention additionally provides a kind of display device, and this display device comprises above-mentioned display panel.

The embodiment of the present invention additionally provides a kind of driving method of above-mentioned array base palte, and described method comprises:

Grid-driving integrated circuit drives the gate line be connected with one-row pixels unit line by line by scanning sequency, the thin film transistor (TFT) conducting be successively connected with the sub-pix in every a line pixel cell;

Source electrode driven integrated circuit exports source electrode drive singal to the source electrode of the thin film transistor (TFT) with conducting or the data line be connected that drains, and is transferred to connected sub-pix by the thin film transistor (TFT) of this conducting.

Preferably, described grid-driving integrated circuit drives the gate line be connected with one-row pixels unit line by line by scanning sequency, comprising:

Using adjacent two gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency; Or,

Using adjacent three gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency.

Accompanying drawing explanation

Fig. 1 is the planar structure schematic diagram of prior art array base palte;

The planar structure schematic diagram of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention;

The planar structure schematic diagram of another array base palte that Fig. 3 provides for the embodiment of the present invention;

The cross section structure schematic diagram of a kind of display panel that Fig. 4 provides for the embodiment of the present invention;

The driving method process flow diagram of a kind of array base palte that Fig. 5 provides for the embodiment of the present invention.

Embodiment

Embodiments provide a kind of array base palte and driving method, display panel, display device, in order to reduce the bad generation of colour contamination, improve the brightness of product.

In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.

The array base palte that the specific embodiment of the invention provides is introduced in detail below in conjunction with accompanying drawing.

As shown in Figure 2, the specific embodiment of the invention provides a kind of array base palte, comprise the pixel cell 20 of some arrayed, the some data line Data1 be connected with source electrode driven integrated circuit, Data2 etc., and the some gate lines G ate1 to be connected with grid-driving integrated circuit, Gate2 etc., wherein, each pixel cell 20 comprises red (R), green (G), blue (B) and except red, green, the 4th kind of sub-pix outside basket, preferably, the 4th kind of sub-pix in the specific embodiment of the invention is white (W) sub-pix or Huang (Y) sub-pix, the specific embodiment of the invention compared with prior art, the 4th kind of sub-pix newly increased only illustrates for W sub-pix, certainly, in actual design, the 4th kind of sub-pix newly increased is not limited to W sub-pix and Y sub-pix, each sub-pix is all corresponding connects a thin film transistor (TFT) 21,

In each pixel cell 20: four kinds of sub-pixs are divided into the first sub-pixel unit group 201 and the second sub-pixel unit group 202 of two in the vertical direction specular arrangements, often group comprises two kinds of sub-pixs, and the region meeting region corresponding to R sub-pix corresponding with G sub-pix is non-conterminous; At least one gate line is distributed with between two sub-pixel unit groups of in the vertical direction arbitrary neighborhood.

Preferably, size, the shape of four sub-pixs in the specific embodiment of the invention in each pixel cell are identical; The color arrangement of the sub-pix of each pixel cell is identical.

The concrete setting of four sub-pixs in the specific embodiment of the invention in each pixel cell as shown in Figures 2 and 3, for the first row, first row pixel cell, R sub-pix is positioned at the lower left corner in the region that the first row gate lines G ate1 and the second row gate lines G ate2 and first row data line Data1 and secondary series data line Data2 forms; B sub-pix is positioned at the upper right corner in the region that the first row gate lines G ate1 and the second row gate lines G ate2 and first row data line Data1 and secondary series data line Data2 forms; W sub-pix is positioned at the upper left corner in the region that the second row gate lines G ate2 and the third line gate lines G ate3 and first row data line Data1 and secondary series data line Data2 forms; G sub-pix is positioned at the lower right corner in the region that the second row gate lines G ate2 and the third line gate lines G ate3 and first row data line Data1 and secondary series data line Data2 forms.Certainly, in actual design, the position of each sub-pix is not limited to the position of Fig. 2 and Fig. 3, as: R sub-pix is positioned at the upper right corner in the region that the first row gate lines G ate1 and the second row gate lines G ate2 and first row data line Data1 and secondary series data line Data2 forms; B sub-pix is positioned at the lower left corner in the region that the first row gate lines G ate1 and the second row gate lines G ate2 and first row data line Data1 and secondary series data line Data2 form, as long as ensure that when designing the region corresponding with G sub-pix, region that R sub-pix is corresponding is non-conterminous.The concrete setting of four sub-pixs in the concrete setting of four sub-pixs in other pixel cell and the first row, first row pixel cell is similar, repeats no more here.

Preferably, the shape of each sub-pix in the specific embodiment of the invention is triangle, as shown in Figures 2 and 3, R sub-pix, B sub-pix, G sub-pix and W sub-pix are designed specifically to right-angle triangle by the specific embodiment of the invention, when R sub-pix, B sub-pix, G sub-pix and W sub-pix distribute by the mode shown in figure, convenient in actual production process, easy.R sub-pix, B sub-pix, G sub-pix and W sub-pix are designed to right-angle triangle by the specific embodiment of the invention, be designed to rectangular shape with W sub-pix compare with by R sub-pix, B sub-pix, G sub-pix, more effectively can reduce the bad generation of colour contamination.Because R sub-pix is away from G sub-pix in the specific embodiment of the invention, even if R sub-pix deflection B sub-pix, because red and blueness are mixed into purple, red relative with the colour system of purple close, old friend's eye not too easily identifies, therefore, the arrangement of specific embodiment of the invention sub-pix can reduce because contraposition offsets the obvious colour contamination produced.

Preferably, in the specific embodiment of the invention, gate line comprises first grid polar curve, second gate line and the 3rd gate line, and for every a line pixel cell, two sub-pixs of position in the first upper sub-pixel unit group connect first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect second gate line and the 3rd gate line respectively; Or two sub-pixs of position in the first upper sub-pixel unit group connect first grid polar curve and second gate line respectively, position under the second sub-pixel unit group in two sub-pixs connect the 3rd gate lines; First grid polar curve, second gate line and the 3rd gate line are adjacent gate line.

Particularly, as shown in Figure 2, in the specific embodiment of the invention, gate line comprises the first grid polar curve Gate1, Gate4 etc., second gate line Gate2, Gate5 etc. and the 3rd gate lines G ate3, Gate6 etc., for the first row pixel cell, two sub-pix R with B of position in the first upper sub-pixel unit group are connected first grid polar curve Gate1; Position under the second sub-pixel unit group in sub-pix W connect second gate line Gate2, position under the second sub-pixel unit group in sub-pix G connect the 3rd gate lines G ate3.Sub-pix in the annexation of the sub-pix in the pixel cell of other row and gate line and the first row pixel cell is identical with the annexation of gate line, repeats no more here.For the connected mode shown in Fig. 2, when needs display grey menu, the first row gate lines G ate1, the second row gate lines G ate2 and the third line gate lines G ate3 must receive raster data model sweep signal simultaneously, fourth line gate lines G ate4, fifth line gate lines G ate5 and the 6th row gate lines G ate6 must receive next line raster data model sweep signal simultaneously, display grey menu that the rest may be inferred.

Preferably, in the specific embodiment of the invention, gate line comprises first grid polar curve and second gate line, and for every a line pixel cell, two sub-pixs of position in the first upper sub-pixel unit group connect first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect second gate lines, first grid polar curve and second gate line are adjacent gate line.

Particularly, as shown in Figure 3, in the specific embodiment of the invention, gate line comprises the first grid polar curve Gate1, Gate3 etc. and second gate line Gate2, Gate4 etc., for the first row pixel cell, two sub-pix R with B of position in the first upper sub-pixel unit group are connected first grid polar curve Gate1, position under the second sub-pixel unit group in two sub-pix W with G be connected second gate line Gate2.Sub-pix in the annexation of the sub-pix in the pixel cell of other row and gate line and the first row pixel cell is identical with the annexation of gate line, repeats no more here.For the connected mode shown in Fig. 3, when needs display grey menu, the first row gate lines G ate1 and the second row gate lines G ate2 must receive raster data model sweep signal simultaneously, the third line gate lines G ate3 and fourth line gate lines G ate4 must receive next line raster data model sweep signal simultaneously, display grey menu that the rest may be inferred.

As shown in Figure 4, the specific embodiment of the invention additionally provides a kind of display panel, comprise the array base palte 41 and color membrane substrates 42 that are oppositely arranged, and the liquid crystal layer 43 between array base palte 41 and color membrane substrates 42, wherein, the above-mentioned array base palte that provides for the specific embodiment of the invention of array base palte 41.

Preferably, the display panel that the specific embodiment of the invention provides also comprises the chock insulator matter 44 be positioned on array base palte 41, the region of the orthogonal projection of chock insulator matter 44 on array base palte 41 between any two sub-pixs, wherein, the region between any two sub-pixs on array base palte 41 is see Fig. 2 and Fig. 3.

The specific embodiment of the invention additionally provides a kind of display device, comprise above-mentioned display panel, this display device can be the display device such as liquid crystal panel, liquid crystal display, LCD TV, Organic Light Emitting Diode (Organic LightEmitting Diode, OLED) panel, OLED display, OLED TV or Electronic Paper.

As shown in Figure 5, the specific embodiment of the invention additionally provides a kind of driving method of array base palte, and the method comprises:

S501, grid-driving integrated circuit drive the gate line be connected with one-row pixels unit line by line by scanning sequency, the thin film transistor (TFT) conducting be successively connected with the sub-pix in every a line pixel cell;

S502, source electrode driven integrated circuit export source electrode drive singal to the source electrode of the thin film transistor (TFT) with conducting or the data line be connected that drains, and are transferred to connected sub-pix by the thin film transistor (TFT) of this conducting.

Preferably, in the specific embodiment of the invention, grid-driving integrated circuit drives the gate line be connected with one-row pixels unit line by line by scanning sequency, comprising:

Using adjacent two gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency, as shown in Figure 3, using the first row gate lines G ate1 and the second row gate lines G ate2 as a gate line unit, using the third line gate lines G ate3 and fourth line gate lines G ate4 as a gate line unit, the rest may be inferred; Or,

Using adjacent three gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency, as shown in Figure 2, using the first row gate lines G ate1, the second row gate lines G ate2 and the third line gate lines G ate3 as a gate line unit, using fourth line gate lines G ate4, fifth line gate lines G ate5 and the 6th row gate lines G ate6 as a gate line unit, the rest may be inferred.

In sum, the specific embodiment of the invention provides a kind of array base palte and driving method thereof, display panel, display device, array base palte comprises the pixel cell of some arrayed, the some data lines be connected with source electrode driven integrated circuit and the some gate lines be connected with grid-driving integrated circuit, wherein, pixel cell described in each comprises red, green, blue and except red, green, the 4th kind of sub-pix outside basket, each sub-pix is all corresponding connects a thin film transistor (TFT), in pixel cell described in each: four kinds of sub-pixs are divided into the first sub-pixel unit group and the second sub-pixel unit group of two in the vertical direction specular arrangements, often group comprises two kinds of sub-pixs, and the region meeting region corresponding to red sub-pix corresponding with green sub-pix is non-conterminous, at least one gate line is distributed with between two described sub-pixel unit groups of in the vertical direction arbitrary neighborhood.Due in array base palte design, the region corresponding with green sub-pix, the region that red sub-pix is corresponding is non-conterminous, thus effectively reduce the bad generation of colour contamination, and owing to adding the 4th kind of sub-pix, therefore the transmitance of array base palte can get a promotion, while reducing colour contamination, the brightness of the effective improving product of energy, can reduce the quantity of backlight light emitting diode further, thus realizes the object reducing production cost.

Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims (10)

1. an array base palte, comprise the pixel cell of some arrayed, the some data lines be connected with source electrode driven integrated circuit and the some gate lines be connected with grid-driving integrated circuit, it is characterized in that, pixel cell described in each comprises red, green, blue and except red, green, the 4th kind of sub-pix outside basket, each sub-pix is all corresponding connects a thin film transistor (TFT), in pixel cell described in each: four kinds of sub-pixs are divided into the first sub-pixel unit group and the second sub-pixel unit group of two in the vertical direction specular arrangements, often group comprises two kinds of sub-pixs, and the region meeting region corresponding to red sub-pix corresponding with green sub-pix is non-conterminous,
At least one gate line is distributed with between two described sub-pixel unit groups of in the vertical direction arbitrary neighborhood.
2. array base palte according to claim 1, is characterized in that, size, the shape of four sub-pixs in pixel cell described in each are identical; The color arrangement of the sub-pix of pixel cell described in each is identical.
3. array base palte according to claim 2, is characterized in that, the shape of sub-pix described in each is triangle.
4. array base palte according to claim 1, it is characterized in that, described gate line comprises first grid polar curve and second gate line, and for pixel cell described in every a line, two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect described second gate line, described first grid polar curve and described second gate line are adjacent gate line; Or,
Described gate line comprises first grid polar curve, second gate line and the 3rd gate line, and for pixel cell described in every a line, two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve; Position under the second sub-pixel unit group in two sub-pixs connect described second gate line and described 3rd gate line respectively; Or two sub-pixs of position in the first upper sub-pixel unit group connect described first grid polar curve and described second gate line respectively, position under the second sub-pixel unit group in two sub-pixs connect described 3rd gate lines; Described first grid polar curve, described second gate line and described 3rd gate line are adjacent gate line.
5. array base palte according to claim 1, is characterized in that, described 4th kind of sub-pix is white sub-pix or yellow sub-pix.
6. a display panel, comprises the array base palte and color membrane substrates that are oppositely arranged, and the liquid crystal layer between described array base palte and described color membrane substrates, it is characterized in that, described array base palte is the array base palte described in the arbitrary claim of claim 1-5.
7. display panel according to claim 6, is characterized in that, also comprises the chock insulator matter be positioned on described array base palte, the region of the orthogonal projection of described chock insulator matter on described array base palte between any two sub-pixs.
8. a display device, is characterized in that, described display device comprises the display panel described in the arbitrary claim of claim 6-7.
9. a driving method for the array base palte as described in claim as arbitrary in claim 1-5, is characterized in that, described method comprises:
Grid-driving integrated circuit drives the gate line be connected with one-row pixels unit line by line by scanning sequency, the thin film transistor (TFT) conducting be successively connected with the sub-pix in every a line pixel cell;
Source electrode driven integrated circuit exports source electrode drive singal to the source electrode of the thin film transistor (TFT) with conducting or the data line be connected that drains, and is transferred to connected sub-pix by the thin film transistor (TFT) of this conducting.
10. driving method according to claim 9, is characterized in that, described grid-driving integrated circuit drives the gate line be connected with one-row pixels unit line by line by scanning sequency, comprising:
Using adjacent two gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency; Or,
Using adjacent three gate lines as a gate line unit, grid-driving integrated circuit drives described gate line unit line by line by scanning sequency.
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Application publication date: 20150715