KR102456941B1 - Liquid crystal display device - Google Patents

Abstract

In order to provide a DRD type liquid crystal display capable of preventing display quality deterioration, the present invention is disposed between the first and second sub-pixels arranged in one row and the third and fourth sub-pixels arranged in a second row. a pair of n-th (n is an integer greater than or equal to 1) gate wiring, an (n+1)-th gate wiring disposed between the pair of n-th gate wirings, n-th and (n+1)-th gate wirings; first and second data lines intersecting and disposed on the left side of the first and third subpixels arranged in the first column and on the right side of the second and fourth subpixels arranged on the second column, respectively, the second and fourth thin film transistors is connected to the n-th gate wiring, the first and third thin film transistors are connected to the (n+1)-th gate wiring, the first and second thin film transistors are connected to the first data line, and the third and fourth thin film transistors are connected to the first data line. The transistor is connected to the second data line, the first and second thin film transistors are connected to the second data line, and the third and fourth thin film transistors are connected to the first data line.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display, and to a DRD type liquid crystal display capable of preventing deterioration of display quality and reducing power consumption.

The liquid crystal display device includes a liquid crystal display panel on which an image is displayed. When the liquid crystal display panel is driven, the inversion driving method is driven by inverting the polarity in a certain unit to prevent deterioration of the liquid crystal and improve the display quality of the image. It is common to use

The inversion driving method is classified into a frame inversion method, a column inversion method, and a dot inversion method according to a unit in which the polarity is inverted.

The liquid crystal display device includes a gate driver for driving the gate lines and a data driver for driving the data lines. As the size and resolution of the liquid crystal display increases, the number of data driver ICs included in the data driver increases.

However, since data driver ICs are relatively expensive compared to other devices, various methods for reducing the number of data driver ICs have been recently researched and developed. A DRD (Double Rate Driving) method that reduces the number of data driving ICs by half, reducing the number of required data driving ICs by half, and implementing the same resolution as the existing ones, has been proposed.

FIG. 1 is a diagram illustrating a conventional DRD liquid crystal display driven by a column inversion method, and FIG. 2 is a diagram illustrating a conventional DRD liquid crystal display driven by a 4-dot inversion method.

1 and 2, the conventional DRD type liquid crystal display device includes first to 32nd thin film transistors T1 to T32, respectively, and the first to 32nd subpixels SP1 are arranged in 4 rows and 8 columns. to SP32), first to eighth gate lines GL1 to GL8, and first to fifth data lines DL1 to DL5.

In addition, the first to 32nd sub-pixels SP1 to SP32 display any one color among red (R), green (G), blue (B), and white (W), and adjacent to each other, red (R), Four sub-pixels displaying green (G), blue (B), and white (W) are gathered to form one unit pixel.

Meanwhile, although the first to 32nd subpixels SP1 to SP32 are illustrated as being arranged in 4 rows and 8 columns in the drawing, a larger number of subpixels may be arranged in multiple rows and columns.

In addition, the first and second gate wirings GL1 and GL2 are respectively disposed above and below the subpixels SP1 to SP8 arranged in one row, and the third and fourth gate wirings GL3 and GL4 are It is disposed above and below the sub-pixels SP9 to SP16 arranged in the second row, respectively, and the fifth and sixth gate wirings GL5 and GL6 are arranged above the sub-pixels SP17 to SP24 arranged in the third row. and the lower side, respectively, and the seventh and eighth gate wirings GL7 and GL8 are respectively disposed above and below the sub-pixels SP25 to SP32 arranged in the fourth row.

Also, the first to fifth data lines DL1 to DL5 intersect the first to eighth gate lines GL1 to GL8, and the first data line DL1 includes the sub-pixels SP1 and SP9 arranged in one column. . SP27), and the third data line DL3 is between the subpixels SP4, SP12, SP20, and SP28 arranged in the fourth column and the subpixels SP5, SP13, SP21, and SP29 arranged in the fifth column. and the fourth data line DL4 is disposed between the sub-pixels SP6, SP14, SP22, and SP30 arranged in the sixth column and the sub-pixels SP7, SP15, SP23, and SP31 arranged in the seventh column, The fifth data line DL5 is disposed on the right side of the sub-pixels SP8, SP16, SP24, and SP32 disposed in the eighth column.

In addition, the first gate line GL1 is connected to the first, third, fifth and seventh thin film transistors T1, T3, T5, and T7, and the second gate line GL2 is connected to the second, fourth, It is connected to the sixth and eighth thin film transistors T2, T4, T6, and T8, and the third gate wiring GL3 is connected to the ninth, eleventh, thirteenth and fifteenth thin film transistors T9, T11, T13, and T15. and the fourth gate wiring GL4 is connected to the 10th, 12th, 14th and 16th thin film transistors T10, T12, T14, and T16, and the fifth gate wiring GL5 is connected to the 17th and 16th thin film transistors T10, T12, T14, T16. It is connected to the 19th, 21st and 23rd thin film transistors T17, T19, T21, and T23, and the sixth gate wiring GL6 is connected to the 18th, 20th, 22nd and 24th thin film transistors T18, T20, T22, T24), the seventh gate wiring GL7 is connected to the 25th, 27th, 29th and 31st thin film transistors T25, T27, T29, T31, and the eighth gate wiring GL8 is the 26th , 28, 30 and 32 are connected to the thin film transistors (T26, T28, T30, T32).

In addition, the first data line DL1 is connected to the first, ninth, 17th, and 25th thin film transistors T1, T9, T17, and T25, and the second data line DL2 is connected to the second, third, The 10th, 11th, 18th, 19th, 26th and 27th thin film transistors T2, T3, T10, T11, T18, T19, T26, T27 are connected to each other, and the third data line DL3 is connected to the fourth , 5th, 12th, 13th, 20th, 21st, 28th and 29th thin film transistors T4, T5, T12, T13, T20, T21, T28, T29 are connected to, and a fourth data line DL4 ) is connected to the 6th, 7th, 14th, 15th, 22nd, 23rd, 30th and 31st thin film transistors (T6, T7, T14, T15, T22, T23, T30, T31), and a fifth The data line DL5 is connected to the eighth, sixteenth, twenty-fourth and thirty-second thin film transistors T8, T16, T24, and T32.

When the conventional DRD type liquid crystal display is driven by the column inversion method, the odd-numbered data line and the even-numbered data line supply data voltages of different polarities for one frame.

For example, as shown in FIG. 1 , the first, third, and fifth data lines DL1 , DL3 and DL5 supply positive (+) data voltages, and the second, fourth, and sixth data lines DL1, DL3, and DL5 The data lines DL2, DL4, and DL6 may supply a negative (-) data voltage for one frame.

In this case, the subpixels ((SP1, SP9, SP17, SP25), (SP4, SP12, SP20, SP28), (SP5, SP13, SP21, SP29) arranged in columns 1, 4, 5 and 8; (SP8, SP16, SP24, SP32)) is supplied with a positive (+) data voltage, and subpixels ((SP2, SP10, SP18, SP26) arranged in columns 2, 3, 6, and 7; (SP3, SP11, SP19, SP27), (SP6, SP14, SP22, SP30), (SP7, SP15, SP23, SP31)) are supplied with negative (-) data voltage, causing flicker between vertical lines. This causes the display quality to deteriorate.

In order to prevent such a flicker phenomenon between vertical lines, as shown in FIG. 2 , the conventional DRD type liquid crystal display is driven in a 4-dot inversion method.

As described above, when driving in the 4-dot inversion method, the polarity of the data voltage supplied from each data line is inverted every 4 horizontal periods.

For example, as shown in FIG. 2 , the first data line DL1 has negative polarity (-) data for four horizontal periods in which gate signals are supplied through the third to sixth gate lines GL3 to GL6. After supplying the voltage, a positive (+) data voltage with inverted polarity is supplied for the next 4 horizontal periods.

In addition, the second data line DL2 supplies a positive (+) data voltage for four horizontal periods in which the gate signals are supplied through the fourth to seventh gate lines GL4 to GL7, and then for the next four horizontal periods. A negative polarity (-) data voltage with inverted polarity is supplied.

Similarly, the third to fifth data lines DL3 to DL5 supply data voltages having inverted polarities every 4 horizontal periods.

As described above, the conventional DRD type liquid crystal display is driven in a 4-dot inversion method, thereby minimizing flicker between vertical lines to prevent display quality deterioration.

However, in the 4-dot inversion method, unlike the column inversion method, since the polarity has to be reversed every 4 horizontal periods, power consumption is increased and reliability is deteriorated due to heat generated by the data driving IC.

In particular, since the number of data driving ICs increases as liquid crystal displays increase in size and high resolution, this problem becomes even greater.

An object of the present invention is to provide a liquid crystal display device capable of reducing power consumption and preventing display quality deterioration.

In order to achieve the above object, the present invention includes first to fourth thin film transistors, respectively, and first to fourth sub-pixels arranged in two rows and two columns in a display area, and first to fourth sub-pixels arranged in one row and a pair of nth (n is an integer greater than or equal to 1) gate wiring disposed between the second subpixel and the third and fourth subpixels arranged in the second row, and a pair of nth gate wirings disposed between the pair of nth gate wirings The (n+1) gate wiring intersects the n-th and (n+1)-th gate wirings, on the left side of the first and third sub-pixels arranged in column 1, and on the right side of the second and fourth sub-pixels arranged on the second column. and first and second data lines respectively disposed, the second and fourth thin film transistors are connected to the n-th gate line, and the first and third thin film transistors are connected to the (n+1)-th gate line, The first and second thin film transistors are connected to the first data line and the third and fourth thin film transistors are connected to the second data line, or the first and second thin film transistors are connected to the second data line and connected to the third and third The 4 thin film transistor provides a liquid crystal display connected to the first data line.

Also, among the pair of n-th gate wirings, an n-th gate wiring disposed above the (n+1)-th gate wiring is connected to the second thin film transistor, and an n-th gate wiring disposed below the (n+1)-th gate wiring. The gate wiring is connected to the fourth thin film transistor.

In addition, the n-th gate wiring connected to the second thin film transistor surrounds the gate electrode of the first thin film transistor, and the n-th gate wiring connected to the fourth thin film transistor surrounds the gate electrode of the third thin film transistor.

In addition, the n-th gate wiring connected to the second thin film transistor overlaps the active layer of the first thin film transistor, and the n-th gate wiring connected to the fourth thin film transistor overlaps the active layer of the third thin film transistor.

The present invention has the effect of preventing display quality deterioration by minimizing the flicker phenomenon.

In addition, there is an effect of reducing power consumption by driving in a column inversion method and preventing reliability from being deteriorated due to heat generation of the data driving IC.

1 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a column inversion method.
2 is a diagram illustrating a conventional DRD type liquid crystal display device driven by a 4-dot inversion method.
3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.
4 and 5 are plan views specifically illustrating first to fourth sub-pixels and data and gate wirings connected thereto of a DRD type liquid crystal display according to an embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a DRD type liquid crystal display device according to an embodiment of the present invention.

As shown in the drawing, the DRD type liquid crystal display device according to the embodiment of the present invention includes first to 32th thin film transistors T1 to T32, respectively, and first to 32nd sub-pixels ( SP1 to SP32, first to tenth gate lines GL1 to GL10, and first to fifth data lines DL1 to DL5 are included.

In addition, the first to 32nd sub-pixels SP1 to SP32 display any one color among red (R), green (G), blue (B), and white (W), and adjacent to each other, red (R), Four sub-pixels displaying green (G), blue (B), and white (W) are gathered to form one unit pixel.

Meanwhile, although the first to 32nd subpixels SP1 to SP32 are illustrated as being arranged in 4 rows and 8 columns in the drawing, a larger number of subpixels may be arranged in multiple rows and columns.

In addition, the first gate line GL1 is disposed above the sub-pixels SP1, SP2, SP9, SP10, SP17, SP18, SP25, and SP26 arranged in one row, and the first gate line GL1 is disposed above the first gate line GL1. A second gate line GL2 is disposed.

In addition, subpixels ((SP1, SP2, SP9, SP10, SP17, SP18, SP25, SP26), (SP3, SP4, SP11, SP12, SP19, SP20, SP27, SP28) arranged in rows 1 and 2, respectively ), a pair of third gate wirings GL3 are disposed, and a fourth gate wiring GL4 is disposed between the pair of third gate wirings GL3 .

In addition, subpixels ((SP3, SP4, SP11, SP12, SP19, SP20, SP27, SP28), (SP5, SP6, SP13, SP14, SP21, SP22, SP29, SP30) arranged in rows 2 and 3, respectively ), a pair of fifth gate wirings GL5 are disposed, and a sixth gate wiring GL6 is disposed between the pair of fifth gate wirings GL5 .

In addition, sub-pixels ((SP5, SP6, SP13, SP14, SP21, SP22, SP29, SP30), (SP7, SP8, SP15, SP16, SP23, SP24, SP31, SP32) arranged in rows 3 and 4, respectively ), a pair of seventh gate lines GL7 is disposed, and an eighth gate line GL8 is disposed between the pair of seventh gate lines GL7 .

In addition, the ninth gate line GL9 is disposed below the sub-pixels SP7, SP8, SP15, SP16, SP23, SP24, SP31, and SP32 arranged in the fourth row, and the ninth gate line GL9 is disposed below the ninth gate line GL9. Ten gate lines GL10 are disposed.

Also, the first to fifth data lines DL1 to DL5 intersect the first to tenth gate lines GL1 to GL10, and the first data line DL1 includes the sub-pixels SP1 and SP3 arranged in one column. . SP15), and the third data line DL3 is between the subpixels SP10, SP12, SP14, and SP16 arranged in the fourth column and the subpixels SP17, SP19, SP21, and SP23 arranged in the fifth column. and the fourth data line DL4 is disposed between the sub-pixels SP18, SP20, SP22, and SP24 arranged in the sixth column and the sub-pixels SP25, SP27, SP29, and SP31 arranged in the seventh column, The fifth data line DL5 is disposed on the right side of the sub-pixels SP26 , SP28 , SP30 , and SP32 disposed in the eighth column.

Also, the first gate line GL1 is connected to the ninth and 25th thin film transistors T9 and T25 , and the second gate line GL2 is connected to the tenth and 26th thin film transistors T10 and T26 .

In addition, the third gate wiring GL3 disposed above the fourth gate wiring GL4 among the pair of third gate wirings GL3 is connected to the first and 17th thin film transistors T1 and T17, and a fourth The third gate wiring GL3 disposed below the gate wiring GL4 is connected to the third and 19th thin film transistors T3 and T19, and the fourth gate wiring GL4 is connected to the second, fourth, 18th and It is connected to the twentieth thin film transistors (T2, T4, T18, T20).

In addition, the fifth gate wiring GL5 disposed above the sixth gate wiring GL6 among the pair of fifth gate wirings GL5 is connected to the eleventh and 27th thin film transistors T11 and T27, and a sixth The fifth gate wiring GL5 disposed below the gate wiring GL6 is connected to the thirteenth and 29th thin film transistors T13 and T29, and the sixth gate wiring GL6 is the twelfth, 14th, 28th and It is connected to the thirtieth thin film transistors T12, T14, T28, and T30.

Also, among the pair of seventh gate wirings GL7 , the seventh gate wiring GL7 disposed above the eighth gate wiring GL8 is connected to the fifth and 21st thin film transistors T5 and T21 , and the eighth The seventh gate wiring GL7 disposed below the gate wiring GL8 is connected to the seventh and 23rd thin film transistors T7 and T23 , and the eighth gate wiring GL8 is connected to the sixth, eighth, 22nd and It is connected to the twenty-fourth thin film transistors T6, T8, T22, and T24.

Also, the ninth gate line GL9 is connected to the 15th and 31st thin film transistors T15 and T31 , and the tenth gate line GL10 is connected to the 16th and 32nd thin film transistors T16 and T32 .

In addition, the first data line DL1 is connected to the first, second, seventh and eighth thin film transistors T1, T2, T7, and T8, and the second data line DL2 is connected to the third to sixth and eighth thin film transistors T1, T2, T7, and T8. The ninth to twelfth thin film transistors T3 to T6 and T9 to T12 are connected, and the third data line DL3 includes the 13th to 16th and 19th to 22nd thin film transistors T13 to T16 and T19 to T22. and the fourth data line DL4 is connected to the 17th, 18th, 23rd, 24th and 29th to 32th thin film transistors T17, T18, T23, T24, T29 to T32, and a fifth The data line DL5 is connected to the 25th to 28th thin film transistors T25 to T28.

A DRD type liquid crystal display device according to an embodiment of the present invention is driven in a column inversion method, and data voltages of different polarities are supplied from odd-numbered data lines and even-numbered data lines for one frame.

For example, as shown in the figure, the first, third, and fifth data lines DL1, DL3, and DL5 supply positive (+) data voltages, and the second, fourth, and sixth data lines DL1, DL3, and DL5. The wirings DL2, DL4, and DL6 may supply a negative (-) data voltage for one frame.

Hereinafter, the arrangement of the polarities of the data voltages applied to each sub-pixel of the DRD type liquid crystal display according to the embodiment of the present invention will be described.

First, when the ninth and 25th thin film transistors T9 and T25 are turned on by the gate signal supplied from the first gate line GL1 , the negative polarity (-) data voltage from the second data line DL2 is The ninth sub-pixel SP9 is supplied, and a positive (+) data voltage is supplied from the fifth data line DL5 to the twenty-fifth sub-pixel SP25 .

Next, when the tenth and twenty-sixth thin film transistors T10 and T26 are turned on by the gate signal supplied from the second gate line GL2 , the negative polarity (-) data voltage from the second data line DL2 is The tenth sub-pixel SP10 is supplied with a positive (+) data voltage from the fifth data line DL5 is supplied to the twenty-sixth sub-pixel SP26.

Next, when the first, third, 17th, and 19th thin film transistors T1 , T3 , T17 , and T19 are turned on by the gate signal supplied from the pair of third gate lines GL3 , the first data A positive (+) data voltage is supplied from the line DL1 to the first sub-pixel SP1 , and a negative (-) data voltage is supplied from the second data line DL2 to the third sub-pixel SP3 . is supplied, a positive (+) data voltage is supplied from the third data line DL3 to the 19th subpixel SP19, and a negative (−) data voltage is supplied from the fourth data line DL4 to the 17th subpixel SP19 . It is supplied to the sub-pixel SP17.

Next, when the second, fourth, 18th, and 20th thin film transistors T2, T4, T18, and T20 are turned on by the gate signal supplied from the fourth gate line GL4, the first data line DL1 ), a positive (+) data voltage is supplied to the second sub-pixel SP2, and a negative (-) data voltage is supplied from the second data line DL2 to the fourth sub-pixel SP4, A positive (+) data voltage is supplied from the third data line DL3 to the twentieth sub-pixel SP20 , and a negative (-) data voltage is supplied from the fourth data line DL4 to the eighteenth sub-pixel SP20 . SP18).

Next, when the eleventh, thirteenth, 27th and 29th thin film transistors T11 , T13 , T27 , and T29 are turned on by the gate signal supplied from the pair of fifth gate lines GL5 , the second data A negative (-) data voltage is supplied from the line DL2 to the eleventh sub-pixel SP11 , and a positive (+) data voltage is supplied from the third data line DL3 to the thirteenth sub-pixel SP13 . is supplied, a negative (-) data voltage is supplied from the fourth data line DL4 to the 29th sub-pixel SP29, and a positive (+) data voltage is supplied from the fifth data line DL5 to the 27th sub-pixel SP29. It is supplied to the sub-pixel SP27.

Next, when the twelfth, 14th, 28th, and 30th thin film transistors T12, T14, T28, and T30 are turned on by the gate signal supplied from the sixth gate line GL6, the second data line DL2 ), a negative (-) data voltage is supplied to the twelfth sub-pixel SP12, and a positive (+) data voltage is supplied from the third data line DL3 to the fourteenth sub-pixel SP14, A negative (-) data voltage is supplied to the thirtieth sub-pixel SP30 from the fourth data line DL4, and a positive (+) data voltage is applied from the fifth data line DL5 to the 28th sub-pixel (SP30). SP28).

Next, when the fifth, seventh, twenty-first, and twenty-third thin film transistors T5, T7, T21, and T23 are turned on by the gate signal supplied from the pair of seventh gate lines DL7, the first data A positive (+) data voltage is supplied from the wiring DL1 to the seventh sub-pixel SP7 , and a negative (-) data voltage is supplied from the second data line DL2 to the fifth sub-pixel SP5 . is supplied, a positive (+) data voltage is supplied from the third data line DL3 to the twenty-first sub-pixel SP21, and a negative (-) data voltage is supplied from the fourth data line DL4 to the twenty-third It is supplied to the sub-pixel SP23.

Next, when the sixth, eighth, twenty-second, and twenty-fourth thin film transistors T6, T8, T22, and T24 are turned on by the gate signal supplied from the eighth gate line GL8, the first data line DL1 ), a positive (+) data voltage is supplied to the eighth sub-pixel SP8, and a negative (-) data voltage is supplied from the second data line DL2 to the sixth sub-pixel SP6, A positive (+) data voltage is supplied from the third data line DL3 to the twenty-second sub-pixel SP22, and a negative (-) data voltage is supplied from the fourth data line DL4 to the twenty-fourth sub-pixel (SP22). SP24).

Next, when the fifteenth and thirty-first thin film transistors T15 and T31 are turned on by the gate signal supplied from the ninth gate line GL9, the positive (+) data voltage from the third data line DL3 A data voltage of negative polarity is supplied to the fifteenth sub-pixel SP15 and a negative polarity data voltage is supplied from the fourth data line DL4 to the thirty-first sub-pixel SP31.

Finally, when the 16th and 32nd thin film transistors T16 and T32 are turned on by the gate signal supplied from the 10th gate line GL10, positive (+) data from the third data line DL3 A voltage is supplied to the sixteenth sub-pixel SP16 , and a negative (-) data voltage is supplied from the fourth data line DL4 to the thirty-second sub-pixel SP32 .

As described above, in the DRD type liquid crystal display according to the embodiment of the present invention, since the polarity is inverted every four subpixels in the horizontal direction and the polarity is inverted every two subpixels in the vertical direction, flicker between vertical and horizontal lines is reduced. It can be minimized to prevent deterioration of display quality.

In addition, since the DRD type liquid crystal display device according to the embodiment of the present invention is driven by the column inversion method, power consumption can be reduced compared to the 4-dot inversion method, and reliability is reduced due to heat generated by the data driving IC. can be prevented

4 and 5 are plan views specifically illustrating first to fourth sub-pixels and data and gate wirings connected thereto of a DRD type liquid crystal display according to an embodiment of the present invention.

First, as shown in FIG. 4 , the DRD type liquid crystal display device according to the embodiment of the present invention includes first to fourth subpixels SP1 to SP4 arranged in two rows and two columns, and a pair of nth ( n is an integer greater than or equal to 1) a gate line GLn, an (n+1)th gate line GL(n+1), and first and second data lines DL1 and DL2.

Specifically, the first to fourth sub-pixels SP1 to SP4 include first to fourth thin film transistors T1 to T4, respectively, and include red (R), green (G), blue (B) and white ( W) can be indicated individually.

In addition, it further includes first to fourth pixel electrodes 101 to 104 respectively disposed in the first to fourth sub-pixels SP1 to SP4, and drain electrodes of the first to fourth thin film transistors T1 to T4. (D) is respectively connected to the first to fourth pixel electrodes 101 to 104 through the drain contact hole DCH.

In addition, the pair of n-th gate wirings GLn is provided between the first and second sub-pixels SP1 and SP2 arranged in the first row and the third and fourth sub-pixels SP3 and SP4 arranged in the second row. They are disposed parallel to each other, and the (n+1)th gate line GL(n+1) is disposed between the pair of nth gate lines GLn.

In addition, the n-th gate wiring GLn connected to the second thin film transistor T2 overlaps the active layer (not shown) between the source electrode S and the drain electrode D of the first thin film transistor T1, and , the n-th gate wiring GLn connected to the fourth thin film transistor T4 overlaps the active layer (not shown) between the source electrode S and the drain electrode D of the third thin film transistor T3 .

Also, the first and second data lines DL1 and DL2 intersect the n-th and (n+1)-th gate lines GLn and GL(n+1). The first and third sub-pixels SP1 and SP3 are arranged on the left side, and the second data line DL2 is arranged on the right side of the second and fourth sub-pixels SP2 and SP4 arranged in the second column.

In this case, the n-th gate wiring GLn disposed above the (n+1)-th gate wiring GL(n+1) among the pair of n-th gate wirings GLn is the second thin film transistor T2 . The n-th gate wiring GLn connected to the gate electrode G and disposed below the (n+1)-th gate wiring GL(n+1) is the gate electrode G of the fourth thin film transistor T4. and the (n+1)th gate line GL(n+1) is connected to the gate electrodes G of the first and third thin film transistors T1 and T3, respectively.

Also, the first data line DL1 is connected to the source electrodes S of the first and second thin film transistors T1 and T2, respectively, and the second data line DL2 is connected to the third and fourth thin film transistors T3. , T4) and respectively connected to the source electrode (S).

In addition, the first and second data lines DL1 and DL2 supply data voltages of different polarities for one frame, and the data voltages supplied by the first and second data lines DL1 and DL2 are inverted every frame. do.

Here, assuming that the first data line DL1 supplies a positive (+) data voltage and the second data line DL2 supplies a negative (−) data voltage, first, When the second and fourth thin film transistors T2 and T4 are turned on by the gate signal supplied from the n-gate line GLn, the positive (+) data voltage from the first data line DL1 becomes the second A data voltage of negative polarity is supplied from the second data line DL2 to the fourth sub-pixel SP4.

Next, when the first and third thin film transistors T1 and T3 are turned on by the gate signal supplied from the (n+1)th gate line GL(n+1), the first data line DL1 The positive (+) data voltage is supplied to the first sub-pixel SP1 from , and the negative (-) data voltage is supplied to the third sub-pixel SP3 from the second data line DL2.

Meanwhile, in the DRD type liquid crystal display device according to the embodiment of the present invention, the (n+1)th gate wiring GL(n+1) is disposed between the pair of nth gate wirings GLn. I will explain about

If, unlike the present invention, when the n-th gate wiring GLn is disposed between the pair of (n+1)-th gate wirings GL(n+1), the first thin film transistor T1 is an n-th gate It is turned on by the gate signal output from the line GLn so that the data voltage is supplied from the first data line DL1 to the first sub-pixel SP1, and the data voltage supplied to the first sub-pixel SP1 is It is maintained for one frame, and in the data voltage maintaining period, the data voltage is applied to the (n+1)th gate line GL(n+1) disposed between the first subpixel SP1 and the nth gate line GLn. It may be affected by the output gate signal.

That is, image quality may be shaken in the first sub-pixel SP1 due to the electric field generated by the gate signal output from the (n+1)th gate line GL(n+1).

Similarly, the image quality is shaken even in the third sub-pixel SP3 due to the (n+1)-th gate line GL(n+1) disposed between the third sub-pixel SP3 and the n-th gate line GLn. This can happen.

Here, when the (n+1)th gate line GL(n+1) is disposed between the pair of nth gate lines GLn as in the present invention, the gate signal is output from the nth gate line GLn. After the first thin film transistor T1 is turned on by the gate signal output from the (n+1)th gate line GL(n+1), the data voltage at the first data line DL1 is first Since the data voltage supplied to the first sub-pixel SP1 and the first sub-pixel SP1 is maintained for one frame, the data voltage is applied to the first sub-pixel SP1 and the (n+)-th sub-pixel SP1 during the data voltage maintenance period. 1) It is not affected by the gate signal output from the n-th gate line GLn disposed between the gate lines GL(n+1).

Similarly, since the n-th gate line GLn is disposed between the third sub-pixel SP3 and the (n+1)-th gate line GL(n+1), the image quality is shaken in the third sub-pixel SP3. this won't happen.

Also, in the DRD type liquid crystal display device according to the embodiment of the present invention, the gate signals supplied from the pair of n-th gate wirings GLn have the same timing.

To this end, the gate driver (not shown) outputs the gate signal having the same timing to the pair of n-th gate wirings GLn, respectively, or the gate driver (not shown) applies the gate signal to the pair of n-th gate wirings. A gate signal having the same timing is outputted to the other gate wirings by outputting only one of (GLn) and connecting the pair of nth gate wirings GLn to each other in the non-display area.

Meanwhile, in order to minimize the decrease in the aperture ratio, the region in which the pair of nth gate wirings GLn and (n+1)th gate wirings GL(n+1) are disposed should be minimized. That is, the gap between the pair of n-th gate wirings GLn and the (n+1)th gate wirings GL(n+1) should be minimized.

To this end, in a state where the distance between the pair of n-th gate wirings GLn and the (n+1)th gate wirings GL(n+1) is minimized, the n-th gate interconnection connected to the second thin film transistor T2 is The gate wiring GLn is disposed to surround the gate electrode G of the first thin film transistor T1, and the nth gate wiring GLn connected to the fourth thin film transistor T4 is the third thin film transistor ( It is disposed to surround the gate electrode G of T3).

Next, as shown in FIG. 5 , the liquid crystal display of the DRD method according to the embodiment of the present invention includes fifth to eighth subpixels SP5 to SP8 arranged in two rows and two columns, and a pair of nth ( n is an integer greater than or equal to 1) a gate line GLn, an (n+1)th gate line GL(n+1), and first and second data lines DL1 and DL2.

Specifically, the fifth to eighth sub-pixels SP5 to SP8 include fifth to eighth thin film transistors T5 to T8, respectively, and include red (R), green (G), blue (B) and white ( W) can be indicated individually.

In addition, it further includes fifth to eighth pixel electrodes 105 to 108 respectively disposed on the fifth to eighth sub-pixels SP5 to SP8, and drain electrodes of the fifth to eighth thin film transistors T5 to T8. (D) is respectively connected to the fifth to eighth pixel electrodes 105 to 108 through the drain contact hole DCH.

In addition, the pair of n-th gate wirings GLn is provided between the fifth and sixth sub-pixels SP5 and SP6 arranged in the first row and the seventh and eighth sub-pixels SP7 and SP8 arranged in the second row. They are disposed parallel to each other, and the (n+1)th gate line GL(n+1) is disposed between the pair of nth gate lines GLn.

In addition, the n-th gate wiring GLn connected to the sixth thin film transistor T6 overlaps the active layer (not shown) between the source electrode S and the drain electrode D of the fifth thin film transistor T5, and , the n-th gate wiring GLn connected to the eighth thin film transistor T8 overlaps the active layer (not shown) between the source electrode S and the drain electrode D of the seventh thin film transistor T7.

Also, the first and second data lines DL1 and DL2 intersect the n-th and (n+1)-th gate lines GLn and GL(n+1). The fifth and seventh sub-pixels SP5 and SP7 are arranged on the left side, and the second data line DL2 is arranged on the right side of the sixth and eighth sub-pixels SP6 and SP8 arranged in the second column.

In this case, the n-th gate wiring GLn disposed above the (n+1)-th gate wiring GL(n+1) among the pair of n-th gate wirings GLn is the sixth thin film transistor T6. The n-th gate wiring GLn connected to the gate electrode G and disposed below the (n+1)-th gate wiring GL(n+1) is the gate electrode G of the eighth thin film transistor T8. and the (n+1)th gate line GL(n+1) is connected to the gate electrode G of the fifth and seventh thin film transistors T5 and T7, respectively.

Also, the first data line DL1 is connected to the source electrodes S of the seventh and eighth thin film transistors T7 and T8, respectively, and the second data line DL2 is connected to the fifth and sixth thin film transistors T5. , T6) are respectively connected to the source electrode (S).

In addition, the first and second data lines DL1 and DL2 supply data voltages of different polarities for one frame, and the data voltages supplied by the first and second data lines DL1 and DL2 are inverted every frame. do.

Here, assuming that the first data line DL1 supplies a positive (+) data voltage and the second data line DL2 supplies a negative (−) data voltage, first, When the sixth and eighth thin film transistors T6 and T8 are turned on by the gate signal supplied from the n-gate line GLn, the positive (+) data voltage from the first data line DL1 becomes the eighth The sub-pixel SP8 is supplied, and a negative (-) data voltage is supplied from the second data line DL2 to the sixth sub-pixel SP6 .

Next, when the fifth and seventh thin film transistors T5 and T7 are turned on by the gate signal supplied from the (n+1)th gate line GL(n+1), the first data line DL1 The positive (+) data voltage is supplied to the seventh sub-pixel SP7 from , and the negative (-) data voltage is supplied to the fifth sub-pixel SP5 from the second data line DL2.

Meanwhile, in the DRD type liquid crystal display device according to the embodiment of the present invention, the (n+1)th gate wiring GL(n+1) is disposed between the pair of nth gate wirings GLn. I will explain about

If, unlike the present invention, when the n-th gate wiring GLn is disposed between a pair of (n+1)-th gate wirings GL(n+1), the fifth thin film transistor T5 has an n-th gate It is turned on by the gate signal output from the line GLn so that the data voltage is supplied from the second data line DL2 to the fifth sub-pixel SP5 and the data voltage supplied to the fifth sub-pixel SP5 is It is maintained for one frame, and in the data voltage maintaining period, the data voltage is applied to the (n+1)th gate line GL(n+1) disposed between the fifth subpixel SP5 and the nth gate line GLn. It may be affected by the output gate signal.

That is, the fifth sub-pixel SP5 may have image quality shake caused by the electric field generated by the gate signal output from the (n+1)th gate line GL(n+1).

Similarly, the image quality is shaken in the seventh sub-pixel SP7 due to the (n+1)-th gate line GL(n+1) disposed between the seventh sub-pixel SP7 and the n-th gate line GLn. This can happen.

Here, when the (n+1)th gate line GL(n+1) is disposed between the pair of nth gate lines GLn as in the present invention, the gate signal is output from the nth gate line GLn. After that, the fifth thin film transistor T5 is turned on by the gate signal output from the (n+1)th gate line GL(n+1), so that the data voltage at the second data line DL2 is first Since the data voltage supplied to the fifth sub-pixel SP5 and the fifth sub-pixel SP5 is maintained for one frame, the data voltage is applied to the fifth sub-pixel SP5 and the (n+)-th 1) It is not affected by the gate signal output from the n-th gate line GLn disposed between the gate lines GL(n+1).

Similarly, since the n-th gate line GLn is disposed between the seventh sub-pixel SP7 and the (n+1)-th gate line GL(n+1), the image quality is shaken in the seventh sub-pixel SP7. this won't happen.

Also, in the DRD type liquid crystal display device according to the embodiment of the present invention, the gate signals supplied from the pair of n-th gate wirings GLn have the same timing.

To this end, the gate driver (not shown) outputs the gate signal having the same timing to the pair of n-th gate wirings GLn, respectively, or the gate driver (not shown) applies the gate signal to the pair of n-th gate wirings. A gate signal having the same timing is outputted to the other gate wirings by outputting only one of (GLn) and connecting the pair of nth gate wirings GLn to each other in the non-display area.

Meanwhile, in order to minimize the decrease in the aperture ratio, the region in which the pair of nth gate wirings GLn and (n+1)th gate wirings GL(n+1) are disposed should be minimized. That is, the gap between the pair of n-th gate wirings GLn and the (n+1)th gate wirings GL(n+1) should be minimized.

To this end, in a state where the distance between the pair of n-th gate wirings GLn and the (n+1)-th gate wirings GL(n+1) is minimized, the n-th gate interconnection connected to the sixth thin film transistor T6 is The gate wiring GLn is disposed to surround the gate electrode G of the fifth thin film transistor T5, and the nth gate wiring GLn connected to the eighth thin film transistor T8 is connected to the seventh thin film transistor ( It is disposed to surround the gate electrode G of the T7).

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

GL1 ~ GL10 : Gate wiring DL1 ~ DL5 : Data wiring
SP1 ~ SP32 : Subpixel T1 ~ T32 : Thin film transistor

Claims (11)

first to fourth sub-pixels each including first to fourth thin film transistors and arranged in two rows and two columns in a display area;
a pair of nth (n is an integer greater than or equal to 1) gate wirings disposed between the first and second subpixels arranged in a first row and the third and fourth subpixels arranged in a second row; a (n+1)th gate wiring disposed between the nth gate wirings; and
first and third subpixels intersecting the nth and (n+1)th gate wirings and disposed on the left side of the first and third subpixels arranged in the first column and on the right side of the second and fourth subpixels arranged on the second column, respectively a second data line;
the second and fourth thin film transistors are connected to the nth gate line, and the first and third thin film transistors are connected to the (n+1)th gate line;
the first and second thin film transistors are connected to a first data line and the third and fourth thin film transistors are connected to a second data line;
The first and second thin film transistors are connected to a second data line, and the third and fourth thin film transistors are connected to a first data line.
The method of claim 1,
Of the pair of n-th gate wirings, the n-th gate wiring disposed above the (n+1)th gate wiring is connected to the second thin film transistor and disposed below the (n+1)th gate wiring. The n-th gate wiring to be a liquid crystal display device is connected to the fourth thin film transistor.
3. The method of claim 2,
The n-th gate wiring connected to the second thin film transistor surrounds the gate electrode of the first thin film transistor, and the n-th gate wiring connected to the fourth thin film transistor connects the gate electrode of the third thin film transistor. Surrounding liquid crystal display.
4. The method of claim 3,
The nth gate wiring connected to the second thin film transistor overlaps the active layer of the first thin film transistor, and the nth gate wiring connected to the fourth thin film transistor overlaps the active layer of the third thin film transistor liquid crystal display device.
5. The method of claim 4,
The pair of n-th gate wirings are connected to each other in a non-display area.
6. The method of claim 5,
It further includes first to fourth pixel electrodes respectively disposed on the first to fourth sub-pixels,
The drain electrodes of the first to fourth thin film transistors are respectively connected to the first to fourth pixel electrodes through a drain contact hole.
The method of claim 1,
The first and second data lines respectively supply data voltages having different polarities for one frame.
8. The method of claim 7,
The polarities of the data voltages respectively supplied by the first and second data lines are inverted every frame.
9. The method of claim 8,
The first to fourth sub-pixels display red, green, blue, and white colors, respectively.
The method of claim 1,
An n-th gate signal of the same timing is commonly applied to the pair of n-th gate wirings.
11. The method of claim 10,
A liquid crystal display in which an n+1th gate signal is applied to the n+1th gate wiring after the nth gate signal is applied.

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