KR20170040866A - Organic Light Emitting Diode Display Device - Google Patents

Abstract

The organic light emitting diode display according to the present invention includes a shift register for driving transistors arranged in pixels and pixels. Each pixel includes a driving transistor, a scanning transistor, a sense transistor, and a storage capacitor. The driving transistor controls a driving current supplied to the organic light emitting diode. The scan transistor is connected between the gate electrode of the drive transistor and the data line, and is switched by the scan signal. The sense transistor is connected between the source electrode of the drive transistor and the initialization line, and is switched by the sense signal. The storage capacitor is connected between the gate electrode and the source electrode of the driving transistor. A shift register includes a sense signal stage for simultaneously applying a sense signal to pixels arranged in k horizontal lines adjacent to each other (k is a natural number), and a scan signal stage for sequentially applying scan signals to pixels arranged in the k horizontal lines adjacent to each other.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

2. Description of the Related Art Flat panel displays (FPDs) are widely used not only for monitors of desktop computers but also for portable computers such as notebook computers and PDAs, as well as mobile phone terminals, because they are advantageous in downsizing and light weight. Such a flat panel display device includes a liquid crystal display (LCD) (LCD), a plasma display panel (PDP), a field emission display (FED) and an organic light emitting diode display (OLED).

Among these organic light emitting diode display devices, the organic light emitting diode display device has a high response speed, high luminance efficiency, and a large viewing angle. In general, an organic light emitting diode display device applies a data voltage to a gate electrode of a driving transistor using a transistor turned on by a scan signal, and charges a data voltage supplied to the driving transistor to a storage capacitor. The organic light emitting diode emits light by outputting the charged data voltage to the storage capacitor using the emission control signal.

The organic light emitting diode display device displays a gray level corresponding to the data voltage but may not display a desired gray level due to a deviation of a threshold voltage or mobility of the driving transistor. To improve this, an organic light emitting diode display device uses a method of sensing a threshold voltage or mobility of a driving transistor and compensating a data voltage based on the sensed threshold voltage or mobility. A sense transistor for switching a path for sensing a threshold voltage or mobility operates in response to a sense signal.

A scan signal for applying a data voltage and a sense signal for switching a sense transistor may be implemented as a gate-in-panel (GIP) in a bezel region of a display panel.

In recent years, there have been attempts to reduce the bezel area according to the user's demand. It is not easy to reduce the bezel size due to the GIP circuit part.

The present invention provides an organic light emitting diode display device capable of reducing a bezel area.

According to an aspect of the present invention, an organic light emitting diode display includes a shift register for driving transistors disposed in pixels and pixels. Each pixel includes a driving transistor, a scan transistor, a sense transistor, and a storage capacitor. The driving transistor controls a driving current supplied to the organic light emitting diode. The scan transistor is connected between the gate electrode of the drive transistor and the data line, and is switched by the scan signal. The sense transistor is connected between the source electrode of the drive transistor and the initialization line, and is switched by the sense signal. The storage capacitor is connected between the gate electrode and the source electrode of the driving transistor. The shift register includes a sense signal stage for simultaneously applying a sense signal to pixels arranged in k (k is a natural number) horizontal lines adjacent to each other, and a scan signal stage for sequentially applying a scan signal to pixels arranged in k horizontal lines adjacent to each other And a scan signal stage.

The organic light emitting diode display device according to the present invention simultaneously supplies sense signals to pixels arranged in a plurality of horizontal lines using a sense signal stage implemented in one stage, It is possible to reduce the number of stages. As a result, the bezel area where the sense signal stage is disposed can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a configuration of an organic light emitting diode display device according to the present invention; FIG.
2 is a view showing a configuration of a shift register according to the present invention;
Fig. 3 is a view showing the pixel structure shown in Fig. 1. Fig.
Figure 4 illustrates one embodiment of the shift register shown in Figure 2;
5 is a diagram showing a driving signal applied to a pixel in a video display driving period;
6A and 6B are diagrams showing pixel operation in an image display driving period.
7 is a diagram showing a drive signal applied to a pixel in a sensing period;
8A and 8C are diagrams illustrating pixel operation in an external compensation driving period.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing a configuration of a display device according to the present invention. FIG. 2 is a view showing a shift register according to the present invention, and FIG. 3 is a diagram showing a pixel structure according to the present invention.

1 to 3, an organic light emitting diode display device according to the present invention includes a display panel 100 in which pixels P are arranged in a matrix, a data driver 120, gate drivers 130 and 140, (110).

The display panel 100 includes a display portion 100A in which pixels P are arranged and an image is displayed and a non-display portion 100B in which a shift register 140 is disposed and an image is not displayed.

The display unit 100A includes a plurality of pixels P, and displays an image based on the gradation displayed by each of the pixels P. The pixels P are arranged along the first to nth horizontal lines HL1 to HL [n].

Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a horizontal line HL. The gate line GL includes a scan line SCL and a sensing line SEL, as shown in FIG. Each of the pixels P includes an organic light emitting diode OLED, a driving transistor DT, a scan transistor ST1, a sense transistor ST2, and a storage capacitor Cst. Each of the transistors DT, ST1, and ST2 may be implemented as a polycrystalline thin film transistor (hereinafter referred to as a transistor) including a polycrystalline semiconductor layer. However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon, polysilicon, or the like.

The timing controller 110 is for controlling the driving timings of the data driver 120 and the gate drivers 130 and 140. To this end, the timing controller 110 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 100 and supplies the digital video data RGB to the data driver 120. The timing controller 110 is also connected to the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate drivers 130 and 140 are generated.

The data driver 120 drives the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into analog data voltages based on the data control signal DDC and supplies the analog data voltages to the data lines DL.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 is formed in a printed circuit board (not shown) connected to the display panel 100 in the form of an IC and the shift register 140 is formed in a non-display area (not shown) of the display panel 100 A gate-in-panel (hereinafter, referred to as GIP) method is formed on the substrate 100B.

The level shifter 130 level-shifts the clock signals (CLK) and the start signal (VST) under the control of the timing controller 110, and supplies the level shift signals to the shift register 140. The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 100B of the display panel 100 by the GIP method.

2, a stage of a shift register 140 for driving pixels Pj arranged in a j-th horizontal line and pixels P [j + k] arranged in a (j + k) As follows. The pixel Pj arranged in the j-th horizontal line includes the j-th scan line SCL [j] and the j-th sensing line SEL [j].

The shift register 140 for driving the pixels arranged in k horizontal lines is connected to the scan signal stages SCAN_STG [j] to SCAN_STG [j + k-1] ), And a j-th sense signal stage (SENSE_STG [j]).

The jth scan signal stage SCAN_STG [j] generates the jth scan signal SCAN [j] and applies it to the scan line SCL [j] of the pixels Pj arranged in the jth horizontal line. The (j + k-1) th scan signal stage SCAN_STG [j + k-1] generates the (j + k-1) th scan signal SCAN [j + k- (J + k-1)] of the pixels P [j + k-1] arranged in the horizontal line. The jth scan signal stages SCAN_STG [j] to (j + k-1) th scan signal stages SCAN_STG [j + k- k-1) th scan line SCL [j + k-1].

The jth sense signal stage SENSE_STG [j] generates the jth sense signal SENSE [j] and outputs it to the sense line SEL [j] of the pixels P [j] To the sense line SEL [j + k-1] of the pixels j + k-1 arranged in the (j + k-1) th horizontal line.

As described above, the pixels Pj and Pj + k-1 arranged on the k horizontal lines use the same sense signal. In order to apply a sense signal having a different timing to each horizontal line, the number of sense signal stages must correspond to the number of horizontal lines. On the other hand, in the present invention, since one sense signal stage is required to apply a sense signal to k horizontal lines, the number of sense signal stages can be reduced to 1 / k. As a result, the present invention can reduce the entire area of the shift register 140 and reduce the bezel area of the non-display portion 100B accordingly.

3 is a diagram showing the pixel structure and the connection between the pixel and the data driver shown in FIG.

Referring to FIG. 3, each of the pixels P includes an organic light emitting diode (OLED), a driving transistor DT, a scan transistor ST1, a sense transistor ST2, and a storage capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The anode electrode of the organic light emitting diode (OLED) is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the ground terminal (VSS).

The driving transistor DT controls the driving current Ioled flowing through the organic light emitting diode OLED according to the gate-source voltage Vgs. The gate electrode of the driving transistor DT is connected to the first node N1, the drain electrode thereof is connected to the high potential voltage (VDD) input terminal, and the source electrode thereof is connected to the second node N2.

The storage capacitor Cst is connected between the first node N1 and the second node N2 to maintain the data voltage supplied from the data line DL for one frame.

The scan transistor ST1 is switched according to the scan signal SCAN to control the potential of the first node N1. The scan transistor ST1 has a gate electrode connected to the scan line SCL, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1.

The sense transistor ST2 is switched in accordance with the sense signal SENSE to control the potential of the second node N2. The gate electrode of the sense transistor ST2 is connected to the sensing line SEL and the drain electrode of the sense transistor ST2 is connected to the second node N2 and the source electrode of the sense transistor ST2 is connected to the initialization voltage Vinit .

Each of the pixels P is connected to the data driver 120 through a data line DL and an initialization line INL. The data driver 120 includes a digital-analog converter (DAC), an analog-digital converter (ADC), first and second switches SW1 and SW2 ) And the like.

The DAC converts the digital data input from the timing controller 110 into an analog data voltage Vdata and outputs it to the data line DL. The first switch SW1 switches the current flow between the initializing voltage Vini input terminal and the initializing line INL. The second switch SW2 switches the current flow between the initialization line INL and the ADC. The ADC converts the analog sensing voltage Vsen into a digital value and supplies the digital value to the timing controller 110.

Hereinafter, the pixel operation according to the present invention will be described.

FIG. 4 shows an embodiment of a shift register in which k is 1 in FIG. 2, that is, a shift register commonly applies a sense signal to pixels arranged in two adjacent horizontal lines. 5A and 5B are timing charts of the driving signals for driving the image display, and FIGS. 6A and 6B are diagrams showing the operation states of the pixels according to the driving signals.

4, a stage of a shift register 140 for driving pixels Pj arranged in a j-th horizontal line and pixels P [j + 1] arranged in a (j + 1) As follows.

4, a shift register 140 for driving pixels arranged in two adjacent horizontal lines is connected to a scan signal stage SCAN_STG [j] and a scan signal stage SCAN_STG [j + 1] j + 1]) and a jth sense signal stage (SENSE_STG [j]).

The jth scan signal stage SCAN_STG [j] generates the jth scan signal SCAN [j] and applies it to the scan line SCL [j] of the pixels Pj arranged in the jth horizontal line. The (j + 1) th scan signal stage SCAN_STG [j + 1] generates the (j + 1) th scan signal SCAN [j + 1] To the scan line SCL [j + 1] of the scan lines P [j + 1]. The jth scan signal stage SCAN_STG [j] and the (j + 1) th scan signal stage SCAN_STG [j + 1] are connected to the jth scan line SCL [j] And sequentially applies a scan signal to the line SCL [j + 1].

The jth sense signal stage SENSE_STG [j] generates the jth sense signal SENSE [j] and outputs it to the sense lines SEL [j] and j (J + 1) of the pixels (j + 1) arranged in the (i + 1) th horizontal line.

Referring to FIG. 5, the video display driving period includes a data writing period Tw and a light emitting period Te. The data writing period Tw and the light emitting period Te shown in FIG. 5 are indicated with the pixels Pj arranged in the j-th horizontal line as the center. During the video display driving period, the first switch SW1 of the data driver 120 shown in FIG. 3 is kept in the ON state, while the second switch SW2 is kept in the OFF state continuously.

5 and 6A, during the data writing period Tw of the j-th horizontal line HLj, the j-th scan signal SCAN [j] and the j-th sense signal SENSE [j] Voltage level. As a result, the scan transistor ST1 of the pixels Pj arranged on the j-th horizontal line is turned on and the data voltage Vdata supplied from the data line DL is supplied to the gate of the driving transistor DT [j] To the electrode. Then, the sense transistor ST2 [j] is turned on to apply an initialization voltage supplied from the initialization line INL to the source electrode of the driving transistor DT [j]. That is, during the data writing period Tw, the gate-source voltage Vgs of the driving transistor DT [j] is written with a voltage corresponding to the "difference between the data voltage () and the initializing voltage Vpre" .

the pixels P [j + 1] disposed in the (j + 1) th horizontal line during the data writing period Tw of the jth horizontal line HLj are connected to the source electrodes The data write operation is not performed because the data voltage Vdata is not applied to the first node N1 even if the initialization voltage Vini is provided to the first node N1.

5 and 6B, during the light emission period Te of the j-th horizontal line HL [j], the jth scan signal SCAN [j] is inverted to the turn-off voltage level, (SENSE [j]) maintains the turn-on voltage level. the scan transistors SCAN [j] of the pixels Pj arranged on the j-th horizontal line are turned off so that the drive transistor DT [j] is turned on in response to the gate-source voltage Vgs level set during the data write- And generates a driving current Ioled to be applied to the organic light emitting diode OLED. As a result, the organic light emitting diode OLED emits light with a brightness corresponding to the driving current Ioled to display the gradation.

the pixels P [j + 1] arranged in the (j + 1) th horizontal line during the emission period of the jth horizontal line HL [j] ]) And the j-th sense signal SENSE [j]. That is, since the timing of the sense signal for writing data in the pixels arranged in the two horizontal lines is the same, the number of stages of the shift register for outputting the sense signal can be reduced.

FIG. 7 is a timing chart of a driving signal for external compensation, and FIGS. 8A to 8C are diagrams illustrating the operation of a pixel during an external compensation driving period. Particularly, FIG. 7 shows driving signals for an embodiment in which sense signals are simultaneously applied to two horizontal lines using the shift register shown in FIG.

Referring to FIGS. 7 and 8A, during the first initialization period Ti, the jth scan signal SCAN [j] and the jth sense signal SENSE [j] are applied at the turn-on voltage level. The first switch SW1 is turned on and the second switch SW2 is turned off so that the sense transistor ST2 [j] is connected to the initializing voltage Vini input terminal. As a result, the scan transistors ST1 [j] of the pixels P [j] arranged on the j-th horizontal line are turned on to supply the sensing data voltages supplied from the data lines DL to the driving transistors DT [ j]. Then, the sense transistor ST2 [j] is turned on to apply an initialization voltage supplied from the initialization line INL to the source electrode of the driving transistor DT.

7 and 8B, during the second initialization period Ti, the (j + 1) th scan signal SCAN [j + 1] is applied as the turn-on voltage and the j th sense signal SENSE [j ] Maintains the turn-on voltage level. The first switch SW1 is turned on and the second switch SW2 is turned off so that the sense transistor SENSE [j + 1] is connected to the initializing voltage Vini input terminal. As a result, the scan transistors ST1 [j + 1] of the pixels P [j + 1] arranged in the (j + 1) th horizontal line are turned on, And applies the data voltage to the gate electrode of the driving transistor DT [j]. The source electrode of the driving transistor DT [j + 1] holds the initialization voltage Vini since the sense transistor ST2 [j + 1] keeps the turn-on state during the second initialization period Ti2.

Referring to FIGS. 7 and 8C, during the sensing period Ts, the jth scan signal SCAN [j] and the (j + 1) th scan signal SCNA [j + 1] , And the j-th sense signal SENSE [j] maintains the turn-on voltage. The first switch SW1 is turned off and the second switch SW2 is turned on so that each of the sense transistors SENSE [j] and SENSE [j + 1] is connected to the ADC. During the sensing period (Ts), a high potential (VDD) is applied to the cathode electrode of the organic light emitting diode (OLED).

The j th scan signal SCAN [j] and the (j + 1) th scan signal SCAN [j] the first node N1 of the pixels (j + 1) arranged in the (j + 1) th horizontal line is floating. The gate-source voltage Vgs of each of the driving transistors DT [j] and DT [j + 1] is higher than the threshold voltage during the first and second initialization periods Ti1 and Ti2, DT [j], and DT [j + 1]). During the sensing period Ts, since the cathode electrode of the organic light emitting diode OLED receives the high potential voltage VDD, the organic light emitting diode OLED does not emit light and the second node N2 [j] , N2 [j + 1]) gradually increase. The voltage of the second node N2 [j], N2 [j + 1] is set so that the gate-source voltage Vgs of the driving transistors DT [j] and DT [j + It increases until saturated.

Since the second switch SW2 is turned on during the sensing period Ts to connect each second node N2 [j], N2 [j + 1] to the ADC, each second node N2 [j ], N2 [j + 1]) is detected by the ADC.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Data driving circuit 130, 140: Gate driving circuit

Claims (9)

And a shift register for driving the pixels and the transistors disposed in the pixels,
Each of the pixels
A driving transistor for controlling a driving current supplied to the organic light emitting diode;
A scan transistor connected between a gate electrode of the driving transistor and a data line and switched by a scan signal;
A sense transistor connected between the source electrode of the driving transistor and the initialization line and switched by a sense signal; And
And a storage capacitor connected between the gate electrode and the source electrode of the driving transistor,
The shift register
A sense signal stage for simultaneously applying the sense signal to pixels arranged in k adjacent (k is a natural number) horizontal lines; And
And a scan signal stage for sequentially applying the scan signals to pixels arranged in k horizontal lines adjacent to each other. The method according to claim 1,
During the data writing period of the video display driving period,
Wherein the scan transistor applies a data voltage to a gate electrode of the driving transistor in response to the scan signal,
And the sense transistor applies an initialization voltage to a source electrode of the driving transistor in response to the sense signal. 3. The method of claim 2,
During a data write period of pixels arranged in j (j is a natural number) horizontal line to (j + k-1)
The scan signal stage
And a (j + k-1) th scan signal stage for sequentially outputting the (j + k-1) th scan signal to the (j + k-1) th scan signal. The method of claim 3,
During the data writing period of the pixels arranged in the j-th horizontal line to the (j + k-1) -th horizontal line,
And the jth sense signal stage simultaneously applies the jth sense signal to the pixels arranged in the jth horizontal line to the (j + k-1) th horizontal line. The method according to claim 1,
During the initialization period of the external compensation driving period
Wherein the scan transistor applies a sensing data voltage to a gate electrode of the driving transistor in response to the scan signal,
And the sense transistor applies an initialization voltage to a source electrode of the driving transistor in response to the sense signal. 6. The method of claim 5,
During the initialization period of the external compensation driving period of the pixels arranged in j (j is a natural number) horizontal line to (j + k-1)
And a (j + k-1) th scan signal stage for sequentially outputting the (j + k-1) th scan signal to the (j + k-1) th scan signal. The method according to claim 6,
During the initialization period of the external compensation driving period of the pixels arranged in the j-th horizontal line to the (j + k-1) -th horizontal line,
And the jth sense signal stage simultaneously applies the jth sense signal to the pixels arranged in the jth horizontal line to the (j + k-1) th horizontal line. 6. The method of claim 5,
During the sensing period of the external compensation drive period
The scan transistor is turned off,
And the sense transistor connects the source electrode of the driving transistor and the analog-digital-to-analog converter in response to the sense signal. 9. The method of claim 8,
During the sensing period of the external compensation drive period
And a cathode electrode of the organic light emitting diode receives a high potential voltage.

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