KR20170033935A - Liquid crystal display device having a compensting thin film transistor - Google Patents

Abstract

The present invention relates to a liquid crystal display device having a high aperture ratio and capable of improving an image quality. The liquid crystal display device includes a plurality of data lines and gate lines crossing each other, first electrodes, at least one second electrode, and a semiconductor layer. Each of the plurality of gate lines is arranged to intersect a plurality of data lines and has a zigzag pattern. The first electrodes are disposed between the data lines, respectively. The second electrode is supplied with a reference voltage to form an electric field with the first electrodes. The semiconductor layer includes a first region connected to the data line, a second region overlapping the gate line at two positions and connected to the first region by a first connection part while overlapping the gate line at a first position, a third region overlapping the gate line at a second position and connected to the second region by a second connection part, and a fourth region connected to the first electrode and connected to the third region by a third connection part.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device having a thin film transistor for compensation,

The present invention relates to a liquid crystal display device having a compensating thin film transistor, and more particularly to a liquid crystal display device having a pixel structure capable of improving image quality and aperture ratio.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. As a result, it has rapidly developed into a flat panel display device (FPD) capable of replacing a bulky cathode ray tube (CRT) with a thin, light and large area. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED) have been developed and utilized.

The display panel constituting the flat panel display device includes a thin film transistor substrate on which thin film transistors allocated in pixel regions arranged in a matrix manner are arranged. For example, a liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field driving the liquid crystal.

The vertical electric field type liquid crystal display device drives a TN (Twisted Nematic) mode liquid crystal by a vertical electric field formed between the pixel electrodes disposed opposite to the upper and lower substrates and the common electrode. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

The horizontal electric field type liquid crystal display device forms a horizontal electric field between a pixel electrode and a common electrode arranged in parallel to a lower substrate to drive an in plane switching (IPS) mode liquid crystal. Such an IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display, in order to form the in-plane field, the interval between the common electrode and the pixel electrode is formed wider than the interval between the upper and lower substrates. In order to obtain an electric field of appropriate intensity, The pixel electrode is formed in a strip shape having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal above the pixel electrode and the common electrode. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial alignment state. The liquid crystal which maintains the initial state can not transmit light, which causes the aperture ratio and the transmittance decrease.

A fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed to overcome the disadvantage of the IPS mode liquid crystal display device. The FFS-type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with an insulating film interposed therebetween. The interval between the common electrode and the pixel electrode is narrower than the interval between the upper and lower substrates, Shaped fringe field. The liquid crystal molecules interposed between the upper and lower substrates are operated by the fringe field, so that the aperture ratio and the transmittance can be improved.

FIG. 1 is a plan view showing a thin film transistor (TFT) substrate constituting a conventional fringe field type liquid crystal display, and FIG. 2 is a cross-sectional view taken along line I-I 'of FIG.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate line GL and a data line DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB and a thin film transistor T). The pixel region is defined by the intersection structure of the gate line GL and the data line DL. The pixel region includes a pixel electrode Px and a common electrode COM formed so as to sandwich the second passivation film PAS2 to form a fringe field. The pixel electrode Px has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM can be formed into a plurality of parallel strips.

The common electrodes COM are connected to the common wiring CL arranged in parallel with the gate lines. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode Px. The thin film transistor T opposes the source electrode S and the source electrode S extending from the gate electrode G extending from the gate line GL, the data line DL, and the pixel electrode Px, And a semiconductor channel A which is disposed on the gate insulating film GI and overlaps the gate electrode G and forms a channel between the source electrode S and the drain electrode D do.

The semiconductor layer SE including the semiconductor channel A includes a source region SA and a drain region DA disposed on both sides of the semiconductor channel A. [ The semiconductor layer SE is formed of a polycrystalline silicon material. The semiconductor channel (A) is formed so as to overlap the gate electrode (G). The source region SA and the drain region DA of the semiconductor layer SE are made conductive by the plasma treatment to form the gate insulating film GI covering the semiconductor layer SE, the gate line GL on the gate insulating film GI, Are connected to the source electrode (S) and the drain electrode (D) through a source contact hole (SH) and a drain contact hole (DH) penetrating the interlayer insulating film (INS) covering the gate electrode (G). Therefore, the semiconductor layer SE made of polycrystalline silicon has a source region SA connected to the source electrode S, a drain region DA connected to the drain electrode D, and a source region SA connected to the drain region D And a semiconductor channel A completely overlapped with the gate electrode G between the source and drain electrodes DA and DA.

The fringe field switching method has a structure in which the pixel electrode Px and the common electrode COM are overlapped. A storage capacitor is formed in this overlap region. A high-capacity thin film transistor is required in order to constitute a fringe field and to secure a sufficient storage capacity. Therefore, in the fringe field method, it is preferable to use a thin film transistor including a polycrystalline silicon semiconductor material having a top gate structure.

2, the structure of a thin film transistor including a polycrystalline silicon semiconductor material having a top gate structure will be described. The semiconductor layer SE having the source region S, the semiconductor channel A and the drain region D is formed on the substrate SUB first. A gate insulating film (GI) is entirely coated on the semiconductor layer. A gate electrode G overlapping the semiconductor channel A, which is the center of the semiconductor layer SE, is formed on the gate insulating film GI.

On the gate electrode G, an interlayer insulating film INS covering the entire substrate SUB is applied. A source contact hole SH and a drain contact hole DH for exposing the source region SA and the drain region DA of the semiconductor layer SE are formed in the interlayer insulating film INS and the gate insulating film GI. A source electrode S connected to the source region SA through the source contact hole SH and a drain electrode D connected to the drain region DA through the drain contact hole DH are formed on the interlayer insulating film INS, .

The first passivation film PAS1 is applied to the entire surface of the substrate SUB on which the top gate type thin film transistor T thus formed is formed. A pixel contact hole PH is formed to expose a part of the drain electrode D through the first passivation film PAS1.

The pixel electrode Px is connected to the drain electrode D through the pixel contact hole PH formed on the first passivation film PAS1. On the other hand, the common electrode COM is formed so as to overlap the pixel electrode Px with the second passivation film PAS2 covering the pixel electrode Px interposed therebetween. When a pixel signal and a common voltage (or reference voltage) are applied to the pixel electrode Px and the common electrode COM, a fringe field type electric field is formed therebetween. Further, an auxiliary capacitance is formed in a region where the pixel electrode Px and the common electrode COM are overlapped. The liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy by the fringe field type electric field. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, so that the gradation according to the pixel data can be realized.

A thin film transistor including a polycrystalline silicon semiconductor material has a problem that its off-current characteristic deteriorates due to its characteristics. Therefore, a compensating thin film transistor is required to compensate for the deteriorated off characteristics of the driving thin film transistor.

Hereinafter, with reference to FIG. 3, a case of a liquid crystal display device further comprising a compensating thin film transistor will be described. 3 is a plan view of a thin film transistor substrate for a liquid crystal display device having a compensating thin film transistor according to the related art. 3 is a view illustrating a thin film transistor substrate for implementing a low resolution liquid crystal display device including a compensating thin film transistor and having a resolution of 300 PPI or less.

In the thin film transistor substrate shown in FIG. 3, a pixel region is defined by a gate line GL and a data line DL crossing a gate insulating film GI on a lower substrate SUB. A pixel electrode Px and a common electrode COM, which are formed with a second passivation film PAS2 interposed therebetween, are disposed to form a fringe field in the pixel region. The pixel electrode Px has a shape corresponding to the pixel region, and the common electrode COM can be formed into a plurality of parallel strips.

And one driving thin film transistor T1 is disposed in each pixel region. In addition, the compensating thin film transistor T2 for compensating the off-current characteristic is disposed in the driving thin film transistor T1. The drain electrode D1 of the driving thin film transistor T1 is connected to the source electrode S2 of the compensation thin film transistor T2.

Hereinafter, the structure of the thin film transistor substrate including the driving thin film transistor T1 and the compensation thin film transistor T2 connected in series will be described in more detail. A matrix type pixel region is defined on the substrate SUB by the intersection structure of the gate lines GL arranged in the horizontal direction and the data lines DL arranged in the vertical direction.

The gate electrode G1 of the driving thin film transistor T1 extends from the gate line GL toward the pixel region. The source electrode S1 of the driving thin film transistor T1 extends from the data line DL toward the pixel region. The semiconductor layer SE of the driving thin film transistor T1 includes the semiconductor region A1 and the source region SA1 and the drain electrode D1 which are each made conductive by the plasma treatment with the semiconductor channel A1 interposed therebetween do.

The semiconductor layer SE of the driving thin film transistor T1 is extended so as to overlap with the source electrode S1 and the gate electrode G1. The drain electrode D1 of the driving thin film transistor T1 is not separately formed but the region extending from the semiconductor channel A1 is used as the drain electrode D1.

The gate electrode G2 of the compensating thin film transistor T2 is not formed separately but a part of the gate line DL is used as the gate electrode G2. The source electrode S2 of the compensating thin film transistor T2 is not formed separately and the drain electrode D1 of the semiconductor layer SE is used as the source electrode S2. That is, the region of the semiconductor layer SE disposed between the gate electrode G1 and the gate line GL functions not only as the drain electrode D1 of the driving thin film transistor T1, (S2). The semiconductor channel A2 of the compensating thin film transistor T2 is a region of the semiconductor layer SE extending from the source electrode S2 and overlapping with the gate electrode G2 of the gate line GL. The drain electrode D2 of the compensating thin film transistor T2 is connected to the drain region DA2 extending from the semiconductor channel A2 of the semiconductor layer SE.

In order to connect the driving thin film transistor T1 and the compensation thin film transistor T2 in series, the gate electrode G1 of the driving thin film transistor T1 has a structure protruding into a pixel region arranged below the corresponding pixel. The semiconductor layer SE extends from the lower pixel region to overlap with the gate line GL and is disposed within the pixel region. The drain electrode D of the compensating thin film transistor T2 is connected to the pixel electrode Px formed in the pixel region through the pixel contact hole PH.

The pixel electrode Px has a structure in which the pixel electrode Px overlaps the common electrode COM with a protective film interposed therebetween. The common electrodes COM are connected to the common wiring CL arranged in parallel with the gate lines. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL. A fringe field type electric field is formed between the pixel electrode Px and the common electrode COM. Further, an auxiliary capacitance is formed in a region where the pixel electrode Px and the common electrode COM are overlapped. The liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy by the fringe field type electric field. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The resolution of the liquid crystal display device of about 300 PPI is large and the proportion of the driving thin film transistor T1 and the compensating thin film transistor T2 in the pixel region is not so large. Particularly, in the liquid crystal display device of the fringe field switching system in which the pixel electrode Px and the common electrode COM are overlapped with each other to form the storage capacitor without separately forming the storage capacitor, the opening area is sufficiently secured. Therefore, the ratio of the opening area, which is reduced due to the size of the compensating thin film transistor T2, does not matter much.

3, the gate electrode G2 of the compensating thin film transistor T2 is not formed separately and the gate line G2 of the compensating thin film transistor T2 is not formed separately, as shown in FIG. 3, in order to apply the structure further including the compensation thin film transistor to the liquid crystal display device for resolution of about 300 PPI. GL). As a result, the area occupied by the driving thin film transistor T1 and the compensation thin film transistor T2 in the pixel region can be reduced to some extent. With such a structure, the aperture ratio can be secured to some extent at a resolution of around 300 PPI, but it is necessary to secure a larger aperture ratio in a high-resolution liquid crystal display device of 300 PPI or more.

In a liquid crystal display device for a high resolution of 300 PPI or more or an ultrahigh resolution of 500 PPI or more, the size of the pixel region is considerably reduced as compared with that for a lower resolution. On the other hand, the size of the thin film transistors T1 and T2 can not have a size reduced in proportion to the shrinking pixel region in order to maintain the characteristics. That is, in a pixel structure for realizing a high resolution or an ultra-high resolution, an area ratio occupied by the thin film transistors T1 and T2 in a pixel area is gradually increased. Since the region occupied by the thin film transistors T1 and T2 is a non-transmissive region, it is an important factor for decreasing the aperture ratio at high resolution and ultra high resolution. A thin film transistor substrate for a liquid crystal display device for a high resolution of 300 PPI or more or an ultrahigh resolution of 500 PPI or more needs a new structure capable of further increasing the ratio of the opening area per pixel area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device having a compensating thin film transistor for compensating off-current characteristics of a thin film transistor having a polycrystalline silicon semiconductor material .

Another object of the present invention is to provide a liquid crystal display device having a compensating thin film transistor having a polycrystalline silicon semiconductor layer and having a pixel structure capable of securing a high aperture ratio.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of data lines and gate lines intersecting with each other, first electrodes, at least one second electrode, and a semiconductor layer. Each of the plurality of gate lines is arranged to intersect a plurality of data lines and has a zigzag pattern. The first electrodes are disposed between the data lines, respectively. The second electrode is supplied with a reference voltage to form an electric field with the first electrodes. And a second region connected to the first region by a first connection portion and overlapped with the gate line at a second position, the first region being connected to the data line, A third region overlapping with the gate line at a second position and connected to the second region by a second connection portion, and a second region connected to the first electrode and connected to the third region by a third connection portion, And the fourth region.

In the above structure, the first thin film transistor is formed by the first connection portion, the second region, the second connection portion, and the gate line, and the second connection portion, the third region, the third connection portion, Wherein the first connection part is a first source electrode of the first thin film transistor and the second area is a first semiconductor channel of the first thin film transistor, Wherein the gate line is a gate electrode of the first thin film transistor, the second connection portion is a second source electrode of the second thin film transistor, the third region is a gate electrode of the first thin film transistor, The second semiconductor channel of the second thin film transistor, and the third connection portion is the second drain electrode of the second thin film transistor, Is the gate electrode of the second thin film transistor.

In addition, the second region and the third region are respectively disposed in regions divided by the data lines.

Also, at least one of the second region and the third region may be a parallelogram.

In addition, the second connection portion intersects the data line at a right angle, and is arranged to cross the gate line in an oblique direction.

The fourth region may be connected to the first electrode through a connection pattern.

The zigzag pattern of the gate line may include first and second oblique lines symmetrical to each other with respect to the data line direction as a central axis, and the connection pattern may include two areas overlapping the first and second oblique lines, .

The semiconductor layer is disposed on a substrate, the gate line is disposed on a gate insulating film covering the semiconductor layer, the data line is disposed on an interlayer insulating film covering a gate line, And is connected to the first region through a first contact hole penetrating the gate insulating film.

The connection pattern is disposed on the interlayer insulating film so as to be spaced apart from the data line and connected to the four regions through the interlayer insulating film and the second contact hole passing through the gate insulating film, And a second passivation film covering the connection pattern and being connected to the fourth region through a third contact hole passing through the first passivation film, and the second electrode is connected to the fourth region through the second passivation film covering the second electrode And is disposed on the passivation film.

The connection pattern is disposed on the interlayer insulating film so as to be spaced apart from the data line and connected to the four regions through the interlayer insulating film and the second contact hole passing through the gate insulating film, And a first passivation film covering the connection pattern, the first electrode being disposed on a second passivation film covering the second electrode, and the second passivation film covering the second passivation film and the first passivation film And is connected to the connection pattern through a third contact hole.

According to the liquid crystal display of the present invention, since the gate line and the semiconductor layer cross each other in a zigzag pattern so that the first semiconductor channel region and the second semiconductor channel region of the semiconductor layer overlapping the gate line are increased . Therefore, since the first semiconductor channel and the second semiconductor channel region can be increased compared with the case where the gate line and the semiconductor layer intersect at right angles, the effect of reducing the opening area by the increment can be obtained.

In addition, since the gate line is formed in a zigzag pattern and the connection pattern connected to the second drain electrode overlaps with a partial region of the first oblique portion and a partial region of the second oblique portion of the gate line, Even when shifted in one direction, there is no great difference in the gate-drain overlap structure. Therefore, it is possible to minimize the variation of the capacitance between the gate line and the drain, thereby improving the image quality deficiency due to the difference in luminance between pixels in the display panel.

1 is a plan view showing a thin film transistor substrate of a conventional liquid crystal display device having an oxide semiconductor layer,
2 is a cross-sectional view taken along line II 'of FIG. 1,
3 is a plan view showing a thin film transistor substrate of a liquid crystal display device including a conventional compensating thin film transistor,
4 is a plan view showing a thin film transistor substrate of a liquid crystal display device including a compensation thin film transistor according to an embodiment of the present invention,
FIG. 5A is a plan view showing an overlapped portion of the semiconductor layer and the gate line in the region R1 shown in FIG. 4,
FIG. 5B is a plan view showing the overlapped portion of the gate line and the connection pattern of the region R1 shown in FIG. 4,
6 is a cross-sectional view showing an example taken along line I-I 'of the thin film transistor substrate shown in FIG. 4,
7 is a sectional view showing another example taken along the line I-I 'of the thin film transistor substrate shown in FIG. 4;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 4 to 7. FIG. 4 is a plan view showing a thin film transistor substrate of a liquid crystal display device including a compensation thin film transistor according to an embodiment of the present invention. 5A is a plan view showing an overlapped portion of the gate line and the semiconductor layer in the region R1 shown in FIG. 5B is a plan view showing the overlapping portion of the gate line and the connection pattern of the region R1 shown in FIG. 6 is a cross-sectional view illustrating an example taken along line I-I 'of the thin film transistor substrate shown in FIG. 7 is a cross-sectional view showing another example taken along line I-I 'of the thin film transistor substrate shown in FIG.

Referring to FIG. 4, a thin film transistor substrate of a liquid crystal display device including a compensating thin film transistor according to an embodiment of the present invention includes a plurality of data lines DL1, DL2, DL3, ..., and gate lines GL1 and GL2 , A plurality of pixel electrodes Px, at least one common electrode (COM of FIGS. 6 and 7), a driving thin film transistor T1, and a compensating thin film transistor T2. In Fig. 4, the configuration of the common electrode is omitted in order to avoid complication of the drawing.

A plurality of data lines DL1, DL2, DL3, ... are arranged in a first direction. The plurality of gate lines GL1, GL2, ... are arranged in a second direction intersecting the plurality of data lines DL1, DL2, DL3, .... Each of the gate lines GL1, GL2, ... has a zigzag pattern. For example, each of the gate lines GL1, GL2, ... has first and second oblique portions symmetrical with respect to a direction in which the data lines DL1, DL2, DL3, As shown in FIG. At this time, the vertexes of the gate lines GL1, GL2, ... are positioned so as to overlap with the data lines. The portion where the first oblique line SL1 and the second oblique line SL2 of the gate lines GL1, GL2, ... are joined may be formed as a horizontal portion.

In the example of FIG. 4, the first direction is the x-axis direction and the second direction is the y-axis direction, but the present invention is not limited thereto. For example, the first direction may be a y-axis direction, the second direction may be an x-axis direction, or a direction having an inclination angle with respect to the x-axis and the y-axis.

The plurality of pixel electrodes Px may be disposed in a pixel region defined by the intersection of the plurality of data lines DL1, DL2, DL3, ... and the gate lines GL1, GL2, .... Alternatively, the pixel electrodes Px arranged on the same line may be arranged between the data lines DL1, DL2, DL3, ..., and overlapped with the gate lines GL1, GL2, ....

At least one common electrode (COM in Fig. 6 and Fig. 7) is arranged so as to form a horizontal electric field with the pixel electrodes Px. The common electrode is supplied with a reference voltage (or a common voltage) for driving the liquid crystal through a common line (not shown) arranged in parallel with the gate line. The common electrode may be composed of one electrode overlapping all the pixel electrodes, or may be divided into a plurality of pixel electrodes overlapping a predetermined number of pixel electrodes.

The driving thin film transistor T1 and the compensation thin film transistor T2 are arranged for each pixel region. The driving thin film transistor T1 and the compensating thin film transistor T2 are connected to each other in such a manner that the drain electrode D1 of the driving thin film transistor T1 is connected to the source electrode S2 of the compensation thin film transistor T2. The pixel signals of the data lines DL1, DL2, DL3, ... can be charged and held in the pixel electrodes Px in response to the gate signals supplied through the gate lines GL1, GL2,

The connection structure between the driving thin film transistor T1 and the compensating thin film transistor T2 will now be described in detail with reference to the region R1 shown in FIG. 4 and FIGS. 5A and 5B.

The driving thin film transistor T1 and the compensating thin film transistor T2 are connected to each other by the semiconductor layer SE.

The semiconductor layer SE is formed using a polycrystalline silicon material. The semiconductor layer SE includes a first region connected to the data line DL1, a second region overlapping with the first oblique portion SL1 of the gate line GL1, A third region overlapped with the pixel electrode SL2, and a fourth region overlapping the pixel electrode Px.

The semiconductor layer SE further includes a first connecting portion C1 connecting the first region and the second region, a second connecting portion C2 connecting the second region and the third region, And a third connecting portion C3 connecting the first and second connecting portions.

Accordingly, the semiconductor layer SE has a structure in which the first region, the first connection portion C1, the second region, the second connection portion C2, the third region, the third connection portion C3, and the fourth region are continuously connected . The first region, the first connection portion C1, the second connection portion C2, the third connection portion C3 and the fourth region of the semiconductor layer SE are portions that are made conductive by the plasma treatment, The second region and the third region are semiconductor channels that are made conductive only when a voltage equal to or greater than a threshold value is applied.

The first gate electrode G1 of the driving thin film transistor T1 is connected to the gate line GL in which the first oblique line SL1 of the gate line GL1 and the semiconductor layer SE overlap, to be. That is, a part of the first hatched portion SL1 of the gate line GL1 serves as the gate electrode G1 of the driving TFT T1.

The first source electrode S1 of the driving thin film transistor T1 does not have a separate electrode and uses the first connection portion C1 of the semiconductor layer SE. That is, the first connection part C1 of the semiconductor layer SE becomes the first source electrode S1 of the driving thin film transistor T1.

A separate electrode is not formed in the first drain electrode D1 of the driving thin film transistor T1 and a second connecting portion C2 of the semiconductor layer SE is used. That is, the second connecting portion C2 of the semiconductor layer SE becomes the first drain electrode D1 of the driving TFT T1.

The first semiconductor channel A1 of the driving thin film transistor T1 is a region of the semiconductor layer SE in which the first hatched portion SL1 of the gate line GL1 and the semiconductor layer SE overlap.

Therefore, the driving thin film transistor T1 includes the first gate electrode G1, the first semiconductor channel A1 overlapping with the first gate electrode G1, the first semiconductor channel A1 overlapping the first semiconductor channel A1, A source electrode S1 and a first drain electrode D1.

The second gate electrode G2 of the compensating thin film transistor T2 is a region of the gate line GL1 in which the second oblique line segment SL2 of the gate line GL1 and the semiconductor layer SE overlap. That is, a part of the second hatched portion SL2 of the gate line GL1 becomes the second gate electrode G2 of the compensating thin film transistor T2.

The second source electrode S2 of the compensating thin film transistor T2 does not form a separate electrode but uses the second connecting portion C2 of the semiconductor layer SE. That is, the second connecting portion C2 of the semiconductor layer SE becomes the second source electrode S2 of the compensating thin film transistor T2.

The second drain electrode D2 of the compensating thin film transistor T2 does not form a separate electrode but uses the third connecting portion C3 of the semiconductor layer SE. That is, the third connecting portion C3 of the semiconductor layer SE becomes the second drain electrode D1 of the compensating thin film transistor T2.

The second semiconductor channel A2 of the compensating thin film transistor T2 is a region of the semiconductor layer SE in which the second hatched portion SL2 of the gate line GL1 and the semiconductor layer SE overlap.

Therefore, the compensating thin film transistor T2 has the second gate electrode G2, the second semiconductor channel A2 overlapping the second gate electrode G2, the second semiconductor channel A2 overlapping the second semiconductor channel A2, A source electrode S2 and a second drain electrode D2.

The drain electrode D of the compensating thin film transistor T2 is connected to the pixel electrode Px formed in the pixel region through the connection pattern CP. The connection pattern CP includes two regions overlapping with the first oblique portion SL1 and the second oblique portion SL2 of the gate line GL1, respectively, as shown in FIG. 5B.

The pixel electrode Px and the common electrode (Figs. 6 and 7, COM) are arranged so as to overlap each other with a silver passivation film interposed therebetween. The common electrode COM is connected to a common wiring (not shown) arranged in parallel with the gate line GL1. The common electrode COM is supplied with a reference voltage (or a common voltage) for liquid crystal driving through a common wiring. A fringe field type electric field is formed between the pixel electrode Px and the common electrode. An auxiliary capacitance is formed in a region where the pixel electrode Px and the common electrode overlap each other. The liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy by the fringe field type electric field. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, so that the gradation according to the pixel data can be realized.

Next, a sectional configuration of a thin film transistor substrate of a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a cross-sectional view illustrating an example taken along line I-I 'of the thin film transistor substrate shown in FIG. 7 is a cross-sectional view showing another example taken along line I-I 'of the thin film transistor substrate shown in FIG.

In the thin film transistor substrate of the liquid crystal display according to the embodiment of the present invention, the driving thin film transistor T1 and the compensating thin film transistor T2 are formed by using the polycrystalline silicon semiconductor material. In this case, since the semiconductor layer SE is disposed below the gate electrode in view of the characteristics of the semiconductor material, a thin film transistor of a top gate structure is applied.

Referring to FIG. 6, light-shielding layers LS1 and LS2 are disposed on a substrate SUB. The light shielding layers LS1 and LS2 are arranged corresponding to the regions where the semiconductor channels are to be formed. That is, the first light-shielding layer LS1 is disposed in an area overlapping with the first semiconductor channel A of the driving thin film transistor T1, and the second light-shielding layer LS2 is disposed in a region overlapping with the first semiconductor channel A of the compensating thin film transistor T2. (A). When the first and second light shielding layers LS1 and LS2 are disposed on the substrate SUB, it is possible to prevent the semiconductor elements from being deteriorated by the light emitted from the backlight unit under the substrate SUB Can be obtained.

A buffer layer BUF is applied on the entire surface of the substrate SUB on which the first and second light blocking layers LS1 and LS2 are formed. A semiconductor layer SE is disposed on the buffer layer BUF. The semiconductor layer SE includes a first region connected to the data line DL1, a first connection C1 as a first source electrode S1, a second connection region C1 as a first semiconductor channel A second connection portion C2 as a first drain electrode D1 and a second source electrode S2, a third region as a second semiconductor channel A2, and a second region as a second drain electrode D2 A third connection part C3, and a fourth area connected to the connection pattern CP.

The semiconductor layer SE is divided into a region in which the gate insulating film GI and the gate line GL1 are overlapped and a non-overlapping region. When the impurity is implanted into the region that is not overlapped with the gate line GL and is made conductive, the semiconductor layer SE overlapping with the gate line GL1 becomes the semiconductor channel A1 or A2. That is, the semiconductor layer SE overlapped with the first gate electrode G1 becomes the first channel region A1 of the driving TFT T1, and the semiconductor layer SE overlapping the compensation gate electrode G2 And becomes the semiconductor channel A2 of the compensating thin film transistor T2.

On the entire surface of the substrate SUB on which the semiconductor layer SE is formed, a gate insulating film GI and a gate line GL1, which are formed by applying and patterning a gate insulating material and a gate metal material, are disposed. The gate line GL1 has two regions crossing the semiconductor layer SE per each pixel. The two regions of the gate line GL1 overlapping the first and second semiconductor channels A1 and A2 of the semiconductor layer SE are electrically connected to the first gate electrode G1 of the driving TFT T1 and the compensation TFT T2 Of the second gate electrode G2.

An interlayer insulating film INS is applied on the entire surface of the substrate SUB on which the gate line GL1 including the first and second gate electrodes G1 and G2 is formed.

A source contact hole SH exposing a part of the first source electrode S1 of the driving thin film transistor T1 and a part of the drain electrode D2 of the compensating thin film transistor T2 are exposed to the interlayer insulating film INS A drain contact hole DH is formed. On the interlayer insulating film INS, the data line DL1 formed of the source-drain metal material and the connection pattern CP are disposed separately from each other. The data line DL1 is connected to the first source electrode S1 through the source contact hole SH. The connection pattern CP is connected to the second drain electrode D2 through the drain contact hole DH. The data line DL1 is arranged to cross the gate line GL1.

In the present invention, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 are not separately formed, Layer (SE) is used. Therefore, it is possible to reduce the size of the non-display region in the pixel region, thereby increasing the aperture ratio.

A first passivation film PAS1 covering the driving thin film transistor T1 and the compensating thin film transistor T2 is applied on the entire surface of the substrate SUB. A pixel contact hole PH exposing a part of the connection pattern CP is formed on the first passivation film PAS1. On the first passivation film PAS1 on which the pixel contact holes PH are formed, the pixel electrodes Px are arranged for each pixel region. The pixel electrode Px is connected to the connection pattern CP exposed through the pixel contact hole PH and is connected to the second drain electrode D2 through the connection pattern CP.

The second passivation film PAS2 is disposed on the entire surface of the first passivation film PAS1 on which the pixel electrode Px is disposed so as to cover the pixel electrode Px. On the second passivation film PAS2, the common electrode COM is disposed so as to overlap the pixel electrode. The common electrode COM may have an opening to form a fringe field type electric field with the pixel electrode Px or may be formed in a comb shape.

Referring to FIG. 6, light-shielding layers LS1 and LS2 are disposed on a substrate SUB. The light shielding layers LS1 and LS2 are arranged corresponding to the regions where the semiconductor channels are to be formed. That is, the first light-shielding layer LS1 is disposed in an area overlapping with the first semiconductor channel A of the driving thin film transistor T1, and the second light-shielding layer LS2 is disposed in a region overlapping with the first semiconductor channel A of the compensating thin film transistor T2. (A). When the first and second light shielding layers LS1 and LS2 are disposed on the substrate SUB, it is possible to prevent the semiconductor elements from being deteriorated by the light emitted from the backlight unit under the substrate SUB Can be obtained.

A buffer layer BUF is applied on the entire surface of the substrate SUB on which the first and second light blocking layers LS1 and LS2 are formed. A semiconductor layer SE is disposed on the buffer layer BUF. The semiconductor layer SE includes a first region connected to the data line DL1, a first connection C1 as a first source electrode S1, a second connection region C1 as a first semiconductor channel A second connection portion C2 as a first drain electrode D1 and a second source electrode S2, a third region as a second semiconductor channel A2, and a second region as a second drain electrode D2 A third connection part C3, and a fourth area connected to the connection pattern CP.

The semiconductor layer SE is divided into a region in which the gate insulating film GI and the gate line GL1 are overlapped and a non-overlapping region. When the impurity is implanted into the region that is not overlapped with the gate line GL and is made conductive, the semiconductor layer SE overlapping with the gate line GL1 becomes the semiconductor channel A1 or A2. That is, the semiconductor layer SE overlapped with the first gate electrode G1 becomes the first channel region A1 of the driving TFT T1, and the semiconductor layer SE overlapping the compensation gate electrode G2 And becomes the semiconductor channel A2 of the compensating thin film transistor T2.

On the entire surface of the substrate SUB on which the semiconductor layer SE is formed, a gate insulating film GI and a gate line GL1, which are formed by applying and patterning a gate insulating material and a gate metal material, are disposed. The gate line GL1 has two regions crossing the semiconductor layer SE per each pixel. The two regions of the gate line GL1 overlapping the first and second semiconductor channels A1 and A2 of the semiconductor layer SE are electrically connected to the first gate electrode G1 of the driving TFT T1 and the compensation TFT T2 Of the second gate electrode G2.

An interlayer insulating film INS is applied on the entire surface of the substrate SUB on which the gate line GL1 including the first and second gate electrodes G1 and G2 is formed.

A source contact hole SH exposing a part of the first source electrode S1 of the driving thin film transistor T1 and a part of the drain electrode D2 of the compensating thin film transistor T2 are exposed to the interlayer insulating film INS A drain contact hole DH is formed. On the interlayer insulating film INS, the data line DL1 formed of the source-drain metal material and the connection pattern CP are disposed separately from each other. The data line DL1 is connected to the first source electrode S1 through the source contact hole SH. The connection pattern CP is connected to the second drain electrode D2 through the drain contact hole DH. The data line DL1 is arranged to cross the gate line GL1.

In the present invention, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 are not separately formed, Layer (SE) is used. Therefore, it is possible to reduce the size of the non-display region in the pixel region, thereby increasing the aperture ratio.

A first passivation film PAS1 covering the driving thin film transistor T1 and the compensating thin film transistor T2 is applied on the entire surface of the substrate SUB. A pixel contact hole PH exposing a part of the connection pattern CP is formed on the first passivation film PAS1. On the first passivation film PAS1 on which the pixel contact holes PH are formed, the pixel electrodes Px are arranged for each pixel region. The pixel electrode Px is connected to the connection pattern CP exposed through the pixel contact hole PH and is connected to the second drain electrode D2 through the connection pattern CP.

The second passivation film PAS2 is disposed on the entire surface of the first passivation film PAS1 on which the pixel electrode Px is disposed so as to cover the pixel electrode Px. On the second passivation film PAS2, the common electrode COM is disposed so as to overlap the pixel electrode. The common electrode COM may have a plurality of openings to form a fringe field type electric field with the pixel electrode Px, or may be formed in a comb shape.

Referring to FIG. 7, the light-shielding layers LS1 and LS2 are disposed on the substrate SUB. The light shielding layers LS1 and LS2 are arranged corresponding to the regions where the semiconductor channels are to be formed. That is, the first light-shielding layer LS1 is disposed in an area overlapping with the first semiconductor channel A of the driving thin film transistor T1, and the second light-shielding layer LS2 is disposed in a region overlapping with the first semiconductor channel A of the compensating thin film transistor T2. (A). When the first and second light shielding layers LS1 and LS2 are disposed on the substrate SUB, it is possible to prevent the semiconductor elements from being deteriorated by the light emitted from the backlight unit under the substrate SUB Can be obtained.

A buffer layer BUF is applied on the entire surface of the substrate SUB on which the first and second light blocking layers LS1 and LS2 are formed. A semiconductor layer SE is disposed on the buffer layer BUF. The semiconductor layer SE includes a first region connected to the data line DL1, a first connection C1 as a first source electrode S1, a second connection region C1 as a first semiconductor channel A second connection portion C2 as a first drain electrode D1 and a second source electrode S2, a third region as a second semiconductor channel A2, and a second region as a second drain electrode D2 A third connection part C3, and a fourth area connected to the connection pattern CP.

The semiconductor layer SE is divided into a region in which the gate insulating film GI and the gate line GL1 are overlapped and a non-overlapping region. When the impurity is implanted into the region that is not overlapped with the gate line GL and is made conductive, the semiconductor layer SE overlapping with the gate line GL1 becomes the semiconductor channel A1 or A2. That is, the semiconductor layer SE overlapped with the first gate electrode G1 becomes the first channel region A1 of the driving TFT T1, and the semiconductor layer SE overlapping the compensation gate electrode G2 And becomes the semiconductor channel A2 of the compensating thin film transistor T2.

On the entire surface of the substrate SUB on which the semiconductor layer SE is formed, a gate insulating film GI and a gate line GL1, which are formed by applying and patterning a gate insulating material and a gate metal material, are disposed. The gate line GL1 has two regions crossing the semiconductor layer SE per each pixel. The two regions of the gate line GL1 overlapping the first and second semiconductor channels A1 and A2 of the semiconductor layer SE are electrically connected to the first gate electrode G1 of the driving TFT T1 and the compensation TFT T2 Of the second gate electrode G2.

An interlayer insulating film INS is applied on the entire surface of the substrate SUB on which the gate line GL1 including the first and second gate electrodes G1 and G2 is formed.

A source contact hole SH exposing a part of the first source electrode S1 of the driving thin film transistor T1 and a part of the drain electrode D2 of the compensating thin film transistor T2 are exposed to the interlayer insulating film INS A drain contact hole DH is formed. On the interlayer insulating film INS, the data line DL1 formed of the source-drain metal material and the connection pattern CP are disposed separately from each other. The data line DL1 is connected to the first source electrode S1 through the source contact hole SH. The connection pattern CP is connected to the second drain electrode D2 through the drain contact hole DH. The data line DL1 is arranged to cross the gate line GL1.

In the present invention, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 are not separately formed, Layer (SE) is used. Therefore, it is possible to reduce the size of the non-display region in the pixel region, thereby increasing the aperture ratio.

A first passivation film PAS1 covering the driving thin film transistor T1 and the compensating thin film transistor T2 is applied on the entire surface of the substrate SUB. A common electrode COM is disposed on the first passivation film PAS1.

A second passivation film PAS2 is disposed on the first passivation film PAS1 on which the common electrode COM is disposed to cover the common electrode COM. A pixel contact hole PH for exposing the connection pattern CP is formed in the first and second passivation films PAS1 and PAS2. On the second passivation film PAS1 on which the pixel contact holes PH are formed, the pixel electrodes Px are arranged for each pixel region. The pixel electrode Px is connected to the connection pattern CP exposed through the pixel contact hole PH and is connected to the second drain electrode D2 through the connection pattern CP. The pixel electrode Px may have a plurality of openings to form a fringe field type electric field with the common electrode COM, or may be formed in a comb shape.

Since the gate line GL1 is formed in a staggered pattern and the gate line GL1 and the semiconductor layer SE cross each other with an oblique line, the gate line GL1, The first semiconductor channel A1 and the second semiconductor channel A2 region of the semiconductor layer SE overlapping with each other become a parallelogram. Therefore, since the first semiconductor channel A1 and the second semiconductor channel A2 region are increased as compared with the case where the gate line GL1 and the semiconductor layer SE intersect at right angles, the opening area can be reduced The effect can be obtained.

The gate line GL1 is formed in a zigzag pattern and the connection pattern CP connected to the second drain electrode D2 is formed in a part of the first oblique portion SL1 of the gate line GL1, The overlapped structure of the gate-drain overlaps with the partial region of the gate-drain overlapping structure SL2, so that even if the connection pattern CP is shifted in any one of the up, down, left, and right directions during the manufacturing process, Therefore, the variation of the capacitance between the gate line and the drain can be minimized, so that the problem of image quality deficiency due to the difference in luminance between pixels in the display panel can be solved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, although the top gate type thin film transistor structure has been described in the above description of the embodiments of the present invention, it may be applied to a bottom gate type.

 Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

GL: gate line DL: data line
CL: common wiring COM: common electrode
Px: pixel electrode PH: pixel contact hole
T1: driving thin film transistor T2: compensating thin film transistor
G, G1, G2: gate electrode S, S1, S2: source electrode
D, D1, D2: drain electrode A, A1, A2: semiconductor channel
GI: Gate insulating film PAS1, PAS2: Passivation film
SH: source contact hole SA: source region
DH: drain contact hole DA: drain region
INS: Interlayer insulating film

Claims (10)

A plurality of data lines;
A plurality of gate lines arranged to cross the plurality of data lines and having a zigzag pattern;
First electrodes disposed between the data lines, respectively;
At least one second electrode to which a reference voltage is supplied to form an electric field with the first electrodes;
A second region connected to the first region by a first connection portion and overlapped with the gate line at a first position, and a second region overlapping the gate line at a second position; A third region overlapping the gate line at a second position and connected to the second region by a second connection portion and a third region connected to the third region by a third connection portion, And a semiconductor layer including a region.
The method according to claim 1,
The first thin film transistor is formed by the first connection portion, the second region, the second connection portion, and the gate line,
The second thin film transistor is formed by the second connection portion, the third region, the third connection portion, and the gate line,
Wherein the first connection portion is a first source electrode of the first thin film transistor, the second region is a first semiconductor channel of the first thin film transistor, and the second connection portion is a first drain electrode of the first thin film transistor , The gate line is a gate electrode of the first thin film transistor,
The second connection portion is a second source electrode of the second thin film transistor, the third region is a second semiconductor channel of the second thin film transistor, and the third connection portion is a second drain electrode of the second thin film transistor And the gate line is a gate electrode of the second thin film transistor.
The method according to claim 1,
And the second region and the third region are respectively disposed in regions divided by the data lines.
The method according to claim 1,
And at least one of the second region and the third region is a parallelogram.
5. The method of claim 4,
Wherein the second connection portion intersects the data line at a right angle and intersects the gate line in an oblique direction.
6. The method according to any one of claims 1 to 5,
And the fourth region is connected to the first electrode through a connection pattern.
6. The method of claim 5,
Wherein the zigzag pattern of the gate line includes first and second oblique lines symmetrical to each other about a central axis of the data line direction,
Wherein the connection pattern includes two regions overlapping with the first and second oblique portions.
6. The method according to any one of claims 1 to 5,
Wherein the semiconductor layer is disposed on a substrate,
Wherein the gate line is disposed on a gate insulating film covering the semiconductor layer,
Wherein the data line is disposed on an interlayer insulating film covering a gate line and is connected to the first region through a first contact hole passing through the interlayer insulating film and the gate insulating film.
9. The method of claim 8,
Wherein the connection pattern is disposed on the interlayer insulating film so as to be spaced apart from the data line and connected to the four regions through the interlayer insulating film and a second contact hole penetrating the gate insulating film,
Wherein the first electrode is disposed on a first passivation film covering the data line and the connection pattern and is connected to the fourth region through a third contact hole passing through the first passivation film,
And the second electrode is disposed on a second passivation film covering the first electrode.
9. The method of claim 8,
Wherein the connection pattern is disposed on the interlayer insulating film so as to be spaced apart from the data line and connected to the four regions through the interlayer insulating film and a second contact hole penetrating the gate insulating film,
The second electrode is disposed on a first passivation film covering the data line and the connection pattern,
Wherein the first electrode is disposed on a second passivation film covering the second electrode and connected to the connection pattern through a third contact hole passing through the second passivation film and the first passivation film.

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