KR20170026900A - Organic light emitting display device - Google Patents

Abstract

Disclosed is an organic light emitting display device comprising: a plurality of data lines; and a display panel having a plurality of sub pixels defined by the plurality of data lines. Each sub pixel includes: an organic light emitting diode; a driving transistor driving the organic light emitting diode; and a first switching transistor connected with the data lines. The driving transistor and the first switching transistor are disposed by overlapping with each other while interposing an insulation layer. Accordingly, the life of the device can be elongated by widening the area of an electrode in the organic light emitting diode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display.

2. Description of the Related Art In recent years, an organic light emitting diode (OLED) display device that has been spotlighted as a display device has a high response speed by using an organic light emitting diode (OLED) that emits light by itself, and has great advantages such as luminous efficiency, luminance and viewing angle.

Such an organic light emitting display device arranges sub-pixels including an organic light emitting diode (OLED) in a matrix form and controls the brightness of sub-pixels selected by a scan signal according to data gradation. In addition to the organic light emitting diode, each sub-pixel of the organic light emitting display includes a data line and a gate line intersecting with each other, and a transistor and a storage capacitor having a connection structure.

In the organic light emitting diode display, signal lines such as a data line, a driving voltage line, and a reference voltage line are disposed on the left and right sides of the sub-pixels, and the aperture ratio (light emitting area) of the sub-pixel is reduced as the area where the signal lines are located is larger.

Particularly, recently, a sub-pixel area has been reduced according to the demand for high resolution. To prevent this, a method of reducing the width of signal lines has been proposed. However, since the resistance increases when the width of signal lines is reduced, Can not be reduced.

As described above, the sub-pixel aperture ratio of the organic light emitting display device must be limited by adjacent signal wirings, and there is a limit to increase the aperture ratio in the sub-pixel.

When the sub-pixel aperture ratio of the organic light emitting display device is reduced, the electrode area of the organic light emitting diode is reduced, and the current density J is increased to cause deterioration of the organic light emitting diode.

In addition, if the sub-pixel aperture ratio of the organic light emitting display device is reduced, the area of the organic light emitting diode and the electrodes constituting the organic light emitting diode are reduced, thereby shortening the lifetime of the device.

It is an object of the present invention to provide an organic light emitting diode display device in which the switching transistor and the driving transistor disposed in each sub pixel region are vertically stacked with an insulating layer interposed therebetween to improve the aperture ratio of the organic light emitting diode.

It is another object of the present invention to provide an organic light emitting diode display device in which the driving transistor disposed in the sub pixel region is three-dimensionally arranged on the switching transistor, thereby widening the electrode area of the organic light emitting diode and increasing the device lifetime.

According to an aspect of the present invention, there is provided an OLED display device including a display panel including a plurality of data lines and a plurality of gate lines, A driving transistor for driving the organic light emitting diode, and a first switching transistor connected to the data line, wherein the driving transistor and the first switching transistor are overlapped with each other with an insulating layer interposed therebetween Thus, the electrode area of the organic light emitting diode is widened and the lifetime of the device is increased.

Also, the organic light emitting diode display of the present invention includes a display panel having a plurality of data lines and a plurality of sub-pixels defined by a plurality of gate lines, each sub pixel including an organic light emitting diode, A first switching transistor connected to the data line, and a second switching transistor electrically connected between a node between the driving transistor and the organic light emitting diode and a reference voltage line, And the second switching transistor are overlapped with each other with the insulating layer interposed therebetween, thereby improving the aperture ratio of the organic light emitting diode.

The organic light emitting diode display according to the present invention has the effect of improving the aperture ratio of the organic light emitting diode by vertically overlapping the switching transistor and the driving transistor disposed in each sub pixel region with an insulating layer interposed therebetween.

In addition, the organic light emitting display according to the present invention has the effect of increasing the device lifetime by enlarging the electrode area of the organic light emitting diode by disposing the driving transistor arranged in the sub pixel region in three dimensions on the switching transistor.

1 is an overall system configuration diagram of an organic light emitting diode display according to the present invention.
2A and 2B are diagrams illustrating an equivalent circuit and a sub-pixel structure of a sub-pixel in the display panel of FIG. 1 according to an embodiment of the present invention.
3A and 3B are diagrams illustrating an equivalent circuit and a sub-pixel structure of a sub-pixel in the display panel of FIG. 1 according to an embodiment of the present invention.
4 is a plan view showing a switching transistor and a driving transistor superimposed in a sub-pixel of the organic light emitting diode display of the present invention.
5 is a cross-sectional view of a sub-pixel of the organic light emitting diode display of the present invention.
6 is a cross-sectional view taken along the line I-I 'of FIG.
7 is a cross-sectional view taken along line II-II 'of FIG.
8 is a cross-sectional view taken along line III-III 'of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is an overall system configuration diagram of an organic light emitting diode display according to the present invention.

1, the OLED display 10 includes a plurality of data lines DL formed in one direction and a plurality of data lines DL formed in the other direction crossing the plurality of data lines DL. And a plurality of data lines DL1 to DLm, m being a natural number of 1 or more) including a plurality of sub pixels (SP: Sub Pixel) arranged in each intersection region of a gate line (GL: Gate Line) A gate driver 13 for supplying a scan signal through a plurality of gate lines GL1 to GLn and n being a natural number greater than or equal to 1 and a data driver 12 for supplying a data voltage to the data driver 12, A timing controller 14 for controlling the driving timing of the gate driver 13, and the like.

In addition, an organic light emitting diode (OLED) is disposed in each sub-pixel SP. The organic light emitting diode OLED receives a driving voltage EVDD by a driving transistor and emits light. EVSS is a base voltage for supplying a low voltage to the organic light emitting diode (OLED).

The data driver 12 drives a plurality of data lines by supplying data voltages to the plurality of data lines.

The gate driver 13 sequentially supplies the scan signals to the plurality of gate lines to sequentially drive the plurality of gate lines.

The timing controller 14 controls the data driver 12 and the gate driver 13 by supplying various control signals to the data driver 12 and the gate driver 13.

The timing controller 14 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 12, and outputs the converted image data , And controls the data driving at a suitable time according to the scan.

The gate driver 13 sequentially supplies the scan signals of the On voltage or the Off voltage to the plurality of gate lines in accordance with the control of the timing controller 14 to sequentially drive the plurality of gate lines.

1, the gate driver 13 may be located only on one side of the display panel 11, or may be located on both sides depending on the driving system, the design method of the display panel 11, and the like .

In addition, the gate driver 13 may include one or more gate driver integrated circuits.

Each gate driver integrated circuit may be connected to a bonding pad of the display panel 11 by a Tape Automated Bonding (TAB) method or a chip on glass (COG) method, or may be connected to a GIP (Gate In Panel) Type and may be directly disposed on the display panel 11, and may be integrated and disposed on the display panel 11 as the case may be.

Each gate driver integrated circuit can be implemented by a chip on film (COF) method. In this case, the gate drive chip corresponding to each gate driver integrated circuit is mounted on the flexible film, and one end of the flexible film can be bonded to the display panel 11. [

When the specific gate line is opened, the data driver 12 converts the image data received from the timing controller 14 into an analog data voltage and supplies the data voltage to a plurality of data lines, thereby forming a plurality of data lines DL1, .., DLm .

The data driver 12 may include at least one source driver integrated circuit to drive a plurality of data lines.

Each source driver integrated circuit is connected to a bonding pad of the display panel 11 by a tape automated bonding (TAB) method or a chip on glass (COG) And may be integrated and disposed on the display panel 11, as the case may be.

In addition, each source driver integrated circuit may be implemented by a chip on film (COF) method. In this case, the source driver chip corresponding to each source driver integrated circuit is mounted on the flexible film, one end of the flexible film is bonded to at least one source printed circuit board, and the other end is connected to the display panel 11).

2A and 2B are diagrams illustrating an equivalent circuit and a sub-pixel structure of a sub-pixel in the display panel of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 1, FIGS. 2A and 2B will be described as follows.

The organic light emitting diode display 10 of the present invention is characterized in that a sub pixel is defined by one gate line GL and one data line DL in the display panel 11 and a plurality of sub pixels are arranged in a matrix form . Here, the sub-pixel is referred to as a first sub-pixel SP1.

The first sub-pixel SP1 includes a switching transistor SW-T, a driving transistor DR-T, a storage capacitor Cst, and an organic light emitting diode (OLED) do. In FIG. 2A, each first sub-pixel SP1 has a 2T (Transistor) and 1C (Capacitor) structure.

The switching transistor SW-T and the driving transistor DR-T are implemented as P-type MOS-FETs, but they are not fixed and can be implemented as N-type MOS-FETs.

The switching transistor SW-T turns on in response to a scan pulse from the gate line GL, thereby conducting a current path between the source electrode and the drain electrode of the switching transistor SW-T. The switching transistor SW-T applies a data voltage from the data line DL to the gate electrode of the driving transistor DR-T and the storage capacitor Cst during the turn-on period.

The driving transistor DR-T receives a driving voltage EVDD through a driving voltage line (DVL) and receives a difference voltage Vgs between a gate electrode and a source electrode of the driving transistor DR-T Thereby controlling the current flowing in the organic light emitting diode OLED. The storage capacitor Cst maintains the gate potential of the driving transistor DR-T constant for one frame. EVSS is the base voltage supplied to the organic light emitting diode (OLED).

In the present invention, in the first sub-pixel SP1 having the 2T1C structure, the switching transistor SW-T and the driving transistor DR-T are arranged vertically and superposedly with an insulating layer (planarizing film) The aperture ratio of each sub-pixel of the display device 10 is increased.

Conventionally, the switching transistor SW-T and the driving transistor DR-T are disposed adjacent to each other on a two-dimensional plane in a sub-pixel, which has a limitation in increasing the aperture ratio. That is, the switching transistor SW-T and the driving transistor DR-T occupy respective regions on the two-dimensional plane of the sub-pixel.

2B, the first sub-pixel SP1 is divided by the data line DL, the gate line GL and the driving voltage line DVL, A switching transistor SW-T is arranged in an intersecting region of the gate line GL and a driving transistor DR-T is arranged to overlap with the switching transistor SW-T.

That is, although the switching transistor SW-T and the driving transistor DR-T of the present invention are located in the same region in the two-dimensional plane of the first sub-pixel SP1, Are vertically stacked.

The conventional driving transistor DR-T is located on the upper side or adjacent side of the switching transistor SW-T and the opening region (light emitting region) of the organic light emitting diode OLED is up to SP1 'indicated by dotted lines. The opening region of the first sub-pixel SP1 is extended to the solid line region where the driving transistor DR-T is disposed. Here, the opening region means the light emitting region of the organic light emitting diode.

This is because the driving transistor DR-T overlaps with the switching transistor SW-T and the organic light emitting diode OLED can be extended and arranged in a region where the previous driving transistor DR-T is disposed.

3A and 3B are diagrams illustrating an equivalent circuit and a sub-pixel structure of a sub-pixel in the display panel of FIG. 1 according to an embodiment of the present invention.

1 to 3B, an OLED display 10 according to another exemplary embodiment of the present invention includes a display panel 11, a gate line GL, and a data line DL. Sub-pixel is defined, which is referred to herein as a second sub-pixel SP2.

The second sub-pixel SP2 includes an organic light emitting diode (OLED) and includes a driving transistor DR-T, a first switching transistor SW1-T, a second switching transistor SW2-T, A storage capacitor Cst, and the like.

 Since each pixel includes three transistors DR-T, SW1-T, and SW2-T and one storage capacitor Cst, each pixel has a 3T (Capacitor) structure do.

The driving transistor DR-T in each pixel receives a driving voltage EVDD supplied from a driving voltage line (DVL: Driving Voltage Line) and is supplied to the gate node N2) (data voltage) to drive the organic light emitting diode OLED.

The driving transistor DR-T has a first node N1, a second node N2 and a third node N3. The first node N1 includes a second switching transistor SW2-T, The second node N2 is connected to the first switching transistor SW1-T and the third node N3 is supplied with the driving voltage EVDD.

Here, in one example, the first node of the driving transistor DR-T is a source node (also referred to as a 'source electrode') and the second node is a gate node , And the third node N3 may be a drain node (also referred to as a drain electrode). The first node, the second node, and the third node of the driving transistor DR-T may be changed depending on the type of the transistor, the circuit change, and the like.

The second switching transistor SW2-T is controlled by a scan signal SCAN supplied from the gate line GL and includes a reference voltage line RVL for supplying a reference voltage Vref Line and the first node N1 of the driving transistor DR-T. This second switching transistor SW2-T is also referred to as a " sensor transistor ".

The first switching transistor SW1-T is controlled by a scan signal SCAN commonly supplied from the gate line GL and is connected to the second node N2 of the corresponding data line DL and the driving transistor DR- N2. The first switching transistor SW1-T is also referred to as a " switching transistor ".

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DR-T to maintain the data voltage for one frame.

As described above, the first switching transistor SW1-T and the second switching transistor SW2-T are controlled by one scan signal supplied through one same gate line (common gate line). As described above, since each pixel uses one scan signal, each pixel in the embodiment has a basic pixel structure of " 3T1C-based one scan structure ".

3B, in another example of the present invention, the second switching transistor SW2-T, which is the sensor transistor, and the driving transistor DR-T are arranged so as to overlap each other with an insulating layer interposed therebetween.

Thus, when the conventional second switching transistor SW2-T is located on the two-dimensional plane in the vicinity of the driving transistor DR-T, it is the opening region of the sub-pixel up to SP'2.

However, as in the present invention, by overlapping the second switching transistor SW2-T and the driving transistor DR-T with the insulating layer interposed therebetween, the second switching transistor SW2- The aperture area of the pixel can be increased.

Although the drawing shows a structure in which the second switching transistor SW2-T and the driving transistor DR-T are superimposed with an insulating layer sandwiched therebetween, this is not fixed.

The first switching transistor SW1, the second switching transistor SW2-T, and the driving transistor DR-T may be formed by overlapping the first switching transistor SW1-T and the driving transistor DR- ) May be alternately arranged so as to overlap each other with the insulating layers interposed therebetween.

As described above, the organic light emitting display according to the present invention has the effect of improving the aperture ratio of the organic light emitting diode by vertically overlapping the switching transistor and the driving transistor disposed in each sub pixel region with an insulating layer interposed therebetween.

In addition, the organic light emitting display according to the present invention has the effect of increasing the device lifetime by enlarging the electrode area of the organic light emitting diode by disposing the driving transistor arranged in the sub pixel region in three dimensions on the switching transistor.

FIG. 4 is a plan view showing a switching transistor and a driving transistor overlapping in a sub-pixel of the organic light emitting display according to the present invention, FIG. 5 is a sectional view of a sub-pixel of the organic light emitting display according to the present invention, FIG. 7 is a cross-sectional view taken along the line II-II 'of FIG. 4, and FIG. 8 is a cross-sectional view taken along the line III-III' of FIG.

FIGS. 4 to 8 show a structure in which switching transistors and driving transistors are vertically stacked on a sub-pixel having a 2T (Capacitor) structure shown in FIG. 2A. Therefore, the transistors arranged in the sub pixel area of the display device can be selectively superposed in the same manner.

Referring to FIG. 2A, FIGS. 4 to 8 will be described. FIG.

The organic light emitting display device of the present invention is characterized in that a data line DL and a gate line GL intersect each other to define a sub-pixel SP and an organic light emitting diode OLED, a switching transistor SW -T, a driving transistor DR-T, a storage capacitor Cst, and the like.

The sub-pixel SP includes an emission area EA for emitting an organic light emitting diode (OLED), a switching transistor SW-T, a driving transistor DR-T, and a storage capacitor Cst And a non-emission area (NEA).

In the present invention, the switching transistor SW-T and the driving transistor DR-T arranged in the non-emission region NEA are arranged three-dimensionally (three-dimensionally) And the area where the switching transistor SW-T is disposed is removed on the plane, thereby increasing the aperture ratio.

As shown in the figure, a first source electrode S1, a first drain electrode D1, a first active pattern ACT1, a first gate pattern GL1, a first interlayer insulating film A switching transistor SW-T constituted by a first gate electrode G1 and a first gate electrode G1 are arranged on the substrate 100. A first flattening film 108 as an insulating layer is stacked on the switching transistor SW- The first gate electrode GL1 and the second gate electrode G2 are formed of the second source electrode S2, the second drain electrode D2, the second active pattern ACT2, the second gate pattern GL2, the second interlayer insulating film 204, A driving transistor DR-T is disposed.

The first gate electrode G1 of the switching transistor SW-T is branched from the gate line 110 and the second gate electrode G2 of the driving transistor DR-T is connected to the first storage electrode E1 ). The first drain electrode D1 of the switching transistor SW-T is connected to the second gate electrode of the driving transistor DR-T disposed on the first planarization layer 108 through the connection pattern CP G2), that is, the first storage electrode E1 formed integrally with the second gate electrode G2 (III-III 'in FIG. 8).

6, a first insulation pattern 121 is disposed on the lower side of the gate line 110, and on the gate line 110, A data line DL is disposed with an interlayer insulating film 104 interposed therebetween.

The first storage electrode E1 is electrically connected to the first drain electrode D1 of the switching transistor SW-T through a connection pattern CP (see II-II 'in FIG. 7). The first storage electrode E1 may be used as a storage electrode in a sub pixel together with a second storage electrode E2 extending from a second drain electrode D2 of the driving transistor DR-T . Since the second gate electrode G2 of the driving transistor DR-T and the first storage electrode E1 are formed together, the second gate electrode G2 and the first storage electrode E1 A second insulating pattern 202 is disposed (II-II 'in FIG. 7 and III-III' in FIG. 8).

4, the first gate electrode G1, the first source electrode S1, the first active pattern ACT1, and the first drain electrode D1 of the switching transistor SW- The second source electrode S2, the second active pattern ACT2, and the second drain electrode D2 of the first data line DR-T are vertically overlapped with each other.

The first source electrode S1 of the switching transistor SW-T connected to the data line DL is connected to the data line DL through the first and second gate electrodes G1 and G2, And the second source electrode S2 of the driving transistor DR-T connected to the line DVL.

That is, in the present invention, the switching transistor SW-T and the driving transistor DR-T are superimposed with the first planarization layer 108 (insulating layer) therebetween so that two transistors Respectively. Therefore, the conventionally arranged transistor region can be used as the light emitting region EA of the organic light emitting diode OLED, and the aperture ratio of the sub-pixel can be increased.

A second planarization layer 208 is disposed on the driving transistor DR-T and a first electrode 111 serving as an anode, an organic emission layer 112, An organic light emitting diode 114 composed of a second electrode 113 serving as a cathode is disposed. The anode and the cathode may be mutually changed depending on the light emission method.

A second substrate 170 is disposed on the organic light emitting diode 114 with a protective layer 160 interposed therebetween. The second substrate 170 may be a color filter substrate. Although not shown in the drawing, the second substrate 170 may include white (W), red (R), green (G ) And blue (B) color filter layers and a black matrix may be disposed.

In addition, the protective layer 160 may have a structure in which a plurality of inorganic films and organic films are alternately stacked. The organic light emitting display of the present invention may be a top emission type, a bottom emission type, or a both-side emission type.

The organic light emitting layer 112 disposed on the organic light emitting diode 114 is not formed on the entire surface of the first substrate 101 and the red (R), green (G), blue (B) (R), green (G), blue (B), and white (W) light emitting layers or a single white (W) light emitting layer for generating light (W)

≪ Method of manufacturing organic light emitting display device &

The manufacturing process of the OLED display of the present invention is as follows.

In the organic light emitting diode display of the present invention, the plurality of sub pixel areas SP and each sub pixel area SP includes a light emitting area EA in which the organic light emitting diode 114 emits light, NEA).

First, a semiconductor layer is formed on a first substrate 101, and then a photolithography process and an etching process are performed to form a first active pattern ACT1 of the switching transistor SW-T. The first active pattern ACT1 may include a doped region doped with impurities at a high concentration on both sides of the channel region.

The first active pattern ACT1 may be an amorphous silicon film, a doped amorphous silicon film, or a crystallized silicon film. Also, the first active pattern ACT1 may be an oxide semiconductor.

The first active pattern ACT1 may be an amorphous oxide containing at least one of indium (In), zinc (Zn), gallium (Ga), and hafnium (Hf) when the first active pattern ACT1 is an oxide semiconductor. For example, when a Ga-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of In2O3, Ga2O3, and ZnO may be used, or a single target of Ga-In-Zn oxide may be used. When the hf-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of HfO 2, In 2 O 3, and ZnO may be used, or a single target of Hf-In-Zn oxide may be used.

As described above, when the first active pattern ACT1 is formed on the first substrate 101, a gate insulating film and a gate metal film are sequentially formed on the first substrate 101, and then a photolithography process and an etching process are performed The first gate pattern GL1 and the first gate electrode G1 are formed on the channel region of the first active pattern ACT1.

The first gate pattern GL2 may be formed of a single layer of silicon oxide (SiOx), or a double layer of silicon nitride (SiNx) and silicon oxide (SiOx) sequentially deposited.

The gate metal layer may include at least one of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum Resistant opaque conductive material such as titanium (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), or the like, or an alloy of these materials, or at least two Or more of the metal film may be laminated.

Then, the first interlayer insulating film 104 is formed on the first substrate 101, and a contact hole process is performed to expose doped regions of the first active pattern ACT1.

As described above, a contact hole is formed on the first interlayer insulating film 104, a source / drain metal film is formed on the entire surface of the first substrate 101, a mask process is performed to form a first source electrode S1 and a second source electrode 1 drain electrode D1 is formed, thereby completing the switching transistor SW-T.

The source / drain metal layer may be a low resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum or tantalum. In addition, a multi-layer structure in which a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) and an opaque conductive material are stacked can be formed.

As described above, when the switching transistor SW-T is formed on the first substrate 101, the first planarization layer 108 is formed on the entire surface of the first substrate 101, and then the switching transistor SW- -T) is repeated to form a driving transistor DR-T so as to overlap with the switching transistor SW-T.

The driving transistor DR-T includes a second source electrode S2, a second drain electrode D2, a second active pattern ACT2, a second gate pattern GL2, a second interlayer insulating film 204, 2 gate electrode G2.

As described above, when the driving transistor DR-T is formed on the first planarization layer 108, a second planarization layer 208 is formed on the entire surface of the first substrate 101, and then a photolithography process is performed. And the drain contact hole process in which the second drain electrode D2 of the driving transistor DR-T is exposed is performed in the etching process.

The first and second planarization layers 108 and 208 may be formed of an organic insulating material such as an acryl based organic compound, a benzo-cyclo-butene (BCB), or a perfluorocyclobutane (PFCB).

As described above, when a drain contact hole is formed in the second planarization layer 208, a first metal layer is formed on the entire surface of the first substrate 101, Electrode 111 is formed.

The area of the first electrode 111 is enlarged as the driving transistor DR-T and the switching transistor SW-T are overlapped with each other, as described with reference to FIG. 2B. That is, since the light emitting region (aperture ratio) of the first sub-pixel SP1 increases, the total area of the organic light emitting diode 114 also increases. As described above, when the aperture ratio is increased, the lifetime of the organic light emitting diode 114 is extended.

The first electrode 111 is electrically connected to the second drain electrode D2 of the driving transistor DR-T disposed below the drain contact hole.

The first metal layer constituting the first electrode 111 may be formed of aluminum (Al), silver (Ag) or an alloy thereof, ITO (Indium Tin Oxide) / Ag, ITO (Indium Tin Oxide) (Indium Tin Oxide) / Ag / IZO (Indium Zinc Oxide), ITO / APC / ITO, and the like.

As described above, when the first electrode 111 is formed, an organic insulating layer is formed on the entire surface of the first substrate 101, and then a part of the first electrode 111 of the drain contact hole region A bank layer 180 is formed between adjacent electrodes.

The organic light emitting layer 112 and the second electrode 113 are formed on the entire surface of the first substrate 101 on which the first electrode 111 and the bank layer 180 are formed to complete the organic light emitting diode 114 do.

As described above, when the organic light emitting diode 114 is formed, the passivation layer 160 is formed, and the second substrate 170 is formed on the passivation layer 160 to complete the OLED display.

The organic light emitting layer 112 may be a single layer made of a light emitting material and may include a hole injection layer, a hole transport layer, an emission material layer, an electron transport layer An electron transport layer, and an electron injection layer.

The hole transport layer HTL may further include an electron blocking layer EBL and the electron transport layer ETL may be formed using a low molecular material such as PBD, TAZ, Alq3, BAlq, TPBI or Bepp2. have.

(R), green (G), and blue (B) light emitting layers are formed for each pixel region to emit light of a full color (full color) (EML) may be implemented as a white light emitting layer in which red (R), green (G), and blue (B) organic materials are laminated.

The second electrode 113 may be formed of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

5 is a cross-sectional view of a region of the gate line 110. As shown in the drawing, the gate line 110 includes a first insulating pattern 121 formed as a gate insulating film on the first substrate 101, (110) are superimposed on each other.

A first interlayer insulating film 104 is formed on the gate line 110. A data line DL connected to the first source electrode S1 of the switching transistor SW- Is formed.

A first planarization layer 108 is formed on the data line DL and a second interlayer insulation layer 204 is formed on the first planarization layer 108. A driving voltage line EVDD (DVL) electrically connected to the second source electrode S2 of the driving transistor DR-T is formed on the second interlayer insulating layer 204. [

A second planarization layer 208 is formed on the driving voltage line EVDD and a bank layer 180, a protective layer 160, and a second layer 180 are formed on the non-emission region NEA, A second substrate (not shown) is formed.

Referring to FIG. 6, a first interlayer insulating layer 104, a data line DL, and a first drain electrode D1 of a switching transistor SW-T are formed on a first substrate 101. A first planarization layer 108 is formed on the first drain electrode D1 and a double layer of the second insulation pattern 202 and the electrode pattern 210 is formed on the first planarization layer 108. [

2, the electrode pattern 210 is formed integrally with the second gate electrode G2 of the driving transistor DR-T. In some cases, the electrode pattern 210 may be a pattern for forming a storage capacitor in a sub- And is used as the first storage electrode E1.

A second storage electrode E2 is formed on the first storage electrode E1 so as to be bent and branched from the second source electrode S2 of the driving transistor DR-T with the second interlayer insulating film 204 interposed therebetween have.

At this time, when the contact hole is formed on the second interlayer insulating film 204 to open the doped region of the second active pattern ACT2, the first drain electrode D1 of the switching transistor SW- 1, a contact hole C exposing a part of the edge of the storage electrode E1 is formed.

When the second source electrode S2 and the second drain electrode D2 of the driving transistor are formed, the first storage electrode E1 electrically connected to the second gate electrode G2, (CP) connecting the first electrode (D1).

The connection pattern CP may be formed when the second source electrode S2 and the second drain electrode D2 are formed and another metal pattern is formed in another process.

The organic light emitting diode display according to the present invention has the effect of improving the aperture ratio of the organic light emitting diode by vertically overlapping the switching transistor and the driving transistor disposed in each sub pixel region with an insulating layer interposed therebetween.

In addition, the organic light emitting display according to the present invention has the effect of increasing the device lifetime by enlarging the electrode area of the organic light emitting diode by disposing the driving transistor arranged in the sub pixel region in three dimensions on the switching transistor.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

10: Organic light emitting display
12:
13: Gate driver
14: Timing controller section
101: first substrate
104: a first interlayer insulating film
108: second planarizing film
204: a second interlayer insulating film
208: second planarizing film
114: organic light emitting diode
SW-T: Switching transistor
DR-T: driving transistor

Claims (9)

And a display panel having a plurality of sub-pixels defined by a plurality of data lines and a plurality of gate lines,
Each sub-
An organic light emitting diode,
A driving transistor for driving the organic light emitting diode,
And a first switching transistor connected to the data line,
Wherein the driving transistor and the first switching transistor are overlapped with each other with an insulating layer interposed therebetween. The method according to claim 1,
The first gate electrode, the first active pattern, the first source electrode, and the second drain electrode of the first switching transistor are connected to the second gate electrode, the second active pattern, the second source electrode, And the organic light emitting display device. 3. The method of claim 2,
Wherein a first drain electrode of the first switching transistor is electrically connected to a second gate electrode of the driving transistor by a connection pattern. 3. The method of claim 2,
Wherein the first source electrode of the first switching transistor and the second source electrode of the driving transistor are disposed to face each other with first and second gate electrodes overlapped with each other. The method according to claim 1,
Wherein the driving transistor is located on an insulating layer disposed on the first switching transistor. A display panel having a plurality of sub-pixels defined by a plurality of data lines and a plurality of gate lines,
Each sub-
An organic light emitting diode,
A driving transistor for driving the organic light emitting diode,
A first switching transistor connected to the data line,
And a second switching transistor electrically connected between a node between the driving transistor and the organic light emitting diode and a reference voltage line,
Wherein the driving transistor and the second switching transistor are overlapped with each other with an insulating layer interposed therebetween. The method according to claim 6,
Wherein the first and second switching transistors and the driving transistors are alternately overlapped with each other with insulating layers interposed therebetween. The method according to claim 6,
Wherein a first drain electrode of the first switching transistor is electrically connected to a second gate electrode of the driving transistor by a connection pattern. The method according to claim 6,
Wherein the driving transistor is located on an insulating layer disposed on the first switching transistor and the second switching transistor.

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