KR20190063907A - Electroluminescent Display Device - Google Patents

Abstract

In an electroluminescent display device according to an embodiment of the present invention, a vertical wiring of a data line/power supply line is arranged in the same layer as a lowermost light-shielding layer, a horizontal wiring of a gate line is arranged in the same layer as a gate electrode, and an electrode or a wiring branched from the vertical wiring is arranged in the same layer as source/drain electrodes, thereby interposing a gate insulating layer and a buffer layer between the vertical wiring and horizontal wiring. Further, the buffer layer does not depend on a capacitor capacity, thereby preventing a short-circuit failure occurring at the intersection of the vertical wiring and horizontal wiring by increasing the thickness of the buffer layer. Accordingly, a gate redundancy pattern in a pixel can be deleted, thereby facilitating pixel design in a high-resolution model and securing an additional aperture ratio.

Description

[0001] Electroluminescent Display Device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display device, and more particularly, to an electroluminescent display device capable of preventing a short circuit failure occurring at an intersection of a gate line and a data line / power line in a pixel.

In the field of information technology, the field of display devices for visually displaying electrical information signals is rapidly developing, and studies for developing performance such as thinning, lightening, and low power consumption for various display devices are continuing.

Typical display devices include a liquid crystal display device (LCD), a field emission display device (FED), an electro-wetting display device (EWD), and an organic light- Light Emitting Display Device (OLED), and the like.

In particular, an electroluminescent display device which is a display device including an organic light emitting display device is a self-luminous display device, and unlike a liquid crystal display device, a separate light source is not required, so that it can be manufactured in a light and thin shape. In addition, the electroluminescent display device is advantageous not only in terms of power consumption by low voltage driving but also excellent in hue of color, response speed, viewing angle, and contrast ratio (CR) .

An electroluminescent display device is constituted by disposing a light emitting layer using an organic material between two electrodes called an anode and a cathode. When holes in the anode are injected into the light emitting layer and electrons in the cathode are injected into the light emitting layer, excited electrons and holes recombine with each other to form an exciton in the light emitting layer, do.

Such a light emitting layer includes a host material and a dopant material, so that interaction between the two materials occurs. The host generates excitons from electrons and holes and transfers energy to the dopant. The dopant is a dye organic material to which a small amount of dopant is added, and receives energy from the host and converts the light into light.

In order to increase the size of the display device and realize a high resolution, it is necessary to secure a high aperture ratio and a gate redundancy pattern for repairing a short circuit between the current horizontal line of the gate line and the vertical line of the data line / .

This is because the intersection point of the horizontal wiring and the vertical wiring includes only the interlayer insulating layer therebetween, so that electrostatic failure may occur due to a short spacing distance, a short circuit due to foreign matter between the horizontal wiring and the vertical wiring, Failure may occur due to the state of the layer, and a structure for repair has to be designed in the pixel to improve the yield. Accordingly, a gate redundancy pattern is applied at a position where the horizontal wiring and the vertical wiring cross each other. Since the gate redundancy pattern is formed to occupy a predetermined region above and below the gate line, the aperture ratio in the pixel is reduced, and the pixel design in the high resolution model is difficult due to the addition of the gate redundancy pattern in the pixel.

The inventors of the present invention have found that the intersection points of the horizontal wiring and the vertical wiring are susceptible to short-circuit defects because only the inter-layer insulating layer is interposed therebetween, and this short-circuit defect is influenced by the distance between wirings, It is difficult to increase the thickness of the gate insulating layer / buffer layer because it affects the capacitance of the capacitor. However, in consideration of the fact that the thickness of the gate insulating layer / buffer layer can be increased regardless of the capacitance of the capacitor, A gate insulation layer and a buffer layer are interposed between the horizontal wiring and the vertical wiring so as to prevent a short circuit failure.

That is, the vertical wirings of the data lines / power supply lines are arranged in the same layer as the lowermost light-shielding layer, the horizontal wirings of the gate lines are arranged in the same layer as the gate electrodes, and the electrodes and wirings branched in the vertical wirings are the same as the source / Layer, a gate insulating layer and a buffer layer can be interposed between the vertical interconnection and the horizontal interconnection. At this time, since the gate insulating layer / buffer layer does not depend on the capacity of the capacitor, it is possible to prevent a short-circuit failure occurring at the intersection of the vertical wiring and the horizontal wiring by increasing the thickness of the gate insulating layer and / or the buffer layer.

Accordingly, an object of the present invention is to provide an electroluminescent display device capable of preventing a short-circuit failure occurring between a vertical wiring and a horizontal wiring without a gate redundancy pattern.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an electroluminescent display device including: a data line arranged in a first direction on a substrate; a first insulating layer disposed on the data line; A gate line arranged in a second direction intersecting the first direction and partitioning the pixel region together with the data line, a second insulating layer provided on the active layer, A third insulating layer disposed over the gate electrode and the gate electrode; a source electrode and a drain electrode disposed on the third insulating layer and connected to a predetermined region of the active layer; And a light emitting element disposed in a light emitting portion of the pixel region above the fourth insulating layer and the fourth insulating layer to be disposed.

According to another aspect of the present invention, there is provided an electroluminescent display device including a plurality of data lines arranged in a first direction on a substrate, An active layer disposed on the first insulating layer, a gate line arranged in the second direction intersecting the first direction with at least a second insulating layer further disposed on the first insulating layer, A third insulating layer disposed on the gate line, a source electrode and a drain electrode disposed on the third insulating layer and connected to a predetermined region of the active layer, a fourth insulating layer disposed on the source electrode and the drain electrode, The first insulating layer and / or the second insulating layer has a thickness larger than that of the third and fourth insulating layers, A short circuit is prevented between the vertical wiring and the horizontal wiring due to at least the first insulating layer and the second insulating layer being interposed between the horizontal wirings and a fourth insulating layer having a relatively thin thickness is interposed between the anode of the light- The capacity of the capacitor can be increased.

The details of other embodiments are included in the detailed description and drawings.

The vertical wiring of the data line / power supply line is arranged in the same layer as the lowermost light-shielding layer, the horizontal wiring of the gate line is arranged in the same layer as the gate electrode, It is possible to prevent short-circuit defects between the vertical wiring and the horizontal wiring. Thus, it is possible to delete the gate redundancy pattern in the pixel, thereby facilitating the pixel design in the high-resolution model, improving the yield, and securing the additional aperture ratio (about 19.1% improvement based on the 55 inch).

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram schematically illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is a circuit diagram of a pixel included in an electroluminescent display device according to an embodiment of the present invention.
3 is a plan view schematically showing an electroluminescent display device according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of an electroluminescent display device according to an embodiment of the present invention shown in FIG.
5 is a plan view schematically showing an electroluminescent display device of a comparative example.
FIG. 6A is a view illustrating an example of a cross-sectional structure of a crossing point in an electroluminescent display device according to a comparative example.
FIG. 6B is a cross-sectional view illustrating a cross-section of a luminescent display in an electroluminescent display device according to an exemplary embodiment of the present invention.
7 is a cross-sectional view illustrating a capacitor in an electroluminescent display according to an exemplary embodiment of the present invention.
8A to 8I are plan views sequentially illustrating the manufacturing process of the electroluminescent display device according to the embodiment of the present invention shown in FIG.
FIGS. 9A to 9J are cross-sectional views sequentially illustrating fabrication processes of an electroluminescence display device according to an embodiment of the present invention shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It will be understood that when an element or layer is referred to as being on another element or layer, it encompasses the case where it is directly on or intervening another element or intervening another element or element.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an electroluminescent display device according to an embodiment of the present invention.

1, an electroluminescent display 100 according to an exemplary embodiment of the present invention includes an image processor 170, a timing controller 180, a data driver 130, a gate driver 140, and a display panel 110 ). ≪ / RTI >

The image processor 170 may output a data enable signal DE and the like in addition to the data signal DATA supplied from the outside. The image processing unit 170 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE.

The timing controller 180 can receive the data signal DATA in addition to the data enable signal DE or the driving signal including the vertical synchronizing signal, the horizontal synchronizing signal and the clock signal from the image processor 170. The timing controller 180 generates a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the drive signal. Can be output.

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 180 in response to the data timing control signal DDC supplied from the timing controller 180, And output it. The data driver 130 may output the data signal DATA through the data lines DL1 to DLn.

The gate driver 140 may output the gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 180. [ The gate driver 140 may output the gate signal through the gate lines GL1-GLm.

The display panel 110 can display an image while the pixel 160 emits light corresponding to the data signal DATA and the gate signal supplied from the data driver 130 and the gate driver 140.

The detailed structure of the pixel 160 will be described in FIG. 2 and FIG.

2 is a circuit diagram of a pixel included in an electroluminescent display device according to an embodiment of the present invention. Hereinafter, the structure and operation of a pixel circuit of a 2T (transistor) 1C (capacitor) according to an embodiment of the present invention will be described for convenience of explanation, but the present invention is not limited thereto .

Referring to FIG. 2, one pixel includes a switching transistor 111, a driving transistor 113, a compensation circuit (not shown), and a reset transistor (not shown) in an electroluminescent display device 100 according to an exemplary embodiment of the present invention. And a light emitting device 114 as shown in FIG.

The light emitting element 114 can operate to emit light in accordance with the driving current generated by the driving transistor 113. [

The switching transistor 111 may be switched so that a data signal supplied through the data line 116 corresponding to the gate signal supplied through the gate line 117 is stored as a data voltage to the capacitor 112. [

The driving transistor 113 may operate so that a constant driving current flows between the high potential power supply line VDD and the low potential power supply line VSS corresponding to the data voltage stored in the capacitor 112. [

The compensation circuit is a circuit for compensating the threshold voltage of the driving transistor 113 and the like, and may include at least one thin film transistor and a capacitor. The configuration of the compensation circuit may vary widely depending on the compensation method.

A pixel includes a switching transistor 111, a driving transistor 113, a capacitor 112, and a light emitting element 114. The switching transistor 111, the driving transistor 113, the capacitor 112, and the light emitting element 114 are formed in the same manner as in the EL display device 100 according to an exemplary embodiment of the present invention. 2T1C structure. However, if a compensation circuit is added, it can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

3 is a plan view schematically showing an electroluminescent display device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of an electroluminescent display device according to an embodiment of the present invention shown in FIG. 5 is a plan view schematically showing an electroluminescent display device of a comparative example.

FIG. 3 schematically shows a planar structure of two neighboring pixels in an electroluminescent display according to an exemplary embodiment of the present invention. Referring to FIG. For convenience of explanation, FIG. 3 shows an example in which a pixel is composed of a 2T1C structure including a switching transistor, a driving transistor, a capacitor, and a light emitting element. However, in the case where a compensation circuit is added as described above, 3T1C and 4T2C , 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.

4 schematically shows a part of a section cut along a line I-I 'and a line II-II' in an electroluminescent display device according to an embodiment of the present invention shown in FIG. 3, A part of the circuit part including the transistor and a part of the light emitting part including the light emitting element are shown as an example.

3 and 4, an electroluminescent display 100 according to an embodiment of the present invention includes a substrate 110, a gate line (or a scan line) 117, a data line 116, (Or the power supply voltage line) 119 may intersect to divide the pixel region. In addition, a sensing control line, a reference line, and the like may be further disposed.

The data line 116 and the power supply line 119 may be disposed in a first direction on the substrate 110. [ The gate line 117 may be arranged in a second direction intersecting the first direction to divide the pixel region together with the data line 116 and the power source line 119. For convenience of explanation, one pixel region can be divided into a light emitting portion for emitting light by the light emitting element and a circuit portion including a plurality of driving circuits for supplying a driving current to the light emitting element.

A plurality of pixel regions may be formed of a red sub-pixel region, a green sub-pixel region, a blue sub-pixel region, and a white sub-pixel region to form a unit pixel. Although only two sub-pixel regions are shown in FIG. 3 by way of example, the present invention is not limited thereto. Each of the red, green, blue, and white sub-pixel regions has a light emitting element and a plurality of pixel driving circuits that independently drive the light emitting element. The pixel driver circuit may include a switching transistor, a driving transistor, a capacitor, and a sensing transistor.

The power supply line 119 may be disposed in one or more pixel regions, but the present invention is not limited thereto.

The reference lines may be arranged in the first direction in the same layer as the data lines 116 and the power supply lines 119 together with the data lines 116 and the power supply lines 119.

The switching transistor may be turned on when a scan pulse is supplied to the gate line 117 to supply the data signal supplied to the data line 116 to the first gate electrode 121a of the capacitor and the driving transistor. The switching transistor includes a second gate electrode 121b connected to the gate line 117, a second source electrode 122b connected to the data line 116 through the seventh contact hole 140g, a sixth contact hole 140f, And a second active layer 124b and a second drain electrode 123b connected to the first gate electrode 121a through the first gate electrode 121a.

The driving transistor controls the current supplied from the power supply line 119 according to the driving voltage charged in the capacitor to supply a current proportional to the driving voltage to the light emitting element to emit the light emitting element. The driving transistor includes a first gate electrode 121a connected to the second drain electrode 123b through the sixth contact hole 140f and a first source electrode 121b connected to the power source line 119 through the eighth contact hole 140h. And the first active layer 124a and the first drain electrode 123a connected to the light emitting element through the second contact hole 140a and the third contact hole 140c.

Here, the power supply line 119 may be connected to the first source electrode 122a of the neighboring pixel region through the bridge wiring 119a projecting to the pixel region. The bridge wiring 119a may extend to neighboring pixel regions in a direction parallel to the second direction. The bridge wiring 119a extending to the neighboring pixel region may be connected to the first source electrode 122a of the neighboring pixel region through the first contact hole 140a.

One side of the bridge wiring 119a may extend vertically along the power supply line 119 and may be connected to the lower power supply line 119 through the eighth contact hole 140h.

4 is a driving transistor, and the first gate electrode 121a is disposed on the first active layer 124a. The top gate structure is a thin film transistor having a coplanar structure . However, the present invention is not limited thereto, and a thin film transistor having a bottom gate structure in which a gate electrode is disposed under an active layer is also applicable. Also, the switching transistor can be applied to both a top gate structure, a coplanar structure, and a bottom gate structure.

Each of the first and second gate electrodes 121a and 121b of the switching transistor and the driving transistor includes a gate insulating layer 115b substantially in the same shape as the first and second gate electrodes 121a and 121b, May be overlapped with each of the first and second active layers 124a and 124b.

Specifically, the first and second active layers 124a and 124b may be disposed on the substrate 110. [

At this time, the light shielding layer 125 may be disposed under the first active layer 124a, and the buffer layer 115a may be disposed between the first active layer 124a and the light shielding layer 125.

The light shielding layer 125 may block the first active layer 124a from being affected by the light of the light emitting element from the outside or the surrounding and may be disposed at the lowest layer of the substrate 110.

The data line 116 and the power source line 119 of the present invention may be disposed in the same direction as the light-shielding layer 125 in the first direction. That is, the data line 116 and the power source line 119 of the present invention are disposed at the lowest layer of the substrate together with the light-shielding layer 125. This is because the vertical wiring of the data line 116 and the power supply line 119 is arranged in a layer different from that of the conventional one by interposing the vertical wiring between the data line 116 and the power supply line 119 and the horizontal wiring of the gate line 117 The buffer layer 115a and the gate insulating layer 115b are interposed between the insulating layer 115c and another insulating layer other than the insulating layer 115c.

The buffer layer 115a may be disposed on the substrate 110 so as to cover the light shielding layer 125, the data line 116, and the power supply line 119. [

Each of the first and second active layers 124a and 124b is formed to overlap with the first and second gate electrodes 121a and 121b on the gate insulating layer 115b, A channel may be formed between the first drain electrode 123a and between the second source electrode 122b and the second drain electrode 123b.

The gate insulating layer 115b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx).

4 illustrates a case where the gate insulating layer 115b is formed only below the first gate electrode 121a. However, the present invention is not limited thereto. The gate insulating layer 115b may be formed on the entire surface of the substrate 110 on which the first and second active layers 124a and 124b are formed. In this case, the first source electrode 122a and the second source electrode 122b are formed in the gate insulating layer 115b. The first drain electrode 123a may be formed with a contact hole for connecting to each of the source region and the drain region of the first active layer 124a. The second source electrode 122b and the second drain electrode 123b may be formed with contact holes for connecting to the source region and the drain region of the second active layer 124b respectively in the gate insulating layer 115b have.

The gate line 117 may be disposed on the same layer as the first and second gate electrodes 121a and 121b. At this time, the above-described gate insulating layer 115b may be disposed under the gate line 117. However, the present invention is not limited thereto.

The first and second gate electrodes 121a and 121b and the gate line 117 may be formed of various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti) And may be composed of any one of nickel (Ni), neodymium (Nd), and copper (Cu), two or more alloys, or multiple layers thereof.

The first and second active layers 124a and 124b may be formed using an oxide semiconductor containing at least one selected from Zn, Cd, Ga, In, Sn, Hf and Zr, (amorphous silicon, a-Si), polycrystalline silicon (poly-Si), organic semiconductor, or the like.

Each of the first and second source electrodes 122a and 122b is electrically connected to the first and second active layers 124a and 124b through the first and fourth contact holes 140a and 140d passing through the interlayer insulating layer 115c, As shown in FIG. The first and second drain electrodes 123a and 123b are electrically connected to the first and second active layers 124a and 124b through the second and fifth contact holes 140b and 140e penetrating the interlayer insulating layer 115c, As shown in FIG.

The interlayer insulating layer 115c may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). The interlayer insulating layer 115c may be formed over the entire surface of the substrate 110 as shown in FIG. 4 and may be formed only in the pixel region, but the present invention is not limited thereto.

The first and second source electrodes 122a and 122b and the first and second drain electrodes 123a and 123b may be formed of various conductive materials such as molybdenum (Mo), aluminum (Al), chrome (Cr) ), Titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or two or more alloys or multilayers thereof.

The second drain electrode 123b of the switching transistor may extend upward and be electrically connected to the first gate electrode 121a of the driving transistor. Specifically, the second drain electrode 123b may be connected to the first gate electrode 121a through a sixth contact hole 140f passing through the interlayer insulating layer 115c.

The first drain electrode 123a may be connected to the anode 126 of the light emitting device through the third contact hole 140c and the hole H that pass through the protective layer 115d and the planarization layer 115e.

Although the thin film transistor is described as being a coplanar structure in this specification, a thin film transistor may be implemented with another structure such as a staggered structure or the like.

As described above, the electroluminescent display 100 according to the embodiment of the present invention is configured such that the vertical lines of the data line 116 and the power line 119 are arranged in the first direction on the substrate 110, 117 are arranged in a second direction intersecting with the first direction to divide the pixel region together with the vertical interconnection.

The electroluminescent display 100 according to an exemplary embodiment of the present invention includes the data line 116 and the power line 119 in the same layer as the lowermost light-blocking layer 125, The gate insulating layer 115b and the buffer layer 115a are formed between the vertical interconnection and the horizontal interconnection in the same layer as the first source / drain electrodes 122a and 123a, To be intervened. At this time, since the gate insulating layer 115b and the buffer layer 115a are independent of the capacitor capacity, the thickness of the gate insulating layer 115b and / or the buffer layer 115a is increased, Short circuit failure can be prevented.

In other words, it is necessary to form a gate redundancy pattern for repairing the short circuit between the horizontal wiring of the gate line and the vertical wiring of the data line / power supply line, Only the interlayer insulating layer is interposed therebetween. As a result, electrostatic failure may occur due to a short spacing distance, a short circuit may occur due to foreign matter between the horizontal wiring and the vertical wiring, or defective due to the state of the insulating layer on the gate line. In order to improve the yield, a structure for repair had to be designed in the pixel. Accordingly, a gate redundancy pattern is applied at a position where the horizontal wiring and the vertical wiring cross each other. Since the gate redundancy pattern is formed to occupy a predetermined region above and below the gate line, the aperture ratio in the pixel is reduced, and the pixel design in the high resolution model is difficult due to the addition of the gate redundancy pattern in the pixel.

Therefore, the inventors of the present invention have found that the intersection of the horizontal wiring and the vertical wiring is susceptible to short-circuit defects because only the inter-layer insulating layer 115c is interposed therebetween, and this short-circuit defect is affected by the wiring- It is difficult to increase the thickness of the insulating layer 115c because the thickness of the insulating layer 115 depends on the capacitance of the capacitor. However, the thickness of the gate insulating layer 115b and / or the buffer layer 115a is not related to the capacitance of the capacitor, By arranging the data line 116 and the power supply line 119 in different layers from each other, the gate insulating layer 115b and the buffer layer 115a are interposed between the horizontal wiring and the vertical wiring, .

That is, the vertical wirings of the data line 116 and the power supply line 119 are arranged in the same layer as the light shielding layer 125 and the horizontal wiring of the gate line 117 is arranged in the same layer as the first gate electrode 121a The gate insulating layer 115b is formed between the vertical interconnection and the horizontal interconnection not by the conventional interlayer insulating layer 115c by disposing the electrodes and the interconnection branching in the vertical interconnection in the same layer as the first source / drain electrodes 122a and 123a, And the buffer layer 115a can be interposed. At this time, since the gate insulating layer 115b and the buffer layer 115a are independent of the capacitor capacity, the thickness of the gate insulating layer 115b and / or the buffer layer 115a is increased, Short circuit failure can be prevented.

Thus, it is possible to delete the gate redundancy pattern in the pixel, thereby facilitating the pixel design in the high-resolution model, improving the yield, and securing the additional aperture ratio (about 19.1% improvement based on the 55 inch).

5, in the electroluminescent display device 10 of the comparative example, the vertical wiring lines of the data line 16 and the power source line 19 are connected to the interlayer insulating layer (not shown) of the horizontal line of the gate line 16 Respectively.

At this time, the electroluminescent display device 10 of the comparative example shown in Fig. 5 is different from the electroluminescent display device 10 except for the arrangement positions of the vertical wirings and the horizontal wirings, the configuration of the capacitors corresponding thereto, the configuration of the electrodes and wirings branched in the vertical wirings, Has a structure similar to that of the electroluminescent display device according to the embodiment of the present invention described above. Therefore, the same reference numerals are used for the sake of convenience only, and only the components that need to be compared will be described.

As described above, at the intersection of the horizontal wiring and the vertical wiring, only the interlayer insulating layer is interposed between the horizontal wiring and the vertical wiring, so that electrostatic failure may occur due to a short spacing distance, a short circuit due to foreign matter between the horizontal wiring and the vertical wiring, 16) Failure may occur due to the state of the above insulating layer, and a structure for repairing has to be designed in the pixel in order to improve the yield. Accordingly, in the comparative example, the gate redundancy pattern 17a is applied at a position where the horizontal wiring and the vertical wiring cross each other. The gate redundancy pattern 17a is formed so as to occupy a predetermined region above and below the gate line 17, so that the opening A 'in the pixel is reduced.

This is because the interlayer insulating layer is interposed between the vertical interconnection and the horizontal interconnection. In order to eliminate the gate redundancy pattern 17a, the thickness of the interlayer insulating layer must be increased. In order to secure the capacity of the capacitor, .

On the other hand, as described above, in one embodiment of the present invention, the vertical interconnection between the data line 116 and the power supply line 119 is disposed in the same layer as the light-shielding layer 125, So that the layer 115b and the buffer layer 115a can be interposed. At this time, since the gate insulating layer 115b and the buffer layer 115a are independent of the capacitor capacity, the thickness of the gate insulating layer 115b and / or the buffer layer 115a is increased, Short circuit failure can be prevented. Accordingly, it is possible to delete the gate redundancy pattern in the pixel, so that the opening A can be expanded more than the opening A 'of the comparative example, and the pixel design can be easily designed and the yield can be improved in the high resolution model.

Next, a protective layer 115d and a planarization layer 115e may be disposed on the thin film transistor. The protective layer 115d protects the gate driver and other wirings disposed outside the thin film transistor and the pixel region and the planarization layer 115e protects the upper surface of the substrate 110 by flattening the step on the substrate 110 Layer.

The planarization layer 115e may be made of an organic insulating material. That is, the planarization layer 115e may be formed of a resin such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, Resist, but is not limited thereto.

The planarization layer 115e is removed in the predetermined region of the circuit portion so that the hole H for exposing the second drain electrode 123a under the part of the surface of the protection layer 115d and the third contact hole 140c is formed .

An intermediate electrode (not shown) may be disposed on the planarization layer 115e. The intermediate electrode is an electrode for electrically connecting the thin film transistor and the anode 126. The intermediate electrode can be electrically connected to the first drain electrode 123a of the transistor through the hole H formed in the planarization layer 115e. The intermediate electrode may be made of the same conductive material as the first source electrode 122a and the first drain electrode 123a of the thin film transistor and may be made of a conductive material different from the anode 126. [

An additional planarization layer (not shown) may be disposed over the planarization layer 115e to cover the intermediate electrode. The additional planarization layer is an insulating layer for planarizing the upper surface of the planarization layer 115e. The additional planarization layer may be formed of a resin such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin , Benzocyclobutene, and photoresist, but is not limited thereto.

However, the present invention is not limited thereto, and the present invention may include only the planarization layer 115e as shown in FIG.

Referring to FIG. 4, a light emitting device may be disposed on the planarization layer 115e. For example, the light emitting device as the organic light emitting device includes an anode 126 formed on the planarization layer 115e and electrically connected to the first drain electrode 123a of the transistor, an organic light emitting layer 127 disposed on the anode 126, And a cathode 128 formed on the light emitting layer 127.

The anode 126 may be disposed on the planarization layer 115e including the hole H and may include a third contact hole 140c and a hole H formed in the protective layer 115d and the planarization layer 115e, And may be electrically connected to the first drain electrode 123a. The anode 126 may be made of a conductive material having a high work function to supply holes to the organic light emitting layer 127. The anode 126 is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO) .

The anode 126 disposed in the hole H overlaps with a part of the second drain electrode 123b under the protective layer 115d (hereinafter referred to as a storage electrode for convenience) to constitute the first capacitor can do. A part of the second drain electrode 123b, that is, the storage electrode, overlaps with a part of the first active layer 124a under the interlayer insulating layer 115c to constitute the second capacitor. As described above, the first capacitor and the second capacitor are connected in parallel to increase the capacitance of the entire capacitor, and at the same time, the thickness of the protective layer 115d and the thickness of the interlayer insulating layer 115c The capacity of each of the first capacitor and the second capacitor can be increased compared to the conventional case. For example, the protective layer 115d and the interlayer insulating layer 115c according to an embodiment of the present invention may have a greater thickness than the gate insulating layer 115b and the buffer layer 115a.

When the electroluminescent display device 100 is a top emission type, the anode 126 includes a reflective layer for reflecting light emitted from the organic light emitting layer 127 toward the cathode 128, and a transparent conductive layer for supplying holes to the organic layer. As shown in FIG. However, the present invention is not limited thereto, and the anode 126 may include only a transparent conductive layer, and the reflective layer may be defined as a separate component from the anode 126.

3 and 4, the anode 126 is electrically connected to the first drain electrode 123a of the driving transistor. However, the present invention is not limited to this, and the type of the thin film transistor, the design of the driving circuit The anode 126 may be configured to be electrically connected to the first source electrode 122a of the driving transistor.

The organic light emitting layer 127 may include any one of a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, and a white organic light emitting layer as an organic layer for emitting light of a specific color. Further, the organic light emitting layer 127 may further include various organic layers such as a hole transporting layer, a hole injecting layer, an electron injecting layer, and an electron transporting layer. In FIG. 4, the organic light emitting layer 127 is patterned for each pixel, but the present invention is not limited thereto. The organic light emitting layer 127 may be a common layer formed in common to a plurality of pixels.

The cathode 128 may be disposed on the organic light emitting layer 127. The cathode 128 can supply electrons to the organic light emitting layer 127. The cathode 128 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) (Tin Oxide) type transparent conductive oxide, or a ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

Referring to FIG. 4, a bank 115f may be disposed over the anode 126 and the planarization layer 115e. The bank 115f may cover a part of the anode 126 of the organic light emitting element and a part of the wiring. The bank 115f may be arranged to separate adjacent pixels in the pixel region.

The bank 115f may be made of an organic insulating material. For example, the bank 115f may be formed of polyimide, acryl, or benzocyclobutene (BCB) resin, but the present invention is not limited thereto.

The bank 115f may be arranged to surround the light emitting portion on the planarization layer 115e and the bank 115f may be arranged to cover the bridge wiring 119a below the flattening layer 115e.

An encapsulant (not shown) may be formed on the organic light emitting device so as to protect the organic light emitting device, which is vulnerable to moisture, from exposure to moisture. For example, the sealing portion may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

The electroluminescent display 100 according to an embodiment of the present invention includes a gate insulating layer 115b and a buffer layer 115a between the gate line 117 and the data line 116, It is possible to prevent a short circuit between the gate line 117 and the data line 116. This will be described in detail with reference to the drawings.

FIG. 6A is a view illustrating an example of a cross-sectional structure of a crossing point in an electroluminescent display device according to a comparative example. FIG. 6B is a view illustrating an example of a cross-sectional structure of a crossing point in an EL display device according to an exemplary embodiment of the present invention. Referring to FIG. Here, the above-mentioned laminar means between the gate line and the data line, but not limited thereto. Gate line and power line, or between a gate line and a reference line.

6A, in an electroluminescent display device according to a comparative example, a buffer layer 15a is disposed on a substrate 10, and a gate insulating layer 15b and a gate line 17 are disposed on a buffer layer 15a. A data line 16 is disposed thereon with an interlayer insulating layer 15c interposed therebetween.

Under such a laminated structure, since only one interlayer insulating layer 15c is interposed between the gate line 17 and the data line 16, the Raman separation distance g1 is relatively short as about 5,000 ANGSTROM, Poor performance may occur. Since the interlayer insulating layer 15c constitutes the dielectric layer of the capacitor, there is a limit to increase the thickness thereof.

6B, in an electroluminescent display device according to an embodiment of the present invention, a data line 116 is disposed on a substrate 110. It can be seen that the buffer layer 115a and the gate insulating layer 115b are stacked and arranged on the data line 116 and the gate line 117 is disposed on the gate insulating layer 115b.

Under such a laminated structure, two insulating layers of the buffer layer 115a and the gate insulating layer 115b are interposed between the gate line 117 and the data line 116, and the thickness of these insulating layers is smaller than that of the interlayer insulating layer The human spacing distance g2 can be increased to more than 10,000 angstroms, and as a result, the electrostatic failure can be prevented.

In addition, since the interlayer insulating layer is not interposed between the gate line 117 and the data line 116 as described above, the electroluminescent display device according to an embodiment of the present invention can reduce the thickness of the interlayer insulating layer The capacity of the capacitor can be increased, which will be described in detail with reference to the drawings.

7 is a cross-sectional view illustrating a capacitor in an electroluminescent display according to an exemplary embodiment of the present invention.

Referring to FIG. 7, in an electroluminescent display according to an exemplary embodiment of the present invention, a capacitor is formed of a parallel structure of a first capacitor C1 and a second capacitor C2.

The first capacitor C1 may be composed of a protective layer 115d as a dielectric and a part of the anode 126 and the second drain electrode 123b disposed at the top and bottom of the protective layer 115d.

The second capacitor C2 may be composed of an interlayer insulating layer 115c as a dielectric and a part of the second active layer 124a and the second drain electrode 123b disposed on the upper and lower portions of the interlayer insulating layer 115c have.

At this time, in the embodiment of the present invention, the gate insulating layer 115b and the buffer layer 115a are interposed between the vertical interconnection and the horizontal interconnection, as described above, so that the interlayer insulating layer 115c and / The thickness of the protective layer 115d can be relatively reduced. Therefore, the thickness of the interlayer insulating layer 115c and / or the protective layer 115d, which determines the capacity of the capacitor, can be reduced as compared with the conventional case, and the capacity of the capacitor is increased.

Hereinafter, a method of manufacturing an electroluminescent display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

8A to 8I are plan views sequentially illustrating the manufacturing process of the electroluminescent display device according to the embodiment of the present invention shown in FIG. 9A to 9J are cross-sectional views sequentially illustrating the fabrication process of the electroluminescent display device according to the embodiment of the present invention shown in FIG.

8A and 9A, a vertical interconnection between the data line 116 and the power supply line 119 and a light shielding layer 125 may be formed on a transparent substrate 110.

At this time, the light shielding layer 125 may block the influence of the first active layer due to the light of the light emitting element from the outside or the surrounding, and may be disposed at the lowest layer of the substrate 110.

The data line 116 and the power source line 119 of the present invention may be disposed in the same direction as the light-shielding layer 125 in the first direction. That is, the data line 116 and the power source line 119 of the present invention are disposed at the lowest layer of the substrate together with the light-shielding layer 125.

The data line 116, the power supply line 119 and the light shielding layer 125 may be formed by forming a first metal layer on the substrate 101 and then selectively patterning the first metal layer through a mask process.

The mask process refers to a series of processes in which a photoresist film is formed on a substrate, a predetermined photoresist pattern is formed by exposure and development using a mask, and then the photoresist pattern is used as an etch mask.

8B and 9B, a buffer layer 115a may be formed on the substrate 110 on which the data line 116, the power supply line 119, and the light shielding layer 125 are formed.

The buffer layer 115a may be disposed on the substrate 110 so as to cover the light shielding layer 125, the data line 116, and the power supply line 119. [

The seventh contact hole 140g and the eighth contact hole 140h exposing a part of the data line 116, the power source line 119 and the light shielding layer 125 by patterning the buffer layer 115a through a mask process, And the ninth contact hole 140i can be formed.

Referring to FIGS. 8C and 9C, a first active layer 124a and a second active layer 124b may be formed on the substrate 110. FIG.

The first and second active layers 124a and 124b may be formed using an oxide semiconductor containing at least one metal selected from Zn, Cd, Ga, In, Sn, Hf and Zr, (amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductor, or the like.

Referring to FIGS. 8D and 9D, after the first and second active layers 124a and 124b are formed on the substrate 110, the gate insulating layer 115b and the second metal layer are sequentially formed on the entire surface of the substrate 110 As shown in FIG.

Thereafter, the gate insulating layer 115b and the second metal layer are selectively patterned through a mask process to form first and second gate electrodes 121a and 121b made of a second metal layer on the first and second active layers 124a and 124b, 121b.

The gate insulating layer 115b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx).

The second metal layer may be formed of various conductive materials such as molybdenum, aluminum, chromium, gold, titanium, Or alloys of two or more of these, or a multilayer thereof.

Each of the first and second active layers 124a and 124b is formed on the gate insulating layer 115b so as to overlap with the first and second gate electrodes 121a and 121b, A channel may be formed between the drain electrode 123a and between the second source electrode 122b and the second drain electrode 123b.

8D and 9D illustrate the case where the gate insulating layer 115b is formed only under the first gate electrode 121a, but the present invention is not limited thereto. The gate insulating layer 115b may be formed on the entire surface of the substrate 110 on which the first and second active layers 124a and 124b are formed.

The gate line 117 may be disposed on the same layer as the first and second gate electrodes 121a and 121b. At this time, the above-described gate insulating layer 115b may be disposed under the gate line 117. However, the present invention is not limited thereto.

Next, referring to FIGS. 8E and 9E, an interlayer insulating layer 115c may be formed on the substrate 110. FIG.

The interlayer insulating layer 115c may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). The interlayer insulating layer 115c may be formed over the entire surface of the substrate 110 as shown in FIG. 9E or may be formed only in the pixel region, but the present invention is not limited thereto.

Thereafter, the interlayer insulating layer 115c is selectively patterned through a mask process to form a first contact hole 140a and a second contact hole 140b exposing the source region and the drain region of the first active layer 124a, The fourth contact hole 140d and the fifth contact hole 140e that expose the source region and the drain region of the second active layer 124b can be formed. In addition, the sixth contact hole 140f exposing a part of the first gate electrode 121a can be formed through the mask process described above.

Referring to FIGS. 8F and 9F, a third metal layer is formed on the substrate 110, and then a third metal layer is selectively patterned through a mask process to form first and second source electrodes 122a and 122b and first The second drain electrodes 123a and 123b, and the bridge wiring 119a can be formed.

The third metal layer may include various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper Or two or more alloys, or multiple layers thereof.

Each of the first and second source electrodes 122a and 122b is electrically connected to the first and second active layers 124a and 124b through the first and fourth contact holes 140a and 140d passing through the interlayer insulating layer 115c, As shown in FIG. The first and second drain electrodes 123a and 123b are electrically connected to the first and second active layers 124a and 124b through the second and fifth contact holes 140b and 140e penetrating the interlayer insulating layer 115c, As shown in FIG.

The second drain electrode 123b of the switching transistor may extend upward and be electrically connected to the first gate electrode 121a of the driving transistor. Specifically, the second drain electrode 123b may be connected to the first gate electrode 121a through a sixth contact hole 140f passing through the interlayer insulating layer 115c.

Here, the power supply line 119 may be connected to the first source electrode 122a of the neighboring pixel region through the bridge wiring 119a projecting to the pixel region. The bridge wiring 119a may extend to neighboring pixel regions in a direction parallel to the first direction. The bridge wiring 119a extending to the neighboring pixel region may be connected to the first source electrode 122a of the neighboring pixel region through the first contact hole 140a.

One side of the bridge wiring 119a may extend vertically along the power supply line 119 and may be connected to the lower power supply line 119 through the eighth contact hole 140h.

8G and 9G, after the first and second source electrodes 122a and 122b and the first and second drain electrodes 123a and 123b and the bridge wiring 119a are formed as described above, A protective layer 115d may be formed.

Thereafter, the third contact hole 140c exposing a part of the first drain electrode 123a may be formed by selectively patterning the passivation layer 115d through a mask process.

Next, referring to FIGS. 8H and 9H, a planarization layer 115e may be formed on the substrate 110. FIG.

The planarization layer 115e may be made of an organic insulating material. That is, the planarization layer 115e may be formed of a resin such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, Resist, but is not limited thereto.

At this time, the predetermined area of the circuit part is removed from the planarization layer 115e and the hole H exposing the second drain electrode 123a under the part of the surface of the protection layer 115d and the third contact hole 140c, Can be formed.

Next, referring to FIGS. 8I, 9I, and 9J, a light emitting device may be formed on the substrate 110. FIG. For example, the light emitting device as the organic light emitting device includes an anode 126 formed on the planarization layer 115e and electrically connected to the first drain electrode 123a of the transistor, an organic light emitting layer 127 disposed on the anode 126, And a cathode 128 formed on the light emitting layer 127.

The anode 126 may be formed on the planarization layer 115e including the inside of the hole H and the third contact hole 140c and the hole H formed in the protective layer 115d and the planarization layer 115e And may be electrically connected to the first drain electrode 123a. The anode 126 may be made of a conductive material having a high work function to supply holes to the organic light emitting layer 127. The anode 126 is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO) .

The anode 126 disposed inside the hole H can overlap the part of the second drain electrode 123b under the protection layer 115d to constitute the first capacitor. A part of the second drain electrode 123b overlaps with a part of the first active layer 124a under the interlayer insulating layer 115c to constitute the second capacitor.

When the electroluminescent display device 100 is a top emission type, the anode 126 includes a reflective layer for reflecting light emitted from the organic light emitting layer 127 toward the cathode 128, and a transparent conductive layer for supplying holes to the organic layer. As shown in FIG. However, the present invention is not limited thereto, and the anode 126 may include only a transparent conductive layer, and the reflective layer may be defined as a separate component from the anode 126.

The organic light emitting layer 127 may include any one of a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, and a white organic light emitting layer as an organic layer for emitting light of a specific color. Further, the organic light emitting layer 127 may further include various organic layers such as a hole transporting layer, a hole injecting layer, an electron injecting layer, and an electron transporting layer. In FIG. 9J, the organic light emitting layer 127 is patterned for each pixel, but the present invention is not limited thereto. The organic light emitting layer 127 may be a common layer formed in common to a plurality of pixels.

The cathode 128 may be formed on the organic light emitting layer 127. The cathode 128 can supply electrons to the organic light emitting layer 127. The cathode 128 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) (Tin Oxide) type transparent conductive oxide, or a ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

Referring to FIG. 9J, a bank 115f may be formed on the anode 126 and the planarization layer 115e. The bank 115f may cover a part of the anode 126 of the organic light emitting element and a part of the wiring. The bank 115f may be formed to separate adjacent pixels in the pixel region.

The bank 115f may be made of an organic insulating material. For example, the bank 115f may be formed of polyimide, acryl, or benzocyclobutene (BCB) resin, but the present invention is not limited thereto.

The bank 115f may be formed to surround the light emitting portion on the planarization layer 115e, and the bank 115f may be formed to cover the bridge wiring 119a under the planarization layer 115e.

An encapsulant (not shown) may be formed on the organic light emitting device so as to protect the organic light emitting device, which is vulnerable to moisture, from exposure to moisture. For example, the sealing portion may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

An exemplary embodiment of the present invention can be described as follows.

An electroluminescent display device according to an embodiment of the present invention includes a data line arranged in a first direction on a substrate, a first insulating layer disposed on the data line, an active layer disposed on the first insulating layer, A gate line arranged at least in the second insulating layer and arranged in a second direction intersecting the first direction to partition the pixel region together with the data line, a gate electrode disposed over the active layer, A third insulating layer disposed over the gate electrode and the gate line, a source electrode and a drain electrode disposed on the third insulating layer and connected to a predetermined region of the active layer, a fourth insulating layer disposed over the source electrode and the drain electrode, And a light emitting element disposed in a light emitting portion of the pixel region above the insulating layer.

According to another aspect of the present invention, the electroluminescent display may further include a power supply line disposed in the same layer as the data line in a direction parallel to the first direction.

According to still another aspect of the present invention, the electroluminescent display device may further include a bridge wiring arranged on the third insulating layer in a direction parallel to the second direction, and extending to a neighboring pixel region.

According to another aspect of the present invention, one side of the bridge wiring may extend vertically along the power line to connect to the lower power line through the eighth contact hole.

According to another aspect of the present invention, the first insulating layer is a buffer layer, the second insulating layer is a gate insulating layer, the third insulating layer is an interlayer insulating layer, and the fourth insulating layer is a protecting layer.

According to another aspect of the present invention, a source electrode is connected to a source region of an active layer through a first contact hole penetrating a third insulating layer, and a drain electrode is connected to a source region of the active layer through a second contact hole penetrating the third insulating layer And can be connected to the drain region of the active layer.

According to another aspect of the present invention, the electroluminescent display may further include a fifth insulating layer disposed on the fourth insulating layer.

According to still another aspect of the present invention, an electroluminescent display device includes a hole in which a fifth insulating layer in a predetermined region of a pixel region is removed to expose a part of a surface of a fourth insulating layer and a portion of a drain electrode through a third contact hole .

According to another aspect of the present invention, an anode of a light emitting device is disposed on a fifth insulating layer including a hole, and electrically connected to a drain electrode through a third contact hole formed in the fourth insulating layer and the fifth insulating layer, As shown in FIG.

According to another aspect of the present invention, an anode disposed in a hole overlaps a storage electrode below the fourth insulating layer to form a first capacitor, and the storage electrode is connected to the lower The second capacitor can be formed by overlapping with the active layer of FIG.

According to another aspect of the present invention, the first insulating layer and / or the second insulating layer may have a greater thickness than the third and fourth insulating layers.

According to another aspect of the present invention, there is provided an electroluminescent display device including: a first insulating layer disposed on a vertical line of a power line and a data line arranged in a first direction on a substrate; a first insulating layer disposed on the vertical wiring; A horizontal wiring of a gate line which is arranged in a second direction intersecting the first direction with at least a second insulating layer further interposed therebetween and which divides the pixel region together with the vertical wiring; A source electrode and a drain electrode connected to a predetermined region of the active layer, a fourth insulating layer disposed on the source electrode and the drain electrode, and a third insulating layer disposed on the third insulating layer, Wherein the first insulating layer and / or the second insulating layer has a thickness greater than that of the third and fourth insulating layers and includes at least a first insulating layer between the vertical interconnection and the horizontal interconnection, A short circuit is prevented between the vertical wiring and the horizontal wiring due to the interposition of the second insulating layer and the fourth insulating layer having a relatively thin thickness is interposed between the anode and the storage electrode of the light emitting device, have.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: electroluminescence display
115a: buffer layer
115b: gate insulating layer
115c: interlayer insulating layer
115d: protective layer
115e: planarization layer
115f: bank
116: Data line
117: gate line
119: Power line
119a: Bridge wiring
121a and 121b: gate electrodes
122a, 122b: source electrode
123a, 123b: drain electrode
124a, 124b: an active layer
125: Shading layer
126: anode
127: organic light emitting layer
128: Cathode

Claims (12)

A data line disposed on the substrate in a first direction;
A first insulating layer disposed over the data line;
An active layer disposed over the first insulating layer;
A gate line disposed further on at least a second insulating layer on the first insulating layer and arranged in a second direction intersecting the first direction to partition the pixel region together with the data line;
A gate electrode disposed on the active layer via the second insulating layer;
A third insulating layer disposed over the gate electrode and the gate line;
A source electrode and a drain electrode disposed on the third insulating layer and connected to a predetermined region of the active layer;
A fourth insulating layer disposed over the source electrode and the drain electrode; And
And a light emitting element disposed in a light emitting portion of the pixel region above the fourth insulating layer. The method according to claim 1,
And a power supply line disposed on the same layer as the data line in a direction parallel to the first direction. 3. The method of claim 2,
Further comprising a bridge wiring disposed on the third insulating layer in a direction parallel to the second direction and extending to a neighboring pixel region. The method according to claim 1,
Wherein one side of the bridge wiring extends vertically along the power supply line and connects to the power supply line below the eighth contact hole. The method according to claim 1,
Wherein the first insulating layer is a buffer layer, the second insulating layer is a gate insulating layer, the third insulating layer is an interlayer insulating layer, and the fourth insulating layer is a protective layer. The method according to claim 1,
The source electrode is connected to a source region of the active layer through a first contact hole passing through the third insulating layer and the drain electrode is connected to a source region of the active layer through a second contact hole passing through the third insulating layer, Drain region of the first conductivity type. The method according to claim 1,
And a fifth insulating layer disposed on the fourth insulating layer. 8. The method of claim 7,
Wherein the fifth insulating layer of the predetermined region of the pixel region is removed to expose a portion of the drain electrode through a part of the surface of the fourth insulating layer and the third contact hole. 9. The method of claim 8,
Wherein the anode of the light emitting device is disposed on the fifth insulating layer including the inside of the hole and electrically connected to the drain electrode through the third contact hole and the hole formed in the fourth insulating layer and the fifth insulating layer And an electroluminescence display device connected thereto. 10. The method of claim 9,
The anode disposed in the hole overlaps the storage electrode under the fourth insulating layer to form a first capacitor, and the storage electrode is connected to the active layer through the third insulating layer, And constitutes a second capacitor. 11. The method according to any one of claims 1 to 10,
Wherein the first insulating layer and / or the second insulating layer has a greater thickness than the third and fourth insulating layers. A vertical wiring of the power line and the data line arranged in the first direction on the substrate;
A first insulating layer disposed on the vertical wiring;
An active layer disposed over the first insulating layer;
A horizontal wiring of a gate line which further includes at least a second insulating layer on the first insulating layer and is arranged in a second direction intersecting with the first direction to partition the pixel region together with the vertical wiring;
A third insulating layer disposed over the gate line;
A source electrode and a drain electrode disposed on the third insulating layer and connected to a predetermined region of the active layer;
A fourth insulating layer disposed over the source electrode and the drain electrode; And
And a light emitting element disposed in a light emitting portion of the pixel region above the fourth insulating layer,
Wherein the first insulating layer and / or the second insulating layer has a thickness greater than that of the third and fourth insulating layers, at least between the first insulating layer and the second insulating layer, A short circuit is prevented between the vertical wiring and the horizontal wiring,
Wherein the capacitance of the capacitor is increased by interposing the fourth insulating layer having a relatively small thickness between the anode and the storage electrode of the light emitting device.

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