KR20170024750A - Multilayer capacitor and board having the same - Google Patents

Abstract

The present invention provides a multilayer capacitor and a mounting substrate thereof. A first active region having first and second internal electrodes is disposed on an upper part. A second active region having third and fourth internal electrodes is disposed on a lower part. The first active region is thicker than the second active region. The thickness of the first dielectric layer included in the first active region is thinner than the thickness of the second dielectric layer included in the second active region. So, acoustic noise can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer capacitor,

The present invention relates to a stacked capacitor and a mounting substrate therefor.

Multilayer ceramic capacitors, which are one of the multilayer electronic components, are widely used as display devices such as a liquid crystal display (LCD) and a plasma display panel (PDP), computers, personal digital assistants (PDAs) And is mounted on a circuit board of an electronic product such as a cellular phone to charge or discharge electricity.

Such a multi-layered ceramic capacitor (MLCC) can be used as a component of various electronic devices because of its small size, high capacity, and easy mounting.

The multilayer ceramic capacitor may have a structure in which a plurality of dielectric layers and internal electrodes of different polarities are alternately stacked between the dielectric layers.

Since the dielectric layer has piezoelectricity and electrostrictive properties, when a direct current or an alternating voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon occurs between internal electrodes and vibration may occur.

Such vibration is transmitted to the circuit board on which the multilayer ceramic capacitor is mounted through the external electrode of the multilayer ceramic capacitor, so that the entire circuit board becomes an acoustic reflection surface, thereby generating a noisy vibration sound.

At this time, the vibration sound may correspond to an audible frequency in the range of 20 to 20,000 Hz which gives an uncomfortable feeling to a person, and the unpleasant vibration sound is called an acoustic noise.

Thus, in order to reduce the acoustic noise, a multilayer ceramic capacitor in which the lower cover layer has an increased shape as compared with the upper cover layer is disclosed.

However, since the equivalent series inductance (ESL) is proportional to the area of the current loop, if the lower cover layer of the multilayer ceramic capacitor is increased, the acoustic noise can be reduced. However, There arises a problem that the ESL is relatively high as compared with the product before the cover layer is increased.

Korean Patent Publication No. 2014-0060392 Japanese Patent Application Laid-Open No. 2007-235170

It is an object of the present invention to provide a laminated capacitor and its mounting substrate which can keep the ESL below a certain level while reducing acoustic noise.

According to an aspect of the present invention, there is provided a capacitor body including a first active region having first and second internal electrodes, a second active region having third and fourth internal electrodes and disposed below the first active region, Wherein the first active region is formed thicker than the second active region and the thickness of the first dielectric layer included in the first active region is smaller than the thickness of the second dielectric layer included in the second active region And a mounting substrate for the capacitor.

According to an embodiment of the present invention, it is possible to reduce the vibration generated in the multilayer capacitor, to reduce the acoustic noise generated in the circuit board by the vibration, and to maintain the ESL of the multilayer capacitor below a certain level have.

1 is a perspective view schematically showing a part of a stacked capacitor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the stacked capacitor of FIG. 1 cut in the longitudinal direction.
3 is a cross-sectional view showing a width-thickness cross-section of the capacitor body of FIG.
4 is a cross-sectional view showing a width-thick cross-section of a capacitor body in a stacked capacitor according to another embodiment of the present invention.
5 is a perspective view showing a state in which the stacked capacitor of FIG. 1 is mounted on a circuit board.
Fig. 6 is a cross-sectional view taken along the longitudinal direction of Fig. 5. Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

In order to clearly illustrate the embodiments of the present invention, when the directions of the hexahedron are defined, L, W, and T shown in the drawings indicate the longitudinal direction, the width direction, and the thickness direction, respectively. Here, the thickness direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated.

In the present embodiment, the lower and upper surfaces of the capacitor body are referred to as first and second surfaces 1 and 2, respectively, and both surfaces in the longitudinal direction of the capacitor body are referred to as third and fourth surfaces 3 and 4, respectively, , And both sides in the width direction are set as the fifth and sixth surfaces 5 and 6, respectively.

Laminated type • Capacitors

Referring to FIGS. 1 and 2, a stacked capacitor 100 according to an embodiment of the present invention includes a capacitor body 110 and first and second external electrodes 131 and 132.

The capacitor body 110 is formed by laminating a plurality of dielectric layers and then firing the capacitor body 110. The shape and dimensions of the capacitor body 110 and the number of stacked dielectric layers are not limited to those shown in the present embodiment.

In addition, the plurality of dielectric layers forming the capacitor body 110 are in a sintered state, and the boundaries between the adjacent dielectric layers can be integrated so that it is difficult to confirm without using a scanning electron microscope (SEM).

The capacitor body 110 includes a first active region 115 and an upper cover layer 112 disposed on top of the first active region 115. The first active region 115 includes a second active region 115, And a lower cover layer 116 disposed under the region 114 and the second active region 115.

The first active region 115 is formed by repeatedly stacking a plurality of first and second internal electrodes 121 and 122 with a first dielectric layer 111 sandwiched therebetween.

The first dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, barium titanate (BaTiO ₃ ) -based or strontium titanate (SrTiO ₃ ) -based powder, and the present invention is not limited thereto.

The first and second internal electrodes 121 and 122 are electrodes having different polarities and are formed by printing a conductive paste containing a conductive metal to a predetermined thickness on the first dielectric layer 111, 111 and the third and fourth surfaces 3, 4 along the stacking direction.

At this time, the first and second inner electrodes 121 and 122 may be electrically insulated from each other by the first dielectric layer 111 arranged in the middle.

The first and second internal electrodes 121 and 122 are electrically connected to the first and second external electrodes 131 and 132 through the portions alternately exposed through the third and fourth surfaces 3 and 4 of the capacitor body 110, 132, respectively.

When a voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrodes 121 and 122 opposing each other. At this time, the capacitance of the stacked capacitor 100 Becomes proportional to the area of the overlapping region of the first and second internal electrodes 121 and 122.

The conductive metal included in the conductive paste forming the first and second internal electrodes 121 and 122 may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof. But is not limited thereto.

At this time, the conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The upper cover layer 112 may have the same material and configuration as the first dielectric layer 111 except that it does not include internal electrodes.

The upper cover layer 112 can be formed by laminating a single dielectric layer or two or more dielectric layers on the upper surface of the first active region 115 and is basically formed by physical or chemical stress And the second internal electrodes 121 and 122 from being damaged.

The second active region 114 is formed by repeatedly stacking a plurality of third and fourth internal electrodes 123 and 124 with a second dielectric layer 113 interposed therebetween and is thinner than the first active region 115 Thickness.

The second dielectric layer 113 may include a ceramic powder having a high dielectric constant, for example, a barium titanate (BaTiO ₃ ) -based or a strontium titanate (SrTiO ₃ ) -based powder, and the present invention is not limited thereto.

The third and fourth internal electrodes 123 and 124 are electrodes having different polarities and are formed by printing an electroconductive paste containing a conductive metal to a predetermined thickness on the second dielectric layer 113, 113 in the stacking direction.

At this time, the third and fourth internal electrodes 123 and 124 may be electrically insulated from each other by the second dielectric layer 113 disposed in the middle.

The third and fourth internal electrodes 123 and 124 are electrically connected to the first and second external electrodes 131 and 132 through the portions alternately exposed through the third and fourth surfaces 3 and 4 of the capacitor body 110, 132, respectively.

Accordingly, when a voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the third and fourth internal electrodes 123 and 124 opposing each other. At this time, the capacitance of the stacked capacitor 100 Becomes proportional to the area of the area where the third and fourth internal electrodes 123 and 124 overlap each other.

The conductive metal included in the conductive paste forming the third and fourth internal electrodes 123 and 124 may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof. But is not limited thereto.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The lower cover layer 116 may have the same material and configuration as the second dielectric layer 113 except that it does not include internal electrodes.

The lower cover layer 116 can be formed by laminating a single dielectric layer or two or more dielectric layers on the upper surface of the second active region 114 and is basically formed by physical or chemical stress, And the fourth inner electrodes 123 and 124 from being damaged.

In the present embodiment, when the thickness of the first dielectric layer 111 is defined as EG1 and the thickness of the second dielectric layer 113 is defined as EG2, EG1 < EG2.

That is, since the volume expansion due to the piezoelectric change is reduced in the second dielectric layer 113 having a large thickness, the second active region 114 has a smaller piezoelectric change than the first active region 115, The vibration transmitted by the solder can be further reduced.

In a stacked capacitor, if the lower cover layer is increased compared to the upper cover layer, the vibration of the internal electrode can be reduced to reduce the acoustic noise. However, since the ESL is proportional to the area of the current loop, there is a problem that the ESL of the stacked capacitor is increased.

The third and fourth internal electrodes 123 and 124 are formed in the second active region 114 disposed under the capacitor body 110 so that the lowermost internal electrode and the capacitor body 110 By reducing the distance from the bottom surface 2 to reduce the area of the current loop, the ESL can be kept below a certain level.

This ESL reduction prevention effect can be further improved when the third and fourth internal electrodes 123 and 124 formed in the lower cover layer 114 are formed closer to the lower end of the lower cover layer 114.

In this embodiment, the lower end margin of the capacitor body 110 also increases in proportion to the thickness of the second dielectric layer 113, which is relatively thicker than the first dielectric layer 111. Therefore, And an effect of reducing the delamination can be expected.

The first and second external electrodes 131 and 132 may be formed of a conductive paste containing a conductive metal.

At this time, the conductive metal may be Ni, Cu, Pd, Au or an alloy thereof, but the present invention is not limited thereto.

On the other hand, when the lengths of the first and second inner electrodes 121 and 122 are defined as EL1 and the lengths of the third and fourth inner electrodes 123 and 124 are defined as EL2, EL1 >

The lengths of the first and second internal electrodes 121 and 122 disposed in the first active area 115 are relatively long and the first and second internal electrodes 121 and 121 included in the first active area 115 122 and the third active area 114 and the third internal electrode 123 and the fourth internal electrode 124 disposed in the second active area 114 are relatively small, And the fourth internal electrodes 123 and 124 is reduced, the increase of the capacitance and the increase of the acoustic noise of the stacked capacitor can be minimized.

At this time, the first and second inner electrodes 121 and 122 and the third and fourth inner electrodes 123 and 124 may be formed such that their overlapped lengths become smaller toward the lower side.

That is, since the first and second inner electrodes 121 and 122 and the third and fourth inner electrodes 123 and 124 have a trapezoidal shape overlapping with each other in the longitudinal direction, .

3, an area formed by a plurality of first or second internal electrodes 121 and 122 exposed through one surface in the longitudinal direction of the capacitor body 110 is denoted by EA1, a length of the capacitor body 110 is denoted by EA1, EA2 < EA1 < 0.5, when a region formed by a plurality of third or fourth internal electrodes 123 and 124 exposed through one side of the first direction is defined as EA2.

At this time, if the EA2 / EA1 is less than 0.2, the area of the EA1 is excessively large, the action of suppressing the volume expansion of the second active region 114 weakens, and the portion soldered at the time of mounting on the substrate and the bottom portion of the first active region 115 The acoustic noise reduction effect is reduced. If the EA2 / EA1 is 0.5 or more, the area of the EA1 is too small to assure the capacity of the capacitor.

Referring to FIG. 4, the first to fourth internal electrodes 121'-124 'may be formed so that their widths become narrower toward the lower side.

That is, since the first and second inner electrodes 121 'and 122' and the third and fourth inner electrodes 123 'and 124' have a trapezoidal shape overlapping in the width direction, Can be prevented from being generated.

Table 1 below shows the difference in length between the first and second internal electrodes and the third and fourth internal electrodes and the width-thickness cross section of the capacitor body and the area formed by the internal electrodes of the first active area and the internal electrodes of the second active area The acoustic noise and the capacity according to the ratio of the area formed by the speaker.

In Table 1, * is an example, the acceptance reference value of acoustic noise is set to 28 dBA or less, and NG in the capacity indicates that the basic condition of the electromotive characteristic condition can not be satisfied.

In this embodiment, a region formed by a plurality of first or second internal electrodes in a width-thickness cross-section of the capacitor body is denoted by EA1, and a plurality of third or fourth internal electrodes are formed on the width-thickness cross section of the capacitor body When the length of the first and second inner electrodes is defined as EL1 and the lengths of the third and fourth inner electrodes are defined as EL2 when satisfying 0.2 < EA2 / EA1 < 0.5, , And EL1 > EL2.

Referring to Table 1, samples 1, 3, 5, and 10-13 of the examples showed that the acoustic noise was observed to be less than 28 dBA, and the capacity met the reference capacity.

On the other hand, in the case of Sample 2 with EL1 as EL2, it was found that the acoustic noise was 28.1 higher than the reference value, and in the case of Sample 4 where EL1 was lower than EL2, the acoustic noise was 28.3 dBA higher.

In the case of samples 8 and 9 in which EA2 / EA1 exceeded 0.5, acoustic noise was low, but NG occurred in the capacity measurement test.

In the case of Samples 6, 7 and 14 having EA2 / EA1 of 0.2 or less, the acoustic noise was higher than the reference value, or NG occurred in the capacity measurement test.

Laminated type The capacitor mounting substrate

5 and 6, the mounting board 200 of the multilayer capacitor 100 according to the present embodiment includes a circuit board 210 on which the multilayer capacitor 100 is mounted, And first and second electrode pads 221 and 222 formed to be spaced apart from each other.

At this time, the stacked capacitor 100 has the second active region 114 disposed on the lower side and the lower surfaces of the band portions of the first and second external electrodes 131 and 132 connected to the first and second electrode pads 221 and 222, respectively. And may be electrically connected to the circuit board 210 by the solder 230 in a state of being in contact with the circuit board 210.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various changes and modifications may be made therein without departing from the scope of the invention. It will be obvious to those of ordinary skill in the art.

100; Stacked capacitor
110; Capacitor body
111, 113; The first and second dielectric layers
112; The upper cover layer
114; The second active area
115; The first active area
116; The lower cover layer
121, 122, 123, 124; The first to fourth internal electrodes
131, 132; The first and second outer electrodes
200; Mounting substrate
210; Circuit board
221, 222; The first and second electrode pads
230; Solder

Claims (6)

A first active region and a second active region, the first active region being formed thicker than the second active region; And
First and second external electrodes formed at both ends in the longitudinal direction of the capacitor body; / RTI &gt;
Wherein the first active region includes first and second internal electrodes disposed alternately through both longitudinal sides of the first active region with a plurality of first dielectric layers therebetween,
The second active region includes third and fourth internal electrodes arranged alternately through both longitudinal sides of the second active region with a plurality of second dielectric layers therebetween,
Wherein a thickness of the first dielectric layer is defined as EG1 and a thickness of the second dielectric layer is defined as EG2, EG1 &lt; EG2.
The method according to claim 1,
Wherein an area formed by the plurality of first or second internal electrodes in the width-thickness cross section of the capacitor body is denoted by EA1 and an area formed by the plurality of third or fourth internal electrodes in the width- thickness section of the capacitor body is denoted by EA2 , Satisfies a range of 0.2 < EA2 / EA1 < 0.5.
The method according to claim 1,
Wherein a length of said first and second inner electrodes is EL1 and a length of said third and fourth inner electrodes is EL2, EL1 > EL2.
The method according to claim 1,
Wherein the first and second internal electrodes and the third and fourth internal electrodes are formed so that their overlapped lengths become smaller toward the lower side.
The method according to claim 1,
And the widths of the first to fourth internal electrodes become narrower toward the lower side.



A circuit board having first and second electrode pads on the top; And
A stacked capacitor according to any one of claims 1 to 5 mounted on the circuit board; And a capacitor connected to the capacitor.

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