KR20170016828A - Imaging element, imaging method and electronic apparatus - Google Patents

Abstract

An image pickup apparatus of the present invention includes a pixel array including a plurality of pixels arranged two-dimensionally in a matrix pattern, and a plurality of pixels arranged in accordance with a first column of the plurality of pixels, A plurality of column signal lines connected to the plurality of pixel signal lines, and an analog-to-digital converter shared by the plurality of column signal lines.

Description

IMAGING ELEMENT, IMAGING METHOD AND ELECTRONIC APPARATUS BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to an image pickup device, an image pickup method, and an electronic apparatus, and more particularly, to an image pickup device, an image pickup method, and an electronic apparatus that can achieve higher speed with lower power consumption.

The present invention

JP2014-114143 filed on June 2, 2014,

JP2014-230001 filed on November 12, 2014,

JP2014-230002 filed on November 12, 2014, and

This application claims priority to JP2014-230000 filed on November 12, 2014.

2. Description of the Related Art Conventionally, in an electronic apparatus having an image pickup function such as a digital still camera or a digital video camera, a solid-state image pickup device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used. The solid-state image pickup device has a PD (photodiode) that performs photoelectric conversion and a pixel in which a plurality of transistors are combined, and an image is constructed based on pixel signals output from a plurality of pixels arranged in a plane. Further, the pixel signals output from the pixels are AD-converted in parallel by a plurality of AD (Analog to Digital) converters arranged for each column of pixels, for example.

In such a solid-state image pickup device, the present applicant has proposed a solid-state image pickup device capable of speeding up AD conversion processing by, for example, performing count processing in the down-count mode and the up-count mode in the AD converter For example, see Patent Document 1).

The applicant of the present application has proposed a solid-state image pickup device capable of reducing noise by AD-converting a pixel signal of a reset level and a pixel signal of a signal level, for example, a plurality of times repeatedly See Document 2).

Patent Document 1: JP-A-2005-303648 Patent Document 2: JP-A-2009-296423

Conventionally, it is strongly desired to read pixel signals at a high speed with respect to solid-state image pickup devices. Further, in recent years, applications for use in small terminals such as so-called smart phones and wearable devices are increasing, and it is also strongly demanded to suppress the power consumption of the solid-state imaging elements. For example, conventionally, the speed is increased by increasing the parallel number of the column parallel AD converters as described above. In this case, the power consumption increases in proportion to increasing the number of parallel parallel AD converters , It has been difficult to improve power efficiency (i.e., speed / power). That is, the power consumption increases with the increase in the speed, and the speed decreases as the power consumption decreases.

So that it is possible to achieve a higher speed with a lower power consumption.

An image pickup apparatus according to the first embodiment of the present disclosure includes a pixel array including a plurality of pixels arranged two-dimensionally in a matrix pattern, a plurality of pixels arranged in accordance with a first column of the plurality of pixels, A plurality of column signal lines connected to two or more pixels of the first column, and an analog-digital converter shared by the plurality of column signal lines.

The electronic apparatus according to the second embodiment of the present disclosure includes the optical system including at least one lens and an imaging device that receives light through the optical system, and the imaging device includes a two-dimensional array A plurality of column signal lines arranged in accordance with a first column of the plurality of pixels and having at least one column signal line connected to two or more pixels of the first column, And an analog-to-digital converter shared by a column signal line of the analog-to-digital converter.

The comparator according to the third embodiment of the present disclosure includes a first differential pair connected to the first column signal line of the image pickup apparatus and a second differential pair connected to the second column signal line of the image pickup apparatus, The first column signal line and the second column signal line are for a column of the same pixel array unit in the pixel array.

According to one aspect of the present disclosure, higher speed can be achieved with lower power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a configuration example of an embodiment of an image pickup device to which the present technology is applied. Fig.
2 is a block diagram showing an example of the configuration of a pixel and column processing unit;
3 is a timing chart for explaining the operation of the AD conversion in the image pickup device.
4 is a timing chart for explaining the operation of the AD conversion in the conventional image pickup device.
5 is a timing chart for explaining the operation of AD conversion in a conventional image pickup device employing the sample-hold technique.
6 is a block diagram showing a part of the configuration example of the second embodiment of the image pickup device.
7 is a block diagram showing a part of the configuration example of the third embodiment of the image pickup device.
8 is a diagram for explaining a sequence of CDS processing by an image pickup device;
9 is a view for explaining a sequence of CDS processing by an image pickup device;
10 is a block diagram showing a part of the configuration example of the fourth embodiment of the image pickup device.
11 is a view showing a first configuration example of a wiring layout of an image pickup device.
12 is a view showing a portion corresponding to the section XII-XII in Fig. 11; Fig.
13 is a view showing a portion corresponding to the section XIII-XIII in Fig. 11; Fig.
14 is a diagram showing a second configuration example of a wiring layout of an image pickup device;
Fig. 15 is a view showing a portion corresponding to the cross section XV-XV in Fig. 14; Fig.
Fig. 16 is a view showing a portion corresponding to the cross section XVI-XVI in Fig. 14. Fig.
17 is a diagram showing the circuit configuration of a comparator.
18 is a timing chart illustrating the driving of the comparator.
19 is a diagram showing a first modification of the circuit configuration of the comparator.
20 is a diagram showing a second modification of the circuit configuration of the comparator.
21 is a diagram showing a third modification of the circuit configuration of the comparator.
22 is a diagram showing a fourth modification of the circuit configuration of the comparator.
23 is a timing chart for explaining driving of an image pickup device.
FIG. 24 is a view for explaining the arrangement of pixels in the timing chart of FIG. 23; FIG.
25 is a timing chart illustrating dummy read control of a transmission signal;
26 is a timing chart for explaining dummy read control of a reset signal;
27 is a diagram showing a configuration example of a pixel region and a part of a vertical driving circuit;
28 is a view for explaining a conventional system separation of sub-potential.
29 is a view for explaining the system separation of the sub-potential in the image pickup device;
30 is a block diagram showing a configuration example of an embodiment of an image pickup apparatus to which the present technology is applied.
31 is a view showing an example of using an image sensor;

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

Fig. 1 is a block diagram showing a configuration example of the first embodiment of an image pickup device to which the present technology is applied.

1, the image pickup device 11 includes a pixel region 12, a vertical drive circuit 13, a column signal processing circuit 14, a horizontal drive circuit 15, an output circuit 16, A signal generating circuit 17, and a control circuit 18. [0033]

The pixel region 12 is a light-receiving surface for receiving light condensed by an optical system (not shown). In the pixel region 12, a plurality of pixels 21 are arranged in a matrix, and each of the pixels 21 is connected to the vertical driving circuit 13 for each row via the horizontal signal line 22, And is connected to the column signal processing circuit 14 column by column through the signal line 23. [ Each of the plurality of pixels 21 outputs a pixel signal of a level corresponding to the light amount of the received light, respectively, and an image of a subject forming an image in the pixel region 12 is constructed from the pixel signal.

The vertical drive circuit 13 sequentially outputs a drive signal for driving (transferring, selecting, resetting, etc.) each pixel 21 for each row of the plurality of pixels 21 arranged in the pixel region 12, And supplies it to the pixel 21 through the horizontal signal line 22.

The column signal processing circuit 14 performs CDS (Correlated Double Sampling) processing on the pixel signals output from the plurality of pixels 21 through the vertical signal line 23, And the reset noise is removed. For example, the column signal processing circuit 14 includes a plurality of column processing sections 41 (refer to FIG. 2 described below) corresponding to the number of columns of pixels 21, CDS processing can be performed.

The horizontal drive circuit 15 sequentially supplies a drive signal for outputting the pixel signal from the column signal processing circuit 14 to the data output signal line 24 for each column of the plurality of pixels 21 arranged in the pixel region 12, To the column signal processing circuit (14).

The output circuit 16 amplifies the pixel signal supplied from the column signal processing circuit 14 through the data output signal line 24 at a timing corresponding to the driving signal of the horizontal driving circuit 15 and outputs the amplified pixel signal to the subsequent signal processing circuit Output.

The ramp signal generating circuit 17 generates a ramp signal of a voltage (ramp voltage) dropping with a constant gradient over time as a reference signal referred to when the column signal processing circuit 14 AD-converts the pixel signal And supplies it to the column signal processing circuit 14.

The control circuit 18 controls the driving of each block in the imaging element 11. [ For example, the control circuit 18 generates a clock signal according to the driving period of each block, and supplies it to each block. Further, for example, the control circuit 18 controls the pixel signal from the pixel 21 to be read out so that the column signal processing circuit 14 can AD-convert the pixel signal at high speed.

Next, Fig. 2 shows a configuration example of the pixel 21 and the column processing section 41 of the image pickup device 11. As shown in Fig.

2 shows two pixels 21a and 21b arranged in a predetermined column (column) among a plurality of pixels 21 arranged in the pixel region 12 in Fig. 2 shows a column processing section 41 arranged corresponding to this column among the plurality of column processing sections 41 included in the column signal processing circuit 14. [

As shown in Figs. 1 and 2, in the image pickup device 11, two of the first vertical signal line 23a and the second vertical signal line 23b are provided for one column of the pixel 21. The pixel 21a (for example, the odd-numbered pixels 21) is connected to the first vertical signal line 23a and the pixel 21b (for example, The pixels 21 in the even-numbered rows) are connected. A constant current source 42a constituting a source follower circuit is connected to the first vertical signal line 23a and a constant current source 42b constituting a source follower circuit is connected to the second vertical signal line 23b Respectively. The first vertical signal line 23a and the second vertical signal line 23b are connected to one column processor 41 arranged corresponding to this column.

The pixel 21a includes a PD 31a, a transfer transistor 32a, an FD portion 33a, an amplification transistor 34a, a selection transistor 35a, and a reset transistor 36a.

The PD 31a is a photoelectric conversion unit for converting incident light into electric charge by photoelectric conversion and accumulating it. The anode terminal is grounded, and the cathode terminal is connected to the transfer transistor 32a.

The transfer transistor 32a is driven in accordance with the transfer signal TRG supplied from the vertical drive circuit 13. When the transfer transistor 32a is turned on, the charge accumulated in the PD 31a is transferred to the FD portion 33a .

The FD portion 33a is a floating diffusion region having a predetermined storage capacitance connected to the gate electrode of the amplifying transistor 34a, and accumulates charges transferred from the PD 31a.

The amplifying transistor 34a outputs the pixel signal of the level corresponding to the charge accumulated in the FD section 33a (that is, the potential of the FD section 33a) through the selection transistor 35a to the first vertical signal line 23a . That is, the FD unit 33a is connected to the gate electrode of the amplifying transistor 34a, so that the FD unit 33a and the amplifying transistor 34a can control the charge generated in the PD 31a to a level Into a pixel signal of a pixel.

The selection transistor 35a is driven in accordance with the selection signal SEL supplied from the vertical driving circuit 13 and when the selection transistor 35a is turned on, the pixel signal output from the amplification transistor 34a becomes the first So that it can be output to the vertical signal line 23a.

The reset transistor 36a is driven in accordance with the reset signal RST supplied from the vertical drive circuit 13. When the reset transistor 36a is turned on, the charge stored in the FD portion 33a is supplied to the power supply line Vdd, and the FD portion 33a is reset.

Similarly to the pixel 21a, the pixel 21b includes the PD 31b, the transfer transistor 32b, the FD portion 33b, the amplification transistor 34b, the selection transistor 35b, and the reset transistor 36b. Respectively. Therefore, the respective portions of the pixel 21b operate in the same manner as the respective portions of the pixel 21a as described above, and a detailed description thereof will be omitted. Hereinafter, when there is no need to distinguish between the pixel 21a and the pixel 21b appropriately, hereinafter, the pixel 21 is referred to simply as the pixel 21, and each portion constituting the pixel 21 is similarly referred to.

The column processor 41 includes two input switches 51a and 51b, a comparator 52, a counter 53, and an output switch 54.

The negative input terminal of the comparator 52 is connected to the first vertical signal line 23a through the input switch 51a and to the second vertical signal line 23b through the input switch 51b . The input terminal on the plus side of the comparator 52 is connected to the ramp signal generating circuit 17 in Fig. The output terminal of the comparator 52 is connected to the input terminal of the counter 53 and the output terminal of the counter 53 is connected to the data output signal line 24 via the output switch 54.

The input switches 51a and 51b are opened and closed under the control of the control circuit 18 of Fig. 1 to connect the negative terminal of the comparator 52 to the first vertical signal line 23a, 2 vertical signal line 23b. For example, when the input switch 51a is closed and the input switch 51b is opened, the negative input terminal of the comparator 52 is connected to the first vertical signal line 23a, Is input to the comparator 52. On the other hand, when the input switch 51b is closed and the input switch 51a is opened, the negative input terminal of the comparator 52 is connected to the second vertical signal line 23b, Is input to the comparator 52. [

The comparator 52 compares the magnitude of the ramp signal input to the input terminal on the positive side with the pixel signal input to the input terminal on the negative side, and outputs a comparison result signal indicating the comparison result. For example, the comparator 52 outputs a high-level comparison result signal when the ramp signal is larger than the analog pixel signal, and outputs a low-level comparison result signal when the ramp signal is less than the analog pixel signal Output.

The counter 53 outputs a comparison result signal outputted from the comparator 52 from a high level to a low level from the timing at which the potential of the ramp signal outputted from the ramp signal generating circuit 17 starts to drop to a constant gradient, Is counted up to a predetermined timing. Therefore, the count value counted by the counter 53 is a value corresponding to the level of the pixel signal input to the comparator 52, whereby the analog pixel signal output from the pixel 21 is converted into a digital value .

For example, in the image pickup device 11, the pixel signal of the reset level in which the FD unit 33 of the pixel 21 is reset and the pixel signal of the FD unit 33 of the pixel 21 in the PD 31 A pixel signal of a signal level in a state in which the photoelectrically converted charge is maintained is output from the pixel 21. [ Then, when the pixel signals are AD-converted by the column processing unit 41, the pixel signals from which the reset noise is removed are obtained by obtaining the difference between the signals. The counter 53 has a holding unit 55 for holding the count value, and can temporarily hold the count value as will be described later.

The output switch 54 opens and closes in accordance with the drive signal output from the horizontal drive circuit 15. [ The output switch 54 is closed in accordance with the driving signal outputted from the horizontal driving circuit 15 and the counter 53 is turned on in response to the timing for outputting the pixel signal of the column in which the predetermined column processing section 41 is arranged, ) Is connected to the data output signal line 24. [ Thus, the pixel signal subjected to AD conversion by the column processing section 41 is outputted to the data output signal line 24. [

In this manner, the image pickup element 11 is configured, and the column processing section 41 can alternately AD-convert the pixel signal output from the pixel 21a and the pixel signal output from the pixel 21b. Therefore, in the image pickup device 11, one of the pixel 21a and the pixel 21b performs a reset operation or a signal transfer operation to perform a settling of the pixel signal, ) Can be alternately and repeatedly subjected to AD conversion by the column processing unit 41. [0064]

As described above, in the image pickup device 11, the AD conversion and the setting of the pixel signals are performed simultaneously in the pixel 21a and the pixel 21b, The AD conversion can be speeded up. Further, in the image pickup device 11, it is possible to speed up the AD conversion without increasing the number of the column processors 41, that is, to avoid an increase in power consumption. That is, the image pickup device 11 can speed up the A / D conversion processing with a lower power consumption.

Next, Fig. 3 shows a timing chart for explaining the operation of the AD conversion in the image pickup device 11. Fig.

3, the operation of the pixel 21a connected to the first vertical signal line 23a, the operation of the pixel 21b connected to the second vertical signal line 23b, and the operation of the column processor 41 Are shown.

First, in the first operation period, the pixel 21a connected to the first vertical signal line 23a resets the FD portion 33a, and waits until the output of the pixel signal of the reset level is sufficiently settled (Reset period). In parallel with this operation, in the first operation period, the pixel 21b connected to the second vertical signal line 23b is connected to the pixel of the signal level corresponding to the light reception amount of the PD 31b settled in the previous operation period And keeps the output of the signal. Then, the column processing section 41 AD-converts the pixel signal of the signal level outputted from the pixel 21b (AD conversion period). At this time, in the column processing unit 41, the counter 53 holds the count value corresponding to the pixel signal of the signal level of the pixel 21b in the holding unit 55. [

Next, in the second operation period, the pixel 21a connected to the first vertical signal line 23a continuously holds the output of the pixel signal of the reset level settled in the first operation period, (41) AD-converts the pixel signal of the reset level output from the pixel (21a). At this time, the column processing unit 41 holds the count value corresponding to the pixel signal of the reset level of the pixel 21a in the holding unit 55. In parallel with this operation, in the second operation period, the pixel 21b connected to the second vertical signal line 23b resets the FD portion 33b, and the output of the pixel signal of the reset level is sufficiently settling Wait until it is.

Thereafter, in the third operation period, the pixel 21a connected to the first vertical signal line 23a transfers the photoelectrically-converted charge from the PD 31a to the FD unit 33a, (Signal transmission period) until the output of the pixel signal of the signal level corresponding to the light reception amount of the light reception signal is sufficiently settled. In parallel with this operation, in the third operation period, the pixel 21b connected to the second vertical signal line 23b keeps the output of the pixel signal of the reset level settled in the second operation period , The column processing section 41 AD-converts the pixel signal of the reset level output from the pixel 21b. The column processing unit 41 then calculates the difference between the count value corresponding to the pixel signal of the reset level and the count value corresponding to the pixel signal of the signal level of the pixel 21b held in the holding unit 55 And outputs a pixel signal from which the reset noise is removed.

In the fourth operation period, the pixel 21a connected to the first vertical signal line 23a continues to output the pixel signal of the signal level settled in the third operation period, 41 convert the pixel signal of the signal level output from the pixel 21a. The column processor 41 obtains the difference between the count value corresponding to the pixel signal of this signal and the count value corresponding to the pixel signal of the reset level of the pixel 21a held in the holding unit 55 , And outputs a pixel signal from which the reset noise is removed. In parallel with this operation, in the fourth operation period, the pixel 21b connected to the second vertical signal line 23b transfers the photoelectrically-converted charge from the PD 31b to the FD portion 33b, And waits until the output of the pixel signal of the signal level corresponding to the light reception amount of the light receiving element 31b is settled sufficiently.

After the end of the fourth operation period, the operation returns to the first operation period, and similarly, similarly, the pixel 21a and the pixel 21b of the next row are sequentially operated as the operation target, The operation up to the operation period of FIG. Further, the pixel 21a and the pixel 21b may be shifted by half a period to perform the respective operation periods.

As described above, in the image pickup device 11, the setting of the other pixel signal is performed in parallel with the AD conversion of one pixel signal of the pixel 21a and the pixel 21b. Therefore, for example, the AD conversion of the pixel signal corresponding to the signal level of the pixel 21b is completed in the first operation period, and the pixel signal corresponding to the reset level of the pixel 21a in the second operation period immediately thereafter Can be performed. Similarly, in the second operation period, the AD conversion of the pixel signal corresponding to the reset level of the pixel 21a is completed, and the pixel signal corresponding to the reset level of the pixel 21b in the third operation period AD conversion can be executed. The AD conversion of the pixel signal corresponding to the reset level of the pixel 21b is completed in the third operation period and the signal level of the pixel 21a and the AD conversion . In the fourth operation period, the signal level of the pixel 21a, the pixel signal and the signal level of the pixel 21a and the pixel signal in the first operation period are accumulated in the respective photodiodes, The reset level or the reset noise is removed so that the pixel signal corresponding to the pixel signal from which the reset noise is removed can be obtained.

Therefore, for example, as compared with the configuration in which the column processing section 41 waits for the AD conversion until the settling of the pixel signal is completed, the image pickup device 11 can perform AD conversion at a higher speed.

Here, referring to the timing chart shown in Fig. 4, the operation of AD conversion in the conventional image pickup device will be described.

The conventional image pickup device is constituted by providing one vertical signal line for one column of pixels. In the first operation period, the pixel resets the FD unit and waits until the output of the pixel signal of the reset level is sufficiently settled And the processing is not performed in the column processing section. Next, in the second operation period, the pixel maintains the output of the pixel signal of the reset level settled in the first operation period, and the column processing section performs the AD conversion of the pixel signal of the reset level outputted from the pixel do.

After the A / D conversion is completed, in the third operation period, the pixel transfers the photoelectrically converted charge in the PD to the FD unit, and waits until the output of the pixel signal at the signal level corresponding to the amount of received light of the PD is sufficiently settled , The processing is not performed in the column processing section. In the fourth operation period, the pixel keeps outputting the pixel signal of the signal level settled in the third operation period, and the column processing section AD-converts the pixel signal of the signal level output from the pixel .

In this way, in the conventional image pickup device, since the AD conversion is not performed in the column processing section while the output of the pixel signal is set, compared with the AD conversion operation shown in Fig. 3, However, it takes about twice the time. Therefore, the AD conversion processing can be speeded up in the image pickup device 11 by that much.

Some conventional image pickup devices employ a sample / hold technique.

Here, with reference to the timing chart shown in Fig. 5, the operation of the AD conversion in the conventional image pickup device employing the sample hold technique will be described.

As shown in Fig. 5, in the conventional image pickup device employing the sample-hold technique, one vertical signal line is provided for each column of pixels, and the settled pixel signal is sampled and held in the capacitor, Lt; / RTI > Thereby, the pixel signal of the signal level held in parallel with the settling of the pixel signal of the reset level is AD-converted, and the pixel signal of the reset level held in parallel with the settling of the pixel signal of the signal level is subjected to AD conversion .

However, in recent years, solid-state image pickup devices used in small terminals such as so-called smart phones and wearable devices have a pixel size as small as 1 占 퐉 and it is difficult to apply the sample hold technique. In addition, if the capacitance element used for the sample hold is too small, noise (so-called kT / C noise) generated by the sample hold becomes large and it is difficult to remove by the CDS processing, do. If the capacitance used in the sample hold is increased to such an extent that the noise does not affect the image quality, it becomes difficult to realize the column signal processing. In addition, with the increase in capacitance load on the vertical signal line, So that the processing speed decreases as a whole.

On the other hand, in the image pickup device 11, noise is not generated in a configuration using such a sample-hold technique, deterioration of image quality can be avoided and processing speed can be increased.

3, the image pickup device 11 AD-converts the pixel signal of the reset level of the pixel 21a, AD-converts the pixel signal of the reset level of the pixel 21b, ), And performs AD conversion on the pixel signals at the signal level of the pixel 21b in the AD conversion sequence. For example, even in the solid-state image pickup device disclosed in the above-described Patent Document 2, the pixel signals are read in the same order, but the AD conversion is repeated for the pixel signals of the same reset level and signal level, (11). With this other technology, the circuit configuration and the operation sequence of the column processing section 41 of the image pickup device 11 are different from those of the solid-state image pickup device of Patent Document 2 in order to remove kT / C noise.

Next, Fig. 6 is a block diagram showing a part of the configuration example of the imaging device 11 according to the second embodiment. In the image pickup device 11A shown in Fig. 6, the same components as those of the image pickup device 11 shown in Fig. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

6, the image pickup device 11A includes a pixel sharing structure (pixel sharing structure) for sharing a part of the pixels 21 such as the FD unit 33 and the amplifying transistor 34 in the plurality of pixels 21 It is different from the imaging element 11 shown in Fig.

The shared pixel 61 constituting the image pickup element 11A employs a pixel sharing structure composed of eight pixels 21 arranged so that row x column is 4 x 2. In the imaging element 11A, a color filter is arranged in the pixel 21 according to a so-called Bayer arrangement. In FIG. 6, the colors R, G and B of the respective color filters appear in the pixel 21 have.

2, the first vertical signal line 23a and the second vertical signal line 23b are provided for each column in which the shared pixel 61 is arranged, similarly to the image pickup device 11 of Fig. And the pixel signals inputted to the comparator 52 can be switched to the input switches 51a and 51b.

Therefore, in the image pickup device 11A, in each of the two shared pixels 61a and the shared pixels 61b arranged in the column direction, the pixel 21 has the AD conversion of the pixel signal of the signal level and the reset level The A / D conversion of the pixel signal is performed. When the AD conversion of the pixel signals of the eight pixels 21 included in the shared pixel 61a and the shared pixel 61b is completed, the shared pixel 61a and the shared pixel 61b in the next row are processed , And AD conversion is repeatedly performed.

As described above, in the image pickup device 11A employing the pixel sharing structure, the AD conversion can be speeded up at a lower power consumption, similarly to the image pickup device 11 in Fig.

Next, Fig. 7 is a block diagram showing a part of the configuration example of the imaging device 11 according to the third embodiment. In the image pickup device 11B shown in Fig. 7, the same components as those of the image pickup device 11A shown in Fig. 6 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

That is, the image pickup device 11B has a different structure from the image pickup device 11A of Fig. 6 in that the auto zero technique is used in view of improving the characteristics. More specifically, in the image pickup device 11B, the capacitor 71a is connected between the input switch 51a and the negative input terminal of the comparator 52, and the input switch 51b and the comparator 52 And a capacitor 71b is connected between the negative input terminal and the negative input terminal. In the image pickup device 11B, the positive input terminal of the comparator 52 is connected to the ramp signal generating circuit 17 (see Fig. 1) via the capacitor 72, and the output of the comparator 52 And the input terminal on the negative side are connected to each other through a feedback switch 73.

Therefore, the image pickup device 11B is configured so that the noise (kT / C noise) generated by the sampling can be canceled by the CDS processing by the column processing unit 41. [

The sequence of CDS processing by the image pickup device 11B will be described with reference to Figs. 8 and 9. Fig.

First, as shown in the upper part of Fig. 8, in a first step, the input switch 51a and the return switch 73 are closed. 8, in the second step, the return switch 73 is opened, the ramp signal starts to drop, and the reset level (the reset level) which is input through the first vertical signal line 23a Are subjected to AD conversion.

8, the input switch 51a is opened and the input switch 51b and the return switch 73 are closed in the third step. 9, in the fourth step, the return switch 73 is opened, the ramp signal starts to drop, and the reset level of the reset level, which is input through the second vertical signal line 23b The pixel signal is AD-converted.

9, in the fifth step, the input switch 51b is opened, the input switch 51a is closed, the ramp signal starts to drop, and the first vertical signal line The pixel signal of the signal level inputted through the signal line 23a is AD-converted. 9, in the sixth step, the input switch 51a is opened, the input switch 51b is closed, the ramp signal starts to drop, and the second vertical signal line The pixel signal of the signal level inputted through the signal line 23b is AD-converted.

Here, in the transition from the first step to the second step, the kT / C noise is applied to the capacitor 71a connected to the first vertical signal line 23a. Thereafter, in the transition from the third step to the fifth step, one side of this capacitance is always the releasing end (high impedance node), and the capacitance charge can not be shifted, so that a new kT / C noise is applied Is avoided. Therefore, kT / C noise can be canceled by obtaining the difference between the results of the AD conversion in the first to fifth steps and performing the digital CDS process.

Therefore, in the image pickup device 11B, it is possible to pick up an image with low noise, avoid deterioration of image quality, and increase the processing speed.

Next, Fig. 10 is a block diagram showing a part of the configuration example of the imaging device 11 according to the third embodiment. In the image pickup device 11C shown in Fig. 10, the same components as those of the image pickup device 11B shown in Fig. 7 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

As shown in Fig. 10, the image pickup device 11C includes a first vertical signal line 23a-1, a second vertical signal line 23b-1, Two column processing sections 41-1 and 41-2 are provided on the upper side and the lower side with respect to the column direction of the pixel region, respectively, and four column signal lines 23-1, It is different from the image pickup device 11B of Fig. 7 in that it is provided. That is, the image pickup device 11C has a configuration in which the third vertical signal line 23c, the fourth vertical signal line 23d, and the column processor 41-2 are added. The constant current source 42a-1 is connected to the first vertical signal line 23a-1, the constant current source 42b-1 is connected to the second vertical signal line 23b-1, A constant current source 42a-2 is connected to the signal line 23a-2 and a constant current source 42b-2 is connected to the fourth vertical signal line 23b-2.

In the image pickup device 11C, the shared pixel 61a-1 is connected to the column processing unit 41-1 via the first vertical signal line 23a-1, and the shared pixel 61b- And is connected to the column processor 41-1 through the vertical signal line 23b-1. In the image pickup device 11C, the shared pixel 61a-2 is connected to the column processing unit 41-2 via the third vertical signal line 23a-2, and the shared pixel 61b- 4 connected to the column processing unit 41-2 through the vertical signal line 23b-2.

Therefore, in the image pickup device 11C, in the pixel 21 each having the shared pixel 61a-1 and the shared pixel 61b-1, the pixel signal of the signal level in the column processing unit 41-1 And the A / D conversion of the pixel signal of the reset level is performed. In parallel with this, in the image pickup device 11C, in the pixel 21 each having the shared pixel 61a-2 and the shared pixel 61b-2, And the A / D conversion of the pixel signal of the reset level is performed.

As described above, in the image pickup device 11C, AD conversion can be performed in parallel in the column processing section 41-1 and the column processing section 41-2. For example, in the image pickup device 11B and the image pickup device 11B shown in Fig. As a result, AD conversion can be performed at a speed approximately twice as high.

As described above, the image pickup device 11 of each of the above-described embodiments is configured so as not to use the above-described sample-hold technique and without increasing the number of the column processing sections 41, that is, It is possible to avoid the increase and realize the speedup of the AD conversion processing. That is, the power efficiency of the imaging device 11 capable of high-speed processing can be improved.

Next, the wiring layout of the imaging element 11 will be described.

First, a first configuration example of the wiring layout of the imaging element 11 will be described with reference to Figs. 11 to 13. Fig. 11 shows a planar configuration of the pixel 21a and the pixel 21b of the image pickup device 11. As shown in Fig. Fig. 12 shows a cross sectional configuration at a portion corresponding to the cross section XII-XII shown in Fig. 11, that is, at a connection portion connecting the pixel 21a and the first vertical signal line 23a. 13 shows a cross-sectional configuration at a portion corresponding to the cross section XIII-XIII shown in Fig. 11, that is, at a connection portion connecting the pixel 21b and the second vertical signal line 23b.

11, the pixel 21a includes a PD 31a, a transfer transistor 32a, an FD portion 33a, an amplification transistor 34a, a selection transistor 35a, and a reset transistor 36a Respectively. The horizontal signal line VSS-a for supplying the source voltage, the horizontal signal line 22TRG-a for supplying the row transfer pulse to the transfer transistor 32a, the reset transistor 36a, A for supplying a row reset pulse to the selection transistor 35a and a horizontal signal line 22SEL-a for supplying a row selection pulse to the selection transistor 35a are connected to the horizontal signal line 22RST- Respectively.

Similarly, the pixel 21b is configured to include a PD 31b, a transfer transistor 32b, an FD portion 33b, an amplification transistor 34b, a selection transistor 35b, and a reset transistor 36b. The horizontal signal line VSS-b for supplying a source voltage, the horizontal signal line 22TRG-b for supplying a row transfer pulse to the transfer transistor 32b, the reset transistor 36b, A horizontal signal line 22RST-b for supplying a row reset pulse to the selection transistor 35b and a horizontal signal line VDD-b for supplying a drain voltage and a horizontal signal line 22SEL-b for supplying a row selection pulse to the selection transistor 35b Respectively.

The first vertical signal line 23a and the second vertical signal line 23b are arranged in the vertical direction arranged by the pixel 21a and the pixel 21b. A signal line shield 101 is disposed between the first vertical signal line 23a and the second vertical signal line 23b and the signal line shield 101 is connected to the horizontal signal line VSS- Is connected to the signal line VSS-b, and is fixed to the source voltage.

Since the uniformity of the shape is important in the pixel layout, the pixel 21a and the pixel 21b are connected to each other at the connection point between the pixel 21a and the first vertical signal line 23a, 21b and the second vertical signal line 23b are the same. That is, the connection point between the pixel 21a and the first vertical signal line 23a shown in FIG. 12 and the connection point between the pixel 21b and the second vertical signal line 23b shown in FIG. 13 , And has a different configuration.

12, in the pixel 21a, a gate layer in which the gate electrodes 122-1a and 122-2a are formed in order from the semiconductor substrate (Well) 121 side, a contact layer 123-1a and 123 A first via layer in which the vias 125a are formed, and a first via layer in which the metal interconnects 124-1a and 124-2a are formed; A second via layer in which the second metal layer, the via 127a is formed and the first vertical signal line 23a, the second vertical signal line 23b, and the signal line shield 101 are formed 3 are stacked.

The metal wiring 124-1a is connected to the FD portion 33a in Fig. 11 and to the gate electrode 122-1a constituting the amplifying transistor 34a via the contact 123-1a . Therefore, a potential of a level corresponding to the charge accumulated in the FD portion 33a is applied to the gate electrode 122-1a through the metal wiring 124-1a and the contact 123-1a.

The gate electrode 122-2a constitutes a selection transistor 35a and is connected to a horizontal signal line 22SEL-a for supplying a row selection pulse as shown in Fig. The diffusion layer on the source side of the selection transistor 35a is electrically connected to the first diffusion layer via the contact 123-2a, the metal wiring 124-2a, the via 125a, the metal wiring 126a, and the via 127a. And is connected to the vertical signal line 23a.

13, in the pixel 21b, the gate electrodes 122-1b and 122-2b are formed in the gate layer like the pixel 21a, and the contacts 123-1b and 123-2b are formed in the contact layer. The via 125b is formed in the first via layer and the metal 125b is formed in the first metal layer and the metal 125b is formed in the second metal layer, A wiring 126b is formed and a via 127b is formed in the second via layer and the first vertical signal line 23a, the second vertical signal line 23b, (Not shown).

The metal wiring 124-1b is connected to the FD portion 33b of Fig. 11 and to the gate electrode 122-1b constituting the amplifying transistor 34b via the contact 123-1b . Therefore, a potential of a level corresponding to the charge accumulated in the FD portion 33b is applied to the gate electrode 122-1b through the metal wiring 124-1b and the contact 123-1b.

The gate electrode 122-2b constitutes a selection transistor 35b and is connected to a horizontal signal line 22SEL-b for supplying a row selection pulse as shown in Fig. The diffusion layer at the source side of the selection transistor 35b is electrically connected to the second diffusion layer via the contact 123-2b, the metal wiring 124-2b, the via 125b, the metal wiring 126b and the via 127b. And is connected to the vertical signal line 23b.

12 and 13, in the third metal layer, between the first vertical signal line 23a and the second vertical signal line 23b, between the signal line shield 101 fixed to the source voltage . Thus, for example, generation of coupling capacitance between the first vertical signal line 23a and the second vertical signal line 23b directly in the third metal layer can be suppressed. Therefore, even if a read operation for switching the AD conversion and the settling of the pixel signals simultaneously and in parallel is carried out alternately, the first vertical signal line 23a and the second vertical signal line 23b are adversely affected , It is possible to suppress the generation of noise, for example.

In the third metal layer, the first vertical signal line 23a, the second vertical signal line 23b, and the signal line shield 101 are arranged in the vertical direction, and in the second metal layer, The wiring 126a and the metal wiring 126b are arranged in the horizontal direction. That is, a wiring layout in which the vertical signal line 23 and the metal wiring 126 intersect each other is formed between the third metal layer and the second metal layer.

12, the coupling capacitance Ca generated between the second vertical signal line 23b of the third metal layer and the metal wiring 126a of the second metal layer is . That is, since the metal interconnection 126a is connected to the first vertical signal line 23a, the coupling capacitance (second interconnection line) 23a is indirectly connected between the first vertical signal line 23a and the second vertical signal line 23b Ca) is generated.

13, the coupling capacitance Cb generated between the first vertical signal line 23a of the third metal layer and the metal wiring 126b of the second metal layer increases (increases) . That is, since the metal interconnection 126b is connected to the second vertical signal line 23b, the coupling capacitance (i) is indirectly provided between the first vertical signal line 23a and the second vertical signal line 23b Cb) is generated.

As described above, in the image pickup device 11, the pixel 21a and the pixel 21b perform the AD conversion and the setting of the pixel signal simultaneously in parallel, and the readout operation for reading the pixel signal so that they are alternately switched . In such a read operation, the first vertical signal line 23a and the second vertical signal line 23b are deviated from each other at the timing of reading the pixel signal. Therefore, for example, when the pixel signal of the pixel 21b is not read and the settling of the pixel signal of the pixel 21a is not performed, the pixel signal of the pixel 21b is read through the coupling capacitors Ca and Cb, The potential fluctuation of the first vertical signal line 23a is transmitted to the first vertical signal line 23b, which may deteriorate the signal quality.

As a result, the noise of the pixel signal transmitted through the first vertical signal line 23a and the second vertical signal line 23b increases, which may seriously affect the image quality. In addition, since it is necessary to secure the settling time for the signal quality to return to the original level sufficiently, there is a possibility that the characteristic of the speed-up is considerably impaired. In this way, adverse effects may occur due to crosstalk caused by the coupling capacitances Ca and Cb indirectly generated between the first vertical signal line 23a and the second vertical signal line 23b.

Thus, in the imaging element 11, a wiring layout capable of suppressing the occurrence of such an adverse influence is employed.

Next, a second configuration example of the wiring layout of the image pickup device 11 will be described with reference to Figs. 14 to 16. Fig. Fig. 14 shows a planar configuration of the pixel 21a and the pixel 21b of the image pickup device 11. As shown in Fig. Fig. 15 shows a cross sectional configuration at a portion corresponding to the cross section XV-XV shown in Fig. 14, that is, at a connection portion connecting the pixel 21a and the first vertical signal line 23a. Fig. 16 shows a cross sectional configuration at a portion corresponding to the cross section XVI-XVI shown in Fig. 14, that is, at a connection portion connecting the pixel 21b and the second vertical signal line 23b.

In the wiring layout of the image pickup device 11 shown in Figs. 14 to 16, the same reference numerals are used for the components common to the wiring layout of the image pickup device 11 described with reference to Figs. 11 to 13 And a detailed description thereof will be omitted. For example, in the second configuration example of the wiring layout of the image pickup device 11, the configuration at the connection points shown in Figs. 14 to 16 is similar to that of the image pickup device 11 described with reference to Figs. 11 to 13 ) Of the wiring layout of FIG.

For example, as shown in Fig. 15, in the connection portion where the pixel 21a and the first vertical signal line 23a are connected, in the first metal layer, the metal wiring 124-3a is connected to the second And down to the vertical signal line 23b. Further, in the second metal layer, the metal wiring 126-1a and the metal wiring 126-2a are separately formed. The metal wiring 126-1a is connected to the metal wiring 124-3a via the via 125a and to the first vertical signal line 23a via the via 127-1a. The metal wiring 126-2a is connected to the inter-signal line shield 101 via the via 127-2a.

As described above, in the connection portion connecting the pixel 21a and the first vertical signal line 23a, the metal wiring 124-3a provided in the first metal layer and the metal wiring 124-3b provided in the second metal layer, A two-layer structure of the metal wiring 126-1a and the metal wiring 126-2a is formed. A metal wiring 126-2a connected to the signal line shield 101 fixed to the source potential is disposed between the second vertical signal line 23b and the metal wiring 124-3a. Thereby, a shield structure for shielding the first vertical signal line 23a from the pixel 21a to the second vertical signal line 23b not used for reading the pixel signal is provided. That is, a coupling capacitance Ca 'is generated between the second vertical signal line 23b and the metal wiring 126-2a, and the first vertical signal line 23a and the second vertical signal line 23b, It is possible to reduce the coupling capacitance Ca (Fig. 12) between itself and the signal line 23b.

16, in the connection portion where the pixel 21b and the second vertical signal line 23b are connected to each other, in the first metal layer, the metal wiring 124-3b is connected to the second vertical signal line 23b, (23b). In the second metal layer, the metal wiring 126-1b and the metal wiring 126-2b are separately formed. The metal wiring 126-2b is connected to the metal wiring 124-3b via the via 125b and to the second vertical signal line 23b via the via 127-1b. The metal wiring 126-1b is connected to the signal line shield 101 through the via 127-2b.

As described above, in the connection portion connecting the pixel 21b and the second vertical signal line 23b, the metal wiring 124-3b provided in the first metal layer and the metal wiring 124-3b provided in the second metal layer, Layer structure of the metal wiring 126-1b and the metal wiring 126-2b is formed. A metal wiring 126-1b connected to the signal line shield 101 fixed to the source potential is disposed between the first vertical signal line 23a and the metal wiring 124-3b. Thereby, a shield structure for shielding the second vertical signal line 23b from the pixel 21b to the first vertical signal line 23a not used for reading the pixel signal is provided. That is, a coupling capacitance Cb 'is generated between the first vertical signal line 23a and the metal wiring 126-1b, and the first vertical signal line 23a and the second vertical signal line 23b, It is possible to reduce the coupling capacitance Cb (Fig. 13) between the signal line 23a and the signal line 23b.

As described above, in the image pickup device 11, the connection portion connecting the pixel 21a and the first vertical signal line 23a and the connection portion connecting the pixel 21b and the second vertical signal line 23b A shield structure that shields complementarily can be formed.

That is, the shield structure for shielding the first vertical signal line 23a with respect to the second vertical signal line 23b at the connection point where the pixel 21a and the first vertical signal line 23a are connected is the metal wiring And the metal wiring 126-2a disposed between the first vertical signal line 124-3a and the second vertical signal line 23b to the inter-signal line shield 101. [ Similarly, in a connection portion for connecting the pixel 21b and the second vertical signal line 23b, the shield structure for shielding the second vertical signal line 23b with respect to the first vertical signal line 23a is a metal wiring And the metal wiring 126-1b disposed between the first vertical signal line 123a and the first vertical signal line 23a to the inter-signal line shield 101. [

Thereby, the coupling capacitance between the first vertical signal line 23a and the second vertical signal line 23b can be reduced, and the occurrence of crosstalk can be suppressed. Therefore, the noise of the pixel signal transmitted through the first vertical signal line 23a and the second vertical signal line 23b can be reduced, and an image of better image quality can be obtained. In addition, since it is not necessary to secure a long settling time for returning the signal quality to the original level sufficiently, and the settling time can be shortened, the characteristics of the speedup can be sufficiently exhibited.

Therefore, the imaging device 11 that performs the reading operation for alternately switching the AD conversion and the setting of the pixel signal in parallel at the same time can achieve higher speed or higher precision.

The wiring layout described with reference to Figs. 14 to 16 is a layout in which the number of shared pixels 21, the number of vertical signal lines 23, the direction of transistors constituting the pixels 21 The present invention can be applied to the imaging device 11 of various configurations without being limited thereto.

The present technology is not limited to a configuration in which two vertical signal lines 23 are arranged with respect to a pixel column. The present invention is applicable to a configuration in which three or more vertical signal lines 23 are arranged, (23) can be complementarily shielded. For example, in the configuration in which the four vertical signal lines 23 are arranged, the pair of the third and fourth vertical signal lines 23 is connected to the pair of the first and second vertical signal lines 23 by a complementary . In this configuration, since the metal wiring 124 of the first metal layer can be shortened by an amount corresponding to the two vertical signal lines 23, it is possible to prevent the load from being increased.

Further, for example, by adding a metal layer to the first to third metal layers as described above to form the same shield structure, the effect of suppressing crosstalk can be improved.

The shield structure described with reference to Figs. 14 to 16 may be applied, for example, between inputs of the source follower circuit (between the FD portions 33). That is, when the capacitances between the FD sections 33 are not negligible with respect to the plurality of FD sections 33 in the unit pixel of the shared pixel 61 as shown in Fig. 6, A shield structure may be formed between the electrodes. Thus, adverse effects generated between the plurality of FD units 33 in the unit pixel can be suppressed in the read operation for alternately switching the AD conversion and the setting of the pixel signal in parallel.

Incidentally, as described above, the image pickup device 11 is configured so that the input of the comparator 52 is switched using the input switches 51a and 51b. However, in such a configuration, it is feared that the injection leakage and the feed-through in the switching operation of the input switches 51a and 51b are added to the comparator 52 as noise. In addition, the resistance when the input switches 51a and 51b are turned on causes a delay in the settling of the pixel signal transmitted through the first vertical signal line 23a and the second vertical signal line 23b There is also concern. On the other hand, in order to accelerate the operation of the image pickup device, a mounting method for realizing double reading speed by disposing two comparators at the same time has been proposed. In such a mounting method, It is doubled and the consumed current is doubled.

Thus, the image pickup device 11 employs the comparator 52 having a configuration in which the differential pair is provided in parallel, and the switching switch for switching the active state and the standby state of each differential pair is assembled, Concerns can be resolved. In this configuration, the first vertical signal line 23a and the second vertical signal line 23b are directly connected to the comparator 52 without providing the input switches 51a and 51b.

17, the circuit configuration of the comparator 52 is shown.

17, the comparator 52 includes a differential pair circuit 201, a second amplification section (2nd AMP) 202, and a third amplification section (3rd AMP 203).

Pixel signals are inputted from the first vertical signal line 23a and the second vertical signal line 23b to the differential pair circuit 201 and a ramp signal is inputted from the ramp signal generating circuit 17. The differential pair output from the differential pair circuit 201 is supplied to the second amplification section 202 and is inverted amplified and the output of the second amplification section 202 is amplified by the third amplification section 203 to a predetermined level After being amplified, it is outputted as the above-mentioned comparison result signal.

The differential pair circuit 201 is constituted by transistors 211 to 213, a first differential pair 214a and a second differential pair 214b. As shown in FIG. 17, A pair of the pair of differential gears 214a and 214b is provided in parallel.

The first differential pair 214a is connected to the first vertical signal line 23a and the ramp signal generation circuit 17 and generates a pixel signal supplied through the first vertical signal line 23a, And compares the lamp signals supplied from the circuit 17 with each other. Likewise, the second differential pair 214b is connected to the second vertical signal line 23b and the ramp signal generation circuit 17, and the pixel signal supplied via the second vertical signal line 23b and the ramp signal And compares the lamp signals supplied from the signal generation circuit 17 with each other.

The first differential pair 214a includes a pair of capacitors 221-1a and 221-2a, a pair of transistors 222-1a and 222-2a, a pair of transistors 223-1a and 223-2a ), And a pair of transistors 224-1a and 224-2a.

The capacitor 221-1a is connected to the first vertical signal line 23a and maintains a potential corresponding to the level of the pixel signal. The capacitor 221-2a is connected to the ramp signal generating circuit 17 The potential corresponding to the level of the ramp signal is maintained.

The potential held by the capacitor 221-1a is applied to the gate electrode of the transistor 222-1a and the potential held by the capacitor 221-2a is applied to the gate electrode of the transistor 222-2a. Therefore, the pair of transistors 222-1a and 222-2a are used for comparison between the pixel signal supplied through the first vertical signal line 23a and the ramp signal supplied from the ramp signal generating circuit 17 do.

The transistor 223-1a is arranged so as to connect between the connection point of the gate electrode of the capacitor 221-1a and the transistor 222-1a and the connection point of the transistor 222-1a and the transistor 224-1a do. The transistor 223-2a is connected between the connection point of the gate electrode of the capacitor 221-2a and the transistor 222-2a and the connection point of the transistor 222-2a and the transistor 224-2a . Then, the pair of transistors 223-1a and 223-2a are driven in accordance with the auto-zero control signal AZP-a to perform the auto zero operation of the first differential pair 214a.

The transistor 224-1a is disposed on the source side of the transistor 222-1a to which the potential corresponding to the level of the pixel signal is applied and the transistor 224-2a is disposed on the source side of the transistor 222-1a, (222-2a). The pair of transistors 224-1a and 224-2a are driven in accordance with the comparison operation selection signal SEL-a to turn on / off power supply to the pair of transistors 222-1a and 222-2a, And is used to switch the active state and the standby state of the first differential pair 214a.

That is, the pair of transistors 224-1a and 224-2a are turned on, and power is supplied to the pair of transistors 222-1a and 222-2a, so that the first differential pair 214a is in the active state (ACTIVE), and the pixel signal is compared with the ramp signal. On the other hand, since the pair of transistors 224-1a and 224-2a are turned off and power is not supplied to the pair of transistors 222-1a and 222-2a, the first differential pair 214a (Standby), and the comparison between the pixel signal and the ramp signal is stopped.

 Like the first differential pair 214a, the second differential pair 214b includes a pair of capacitors 221-1b and 221-2b, a pair of transistors 222-1b and 222-2b, Transistors 223-1b and 223-2b, and a pair of transistors 224-1b and 224-2b.

Accordingly, the pair of transistors 224-1b and 224-2b are turned on, and power is supplied to the pair of transistors 222-1b and 222-2b, so that the second differential pair 214b is in an active state And the pixel signal and the ramp signal are compared with each other. On the other hand, since the pair of transistors 224-1b and 224-2b are turned off and power is not supplied to the pair of transistors 222-1b and 222-2b, the second differential pair 214b And the comparison between the pixel signal and the ramp signal is stopped.

In this manner, the comparator 52 is constituted, and the comparison operation selection signal SEL-a supplied to the transistors 224-1a and 224-2a and the comparison operation supplied to the transistors 224-1b and 224-2b The level of the selection signal SEL-b is inverted from each other at the same timing. Thereby, the active state and the standby state of the first differential pair 214a and the second differential pair 214b can be alternately switched.

For example, in the AD conversion period (the second and fourth operation periods of FIG. 3 described above) of the pixel signal output from the pixel 21a connected to the first vertical signal line 23a, The second differential pair 214b may be put into an active state and the second differential pair 214b may be put into a standby state. In the AD conversion period (the first and third operation periods in FIG. 3 described above) of the pixel signal output from the pixel 21b connected to the second vertical signal line 23b, the second differential pair 214b ) To the active state, and the first differential pair 214a can be put in the standby state.

As described above, in the image pickup device 11, the switching unit (the pair of transistors 224-1a and 224-2a and the pair of transistors 224-1b and 224-2b) incorporated in the comparator 52, The pixel signal to be subjected to AD conversion in the column processing section 41 can be switched.

Therefore, the image pickup device 11 including the comparator 52 having the above-described configuration can switch the input within the comparator 52, so that it is necessary to provide the input switches 51a and 51b as described above Can be used. As a result, it is possible to prevent the adverse influences due to the configuration in which the input switches 51a and 51b are provided, for example, noise caused when the input switches 51a and 51b are switched or the ON resistance of the input switches 51a and 51b It is possible to avoid adverse influences such as delays in settling.

Thereby, the image pickup device 11 can pick up an image of a lower noise, and can further increase the speed.

In addition, compared with the configuration in which two comparators are simply provided to increase the speed, the comparator 52 can reduce the power consumption and reduce the size. That is, the comparator 52 shares the current paths of the first differential pair 214a and the second differential pair 214b and shares the second amplification unit 202 and the third amplification unit 203 And can be driven with a current consumption equivalent to that of a configuration in which one comparator is provided, and can be mounted with a small area corresponding to those sharing the same. For example, as compared with the comparator having the configuration including only the second differential pair 214b, the comparator 52 is provided with the first differential pair 214a on the outer side of the second differential pair 214b And it is possible to reduce the trade-off to the chip specification.

Next, a timing chart for explaining the driving of the comparator 52 is shown in Fig.

18 shows, in order from the top, the ramp signal RAMP supplied from the ramp signal generating circuit 17, the comparison operation selection signal SEL-a supplied to the pair of transistors 224-1a and 224-2a, A comparison operation selection signal SEL-b supplied to the pair of transistors 224-1b and 224-2b, an auto zero control signal AZP-a supplied to the pair of transistors 223-1a and 223-2a An auto-zero control signal AZP-b supplied to the pair of transistors 223-1b and 223-2b, and a comparison result signal VCO output from the comparator 52 are shown.

First, on the first P, the comparison operation selection signal SEL-a becomes L level so that the first differential pair 214a becomes active, while the comparison operation selection signal SEL-b becomes H level And the second differential pair 214b becomes a standby state. Further, after the auto zero control signal AZP-a becomes L level in the first half of the P phase to perform the auto zero operation of the first differential pair 214a, the first differential pair 214a The AD conversion of the pixel signal of the reset level is performed. Thus, the comparison result signal VCO is inverted in response to the pixel signal of the reset level input through the first vertical signal line 23a.

Next, on the second P, the comparison operation selection signal SEL-a becomes H level so that the first differential pair 214a becomes a standby state, while the comparison operation selection signal SEL-b becomes L level And the second differential pair 214b becomes active. Further, the auto zero control signal AZP-b becomes L level in the first half of the second P phase and the auto zero operation of the second differential pair 214b is performed. Thereafter, the second differential pair 214b The AD conversion of the pixel signal of the reset level is performed. As a result, the comparison result signal VCO is inverted in response to the pixel signal of the reset level inputted through the second vertical signal line 23b.

Subsequently, on the first D, the comparison operation selection signal SEL-a becomes L level so that the first differential pair 214a becomes active, while the comparison operation selection signal SEL-b becomes H level And the second differential pair 214b is in a standby state. Then, the first differential pair 214a performs AD conversion of the pixel signal of the signal level, and the comparison result signal VCO is inverted in response to the pixel signal of the signal level inputted through the first vertical signal line 23a do.

On the second D, the comparison operation selection signal SEL-a becomes H level and the first differential pair 214a becomes the standby state, while the comparison operation selection signal SEL-b becomes L level And the second differential pair 214b becomes active. The pixel signal of the signal level is subjected to the A / D conversion by the second differential pair 214b, and the comparison result signal VCO is inverted in response to the pixel signal of the signal level inputted through the second vertical signal line 23b. do.

As described above, also in the image pickup device 11 including the comparator 52 having the configuration shown in Fig. 17, the CDS operation by the P-phase and D-phase becomes possible as in the conventional case.

18, by inverting the comparison operation selection signal SEL-a and the comparison operation selection signal SEL-b, the first differential pair 214a and the second differential pair 214b And the standby state are alternately selected. Therefore, when the comparison operation selection signal SEL-a is at the H level, the comparison operation selection signal SEL-b is at the L level, and the signal on the active second differential pair 214b side Lt; RTI ID = 0.0 > 214a. ≪ / RTI > Conversely, when the comparison operation selection signal SEL-b is at the H level, the comparison operation selection signal SEL-a is at the L level and the signal on the first differential pair 214a side in the active state, It is possible to reduce the propagation to the second differential pair 214b in the standby state.

The comparison operation selection signal SEL-b supplied to the transistors 224-1b and 224-2b and the comparison operation selection signal SEL-b supplied to the transistors 223-1b and 223-2b, for example, The auto-zero control signal AZP-b can always be fixed at the H level. In this case, the first differential pair 214a is always in the active state, and the second differential pair 214b is always in the standby state. When the comparator 52 is in the standby state, only the first differential pair 214a is used It is possible to perform the same driving as that of the conventional single comparator. Conversely, when the comparison operation selection signal SEL-a and the auto-zero control signal AZP-a are always fixed at the H level, the comparator 52 compares the comparison result signal SEL- It is possible to perform the same drive as the comparator.

19 shows a first modification of the circuit configuration of the comparator 52. As shown in Fig.

In the comparator 52A shown in Fig. 19, the same components as those of the comparator 52 in Fig. 17 are denoted by the same reference numerals, and a detailed description thereof will be omitted. That is, the comparator 52A has the second amplifying unit 202 and the third amplifying unit 203, and the differential pair circuit 101A has the transistors 211 to 213, 52). Since the first differential pair 214a-a and the second differential pair 214b-A are provided in parallel, the comparator 52A has a configuration common to the comparator 52 of Fig. 17 do.

On the other hand, in the comparator 52A, the arrangement of the transistors used for switching between the active state and the standby state of the first differential pair 214a-a and the second differential pair 214b-A is the same as that of the comparator 52).

That is, in the first differential pair 214a of the comparator 52 in Fig. 17, on the source side of the pair of transistors 222-1a and 222-2a used for signal comparison, A pair of transistors 224-1a and 224-2a used for switching are disposed, respectively. In the second differential pair 214b of the comparator 52 in Fig. 17, on the source side of the pair of transistors 222-1b and 222-2b used for signal comparison, And a pair of transistors 224-1b and 224-2b used for switching are disposed, respectively.

On the other hand, in the first differential pair 214a-A of the comparator 52A, on the drain side of the pair of transistors 222-1a and 222-2a used for signal comparison, And a pair of transistors 225-1a and 225-2a used for switching are respectively disposed. Similarly, in the second differential pair 214b-A of the comparator 52A, on the drain side of the pair of transistors 222-1b and 222-2b used for signal comparison, switching between the active state and the standby state And a pair of transistors 225-1b and 225-2b used in the first embodiment.

As described above, the comparator 52A is configured so that the driving as described above with reference to Fig. 18 can be performed as with the comparator 52 of Fig.

The comparator 52A compares the ramp signal applied to the gate electrodes of the transistors 222-2a and 222-2b through the junction of the drains of the transistors 222-2a and 222-2b, It is possible to suppress propagation as noise to the transistors 222-1a and 222-1b. Thus, in the image pickup device 11 including the comparator 52A, it is possible to pick up a better image with a lower noise.

20 shows a second modification of the circuit configuration of the comparator 52. In Fig.

In the comparator 52B shown in Fig. 20, the same components as those of the comparator 52 in Fig. 17 are denoted by the same reference numerals, and a detailed description thereof will be omitted. That is, the comparator 52B has the second amplifying unit 202 and the third amplifying unit 203, and the differential pair circuit 101B has the transistors 211 to 213, 52). Since the first differential pair 214a-b and the second differential pair 214b-B are provided in parallel, the comparator 52B has a configuration common to the comparator 52 of Fig. 17 do.

On the other hand, in the comparator 52B, the arrangement of the transistors used for switching between the active state and the standby state of the first differential pair 214a-b and the second differential pair 214b-B is the same as that of the comparator 52).

That is, in the first differential pair 214a-B of the comparator 52B, as in the comparator 52 of Fig. 17, the source of the pair of transistors 222-1a and 222-2a A pair of transistors 224-1a and 224-2a used for switching between the active state and the standby state are arranged respectively. In addition, in the first differential pair 214a-B of the comparator 52B, on the drain side of the pair of transistors 222-1a and 222-2a used for signal comparison, And a pair of transistors 225-1a and 225-2a used for switching are respectively disposed.

That is, in the first differential pair 214a-B of the comparator 52B, a pair of transistors 224-1a and 222-2b are provided on both the source side and the drain side of the pair of transistors 222-1a and 222-2a And 224-2a and a pair of transistors 225-1a and 225-2a, respectively.

Similarly, in the second differential pair 214b-B of the comparator 52B, a pair of transistors 224-1b and 222-2b are provided on both the source side and the drain side of the pair of transistors 222-1b and 222-2b, And 224-2b and a pair of transistors 225-1b and 225-2b, respectively.

As described above, the comparator 52B is configured so that the driving as described above with reference to Fig. 18 can be performed as with the comparator 52 of Fig.

The comparator 52B compares the ramp signal applied to the gate electrodes of the transistors 222-2a and 222-2b through the junction of the drain sides of the transistors 222-2a and 222-2b, It is possible to suppress propagation as noise to the transistors 222-1a and 222-1b. In addition, the comparator 52B is configured such that the load of the standby differential pair (either one of the first differential pair 214a-b and the second differential pair 214b-B) does not appear as a differential pair output Therefore, it is possible to avoid the deterioration of the speed due to the increase of the load. Thereby, in the image pickup device 11 including the comparator 52B, it is possible to image a good image with a lower noise at a high speed.

Fig. 21 shows a third modification of the circuit configuration of the comparator 52. In Fig.

In the comparator 52C shown in Fig. 21, the same components as those of the comparator 52 in Fig. 17 are denoted by the same reference numerals, and a detailed description thereof will be omitted. That is, the comparator 52C includes the second amplifying unit 202 and the third amplifying unit 203, and the differential pair circuit 201C includes the transistors 211 to 213, 52). Since the first differential pair 214a-C and the second differential pair 214b-C are provided in parallel, the comparator 52C has a configuration common to the comparator 52 of Fig. 17 do.

On the other hand, the comparator 52C differs from the comparator 52 of FIG. 17 in the connection configuration of the pair of transistors 223-1a and 223-2a for performing the auto zero operation.

That is, in the first differential pair 214a of the comparator 52 of Fig. 17, the gate electrodes of the pair of transistors 222-1a and 222-2a used for signal comparison and the pair of capacitors 221-1a and 221-2a), a pair of transistors 222-1a and 222-2a used for signal comparison, and a pair of transistors A pair of transistors 223-1a and 223-2a for performing an auto zero operation are arranged so as to connect between the connection points of the transistors 224-1a and 224-2a. In the second differential pair 214b of the comparator 52 in Fig. 17, the gate electrodes of the pair of transistors 222-1b and 222-2b used for signal comparison and the pair of capacitors 221-1b and 221-2b), a pair of transistors 222-1b and 222-2b used for signal comparison, and a pair of transistors A pair of transistors 223-1b and 223-2b for performing an auto-zero operation are arranged so as to connect between the connection points of the transistors 224-1b and 224-2b.

In contrast, in the first differential pair 214a-C of the comparator 52C, the gate electrodes of the pair of transistors 222-1a and 222-2a used for signal comparison and the pair of capacitors 221-a and 221-2a and the source side of a pair of transistors 224-1a and 224-2a used for switching between the active state and the standby state, A pair of transistors 223-1a and 223-2a for performing the operation shown in FIG.

Similarly, in the second differential pair 214b-C of the comparator 52C, the gate electrodes of the pair of transistors 222-1b and 222-2b used for signal comparison and the pair of capacitors 221 -1b and 221-2b and the source side of the pair of transistors 224-1b and 224-2b used for switching between the active state and the standby state, A pair of transistors 223-1a and 223-2a are arranged.

The comparator 52C configured as described above can perform the auto zero operation including the pair of transistors 224-1a and 224-2a and the pair of transistors 224-1b and 224-2b, The difference in the voltage threshold of the transistor can be adjusted.

22 shows a fourth modification of the circuit configuration of the comparator 52. As shown in Fig.

In the comparator 52D shown in Fig. 22, the same components as those of the comparator 52 in Fig. 17 are denoted by the same reference numerals, and a detailed description thereof will be omitted. That is, the comparator 52D has the second amplifying unit 202 and the third amplifying unit 203, and the differential pair circuit 201D has the transistors 211 to 213, 52). Since the first differential pair 214a-D and the second differential pair 214b-D are provided in parallel, the comparator 52D has a configuration common to the comparator 52 of Fig. 17 do.

On the other hand, the comparator 52D is connected to the ramp signal generating circuit 17 so that the circuit configuration on the side to which the ramp signal is supplied is the first differential pair 214a-D and the second differential pair 214b- And is different from the comparator 52 of Fig. That is, in the comparator 52D, the circuit configuration of the lamp signal side including the capacitor 221, the transistor 222, and the transistor 223 is the same as the circuit configuration of the first differential pair 214a-D and the second differential pair (214b-D).

That is, the first differential pair 214a-D has a circuit configuration on the pixel signal side composed of the capacitors 221-1a, 222-1a, and 223-1a, and a circuit configuration on the sides of the capacitors 221, The comparison operation of the pixel signal and the ramp signal is performed by the circuit configuration on the ramp signal side consisting of the transistor 222 and the transistor 223. [ Similarly, the second differential pair 214b-D includes a circuit configuration on the pixel signal side composed of the capacitor 221-1b, the transistor 222-1b, and the transistor 223-1b, and a circuit configuration on the side of the capacitor 221, The comparison operation of the pixel signal and the ramp signal is performed by the circuit configuration on the ramp signal side consisting of the transistor 222 and the transistor 223. [

The transistor 224-1a connected to the circuit configuration on the pixel signal side of the first differential pair 214a-D and the transistor 224-1b connected to the circuit configuration on the pixel signal side of the second differential pair 214b-D Transistor 224-1b is used for switching between the active state and the standby state.

In the comparator 52D configured as described above, the circuit configuration on the ramp signal side is shared by the first differential pair 214a-D and the second differential pair 214b-D, for example, Compared with the comparator 52 of FIG. As a result, the entire imaging device 11 can be downsized.

Next, the driving signal and the pixel signal of the imaging element 11 will be described with reference to Fig.

23 shows a case where pixel signals are read out in order of the pixels 21a-1, 21b-1, 21a-2 and 21b-2 arranged as shown in Fig. In a horizontal period (1H).

A selection signal SEL1, a reset signal RST1, and a transmission signal TG1, which are supplied to the pixel 21a-1 and the pixel 21a-2 connected to the first vertical signal line 23a, The selection signal SEL2, the reset signal RST2, the transmission signals TG3 and TG4 supplied to the pixel 21b-1 and the pixel 21b-2 connected to the second vertical signal line 23b, The pixel signal VSL1 outputted through the first vertical signal line 23a, the pixel signal VSL2 outputted through the second vertical signal line 23b and the pixel signal VSL2 output from the ramp signal generating circuit 17 The signal Ramp is shown.

First, after the pixel 21a-1 and the pixel 21b-1 are driven to read the P-phase (pixel signal at the reset level) of the pixel 21a-1, do. Thereafter, the D phase (signal level pixel signal) of the pixel 21a-1 is read, and then the D phase of the pixel 21b-1 is read. Next, after the pixel 21a-2 and the pixel 21b-2 are driven to read the P-phase of the pixel 21a-2, the P-phase of the pixel 21b-2 is read. Thereafter, after the D phase of the pixel 21a-2 is read, the D phase of the pixel 21b-2 is read.

Hereinafter, regarding the pixel 21a-1 and the pixel 21b-1, the pixel 21a-1 in which the pixel signal is first read is referred to as a primer, and the pixel 21b- Is referred to as secondary. Similarly, the pixel 21a-2 is referred to as a primer, and the pixel 21b-2 is referred to as a secondary.

When the shutter operation of the other one of the pixels 21a and 21b is completed during one of the read operations in the image pickup device 11 driven in accordance with the timing chart as described above, the power supply load changes. For this reason, there may occur a transverse noise called a shutter step between a row in which the read operation and the shutter operation are simultaneously performed and a row in which only the read operation is performed.

Thus, in the image pickup device 11, in order to avoid such a change in the power supply load, a dummy read line in which pixels 21 that do not read pixel signals are arranged is provided, and a reset pulse and a transfer pulse A dummy read control can be employed.

Referring to Figs. 25 and 26, dummy read control will be described.

Fig. 25 shows a timing chart when control for suppressing the fluctuation of the power supply load due to the transmission signal in the dummy read row is performed.

25, the ramp signal Ramp outputted from the ramp signal generating circuit 17, the primary transfer signal and the secondary transfer signal in the aperture row for reading the pixel signal, the primary transfer signal and the secondary transfer signal in the dummy read row, The head transmission signal and the secondary transmission signal, the sub-potential variation when the dummy read control is not performed, and the sub-potential variation when the dummy read control is performed. The negative potential fluctuation relates to a power source connected to the second vertical signal line 23b.

As shown in Fig. 25, when dummy read control is performed, control is performed to generate pulses in the secondary transfer signal of the dummy read row so as to coincide with the timing of generating the pulse of the secondary transfer signal. Further, at the timing when the D phase of the primary ends, control is performed to generate a pulse in the primary transfer signal of the dummy read row.

By performing such dummy read control, it is possible to match the sub-potential variation of the power source connected to the second vertical signal line 23b on the P-phase and D-phase of the primary row and on the P-phase and D-phase of the secondary row . By this, in the image pickup device 11, it is possible to avoid generation of a transverse noise called a shutter step as described above.

Fig. 26 shows a timing chart when control for suppressing the fluctuation of the power supply load due to the reset signal in the dummy read row is performed.

26, the ramp signal Ramp output from the ramp signal generating circuit 17, the primary selection signal in the aperture row for reading the pixel signal, the secondary selection signal, and the pixel signal The primary reset signal and the secondary reset signal in the aperture row, the primary selection signal and the secondary selection signal in the dummy read row, and the primary reset signal and the secondary reset signal in the dummy read row, .

26, in the primary reset signal of the dummy read row, dummy read control is performed to generate a pulse for performing the dummy read operation between the primary P phase and the secondary P phase Loses.

By performing such dummy read control, it is possible to match the sub-potential variation of the power source connected to the second vertical signal line 23b on the P-phase and D-phase of the primary row and on the P-phase and D-phase of the secondary row . By this, in the image pickup device 11, it is possible to avoid generation of a transverse noise called a shutter step as described above.

As described above, the dummy read lines in which the pixels 21 that do not read the pixel signals are arranged are provided, and the dummy read lines for suppressing the variations in the sub-potentials between the primary pixels 21a and the secondary pixels 21b By performing the control, the imaging element 11 can suppress the generation of noise and can capture an image of higher image quality.

When the sub-potential is used as the OFF potential of the transfer transistor 32 or the selection transistor 35 in the image pickup device 11, the sub-potential fluctuation caused by the shutter operation or the fluctuation of the potential fluctuation from the vertical signal line 23 Or the like may affect the read signal (the signal read from the pixel 21).

Thus, in the image pickup device 11, in order to avoid adverse influences due to a sub-potential fluctuation caused by a shutter operation or a fluctuation of a potential fluctuation from the vertical signal line 23, the sub-potential is divided into two systems for the lead and the shutter May be adopted.

Next, with reference to Figs. 27 to 29, the image pickup device 11 constructed by systematically separating the sub-potentials will be described.

Fig. 27 shows a part of the pixel region 12 and the vertical drive circuit 13 of the image pickup device 11. Fig.

The pixel region 12 shown in Fig. 27 shows pixels 21 of 4 columns x 16 rows among a plurality of pixels 21 arranged in a matrix, The pixel sharing structure as described above is adopted. That is, in the shared pixel 303 in Fig. 27, the pixel shared structure is constituted by eight pixels 21 in two columns by four rows, and eight shared pixels 303 are arranged in two columns by four rows have. Here, the shared pixel 303a-1 and the shared pixel 303a-2 are primary, and the shared pixel 303b-1 and shared pixel 303b-2 are secondary.

The vertical drive circuit 13 also includes four 16-row drive units 301 for driving the 16-row pixels 21, four 4-row drive units (corresponding to the shared pixels 303 arranged in 4 rows) 302 are provided.

The four-row drive unit 302a-1 supplies the drive signal to the shared pixel 303a-1, the four-row drive unit 302a-2 supplies the drive signal to the shared pixel 303a-2, The driving unit 302b-1 supplies the driving signal to the shared pixel 303b-1, and the four-row driving unit 302b-2 supplies the driving signal to the shared pixel 303b-2.

At this time, a four-row drive unit 302a-1 for driving the shared pixel 303a-1 and a four-row drive unit 302a-2 for driving the shared pixel 303a-2, 2) for driving the common pixel 303b-2 and the four-row drive unit 302b-1 for driving the common pixel 303b-2 and the four-row drive unit 302b-2 for driving the shared pixel 303b- do.

Thus, by separating the sub-potential from the primary and secondary, it is possible to prevent the sub-potential fluctuation caused by the shutter operation and the return of the potential fluctuation from the vertical signal line 23 from affecting the read signal.

Here, with reference to Fig. 28, the conventional system separation of the negative potential will be described.

28, the transmission signal supply section 311 connected to the pixel 21 is constituted by a pair of transistors 321-1 and 321-2 and an amplifier 322. As shown in Fig. A pulse to be a transfer signal is supplied to the transistor 321-1 in an inverted manner through the inverting amplifier 312 and a pulse to be a transfer signal is supplied to the transistor 321-2 in a non-inverted manner. The transistor 321-1 is grounded via the capacitor 314-1 and the charge pump 313-1 is connected to the connection point between the transistor 321-1 and the capacitor 314-1. Similarly, the transistor 321-2 is grounded via the capacitor 314-2, and the charge pump 313-2 is connected to the connection point of the transistor 321-2 and the capacitor 314-2.

The transmission signal supply unit 311 is configured to switch the charge pump 313-1 and the charge pump 313-2 in the lead state and the settling state in accordance with the pulse to separate the sub-potentials for each state .

Thus, conventionally, the sub-potential is separated in the lead state and the sooting state of one pixel 21, and the sub-potential separation between the primary pixel 21a and the secondary pixel 21b is Were not considered.

On the other hand, with reference to Fig. 29, the system separation of the sub-potential in the image pickup device 11 will be described.

As shown in Fig. 29, in the image pickup device 11, system separation of the sub-potential is not performed with the primary pixel 21a and the secondary pixel 21b.

That is, the transmission signal supply unit 311 is configured to include an amplifier 322a that supplies a transmission signal to the pixel 21a and an amplifier 322b that supplies a transmission signal to the pixel 21b. The amplifier 322a is grounded via the capacitor 314a and the charge pump 313a is connected to the connection point of the amplifier 322a and the capacitor 314a. Similarly, the amplifier 322b is grounded via the capacitor 314b, and the charge pump 313b is connected to the connection point of the amplifier 322b and the capacitor 314b.

As described above, the imaging element 11 is configured to separate the sub-potential from the primary pixel 21a and the secondary pixel 21b. Thus, it is possible to suppress the return of noise between the pixel 21a and the pixel 21b. Therefore, in the image pickup device 11, the influence of the noise on the pixels can be suppressed, and a higher-quality image can be picked up.

In the present embodiment, two first vertical signal lines 23a and a second vertical signal line 23b are provided for one column of the pixels 21 arranged in a matrix form in the pixel region 12 It is also possible to adopt a configuration in which two or more vertical signal lines 23 are provided. For example, in the example of Fig. 3, almost the same time is required for settling and holding of the pixel signal. However, for example, it is possible to speed up the AD conversion process itself and shorten the time for holding the output of the pixel signal The AD conversion of the pixel signals output from the plurality of other pixels can be sequentially performed while the plurality of pixels perform settling of the pixel signals. As a result, the AD conversion process as a whole can be performed at a higher speed.

The imaging element 11 is a surface-irradiation-type CMOS image sensor in which light is irradiated to a surface on which a wiring layer is laminated on a semiconductor substrate on which the pixel 21 is formed, Can be applied to any of back-illuminated CMOS image sensors to be irradiated. The image pickup device 11 can also be applied to a stacked CMOS image sensor in which a sensor substrate on which pixels 21 are formed and a circuit substrate on which the control circuit 18 . The process of reading out the pixel signals and performing the AD conversion as described above can be realized by the control circuit 18 executing the program.

The imaging device 11 of each of the above-described embodiments can be used as an imaging system such as a digital still camera or a digital video camera, a mobile phone having an imaging function, It can be applied to various kinds of electronic devices.

30 is a block diagram showing a configuration example of an image pickup apparatus mounted on an electronic apparatus.

30, the image capturing apparatus 401 includes an optical system 402, an image capturing element 403, a signal processing circuit 404, a monitor 405, and a memory 406, An image and a moving image can be captured.

The optical system 402 is constituted by a single lens or a plurality of lenses and guides the incoming light from the subject to the imaging device 403 and forms an image on the light receiving surface (sensor unit) of the imaging device 403.

As the image pickup element 403, the image pickup element 11 of each of the above-described embodiments is applied. Electrons are accumulated in the image pickup element 403 for a predetermined period of time in response to the image formed on the light receiving surface through the optical system 402. [ Then, a signal corresponding to the electrons accumulated in the image pickup element 403 is supplied to the signal processing circuit 404.

The signal processing circuit 404 performs various kinds of signal processing on the pixel signal outputted from the image pickup element 403. [ The image (image data) obtained by the signal processing circuit 404 performing the signal processing may be supplied to the monitor 405 and displayed or may be supplied to the memory 406 to be stored (recorded).

In the image pickup apparatus 401 structured in this way, by applying the image pickup device 11 of the above-described embodiments to the AD conversion processing at a high speed, it is possible to pick up an image at a higher frame rate, for example .

31 is a diagram showing an example of using the above-described image sensor.

The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, for example, as follows.

Devices for capturing images provided for listening, such as digital cameras and portable devices with camera functions

A sensor for mounting on a vehicle that takes a picture of the front or rear of the vehicle, the surroundings, a vehicle, a surveillance camera for monitoring a driving vehicle or a road, A device provided for traffic, such as a range sensor that performs a measurement

A device provided in a home appliance such as a TV, a refrigerator, and an air conditioner for photographing a gesture of a user and operating the device in accordance with the gesture

· Devices provided for medical or health care, such as an endoscope or a device that performs blood vessel imaging by receiving infrared light

· Devices provided for security, such as surveillance cameras for crime prevention and cameras for person authentication

· Apparatus provided for beauty purposes, such as a skin measuring device for photographing the skin or a microscope for photographing the scalp

· Devices provided for sports, such as action cameras or wearable cameras for sports purposes

· Devices provided for agriculture, such as cameras for monitoring the condition of fields and crops

Further, for example, the present technology has the following configuration.

(1) An image pickup apparatus, comprising: a pixel array including a plurality of pixels arranged two-dimensionally in a matrix pattern; and a plurality of pixels arranged in accordance with a first column of the plurality of pixels, A plurality of column signal lines connected to two or more pixels, and an analog-to-digital converter shared by the plurality of column signal lines. (2) The imaging apparatus described in (1), wherein the plurality of column signal lines arranged in accordance with the first column are expanded together.

(3) a first column signal line in the plurality of column signal lines, and a second column signal line in the plurality of column signal lines, the pixels in the even number row share the first column signal line, (1) or (2), wherein the pixels in the row of the number share the second column signal line.

(4) The imaging device according to (1) to (3), wherein at least one of the plurality of column signal lines is selectively coupled to the same comparator.

(5) The imaging apparatus according to (4), further comprising a switch for each of the plurality of column signal lines, wherein each of the switches is coupled to a first terminal of the comparator.

(6) a lamp signal generation circuit connected to a second terminal of the comparator, and a counter section connected to the output terminal of the compressor, wherein the counter section is connected to the data output signal line, .

(7) The comparator includes a first differential pair connected to a first column signal line of the plurality of column signal lines, and a second differential pair connected to a second column signal line of the plurality of column signal lines (5) to (6).

(8) The imaging apparatus according to (7), wherein the first differential pair and the second differential pair are connected to a ramp signal node provided from the ramp signal generation circuit.

(9) The image pickup apparatus according to (8), wherein when the first differential pair is active, the second differential pair is inactive, and when the first differential pair is inactive, the second differential pair is active.

(10) The imaging apparatus according to (9), wherein pixels of an even numbered row share the first column signal line, and pixels of an even numbered row share the second column signal line.

(11) An output from at least one of the first differential pair and the second differential pair is provided in at least one of the first amplifier and the second amplifier, .

(12) the first differential pair includes two transistors connected to a first auto-zero connection node, and the second differential pair includes two transistors connected to a second auto- (7) to (11).

(13) the first differential pair portion includes a transistor connected to a first auto zero connection node, the second differential pair portion includes a transistor connected to a second auto zero connection node, (7) to (12), wherein the differential pair of the first differential pair and the second differential pair share a transistor connected to the third auto zero connection node.

(14) for each of the plurality of column signal lines, and a capacitor for each of the plurality of column signal lines, wherein the first terminal of the capacitor is connected to the switch and the second terminal of the capacitor Is connected to the first terminal of the comparator (4) to (6).

(15) a first pixel sharing structure including at least two pixels in an adjacent column and at least two pixels in an adjacent row, and a second pixel sharing structure including at least two pixels in a neighboring column and a second Wherein the first pixel sharing structure and the second pixel sharing structure are arranged in the same column, and the first pixel sharing structure includes a first pixel sharing structure and a second pixel sharing structure which are connected to a first column signal line of the plurality of column signal lines And the second pixel sharing structure is connected to a second column signal line of the plurality of column signal lines.

(16) The imaging apparatus according to (15), further comprising a color filter arranged on at least two pixels in the adjacent column and at least two pixels in the adjacent row, the color filter being arranged according to the Bayer pattern.

(17) The reading of the reset signal related to the second signal column line of the plurality of signal column lines is performed by reading out the reset signal related to the first signal column line of the plurality of signal column lines and connecting to the first column signal line (1) to (16) that occur between readout of a signal corresponding to the amount of light received by the photodiode.

(18) An optical system including at least one lens and an imaging device for receiving light through the optical system, the imaging device comprising: a plurality of pixels arranged two-dimensionally in a matrix pattern; A plurality of column signal lines arranged in accordance with a first column of the plurality of column signal lines and having at least one column signal line connected to at least two pixels of the first column and an analog digital converter shared by the plurality of column signal lines .

(19) A liquid crystal display device comprising: a first differential pair connected to a first column signal line of an image pickup device; and a second differential pair connected to a second column signal line of the image pickup device, And the second column signal line is a column of the same pixel array unit in the pixel array.

(20) The comparator according to (19), wherein the first differential pair and the second differential pair are connected to a ramp signal node provided from the ramp signal generating circuit.

(21) A comparator according to any one of (19) to (20), wherein the first differential pair is active and the second differential pair is inactive when the first differential pair is inactive and the second differential pair is active when the first differential pair is inactive. .

(22) The comparator according to (19) to (21), wherein the pixels of the even-numbered row share the first column-signal line and the pixels of the even-numbered row share the second column-signal line.

(23) The apparatus according to any one of the above claims, further comprising: a first amplifying section and a second amplifying section, and an output from at least one of the first differential pair and the second differential pair is amplified by the first amplifying section The comparator according to any one of (19) to (22).

(24) the first differential pair includes two transistors connected to a first auto-zero connection node, and the second differential pair comprises two transistors connected to a second auto- (19) to (23).

(25) The semiconductor memory according to (25), wherein the first differential pair portion includes a transistor connected to a first auto zero connection node, the second differential pair portion includes a transistor connected to a second auto zero connection node, (19) to (23), wherein the differential pair of the first differential pair and the second differential pair share a transistor connected to the third auto zero connection node.

(26) A liquid crystal display device comprising: a pixel region in which a plurality of pixels are arranged in a matrix; and an A / D converting section for AD-converting the pixel signals output from the pixels, And a column AD signal processing unit connected to the A / D converter through a predetermined number of vertical signal lines, wherein the pixels of the predetermined number of the vertical signal lines, which are connected via a part of the vertical signal lines, In which the pixel signal outputted from the pixel connected via the other vertical signal line is subjected to the A / D conversion of the A / D conversion section and the operations thereof are alternately repeated.

(27) The liquid crystal display device according to any one of (27) to (30), wherein, for each shared pixel that shares a part constituting the pixel with the plurality of pixels, the reset operation or the signal transmission operation and the AD conversion are performed in parallel (26).

(28) A semiconductor memory device according to (26) or (26), wherein a predetermined number of capacitors are provided between a predetermined number of vertical signal lines and an input terminal of the AD conversion unit, and between the capacitors and the output terminal of the A / (28).

(29) The image pickup device according to any one of (26) to (28), wherein the two column AD signal processing units are provided on the upper side and the lower side with respect to the column direction of the pixel region.

(30) The AD converter is provided for each column of the pixels, and a plurality of the pixels arranged in the first column are connected to the AD converter through the first vertical signal line or the second vertical signal line A reset operation period of the pixel connected to the first vertical signal line and an A / D conversion period for AD-converting the pixel signal of the signal level outputted from the pixel connected to the second vertical signal line in parallel, An A / D conversion period for A / D-converting a pixel signal of a reset level outputted from the pixel connected to the first vertical signal line and a reset operation period of the pixel connected to the second vertical signal line in parallel, A signal transfer period of the pixel connected to the first vertical signal line and a pixel signal of the reset level outputted from the pixel connected to the second vertical signal line are A D converters connected in parallel to the first vertical signal line and performing A / D conversion on the pixel signals of the signal levels in the pixels connected to the first vertical signal lines; The image pickup device according to any one of (26) to (29), wherein the periods are performed in parallel.

(31) The AD conversion unit has a holding unit that holds a value obtained by performing AD conversion on the pixel signal, and maintains a value obtained by AD-converting the pixel signal of the signal level outputted from the pixel connected to the second vertical signal line And outputs a difference between the first and second vertical signal lines after the A / D conversion of the pixel signal of the reset level output from the pixel connected to the second vertical signal line, (30) for holding the value obtained by A / D-converting the pixel signal of the first vertical signal line and outputting the difference between the pixel signals of the signal level output from the pixel connected to the first vertical signal line An imaging device.

(32) An image pickup device according to any one of (26) to (31), wherein in the metal layer in which a predetermined number of the vertical signal lines are formed, a shield between signal lines fixed at predetermined potentials is formed between the vertical signal lines.

(33) The liquid crystal display device according to any one of (33) to (30), wherein at a connection between a predetermined pixel and a predetermined vertical signal line used for reading a pixel signal from the pixel, And a shield structure for shielding the other vertical signal lines is provided.

(34) The shield structure is formed by using at least two metal layers provided between a metal layer on which a shield is formed between the vertical signal line and the signal line and a semiconductor substrate, and is connected to a predetermined vertical signal line And the upper metal layer disposed between the lower metal layer and the other vertical signal line is connected to the shield between the signal lines.

(35) The comparator included in the A / D conversion section includes a differential pair section in which a pixel signal output from the pixel and a ramp signal to be compared for AD conversion of the pixel signal are inputted, (26) to (26), wherein a switching section for switching between an active state for comparing the pixel signal and the ramp signal and a standby state for stopping the comparison of the pixel signal and the ramp signal is provided for each of the differential pairs, 34).

(36) The image pickup device according to any one of (26) to (34), wherein the switching unit is disposed on a source side of a pair of transistors to which the pixel signal and the ramp signal are respectively applied to the gate electrode.

(37) The image pickup device according to (35), wherein the switching unit is disposed on a drain side of a pair of transistors to which the pixel signal and the ramp signal are respectively applied to the gate electrode.

(38) The image pickup device according to (35), wherein the switching unit is disposed on both the source side and the drain side of the pair of transistors, in which the pixel signal and the ramp signal are respectively applied to the gate electrode.

(39) a pair of capacitors for holding the potentials corresponding to the level of the pixel signal and the ramp signal for each of the differential pairs, and a pair of transistors for auto-zero for performing the auto zero operation of the differential pair And a pair of said transistors for auto-zero are respectively connected to a pair of comparison transistors to which said pixel signal and said ramp signal are respectively applied to the gate electrode and each said connection point between said capacitor and said comparator transistor, And the connection point of each of the switching units.

(40) a pair of capacitors each for holding the potential corresponding to the level of the pixel signal and the ramp signal for each of the differential pairs, and a pair of transistors for performing the auto zero operation of the differential pair, The switching section is arranged on the source side of a pair of comparison transistors to which the pixel signal and the ramp signal are respectively applied to the gate electrode and the pair of transistors for auto- (35) arranged so as to connect between each of the connection points of the switching unit and the source side of the switching unit.

(41) The image pickup apparatus according to (35) to (40), wherein a circuit configuration of a predetermined number of the differential pairs on the side to which the ramp signal is inputted is shared.

(42) A dummy read line in which pixels for which pixel signals are not read are arranged, and a control for suppressing variations in the sub-potential between the pixels in which the reset operation or the signal transmission operation and the AD conversion operation are performed in parallel alternately (26) to (41).

(43) The image pickup apparatus according to any one of (26) to (41), wherein the sub-pixel is divided for each of the pixels for alternately performing the reset operation or the signal transmission operation and the AD conversion operation.

(44) A liquid crystal display device comprising: a pixel region in which a plurality of pixels are arranged in a matrix; and an A / D converting section for AD-converting the pixel signals output from the pixels, And a column AD signal processing section connected to the AD conversion section via a predetermined number of vertical signal lines, the method comprising the steps of: connecting a plurality of vertical signal lines An operation of performing AD conversion on the pixel signal output from the pixel connected via the other vertical signal line in parallel with the pixel performing the reset operation or the signal transfer operation is performed and the operations thereof are alternately repeated Wherein the step (c)

(45) A liquid crystal display comprising: a pixel region in which a plurality of pixels are arranged in a matrix; and an A / D converting section for AD-converting the pixel signals output from the pixels, Wherein the pixel has a column AD signal processing section connected to the AD conversion section via a predetermined number of vertical signal lines and wherein the pixel connected through a part of the vertical signal lines of the predetermined number of vertical signal lines is a reset operation or a signal transfer operation And an image pickup device in which an operation of performing AD conversion of the pixel signal output from the pixel connected via the other vertical signal line to the A / D conversion section is performed in parallel, .

While the present invention has been described with reference to the above embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but includes various variations and modifications which may be made by those skilled in the art within the scope of the invention. Of course.

11:
12: pixel area
13: vertical driving circuit
14: Column signal processing circuit
15: Horizontal driving circuit
16: Output circuit
17: lamp signal generating circuit
18: Control circuit
21: pixel
22: horizontal signal line
23: vertical signal line
24: Data output signal line
31: PD
32: transfer transistor
33: FD section
34: amplifying transistor
35: selection transistor
36: reset transistor
41: Column processor
42: constant current source
51: Input switch
52: comparator
53: Counter
54: Output switch
55:
61: shared pixel
71 and 72: capacitors
73: Return switch

Claims (18)

In the image pickup apparatus,
A pixel array including a plurality of pixels arranged two-dimensionally in a matrix pattern;
A plurality of column signal lines arranged according to a first column of the plurality of pixels and having at least one column signal line connected to two or more pixels of the first column,
And an analog-to-digital converter shared by the plurality of column signal lines. The method according to claim 1,
Wherein the plurality of column signal lines arranged in accordance with the first column are expanded with respect to each other. The method according to claim 1,
A first column signal line of the plurality of column signal lines, and a second column signal line of the plurality of column signal lines,
Pixels in an even-numbered row share the first column signal line,
And the pixels in the odd-numbered rows share the second column signal line. The method according to claim 1,
Wherein at least one of the plurality of column signal lines is selectively coupled to the same comparator. 5. The method of claim 4,
Further comprising a switch for each of the plurality of column signal lines,
Each of said switches being coupled to a first terminal of said comparator. 6. The method of claim 5,
A ramp signal generation circuit connected to a second terminal of the comparator,
Further comprising a counter connected to the output terminal of the compressor,
And the counter unit is coupled to the data output signal line. 5. The method of claim 4,
The comparator comprising:
A first differential pair connected to a first column signal line of the plurality of column signal lines,
And a second differential pair connected to a second column signal line of the plurality of column signal lines. 8. The method of claim 7,
And the first differential pair and the second differential pair are connected to a ramp signal node provided from the ramp signal generation circuit. 9. The method of claim 8,
The second differential pair is inactive when the first differential pair is active,
And the second differential pair is active when the first differential pair is inactive. 10. The method of claim 9,
Numbered rows of pixels share the first column signal line, and even-numbered rows of pixels share the second column signal line. 8. The method of claim 7,
And an output from at least one of the first differential pair and the second differential pair is provided in at least one of the first amplifying unit and the second amplifying unit. 8. The method of claim 7,
The first differential pair portion includes two transistors connected to a first auto zero connection node and the second differential pair portion includes two transistors connected to a second auto zero connection node . 8. The method of claim 7,
Wherein the first differential pair portion includes a transistor connected to a first auto zero connection node and the second differential pair portion includes a transistor connected to a second auto zero connection node, And said second differential pair portion shares a transistor connected to a third auto zero connection node. 5. The method of claim 4,
A switch for each of the plurality of column signal lines,
Further comprising a capacitor for each of the plurality of column signal lines,
Wherein the first terminal of the capacitor is connected to the switch and the second terminal of the capacitor is connected to the first terminal of the comparator. The method according to claim 1,
A first pixel sharing structure including at least two pixels in an adjacent column and at least two pixels in an adjacent row,
Further comprising a second pixel sharing structure including at least two pixels in an adjacent column and at least two pixels in an adjacent row,
Wherein the first pixel sharing structure and the second pixel sharing structure are arranged in the same column and the first pixel sharing structure is connected to a first column signal line of the plurality of column signal lines, And the shared structure is connected to the second column signal line of the plurality of column signal lines. 16. The method of claim 15,
Further comprising a color filter arranged on at least two pixels in an adjacent column and at least two pixels in an adjacent row,
Wherein the color filters are arranged according to a Bayer pattern. The method according to claim 1,
Wherein the reading of the reset signal related to the second signal column line of the plurality of signal column lines is performed by reading out the reset signal related to the first signal column line of the plurality of signal column lines and reading the reset signal associated with the first column signal line, And the reading of the signal corresponding to the amount of light received by the imaging device. In the electronic device,
An optical system comprising at least one lens,
And an imaging device that receives light through the optical system,
The imaging device includes a plurality of pixels arranged two-dimensionally in a matrix pattern,
A plurality of column signal lines arranged according to a first column of the plurality of pixels and having at least one column signal line connected to two or more pixels of the first column,
And an analog-to-digital converter shared by the plurality of column signal lines.

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