JP6778595B2 - Image sensor - Google Patents

Description

The present invention relates to an image sensor, for example, an image sensor that converts a pixel signal obtained from a pixel into a digital value and outputs pixel information.

In recent years, the use of image sensors for capturing images has been expanding in surveillance applications and measurement applications. An example of this image sensor is disclosed in Patent Document 1. In the image pickup device described in Patent Document 1, the image pickup device uses a pixel, a lamp wave generator that generates a lamp wave voltage having a lamp waveform, and a lamp wave voltage to determine the amount of light incident on the pixel. It includes an AD conversion unit that converts the corresponding input analog signal into an output digital signal and outputs the output digital signal.

Japanese Unexamined Patent Publication No. 2013-175936

In the image sensor, analog-to-digital conversion processing is performed by the AD conversion unit for each pixel to generate a digital value of a pixel signal output as an analog value according to the voltage level of the pixel signal. However, in recent years, in the image pickup device, the number of pixels has increased or the frame rate has been remarkably improved. Such an improvement in the required performance of the image sensor increases the limit on the time allowed to output the digital value for one pixel. Therefore, recent image sensors are required to output a digital value for one pixel in a shorter time.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

According to one embodiment, the image pickup element is connected to a first pixel unit connected to a first vertical read line and a second vertical read line, and is arranged in the same row as the first pixel unit. It has a second pixel unit, a first transfer switch provided at one end of the first read line, and a second transfer switch provided at one end of the second read line. Vertical readout by a dark level signal output from one of the first pixel unit and the second pixel unit while the transfer switch is controlled to the cutoff state and the second transfer switch is controlled to the conduction state. The line reset processing and the conversion processing of the dark level signal and the pixel signal read from the other of the first pixel unit and the second pixel unit into digital values are performed.

According to the above-described embodiment, the pixel information reading process can be speeded up.

FIG. 5 is a block diagram of a camera system to which the image sensor according to the first embodiment is applied. It is a block diagram of the image pickup device which concerns on Embodiment 1. FIG. It is a block diagram explaining the structure of the vertical read line of the image pickup device, and the transfer switch which concerns on Embodiment 1. FIG. It is a circuit diagram of the pixel unit in the image pickup device which concerns on Embodiment 1. FIG. It is a circuit diagram of the analog-to-digital conversion circuit of the image pickup device which concerns on Embodiment 1. FIG. It is a timing chart explaining the 1st operation example of the image pickup device which concerns on Embodiment 1. FIG. It is a timing chart explaining the 2nd operation example of the image pickup device which concerns on Embodiment 1. FIG. It is a timing chart explaining the 3rd operation example of the image pickup device which concerns on Embodiment 1. FIG. It is a timing chart explaining the 4th operation example of the image pickup device which concerns on Embodiment 1. FIG. It is a block diagram of the image pickup device which concerns on Embodiment 2. FIG. It is a circuit diagram of the pixel unit in the image pickup device which concerns on Embodiment 2. FIG. It is a block diagram of the image pickup device which concerns on Embodiment 3. FIG. It is a circuit diagram of the pixel unit in the image pickup device which concerns on Embodiment 3. FIG. It is a timing chart explaining the operation example of the image pickup device which concerns on Embodiment 3. FIG. It is a block diagram of the image pickup device which concerns on Embodiment 4. FIG. It is a block diagram explaining the structure of the vertical read line of the image pickup device, and the transfer switch which concerns on Embodiment 4. FIG. It is a circuit diagram of the pixel unit in the image pickup device which concerns on Embodiment 4. FIG. It is sectional drawing explaining the structure of the photodiode of the image pickup device which concerns on Embodiment 4. FIG. It is a timing chart explaining the operation example of the image pickup device which concerns on Embodiment 4. FIG. It is a flowchart explaining the output processing of the image information in the image pickup device which concerns on Embodiment 4. It is a flowchart explaining the output processing of the image feature information in the image pickup device which concerns on Embodiment 4. FIG. It is a figure explaining the principle of the phase difference autofocus in the image pickup device which concerns on Embodiment 4. FIG. It is a graph explaining the output of the photodiode when the focus shift occurs in the image pickup device which concerns on the image pickup device which concerns on Embodiment 4. FIG. It is a block diagram of the image pickup device which concerns on Embodiment 5. It is a block diagram explaining the circuit structure of the pixel array of the image pickup device which concerns on Embodiment 5. FIG. FIG. 5 is a circuit diagram of a pixel unit and a floating diffusion common switching circuit in an image sensor according to a fifth embodiment. It is a block diagram which shows the structure of the pixel unit in the 1st operation mode of the image pickup element which concerns on Embodiment 5. FIG. It is a block diagram which shows the structure of the pixel unit in the 2nd operation mode of the image pickup element which concerns on Embodiment 5. FIG. It is a timing chart explaining the operation example in the 2nd operation mode of the image pickup device which concerns on Embodiment 5. FIG. It is a figure explaining the modification of the reading operation in the 1st operation mode of the image pickup device which concerns on Embodiment 5. FIG.

Embodiment 1
In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. In addition, each element described in the drawing as a functional block that performs various processes can be composed of a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. It is realized by such as. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any of them. In each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary.

In addition, the programs described above can be stored and supplied to a computer using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-temporary computer-readable media include magnetic recording media (eg, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (eg, magneto-optical disks), CD-ROMs (Read Only Memory) CD-Rs, CDs. -R / W, including semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transient computer readable media. Examples of temporary computer-readable media include electrical, optical, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

FIG. 1 shows a block diagram of the camera system 1 according to the first embodiment. As shown in FIG. 1, the camera system 1 includes a zoom lens 11, an aperture mechanism 12, a fixed lens 13, a focus lens 14, a sensor 15, a zoom lens actuator 16, a focus lens actuator 17, a signal processing circuit 18, and a system control MCU 19. It has a monitor and a storage device. Here, the monitor and the storage device confirm and store the images taken by the camera system 1, and these may be provided on another system separated from the camera system 1.

The zoom lens 11, the aperture mechanism 12, the fixed lens 13, and the focus lens 14 form a lens group of the camera system 1. The position of the zoom lens 11 is changed by the zoom actuator 16. The position of the focus lens 14 is changed by the focus actuator 17. Then, in the camera system 1, the zoom magnification and the focus are changed by moving the lens by various actuators, and the incident light amount is changed by operating the aperture mechanism 12.

The zoom actuator 16 moves the zoom lens 11 based on the zoom control signal SZC output by the system control MCU 19. The focus actuator 17 moves the focus lens 14 based on the focus control signal SFC output by the system control MCU 19. The aperture mechanism 12 adjusts the aperture amount by the aperture control signal SDC output by the system control MCU 19.

The sensor 15 corresponds to the image pickup device according to the first embodiment, and has, for example, a photoelectric conversion element such as a photodiode, and converts the light receiving pixel information obtained from the light receiving element into a digital value to obtain a pixel. Output information Do. Further, the sensor 15 can add a function of analyzing the pixel information Do output by the sensor 15 and outputting the image feature information DCI representing the feature of the image information Do. The image feature information DCI includes two images acquired in the autofocus process described in the fourth embodiment. Further, the sensor 15 performs gain control for each pixel of pixel information Do, exposure control of pixel information Do, and HDR (High Dynamic Range) control of pixel information Do based on the sensor control signal SSC given from the module control MCU 18. .. Details of the sensor 15 will be described later.

The signal processing circuit 18 performs image processing such as image correction on the image information Do received from the sensor 15 and outputs the image data Dimg. The signal processing circuit 18 analyzes the received pixel information Do and outputs the color space information DCD. The color space information DCD includes, for example, the luminance information of the pixel information Do and the color information. When the sensor 15 does not output the image feature information DCI, the signal processing circuit 18 outputs the image feature information DCI.

The system control MCU 19 controls the focus of the lens group based on the image feature information DCI output from the signal processing circuit 18 or the sensor 15. More specifically, the system control MCU 19 controls the focus of the lens group by outputting the focus control signal SFC to the focus actuator 17. The system control MCU 19 outputs the aperture control signal SDC to the aperture mechanism 12 to adjust the aperture amount of the aperture mechanism 12. Further, the system control MCU 19 controls the zoom magnification of the lens group by generating a zoom control signal SZC according to a zoom instruction given from the outside and outputting the zoom control signal SZC to the zoom actuator 16.

More specifically, the focus is shifted by moving the zoom lens 11 by the zoom actuator 16. Therefore, the system control MCU 19 calculates the positional phase difference between the two object images based on the two images included in the image feature information DCI obtained from the signal processing circuit 18 or the sensor 15, and based on this positional phase difference. Calculate the amount of defocus of the lens group. The system control MCU 19 automatically focuses according to this defocus amount. This process is autofocus control.

Further, the system control MCU 19 calculates an exposure control value for instructing the exposure setting of the sensor 15 based on the brightness information included in the color space information DCD output by the signal processing circuit 18, and the color output from the signal processing circuit 18. The exposure setting and gain setting of the sensor 15 are controlled so that the brightness information included in the spatial information DCD approaches the exposure control value. At this time, the system control MCU 19 may calculate the control value of the aperture mechanism 12 when changing the exposure.

Further, the system control MCU 19 outputs a color space control signal SIC that adjusts the brightness or color of the image data Dimg based on an instruction from the user. The system control MCU 19 generates a color space control signal SIC based on the difference between the color space information DCD acquired from the signal processing circuit 18 and the information given by the user.

The camera system 1 according to the first embodiment has one of features in a circuit used when reading a pixel signal from the pixel unit of the sensor 15 and a reading control method. Further, the pixel information Do described above is digital data obtained by performing analog-digital conversion processing on a pixel signal read from a pixel unit. Therefore, the sensor 15 will be described in more detail below.

FIG. 2 shows a schematic view of a part of the floor layout of the sensor 15 according to the first embodiment. FIG. 2 shows only the floor layout of the row controller 20, the column controller 21, and the pixel array 22 among the floor layouts of the sensor 15.

The row controller 20 controls the active state of the pixel units 23 arranged in a grid pattern for each row. The column controller 21 reads the pixel signals read from the pixel units 23 arranged in a grid pattern for each column. The column controller 21 includes a switch circuit for reading a pixel signal and an output buffer. Further, the operation timing of the circuit included in the column controller 21 is controlled based on the control signal output by the row controller 20. That is, in the sensor 15 according to the first embodiment, the row controller 20 is used as the timing control circuit of the column controller 21.

Pixel units 23 are arranged in a grid pattern on the pixel array 22. In the example shown in FIG. 2, each pixel unit 23 includes a photodiode group including one or more photoelectric conversion elements (for example, photodiode PD) in the column direction. More specifically, each pixel unit 23 is composed of four photodiodes (for example, photodiodes PD0 to PD3). Further, each photodiode is provided with a color filter. In the example shown in FIG. 2, an array of Bayer color filters is adopted. In the Bayer method, green (G) color filters having a large proportion of contributing to the luminance signal are arranged in a checkered pattern, and red (R) and blue (B) color filters are arranged in a checkered pattern in the remaining portion. From another point of view, it can be said that the color filter is arranged so as to transmit different colors in the pixels adjacent to each other in the vertical and horizontal directions among the plurality of pixels. Since the pixel array 22 operates in units of the above pixel units, the configuration and operation of each pixel unit will be described below.

FIG. 3 shows a block diagram illustrating a configuration of a vertical read line and a transfer switch of the sensor 15 according to the first embodiment. Further, in FIG. 3, an analog-to-digital conversion circuit 24 included in the pixel unit 23 and the column controller 21 is shown in order to more clearly explain the configuration of the vertical read line and the transfer switch. Further, in FIG. 3, only the pixels unit for 2 rows and 2 columns and the circuit in the column controller 21 are shown. Further, in the drawings after FIG. 3, the row number in which the pixel unit is arranged is shown in <>, and the column number is shown in [].

As shown in FIG. 3, the sensor 15 according to the first embodiment has a first vertical read line (for example, vertical read line PIXOUT_L) and a second vertical read line with respect to the pixel units arranged in one row. (For example, the vertical readout line PIXOUT_R) is provided. A first pixel unit (for example, a pixel unit of even-numbered rows (0th row, 2nd row, ...)) Is connected to the vertical readout line PIXOUT_L. A second pixel unit (for example, a pixel unit in the odd-numbered rows (first column, third row, ...)) Is connected to the vertical readout line PIXOUT_R.

The column controller 21 has a first pixel current source (for example, pixel current source Ipx_L), a second pixel current source (pixel current source Ipx_R), and a first transfer switch (for example, transfer switch 25) for each column. , A second transfer switch (eg, transfer switch 26), analog-digital conversion circuit 24.

The pixel current source Ipx_L is provided corresponding to the vertical readout line PIXOUT_L, and draws a current from the vertical readout line PIXOUT_L. The pixel current source Ipx_R is provided corresponding to the vertical readout line PIXOUT_R, and draws a current from the vertical readout line PIXOUT_R. The transfer switch 25 is provided at one end of the vertical read line PIXOUT_L. The open / closed state of the transfer switch 25 is controlled based on the read line selection signal LINE_SEL_L output from the row controller 20. The transfer switch 26 is provided at one end of the vertical read line PIXOUT_R. The open / closed state of the transfer switch 26 is controlled based on the read line selection signal LINE_SEL_L.

In FIG. 3, the pixel current source is provided on the vertical readout line between the pixel unit and the pixel switch, but it is also conceivable to provide the pixel current source on the path from the transfer switch to the analog-to-digital conversion circuit. However, when the pixel current source is provided in the path from the transfer switch to the analog-to-digital conversion circuit, the potential of the vertical readout line becomes high during the period when the selection transistor in the pixel unit is in the cutoff state and the transfer switch is in the open state. It may become unstable and it may take time to set the dark level for the vertical readout line described later. Therefore, the pixel current source is preferably provided on the vertical readout line between the pixel unit and the pixel switch.

The analog-to-digital conversion circuit 24 outputs a digital value according to the signal level of the signal input via the transfer switch 25 and the transfer switch 26. That is, one analog-to-digital conversion circuit 24 is provided for a set of vertical read lines PIXOUT_L and PIXOUT_R.

Further, in FIG. 3, the load resistance Ri (Ri_R, Ri_R in FIG. 3) connected in parallel with the pixel current source, the parasitic resistance Rware of the vertical readout line (Rwire_L, Rwire_L in FIG. The parasitic capacitance Cline (Cline_L, Cline_R) is shown.

Subsequently, the pixel unit 23 of the sensor 15 according to the first embodiment will be described. FIG. 4 shows a circuit diagram of a pixel unit in the image sensor according to the first embodiment. The pixel units 23 arranged in the pixel array 22 differ only in the corresponding rows, and the same circuit is used as the circuit. Therefore, the circuit of the pixel unit 23 will be described by taking the pixel unit arranged on the 0th line as an example.

As shown in FIG. 4, the pixel unit 23 includes a photoelectric conversion element (for example, photodiodes PD0 to PD3), transfer transistors 310 to 313, a reset transistor 32, an amplification transistor 33, and a selection transistor 34. The transfer transistor 310 to 313, the reset transistor 32, the amplification transistor 33, and the selection transistor 34 are NMOS transistors.

The transfer transistors 310 to 313 are transistors provided corresponding to the photodiodes PD0 to PD3. The transfer transistors 310 to 313 function as switches whose open / closed state is controlled by the transfer control signals TX0 to TX3. The transfer transistors 310 to 313 are in a conductive state (switch closed state) to transfer the electric charge accumulated in the photodiode corresponding to the floating diffusion FD. Although details will be described later, the sensor 15 according to the first embodiment controls to read out a pixel signal by transferring an electric charge to the floating diffusion FD for each photodiode.

The reset transistor 32 is provided between the power supply wiring VDD_PX and the floating diffusion FD. The reset transistor 32 is a switch whose open / closed state is controlled by the reset control signal RST. In the sensor 15 according to the first embodiment, the potential of the floating diffusion FD is set to the reset level by making the reset transistor 32 conductive.

In the amplification transistor 33, a floating diffusion FD is connected to the gate, and the drain is connected to the power supply wiring VDD_PX. The source of the amplification transistor 33 is connected to the drain of the selection transistor 34. A selection signal SEL is input to the gate of the selection transistor 34, and the source is connected to the vertical read line PIXOUT_L. The amplification transistor 33 generates a pixel signal according to the voltage level of the floating diffusion FD. The selection transistor 34 is a switch whose open / closed state is controlled by the selection signal SEL. In the sensor 15 according to the first embodiment, the selection transistor 34 is made conductive, so that the pixel signal generated by the amplification transistor 33 is output to the vertical readout line PIXOUT_L.

Subsequently, the analog-to-digital conversion circuit 24 of the sensor 15 according to the first embodiment will be described. The analog-to-digital conversion circuit 24 according to the first embodiment has an input terminal commonly provided for the transfer switch 25 and the transfer switch 26, and converts the dark level signal to the digital value input via the transfer switch 25. The conversion of the pixel signal to the digital value, the conversion of the dark level signal input via the transfer switch 26 to the digital value, and the conversion of the pixel signal to the digital value are alternately performed. That is, the analog-to-digital conversion circuit 24 converts the input signals into digital values one by one in the order of input.

Here, FIG. 5 shows a circuit diagram of the analog-to-digital conversion circuit 24 of the sensor 15 according to the first embodiment. In FIG. 5, a row controller 20 is shown for explaining the components of the analog-to-digital conversion circuit 24. The analog-to-digital conversion circuit 24 operates by receiving various control signals and voltages used for operation from the reference voltage generation circuit 41, the control signal generation circuit 42, and the lamp signal generation circuit 43 included in the row controller 20. Further, the analog-to-digital conversion circuit 24 has an amplifier OP that functions as a programmable gain amplifier (hereinafter referred to as PGA) and a comparator CMP that operates as an analog-digital converter.

As shown in FIG. 5, the analog-to-digital conversion circuit 24 includes an amplifier OP, a comparator CMP, capacitors C1 to C4, switches SW1 and SW2. In the amplifier OP, a pixel signal is input to the inverting input terminal via the capacitor C1. A capacitor C2 is provided between the output terminal of the amplifier OP and the inverting input terminal. Then, a PGA reference voltage is applied to the forward rotation input terminal of the amplifier OP from the reference voltage generation circuit 41. The capacitor C1 is a variable capacitance whose capacitance value is determined by the PGA gain setting signal output by the control signal generation circuit 42. Here, the amplifier OP and the capacitors C1 and C2 function as programmable gain amplifiers. This programmable gain amplifier changes the amplification factor of the pixel signal by changing the capacitance ratio between the capacitor C1 and the capacitor C2 according to the PGA gain setting signal.

In the comparator CMP, a capacitor C4 is connected between the inverting input terminal and the ground wiring, and the forward rotation input terminal is connected to the output terminal of the amplifier OP via the switch SW1. One end of the capacitor C3 is connected to the forward rotation input terminal of the comparator CMP. A lamp signal is input from the lamp signal generation circuit 43 to the other end of the capacitor C3. Further, a switch SW2 is connected between the inverting input terminal and the output terminal of the comparator CMP. The open / closed state of the switch SW1 is controlled by the ADC sampling pulse signal output from the control signal generation circuit 42. The open / closed state of the switch SW2 is controlled by the ADC auto zero pulse signal output by the control signal generation circuit 42. Further, the analog-to-digital converter 11 has a counter that counts the reference clock according to the output value of the comparator CMP. This reference clock is output by an oscillator circuit or the like (not shown). The analog-to-digital conversion circuit 24 stops the counting operation of the counter according to the inversion of the magnitude relationship between the signal level of the lamp signal and the signal level of the pixel signal, and digitally sets the count value output by the counter at the time of stopping. Is output as.

Here, the comparator CMP and the capacitors C3 and C4 function as a single slope integral type AD conversion circuit. The single slope integral type AD conversion circuit uses a lamp signal having a correlation with the count value of the counter that counts the output value of the comparator CMP as a reference reference voltage. Then, the single slope integral type AD conversion circuit inputs the lamp signal to the comparator CMP, compares the analog signal to be converted with this lamp signal, holds the count value at the time when both match, and AD. Output as a conversion result. In the example shown in FIG. 5, the analog level of the pixel signal input from the programmable gain amplifier side is held in the capacitors C3 and C4. Then, in the single-slope integral type AD conversion circuit according to the first embodiment, the voltage generated by the charges accumulated in the two capacitors is compared while changing the voltage level of the lamp signal given to the other end of the capacitor C3. ..

Subsequently, the operation of the sensor 15 according to the first embodiment will be described. In the sensor 15 according to the first embodiment, the pixel unit 23 in the odd-numbered rows and the pixel unit 23 in the even-numbered rows are connected to different vertical readout lines among the two vertical readout lines in a pair, and the two vertical readout lines are connected. Turn on (closed) the transfer switch provided at one end of the readout line. As a result, the sensor 15 according to the first embodiment performs the conversion process of the pixel signal read from the pixel unit 23 and the reset process of setting the vertical read line to the dark level in parallel.

Therefore, FIG. 6 shows a timing chart for explaining the first operation example of the sensor 15 according to the first embodiment. It is assumed that the switching timing of each operation and the circuit state for each process shown in FIG. 6 are controlled by the row controller 20 that functions as a timing control circuit.

As shown in FIG. 6, in the sensor 15 according to the first embodiment, the pixel signal reading process from the pixel unit 23 in the 0th row and the pixel signal reading from the pixel unit 23 in the 1st row are alternately performed.

In the example shown in FIG. 6, the read line selection signals LINE_SEL_L and LINE_SEL_R are both set to low levels during the period between timings TB0 to TB10. Then, the reset control signal RST <0> and the selection signal SEL <0> are activated during the period of timings TB0 to TB1. As a result, the floating diffusion FD in the pixel unit 23 on the 0th row is reset to the dark level (RST in the figure). Subsequently, at the timing TB1, the reset control signal RST <0> is switched from the high level to the low level to end the reset of the floating diffusion FD. During the subsequent period from timing TB1 to TB10, the selection signal SEL <0> is maintained at a high level, and the dark level is read out to the vertical read line PIXOUT_L based on the dark level of the floating diffusion FD (LINE DARK in FIG. 6). .. The reset process of the vertical read line PIXOUT_L is started from the timing TB0, but the vertical read line PIXOUT_L has a larger capacitance than the floating diffusion FD, and therefore takes longer to reset than the floating diffusion FD.

Subsequently, the read line selection signal LINE_SEL_L is switched from the low level to the high level from the timing TB10 to the timing TB11. At this time, the read line selection signal LINE_SEL_R maintains a low level. As a result, the transfer switch 25 is turned on, and the transfer switch 26 is maintained in the off state. Here, when the transfer switch 25 is switched from the off state to the on state, the read line selection signal LINE_SEL_L accompanying the voltage change of the gate of the transistor constituting the transfer switch 25 and the wiring connecting the transfer switch 25 and the analog-digital conversion circuit 24. There is an injection that causes noise in the switch. Therefore, the sensor 15 starts the analog-to-digital conversion process after the noise due to the injection has converged. This injection occurs when the transfer switches 25 and 26 are switched from the on state to the off state and when the transfer switches 25 and 26 are switched from the off state to the on state. Therefore, in the sensor 15, the operation timing is controlled so that the analog-to-digital conversion process is not performed during the injection period even in the operation after the timing TB11.

Then, the dark level is transferred from the vertical readout line PIXOUT_L to the analog-digital conversion circuit 24 during the period from the timing TB11 to the timing TB12 (ADC DARK in FIG. 6). After that, the charge generated by the photodiode PD0 is transferred to the floating diffusion FD of the pixel unit 23 on the 0th line with the transfer control signal TX0 <0> as the high level during the period from the timing TB12 to the timing TB13 (TX in FIG. 6). .. Subsequently, during the period from the timing TB13 to the timing TB20, the pixel signal generated based on the charge read by the floating diffusion FD of the pixel unit 23 on the 0th line is transferred to the vertical read line PIXOUT and the analog-to-digital conversion circuit 24 (FIG. SIG in 6).

In the sensor 15, the time required to output one pixel signal is referred to as 1H time. In the example shown in FIG. 6, 1H time is the time between the timing TB10 and the timing TB20. The time from timing TB20 to timing TB30, from timing TB30 to timing TB40, and from timing TB40 to timing TB50 is the same as the time from timing TB10 to timing TB20.

Further, in the sensor 15 according to the first embodiment, the final pixel information Do is generated by using the difference between the dark level and the pixel signal as the value of the pixel signal. As a result, the sensor 15 according to the first embodiment outputs pixel information Do having a small noise level by removing noise superimposed on the dark level signal.

Further, the sensor 15 according to the first embodiment resets the vertical read line PIXOUT_R corresponding to the transfer switch 26 which is turned off during the period from the timing TB10 to the timing TB20. Specifically, by switching the reset control signal RST <1> and the selection signal SEL <1> from the low level to the high level during the injection period from the timing TB10 to the timing TB11, the floating diffusion FD of the pixel unit 23 on the first line is set. Set to dark level. Further, during the period from the timing TB12 to the timing TB20, the dark level in the pixel unit 23 on the first line is read out to the vertical read line PIXOUT_R.

Subsequently, during the period from the timing TB20 to the timing TB30, the vertical read line for reading the pixel signal and the vertical read line for resetting are replaced with the timing TB20 from the timing TB10, and the processing from the timing TB10 to the timing TB20 is performed. Do. Specifically, with the transfer switch 25 in the off state and the transfer switch 26 in the on state, the transfer to the dark level analog-to-digital conversion circuit 24 read by the vertical read line PIXOUT_R and the pixel unit in the first line. The electric charge is transferred from the photodiode PD0 to the floating diffusion FD in 23, and the pixel signal is read out to the vertical read line PIXOUT_R and the analog-to-digital conversion circuit 24. Further, in the pixel unit 23 on the 0th row, a reset process in which the floating diffusion FD in the pixel unit 23 on the 0th row is set to a dark level and a dark level read to the vertical read line PIXOUT_L are performed.

Subsequently, during the period from the timing TB30 to the timing TB40, the vertical read line for reading the pixel signal and the vertical read line for performing the reset process are replaced with the timing TB20 to the timing TB30, and the processing from the timing TB20 to the timing TB30 is performed. Do. Specifically, with the transfer switch 25 in the on state and the transfer switch 26 in the off state, transfer to the dark level analog-to-digital conversion circuit 24 read by the vertical read line PIXOUT_L, and the pixel unit on the 0th line. The electric charge is transferred from the photodiode PD1 to the floating diffusion FD in 23, and the pixel signal is read out to the vertical read line PIXOUT_R and the analog-to-digital conversion circuit 24. Further, in the pixel unit 23 of the first row, a reset process in which the floating diffusion FD in the pixel unit 23 of the first row is set as a dark level and a dark level read out to the vertical read line PIXOUT_R are performed.

Subsequently, during the period from the timing TB20 to the timing TB30, the vertical read line for reading the pixel signal and the vertical read line for resetting are replaced with the timing TB20 from the timing TB10, and the processing from the timing TB10 to the timing TB20 is performed. Do. Specifically, with the transfer switch 25 in the off state and the transfer switch 26 in the on state, the transfer to the dark level analog-to-digital conversion circuit 24 read by the vertical read line PIXOUT_R and the pixel unit in the first line. The electric charge is transferred from the photodiode PD0 to the floating diffusion FD in 23, and the pixel signal is read out to the vertical read line PIXOUT_R and the analog-to-digital conversion circuit 24. Further, in the pixel unit 23 on the 0th row, a reset process in which the floating diffusion FD in the pixel unit 23 on the 0th row is set to a dark level and a dark level read to the vertical read line PIXOUT_L are performed.

Subsequently, during the period from the timing TB40 to the timing TB50, the vertical read line for reading the pixel signal and the vertical read line for performing the reset process are replaced with the timing TB30 to the timing TB40, and the processing from the timing TB30 to the timing TB40 is performed. Do. Specifically, with the transfer switch 25 in the off state and the transfer switch 26 in the on state, the transfer to the dark level analog-to-digital conversion circuit 24 read by the vertical read line PIXOUT_L and the pixel unit in the first line The electric charge is transferred from the photodiode PD1 to the floating diffusion FD in 23, and the pixel signal is read out to the vertical read line PIXOUT_R and the analog-to-digital conversion circuit 24. Further, in the pixel unit 23 of the first row, a reset process in which the floating diffusion FD in the pixel unit 23 of the first row is set as a dark level and a dark level read out to the vertical read line PIXOUT_R are performed.

In the sensor 15 according to the first embodiment, the analog-to-digital conversion circuit 24 that has received the transfer of the dark level and the pixel signal converts the transferred signal level into a digital value and outputs the pixel output value DOUT. That is, in the sensor 15 according to the first embodiment, the timing control circuit (for example, the row controller 20) has a pixel unit and a transfer switch so that the reset process and the conversion output process are performed in parallel within one period. It controls 25, 26, and the analog-to-digital conversion circuit 24. Here, in the reset process, the reset target vertical read line connected to the transfer switch controlled in the cutoff state among the transfer switch 25 and the transfer switch 26, and the floating in the pixel unit connected to the reset target vertical read line. Reset the signal level of the diffusion to the dark level. Further, in the output conversion process, the dark level signal having a dark level output from the read target vertical read line connected to the transfer switch controlled to be conductive among the transfer switch 25 and the transfer switch 26 is converted to a digital value. Conversion, output of the pixel signal from the pixel unit connected to the read target vertical read line to the analog-to-digital conversion circuit, and conversion of the pixel signal to a digital value are performed.

The timing chart described with reference to FIG. 6 is an example, and another operation timing can be considered as the operation of the sensor 15. Therefore, FIG. 7 shows a timing chart for explaining a second operation example of the sensor 15 according to the first embodiment. In the example shown in FIG. 7, the reset timing of the floating diffusion FD in the pixel unit 23 connected to the vertical read line controlled in the off state is different from the example shown in FIG. Specifically, in the example shown in FIG. 7, the state is turned off at the timing of transferring the charge of the photodiode to the floating diffusion FD in the pixel unit 23 connected to the vertical readout line corresponding to the transfer switch turned on. The floating diffusion FD in the pixel unit 23 connected to the vertical read line corresponding to the transfer switch is reset. Further, in the example shown in FIG. 7, the off state is set at the timing of transferring the pixel signal from the inside of the pixel unit 23 connected to the vertical read line corresponding to the transfer switch to be turned on to the analog-to-digital conversion circuit 24. Performs vertical read reset processing corresponding to the transfer switch.

As described above, it is conceivable that the reset process for the vertical read line is performed at various timings, but there is also an unfavorable timing of the reset process. Therefore, as an unfavorable operation timing, FIG. 8 shows a timing chart for explaining a third operation example of the image sensor according to the first embodiment. In the example shown in FIG. 8, there is a rise timing of the reset control signal within the period for transferring the dark level read to the vertical read line corresponding to the transfer switch to be turned on to the analog-to-digital conversion circuit 24. Further, in the example shown in FIG. 8, the reset control signal is transferred within the period for transferring the pixel signal from the pixel unit 23 connected to the vertical read line corresponding to the transfer switch to be turned on to the analog-to-digital conversion circuit 24. There is a fall timing. In this way, if the logic level of the reset control signal RST or the like is switched within the period during which the signal to be converted is being transferred to the analog-to-digital conversion circuit 24, the current consumption in the sensor 15 is reduced to that of the analog-to-digital conversion circuit 24. The power supply noise increases as it increases during the conversion process. Such an increase in power supply noise has a problem of causing an error in the conversion processing result of the analog-digital conversion circuit 24. Therefore, in the sensor 15 according to the first embodiment, the row controller 20 is in a period other than the period during which the analog-to-digital conversion circuit is performing the analog-digital conversion process for converting the signal having the analog value into the digital value. Switches the logic level of the reset control signal that instructs the pixel unit to perform the reset operation.

Further, in the sensor 15 according to the first embodiment, the vertical read line reset process and the signal transfer process to the analog-to-digital conversion circuit 24 are not performed in parallel, and the vertical read line reset process and the vertical read line reset process are performed for each pixel unit. The signal transfer process to the analog-to-digital conversion circuit 24 can also be continuously performed. Therefore, FIG. 9 shows a timing chart for explaining a fourth operation example of the sensor 15 according to the first embodiment. In the example shown in FIG. 9, no operation is performed on the other pixel units until the reset processing of the vertical read line for the pixel unit to be read the pixel signal and the signal transfer processing to the analog-digital conversion circuit 24 are completed. Further, in the example shown in FIG. 9, a dark level readout to the vertical readout line and a transfer to the dark level analog-to-digital conversion circuit 24 are performed as one process. Therefore, in FIG. 9, the reading of the dark level analog-to-digital conversion circuit 24 is shown by DARK. Further, in the example shown in FIG. 9, the pixel signals are the photodiode PD0 of the pixel unit 23 in the 0th row, the photodiode PD0 of the pixel unit 23 in the 1st row, and the photodiode PD1 and 1 of the pixel unit 23 in the 0th row. The photodiode PD1 of the pixel unit 23 in the row is read out in this order. At this time, the vertical read line to which the pixel unit 23, which is not the target for reading the pixel signal, is connected is left blank.

Here, in the sensor 15 according to the first embodiment, the effect of shortening the read time when the reset process of the vertical read line and the signal transfer process to the analog-to-digital conversion circuit 24 are performed in parallel will be described.

First, as in the example shown in FIG. 9, when the dark level read to the vertical read line and the dark level transfer to the analog-digital conversion circuit 24 are performed as one process, the input of the analog-digital conversion circuit 24 is performed. The static time x (t) when the capacity is set to the dark level is shown in Eq. (1). Here, the statically indeterminate time is the time from the lowest voltage level (for example, the ground voltage) to 90% of the signal level assumed as the dark level. Further, in the following description, gm is connected to the transconductance of the amplification transistor 33, Rwire is the resistance value of the parasitic resistance of the vertical readout line, Cline is the capacitance value of the parasitic capacitance of the vertical readout line, and the resistor Ri is connected to the vertical readout line. Let the resistance value of the load resistance, C_ADC be the capacitance value of the input capacitance of the analog-digital conversion circuit 24, and t be the time.

On the other hand, as in the example shown in FIG. 6, when the dark level readout to the vertical readout line and the dark level transfer to the analog-digital conversion circuit 24 are performed as separate processes, the vertical readout line is defined as the dark level. The statically indeterminate time x_line (t) at the time of operation is shown in Eq. (2).

Further, as in the example shown in FIG. 6, when the dark level read to the vertical read line and the dark level transfer to the analog-digital conversion circuit 24 are performed as separate processes, the input of the analog-digital conversion circuit 24 is performed. The static time x_ADC (t) when the capacity is set to the dark level is shown in Eq. (3).

Comparing Eqs. (1) and (3), Eq. (3) has a smaller term related to the volume value of the molecule than Eq. (1). That is, when the dark level read to the vertical read line and the dark level transfer to the analog-to-digital conversion circuit 24 are performed in parallel and as separate processes, the time required for the dark level read within 1H time is shortened. be able to. Further, the static time x_line represented by the equation (2) is larger than the pixel signal read time, considering that the pixel signal is read while charging the parasitic capacitance of the vertical read line and the input capacitance of the analog-to-digital conversion circuit 24. You can see that it gets shorter. That is, in the sensor 15 according to the first embodiment, the dark level readout to the vertical readout line and the dark level transfer to the analog-to-digital conversion circuit 24 are performed in parallel and as separate processes to the vertical readout line. The 1H time can be shortened as compared with the case where the reading of the dark level and the transfer of the dark level to the analog-to-digital conversion circuit 24 are executed as one process.

From the above description, in the sensor 15 according to the first embodiment, the pixel units arranged in the same row are classified into two groups. Then, in the sensor 15 according to the first embodiment, an analog-to-digital conversion process for reading a dark level and a pixel signal output from a pixel unit belonging to one group to an analog-to-digital conversion circuit 24 and a pixel unit belonging to the other group are used. The reset process that resets the corresponding vertical read line at the output dark level is performed in parallel. Further, in the sensor 15 according to the first embodiment, the analog-to-digital conversion process and the reset process are alternately performed between the two groups. As a result, in the sensor 15 according to the first embodiment, the voltage of the vertical readout line is set to the dark level before the dark level output from the pixel unit belonging to one group is transferred to the analog-to-digital conversion circuit 24. Therefore, the dark level transfer time to the analog-to-digital conversion circuit 24 can be shortened. Further, in the sensor 15 according to the first embodiment, the analog-to-digital conversion process and the reset process are performed in parallel to perform the analog-to-digital conversion process within 1 H time required for reading the pixel signal for one pixel. It is possible to shorten the 1H time as close as possible to the time required for.

That is, in the sensor 15 according to the first embodiment, the time required for reading the pixel signal of one pixel can be shortened. Further, in the sensor 15 according to the first embodiment, the reading time of the pixel signal for one pixel can be shortened, so that the number of pixels that can be read within a predetermined period can be increased. According to the study by the inventors, when the dark level read to the vertical read line and the dark level transfer to the analog-to-digital conversion circuit 24 are performed in parallel and as separate processes, the dark level read to the vertical read line is performed. It has been confirmed that there is a time saving effect of about 10 to 20% as compared with the case where the dark level transfer to the analog-to-digital conversion circuit 24 is performed as one process.

Further, when considering increasing the reading speed of the pixel signal, it is conceivable to convert the pixel signals read from different pixel units in parallel using a plurality of analog-to-digital conversion circuits. However, in this case, there arises a problem that the number of analog-to-digital conversion circuits per row increases. On the other hand, in the sensor 15 according to the first embodiment, one analog-to-digital conversion circuit 24 is provided for one row of pixel units. Therefore, the sensor 15 according to the first embodiment can realize an increase in the reading speed of the pixel signal without increasing the circuit scale. In particular, since the number of pixels of the sensor 15 has increased in recent years and the demand for suppressing the circuit scale has increased, the effect of increasing the read speed without increasing the circuit scale is great.

Embodiment 2
In the second embodiment, the pixel unit 23a, which is another form of the pixel unit 23, will be described. The pixel unit 23a is a pixel unit including two photodiodes. Further, in the second embodiment, the sensor 15 including the pixel unit 23a is referred to as a sensor 15a. Therefore, FIG. 10 shows a block diagram of the sensor 15a according to the second embodiment.

As shown in FIG. 10, the sensor 15a according to the second embodiment has a pixel array 22a in which the pixel units 23a are arranged in a grid pattern. The pixel unit 23a according to the second embodiment has two photodiodes per pixel unit. Therefore, in the pixel array 22a according to the second embodiment, the color filters are Bayer-arranged by using the pixel units for two adjacent rows. Further, also in the sensor 15a according to the second embodiment, two vertical read lines are provided for one row of pixel units.

Subsequently, the circuit of the pixel unit 23a according to the second embodiment will be described. Therefore, FIG. 11 shows a circuit diagram of the pixel unit 23a in the sensor 15a according to the second embodiment. As shown in FIG. 11, the pixel unit 23a according to the second embodiment has two diodes, the photodiodes PD0 and PD1. That is, the pixel unit 23a is obtained by removing the photodiodes PD2 and PD3 and the transfer transistors 312 and 313 from the pixel unit 23 according to the first embodiment.

Since the operation when the pixel unit 23a according to the second embodiment is used is substantially the same as the operation of the timing chart shown in FIG. 6, description thereof will be omitted here.

From the above description, even if the number of photodiodes included in the pixel unit 23 according to the first embodiment is reduced, the pixel signal reading speed can be increased as in the pixel unit 23 according to the first embodiment. I understand.

Embodiment 3
In the third embodiment, the pixel unit 23b, which is another form of the pixel unit 23, will be described. The pixel unit 23b is a pixel unit including one photodiode. Further, in the third embodiment, the sensor 15 including the pixel unit 23b is referred to as a sensor 15b. Therefore, FIG. 12 shows a block diagram of the sensor 15b according to the third embodiment.

As shown in FIG. 10, the sensor 15b according to the third embodiment has a pixel array 22b in which pixel units 23b are arranged in a grid pattern. In the pixel unit 23b according to the third embodiment, the number of photodiodes per pixel unit is one. Therefore, in the pixel array 22b according to the third embodiment, the color filters are Bayer-arranged by using the pixel units for two rows and two columns adjacent to each other. Further, also in the sensor 15b according to the third embodiment, two vertical read lines are provided for one row of pixel units.

Subsequently, the circuit of the pixel unit 23b according to the third embodiment will be described. Therefore, FIG. 13 shows a circuit diagram of the pixel unit 23b in the sensor 15b according to the third embodiment. As shown in FIG. 13, the pixel unit 23b according to the third embodiment has one diode of the photodiode PD. That is, the pixel unit 23b is obtained by removing the photodiodes PD1, PD2, PD3, and transfer transistors 311, 312, and 313 from the pixel unit 23 according to the first embodiment.

Subsequently, the operation of the pixel unit 23b according to the third embodiment will be described. Therefore, FIG. 14 shows a timing chart for explaining an operation example of the image pickup device according to the third embodiment. As shown in FIG. 14, in the sensor 15b according to the third embodiment, the first line is during the period in which the dark level and the pixel signal output from the pixel unit 23b on the 0th line are transferred to the analog-to-digital conversion circuit 24. The vertical readout line PIXOUT_L to which the pixel unit 23b of the above is connected is reset to a dark level. Further, in the sensor 15b according to the first embodiment, the pixel unit 23b of the second line is connected during the period in which the dark level and the pixel signal output from the first line are transferred to the analog-digital conversion circuit 24. Reset the vertical readout line PIXOUT_R to dark level. As described above, in the sensor 15b according to the third embodiment, the vertical read line for transferring the dark level and the pixel signal to the analog-digital conversion circuit 24 and the vertical read line PIXOUT_R and the vertical read line PIXOUT_L for resetting are Pixel signal reading processing is performed while switching between.

From the above description, even if the number of photodiodes included in the pixel unit 23 according to the first embodiment is reduced, the pixel signal reading speed can be increased as in the pixel unit 23 according to the first embodiment. I understand.

Embodiment 4
In the fourth embodiment, the pixel unit 23c, which is another form of the pixel unit 23, will be described. The pixel unit 23c is a pixel unit in which two photodiodes are used to form a light receiving element for one pixel, and the pixel unit 23c includes two light receiving elements. Further, in the fourth embodiment, the sensor 15 including the pixel unit 23c is referred to as a sensor 15c. Therefore, FIG. 15 shows a block diagram of the sensor 15c according to the fourth embodiment.

As shown in FIG. 15, the sensor 15c according to the fourth embodiment has a pixel array 22c in which the pixel units 23c are arranged in a grid pattern. The pixel unit 23c according to the fourth embodiment has two photodiodes per pixel unit. Therefore, in the pixel array 22c according to the fourth embodiment, the color filters are Bayer-arranged by using the pixel units for two adjacent rows. Further, also in the sensor 15c according to the fourth embodiment, two vertical read lines are provided for one row of pixel units. The photodiode included in the pixel unit 23c includes two photodiodes.

Subsequently, the configuration of the vertical read line and the transfer switch of the sensor 15c according to the fourth embodiment will be described. Therefore, FIG. 16 shows a block diagram illustrating a configuration of a vertical read line and a transfer switch of the sensor 15c according to the fourth embodiment. In addition, in FIGS. 16 to 18, the row number and the column number in which the pixel unit 23 is arranged are shown in parentheses.

As shown in FIG. 16, in the pixel unit 23c according to the fourth embodiment, in addition to the vertical read line PIXOUT_L or the vertical read line PIXOUT_R corresponding to the arranged row, the vertical read line PIXOUT_L or the vertical read line of the adjacent row It is also connected to PIXOUT_R. That is, in the sensor 15c according to the fourth embodiment, the vertical read lines are shared by adjacent columns. This is because one light receiving element in the pixel unit 23 is composed of two photodiodes, and the pixel signals generated by the two photodiodes are individually read out.

Subsequently, the circuit of the pixel unit 23c according to the fourth embodiment will be described. Therefore, FIG. 17 shows a circuit diagram of the pixel unit 23c in the sensor 15c according to the fourth embodiment. In the example shown in FIG. 17, four pixel units 23c for two rows and two columns are shown. Further, as shown in FIG. 17, in the sensor 15c according to the first embodiment, the photodiodes PD0 and PD1 are arranged in the pixel units 23c arranged in the even-numbered rows, and the photodiodes are arranged in the pixel units 23c arranged in the odd-numbered rows. PD2 and PD3 are arranged. Each photodiode is composed of a left pixel photodiode PDx_L (x is a value indicating a photodiode number) constituting the left pixel and a right pixel photodiode PDx_R constituting the right pixel.

Further, in the example shown in FIG. 17, the pixel signal of the left pixel of the photodiode of the pixel unit 23c is generated by the amplification transistor 33 provided corresponding to the right pixel of the pixel unit 23c arranged in the row having the column number one smaller. Read out. That is, in the sensor 15c according to the fourth embodiment, the set of vertical readout lines is the right pixel photodiode of the pixel unit arranged in the nth row and the left side of the pixel unit arranged in the n + 1th row, respectively. It is shared by the pixel photodiode. As for the pixel unit 23c arranged in the 0th row, since there is no column whose column number is one smaller, the amplification transistor 33 is provided for the left pixel.

Further, in the example shown in FIG. 17, the transfer transistor 510 is provided corresponding to the photodiode PD0_L. A transfer transistor 511 is provided corresponding to the photodiode PD0_R. A transfer transistor 512 is provided corresponding to the photodiode PD1_L. A transfer transistor 513 is provided corresponding to the photodiode PD1_R. A transfer transistor 514 is provided corresponding to the photodiode PD2_L. A transfer transistor 515 is provided corresponding to the photodiode PD2_R. A transfer transistor 516 is provided corresponding to the photodiode PD3_L. A transfer transistor 516 is provided corresponding to the photodiode PD3_R. The configuration of the reset transistor 32, the amplification transistor 33, and the selection transistor 34 in the pixel unit 23c is substantially the same as that of the pixel unit described with reference to FIG. 4 and the like.

Here, the structure of the photodiode of the sensor 15c according to the fourth embodiment will be described. Therefore, FIG. 18 shows a cross-sectional view illustrating the structure of the photodiode of the sensor 15c according to the fourth embodiment. As shown in FIG. 18, in the pixel unit 23c, the P-well layer 62 is formed on the upper layer of the N-sub layer 61, and the photodiodes PD0_L and PD0_R are formed on the surface of the P-well layer 62. A wiring layer on which the wirings 63 to 65 are formed is provided on the upper layer of the substrate layer composed of the N-sub layer 61 and the P-well layer 62. The microlens in the pixel unit 23c is formed on the upper layer of the wiring layer. In the microlens layer on which the microlens is formed, the microlens 67 is formed on the upper layer of the color filter 66. Then, as shown in FIG. 18, in the pixel unit 23c, the microlens 67 is formed so as to cover the photodiode pair.

Subsequently, the operation of the sensor 15c according to the fourth embodiment will be described. Therefore, FIG. 19 shows a timing chart for explaining an operation example of the sensor 15c according to the fourth embodiment. Note that FIG. 19 shows only the signals read by the vertical readout line during operation of the sensor 15c, and the transition of the logic level of various control signals is omitted. The transition of the logic level of various control signals shall be in accordance with that described in the first embodiment.

As shown in FIG. 19, in the sensor 15c according to the fourth embodiment, when one vertical read line is viewed, a reset operation by a dark level output from a pixel unit connected to each vertical read line (in the figure). "Preparation for reading") and the operation of transferring the dark level and pixel signals output from the pixel unit to the analog-to-digital conversion circuit 24 ("reading execution" in the figure) are repeatedly performed. Looking between the vertical read lines belonging to the same column, the read execution process for the pixel unit 23c arranged on one of the even and odd rows and the pixel unit 23c arranged on the other of the even and odd rows Read preparation and read preparation are performed in parallel. Looking at the vertical readout line shared with the pixel unit 23c in the row with the column number one smaller, the usage period by the pixel unit 23c in the row with the column number one smaller and the usage period by the pixel unit 23c belonging to the own row Can be seen to be continuous.

By sharing the vertical readout line between adjacent columns in this way, the number of analog-to-digital conversion circuits 24 even when one photodiode in the pixel unit 23c is composed of a right pixel and a left pixel. Can be avoided.

Further, by using the pixel unit 23c in which one photodiode PD is composed of two photodiodes, image feature information DCI used for autofocus processing can be generated. Therefore, a method of generating pixel information Do and a method of generating image feature information DCI in the sensor 15c according to the fourth embodiment will be described below.

FIG. 20 shows a flowchart illustrating an image information output process in the sensor 15c according to the fourth embodiment. As shown in FIG. 20, in the sensor 15c according to the fourth embodiment, the pixel information of the right pixel and the left pixel is individually read from the pixel array 22c (step S1). After that, in the sensor 15c according to the fourth embodiment, the pixel information of the right pixel and the pixel information of the left pixel are combined and one pixel information Do is output (step S2). By synthesizing the pixel information of the right pixel and the pixel information of the left pixel in the sensor 15c in this way, the sensor 15c outputs one pixel information Do.

FIG. 21 shows a flowchart for explaining the output processing of the image feature information DCI in the sensor 15c according to the fourth embodiment. As shown in FIG. 21, in the sensor 15c according to the fourth embodiment, the pixel information of the right pixel and the left pixel is individually read from the pixel array 22c (step S11). After that, the sensor 15c according to the fourth embodiment outputs the edge information of the image obtained from the pixel information of the right pixel and the edge information of the image obtained from the pixel information of the left pixel as image feature information DCI, respectively ( Step S12).

Here, the image feature information DCI will be described in more detail. First, FIG. 22 shows a diagram illustrating the principle of phase difference autofocus in the sensor 15c according to the fourth embodiment. FIG. 22 shows the positional relationship between the evaluation surface (for example, the image surface) formed on the sensor surface and the focal surface on which the image of the light incident from the focus lens is in focus.

As shown in FIG. 22, when the focus is aligned, the focal plane in which the image of the light incident from the focus lens is in focus coincides with the image plane (upper view of FIG. 22). On the other hand, when the focus is off, the focal plane in which the image of the light incident from the focus lens is in focus is formed at a position different from the image plane (lower figure of FIG. 22). The amount of deviation between the focal plane and the image plane is the defocus amount.

Here, an image formed on the image plane when the focus shift occurs will be described. Therefore, FIG. 23 shows a graph for explaining the output of the photodiode when the focus shift occurs. In FIG. 23, the horizontal axis shows the image height indicating the distance of the pixel unit 23c from the lens center axis, and the vertical axis shows the magnitude of the output of the pixel unit 23c.

As shown in FIG. 23, when the focus is off, the signal output from the left pixel and the signal output from the right pixel are shifted in the image height direction. This image shift amount is proportional to the defocus amount. Therefore, in the camera system 1 using the sensor 15c according to the fourth embodiment, the defocus amount is calculated based on the image shift amount to determine the position of the focus lens 14.

In the autofocus process of the camera system 1 using the sensor 15c according to the fourth embodiment, the output signals output from all the pixel units arranged in the pixel array 22c of the sensor 15c are matched between the left pixel and the right pixel. The position of the focus lens 14 is controlled. Further, in the camera system 1 using the sensor 15c according to the fourth embodiment, the position of the focus lens 14 is controlled based on the image feature information DCI output from the sensor 15c by the system control MCU 19.

From the above description, the image feature information DCI used for the autofocus process can be generated by using the sensor 15c according to the fourth embodiment. Then, in the camera system 1 using the sensor 15c according to the fourth embodiment, the autofocus process based on the image feature information DCI can be performed. Further, in the sensor 15c according to the fourth embodiment, while adding a function of generating the image feature information DCI, the increase in the circuit scale is avoided and the pixel signal reading speed is increased as in the first embodiment. can do.

Embodiment 5
In the fifth embodiment, the pixel array 22d including the pixel unit 23d and the pixel unit 23d, which are different forms of the pixel unit 23, will be described. The pixel array 22d has a function of switching whether the floating diffusions of different pixel units 23d arranged in the same row are treated as one common floating diffusion or treated as independent floating diffusions for each pixel unit. Further, in the fifth embodiment, the sensor 15 including the pixel unit 23d is referred to as a sensor 15d. Therefore, FIG. 24 shows a block diagram of the sensor 15d according to the fourth embodiment.
As shown in FIG. 24, the sensor 15d according to the fifth embodiment has a pixel array 22d in which the pixel units 23d are arranged in a grid pattern. The pixel unit 23d according to the fifth embodiment has two photodiodes per pixel unit. Therefore, in the pixel array 22d according to the fifth embodiment, the color filters are Bayer-arranged by using the pixel units for two adjacent rows. Further, also in the sensor 15d according to the fifth embodiment, two vertical read lines are provided for one row of pixel units.
Further, as shown in FIG. 24, the pixel unit 23d has two transfer control signals TX (TX0 and TX1 in FIG. 24), a reset control signal RST, and two selection signals SEL (SEL_L and SEL_R in FIG. 24), respectively. , Power supply wiring In addition to VDD_PX, a local FD control signal FDSWL and a global FD control signal FDSWG are given.

Subsequently, a specific circuit configuration of the pixel array 22d according to the fifth embodiment will be described. Therefore, FIG. 25 shows a block diagram illustrating the circuit configuration of the pixel array 22d according to the fifth embodiment. As shown in FIG. 25, in 15d according to the fifth embodiment, the configuration of the column controller 21 is the same as that of the first embodiment, for example. On the other hand, the pixel array 22d is different from other embodiments in that a floating diffusion common switching circuit 232 for switching the configuration in the arranged pixel unit and whether or not the floating diffusion in the pixel unit is shared is added. different.

Each of the pixel units 23d has an output wiring switching circuit 231. The output wiring switching circuit 231 is provided in place of the selection transistor 34. The output wiring switching circuit 231 transfers the output signal of the first amplification transistor (for example, the amplification transistor 33 in the own pixel unit) to the first vertical read wiring (for example, the vertical read line PIXOUT_L) and the second vertical read wiring (for example, the vertical read wiring PIXOUT_L). For example, it is switched to which of the vertical read line PIXOUT_R) is output.

The floating diffusion common switching circuit 232 switches whether the floating diffusion in the pixel unit to be shared is used in common among the pixel units to be shared or used as an individual floating diffusion. Specifically, assuming that the floating diffusion included in one of the pixel units to be shared is the first floating diffusion and the second floating diffusion included in the other, it is considered as follows. The floating diffusion common switching circuit 232 switches whether the first floating diffusion and the second floating diffusion are shared or made independent.

Subsequently, a specific circuit of the pixel unit 23d and the floating diffusion common switching circuit 232 according to the fifth embodiment will be described. Therefore, FIG. 26 shows a circuit diagram of the pixel unit 23d and the floating diffusion common switching circuit 232 in the image pickup device according to the fifth embodiment.

As shown in FIG. 26, the pixel unit 23d replaces the selection transistor 34 of the pixel unit 23a described in the second embodiment with the output wiring switching circuit 231. Further, the output wiring switching circuit 231 has a selection transistor 34 and a selection transistor 35. The analog-to-digital conversion circuit 24 is provided between the source of the amplification transistor 33 and the vertical readout line PIXOUT_L. The conduction state of the selection transistor 34 is controlled by the selection signal SEL_L. The selection transistor 35 is provided between the source of the amplification transistor 33 and the vertical readout line PIXOUT_R. The conduction state of the selection transistor 35 is controlled by the selection signal SEL_R.

The floating diffusion common switching circuit 232 includes a local switch transistor 36 and a global switch transistor 37. The local switch transistor 36 connects the floating diffusion of the corresponding pixel unit 23d to the source of the global switch transistor 37. The global switch transistor 37 is connected to the source of the global switch transistor 37 of the floating diffusion common switching circuit 232 whose drain is arranged corresponding to the pixel unit 23d in the row one row above. The source of the global switch transistor 37 of the floating diffusion common switching circuit 232 provided corresponding to the pixel unit 23d on the 0th row of the floating diffusion common switching circuit 232 is connected to the drain of the global wiring reset transistor. This global wiring reset transistor is provided between the source of the global switch transistor 37 of the floating diffusion common switching circuit 232 provided corresponding to the pixel unit on the 0th line and the power supply wiring VDD_PX. Further, the conduction state of the global wiring reset transistor is controlled by the global FD reset control signal FDGRST.

The image sensor 15d according to the fifth embodiment has, in addition to the first operation mode in which the normal pixel read-out process is performed, a second operation mode in which the pixel read-out process is performed after the intra-pixel synthesis process. Therefore, the unit of the pixel unit to be read out for each operation mode will be described.

First, FIG. 27 shows a block diagram showing a configuration of a pixel unit in the first operation mode of the image sensor according to the fifth embodiment. As shown in FIG. 27, in the first operation mode in which one pixel unit is one read unit, the floating diffusion common switching circuit 232 is disabled, and the floating diffusion in each pixel unit is used independently. .. Further, the output wiring switching circuit 231 in the pixel unit 23d arranged in even-numbered rows outputs a signal output from the pixel unit to the vertical read line PIXOUT_L. The output wiring switching circuit 231 in the pixel unit 23d arranged in the odd-numbered lines outputs a signal output from the pixel unit to the vertical read line PIXOUT_R.

Subsequently, FIG. 28 is shown in a block diagram showing the configuration of the pixel unit in the second operation mode of the image pickup device according to the fifth embodiment. As shown in FIG. 28, in the second operation mode, the pixel units arranged in the odd-numbered rows and the pixel units arranged in the even-numbered rows in the first operation mode are used as one pixel unit. The second operation mode also enables the floating diffusion common switching circuit 232 in which the pixel units combined as one pixel unit are arranged between the two pixel units. As a result, the floating diffusion in the pixel units combined as one pixel unit is standardized. Then, in the second operation mode, for example, the pixel units whose physical arrangements are the 0th row and the 1st row are combined to form the composite pixel unit of the 0th row after the synthesis, and the physical arrangements are the 2nd row and the 3rd row. The pixel units in the first row are combined to form the composite pixel unit in the first row after synthesis. Further, the output wiring switching circuit 231 of the composite pixel unit whose line number after the combination is an even number outputs the output of the amplification transistor 33 to the vertical read line PIXOUT_L. The output wiring switching circuit 231 of the composite pixel unit whose line number after the combination is an odd number outputs the output of the amplification transistor 33 to the vertical read line PIXOUT_R.

That is, in the image sensor 15d according to the fifth embodiment, in the second operation mode, the first composite pixel unit and the second composite pixel unit each have at least two composite target pixel units (for example, FIG. 28). Floating diffusion common switching circuit that switches whether the two pixel units 23d) included in the pixel units belonging to each row and the floating diffusions in the plurality of synthesis target pixel units share or make the synthesis target pixel units common to each other. It has 232 and. On the other hand, the image sensor 15d according to the fifth embodiment controls the synthesis target pixel unit as an independent pixel unit in the first operation mode.

Further, in the image pickup element 15d according to the fifth embodiment, the plurality of synthesis target pixel units are each of a light receiving element (for example, photodiodes PD0 and PD1) and a transfer transistor (for example, a transfer transistor) provided corresponding to the light receiving element. The transfer transistor 310, 311), the floating diffusion FD and amplification transistor 33 provided for the transfer transistor, and the output signal of the amplification transistor 33 are connected to the first vertical read wiring (for example, vertical read line PIXOUT_L) and the second vertical. It has an output wiring switching circuit 231 for switching which output is output to the read wiring (for example, the vertical read line PIXOUT_R).

Then, in the image pickup element 15d according to the fifth embodiment, the timing control circuit (for example, the row controller 20) makes the floating diffusion in the plurality of synthesis target pixel units independent of the floating diffusion common switching circuit 232. In the first operation mode to be instructed, the wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit 231 in the pixel unit to be combined, which is on the even line, is the vertical read wiring PIXOUT_L, and the composition is on the odd line. An instruction is given to the output wiring switching circuit 231 in the target pixel unit so that the wiring that outputs the output signal of the amplification transistor becomes the vertical read wiring PIXOUT_R. Further, in the second operation mode, the timing control circuit (for example, the row controller 20) instructs the floating diffusion common switching circuit 231 to share the floating diffusion in the plurality of synthesis target pixel units. The wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit 231 of the synthesis target pixel unit belonging to the first synthesis pixel unit arranged in the odd line after synthesis becomes the vertical read wiring PIXOUT_L, and the odd line after synthesis An instruction is given to the output wiring switching circuit 231 of the synthesis target pixel unit belonging to the second synthesis pixel unit arranged in the eye so that the wiring for outputting the output signal of the amplification transistor becomes the vertical read wiring PIXOUT_R.

Subsequently, the operation of the image pickup device 15d according to the fifth embodiment will be described using a timing chart. In the operation of the first operation mode of 15d according to the first embodiment, for example, by setting both the local FD control signal FDSWL and the global FD control signal FDSWG to a low level, the image sensor 15a according to the second embodiment can be operated. Since the operation is the same as the operation, the description of the first operation mode will be omitted here. Therefore, FIG. 29 shows a timing chart for explaining an operation example of the image pickup device according to the fifth embodiment in the second operation mode.

As shown in FIG. 29, in the second operation mode, the local FD control signals FDSWL <0> and FDSWL <1>, the global FD control signals FDSWG <0>, and the selection signals SEL_L <0> and SEL_L <1> are used. The high level and the low level are switched according to the output timing from the composite pixel unit, and the global FD control signal FDSWG <1> and the selection signals SEL_R <0> and SEL_R <1> are maintained at the low level. Further, the local FD control signals FDSWL <2>, FDSWL <3>, global FD control signals FDSWG <2>, and selection signals SEL_R <2> and SEL_R <3> are set at a high level according to the output timing from the composite pixel unit. And the low level are switched, and the global FD control signal FDSWG <3> and the selection signals SEL_L <2> and SEL_L <3> are maintained at the low level. By performing such control, the image sensor 15d according to the fifth embodiment has the circuit configuration shown in FIG. 28, and performs the same reading operation as the image sensor 15d according to the second embodiment. Further, in the image sensor according to the fifth embodiment, the signals output to the vertical readout lines PIXPOUT_L and PIXOUT_R are obtained by synthesizing the signals generated by the two photodiodes in the two pixel units to be combined.

From the above description, in the image sensor 15d according to the fifth embodiment, one composite pixel unit is configured by the two synthesis target pixel units, and the floating diffusion in the two synthesis target pixel units is shared. Then, in the image pickup device 15d according to the fifth embodiment, the signals generated by the two photodiodes in the two synthesis target pixel units are combined in the synthesis pixel unit and then output to the vertical readout line. As a result, the image sensor 15d according to the fifth embodiment can increase the S / N ratio of the signal generated in the pixel array 22d.

Further, in the image pickup device 15d according to the fifth embodiment, by having the output wiring switching circuit 231 in the pixel unit, the color of the color filter corresponding to the signal transmitted for each vertical readout line can be fixed. Therefore, the correspondence between the color of the color filter and the vertical readout line for transmitting the signal will be described. FIG. 30 shows a diagram illustrating a modified example of the read operation in the first operation mode of the image sensor according to the fifth embodiment. In the example shown in FIG. 30, the operation in the first operation mode is described, but the same operation is possible in the second operation mode.

As shown in FIG. 30, the image sensor 15d according to the fifth embodiment is used for signal output at the first read timing and the second read timing even when a signal is output from the same pixel unit. Switch the selected transistor. Thereby, for example, an image sensor that outputs the output signal corresponding to the red color filter via the vertical readout line PIXOUT_R can be configured.

Although the invention made by the present inventor has been specifically described above based on the embodiments, the present invention is not limited to the embodiments already described, and various changes can be made without departing from the gist thereof. It goes without saying that it is possible.

1 Camera system 11 Zoom lens 12 Aperture mechanism 13 Fixed lens 14 Focus lens 15, 15a, 15b, 15c Sensor 16 Zoom lens actuator 17 Focus lens actuator 18 Signal processing circuit 19 System control MCU
20 Row controller 21 Column controller 22, 22a, 22b, 22c, 22d Pixel array 23, 23a, 23b, 23c, 23d Pixel unit 24 Analog digital conversion circuit 25, 26 Transfer switch 310-313 Transfer transistor 32 Reset transistor 33 Amplification transistor 34 Selective transistor 35 Selective transistor 36 Local switch transistor 37 Global switch transistor 231 Output wiring switching circuit 232 Floating diffusion common switching circuit 41 Reference voltage generation circuit 42 Control signal generation circuit 43 Lamp signal generation circuit 510-517 Transfer transistor 61 N sublayer 62 P Well layer 63-65 Wiring 66 Color filter 67 Microlens PD0 to PD4 Photo diode FD Floating diffusion Cline_L, Cline_R Wiring capacity Rware_L, Rwire_R Wiring resistance Ri_L, Ri_R resistance Ipx_L, Ipx_R Pixel current source PIXOUT_R Pixel output value TX Transfer control signal RST Reset control signal SEL selection signal LINE_SEL_L, LINE_SEL_R Read line selection signal VDD_PX Power supply wiring FDSWL Local FD control signal FDSWG Global FD control signal

Claims (11)

A pixel array that has multiple pixel units in an array,
A first pixel unit included in the pixel array and a second pixel unit arranged in the same row as the first pixel unit,
With the first floating diffusion provided in the first pixel unit,
With the second floating diffusion provided in the second pixel unit,
A first vertical readout line connected to the first pixel unit,
A second vertical readout line connected to the second pixel unit,
A first transfer switch provided at one end of the first vertical read line and
A second transfer switch provided at one end of the second vertical read line and
An analog-to-digital conversion circuit that outputs a digital value corresponding to any one of the signal levels of the signal input via the first transfer switch and the second transfer switch.
A timing control circuit that controls the operation timing of the first and second pixel units, the first and second transfer switches, and the analog-to-digital conversion circuit.
Have,
The timing control circuit is within the conversion processing period for one pixel.
When the first transfer switch is turned off, the signal levels of the first floating diffusion and the first vertical readout line are reset to dark levels.
Before the dark level signal is set to said second vertical read lines in the conversion processing period, through the second SL prior to the transfer switch in a conducting state the second floating diffusion and the second vertical read lines An image pickup device that sequentially feeds a pixel signal of the second pixel unit to be transferred to the analog-to-digital conversion circuit. The timing control circuit
When the second transfer switch is made conductive, before transferring the pixel signal of the second pixel unit to the analog-to-digital conversion circuit,
The image pickup device according to claim 1, wherein the dark level of the second floating diffusion and the second vertical readout line is transferred to the analog-to-digital conversion circuit. It has a first and second composite pixel unit provided in place of the first pixel unit and the second pixel unit, and the first composite pixel unit and the second composite pixel unit are each provided.
At least two pixel units to be combined and
It has a floating diffusion in a plurality of pixel units to be combined and a floating diffusion common switching circuit for switching whether the pixel units to be combined are shared or independent.
The plurality of pixel units to be combined are each
With the light receiving element
A transfer transistor provided corresponding to the light receiving element and
Floating diffusion and amplification transistors provided for the transfer transistor, and
It has an output wiring switching circuit for switching whether the output signal of the amplification transistor is output to the first vertical read wiring or the second vertical read wiring.
The timing control circuit
In the first operation mode in which the floating diffusion common switching circuit is instructed to make the floating diffusion in the plurality of synthesis target pixel units independent.
The wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit in the synthesis target pixel unit on the even-numbered line becomes the first vertical read wiring.
An instruction is given to the output wiring switching circuit in the synthesis target pixel unit on the odd-numbered line so that the wiring that outputs the output signal of the amplification transistor becomes the second vertical read wiring.
In the second operation mode in which the floating diffusion common switching circuit is instructed to make the floating diffusion in the plurality of synthesis target pixel units common.
The wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit of the synthesis target pixel unit belonging to the first synthesis pixel unit becomes the first vertical read wiring.
The first aspect of claim 1 is instructing the output wiring switching circuit of the synthesis target pixel unit belonging to the second synthesis pixel unit so that the wiring that outputs the output signal of the amplification transistor becomes the second vertical read wiring. The image pickup device described. The first pixel unit connected to the first vertical readout line and
A second pixel unit connected to the second vertical readout line and arranged in the same row as the first pixel unit.
A first transfer switch provided at one end of the first vertical read line and
A second transfer switch provided at one end of the second vertical read line and
An analog-to-digital conversion circuit that outputs a digital value according to the signal level of a signal input via the first transfer switch and the second transfer switch.
It has the first and second pixel units, the first and second transfer switches, and a timing control circuit that controls the operation timing of the analog-to-digital conversion circuit.
The timing control circuit
Within the pixel unit connected to the reset target vertical read line connected to one of the first transfer switch and the second transfer switch controlled to the cutoff state, and the reset target vertical read line. Floating diffusion, reset processing to reset the signal level to dark level,
To the digital value of the dark level signal having a dark level output from the read target vertical read line connected to the other transfer switch controlled to be conductive among the first transfer switch and the second transfer switch. a first conversion processing for converting an output of the pixel signal from the pixel unit connected to the read-target vertical read-out line to the analog-to-digital converter, and a second to convert to a digital value of the pixel signal Conversion processing that performs conversion processing and conversion output processing
An image pickup device that controls the first and second pixel units, the first and second transfer switches, and the analog-to-digital conversion circuit so that the above can be performed in parallel within one period. The timing control circuit
A claim for switching the logic level of a reset control signal that instructs the pixel unit to perform the reset process during a period other than the period during which the analog-to-digital conversion circuit converts a signal having an analog value into a digital value. The imaging element according to 4. The first and second pixel units include a plurality of light receiving elements, a plurality of transfer transistors provided corresponding to the light receiving elements, and floating diffusion and amplification transistors commonly provided for the plurality of transfer transistors. Have,
The timing control circuit
4. Claim 4 that controls the transfer transistor in the first pixel unit and the second pixel unit so that the pixel signals are alternately output from the first pixel unit and the second pixel unit. The image pickup device according to. The first and second pixel units include a right photoelectric conversion element and a left photoelectric conversion element arranged adjacent to each other under one microlens as one light receiving element.
The first and second vertical readout lines are shared by the right photoelectric conversion element of the pixel unit arranged in the nth row and the left photoelectric conversion element of the pixel unit arranged in the n + 1 row, respectively. The image pickup device according to claim 4. The image pickup device according to claim 4, wherein each of the first vertical read line and the second vertical read line is provided with a pixel current source that draws a current from the corresponding read line. The analog-to-digital conversion circuit has an input terminal commonly provided for the first transfer switch and the second transfer switch.
The conversion of the dark level signal input via the first transfer switch to a digital value, the conversion of the pixel signal to a digital value, and the digital conversion of the dark level signal input via the second transfer switch. The imaging device according to claim 4, wherein conversion to a value and conversion of the pixel signal to a digital value are alternately performed. It has a first and second composite pixel unit provided in place of the first pixel unit and the second pixel unit, and the first composite pixel unit and the second composite pixel unit are each provided.
At least two pixel units to be combined and
It has a floating diffusion in a plurality of pixel units to be combined and a floating diffusion common switching circuit for switching whether the pixel units to be combined are shared or independent.
The plurality of pixel units to be combined are each
With the light receiving element
A transfer transistor provided corresponding to the light receiving element and
Floating diffusion and amplification transistors provided for the transfer transistor, and
It has an output wiring switching circuit for switching whether the output signal of the amplification transistor is output to the first vertical read wiring or the second vertical read wiring.
The timing control circuit
In the first operation mode in which the floating diffusion common switching circuit is instructed to make the floating diffusion in the plurality of synthesis target pixel units independent.
The wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit in the synthesis target pixel unit on the even-numbered line becomes the first vertical read wiring.
An instruction is given to the output wiring switching circuit in the synthesis target pixel unit on the odd-numbered line so that the wiring that outputs the output signal of the amplification transistor becomes the second vertical read wiring.
In the second operation mode in which the floating diffusion common switching circuit is instructed to make the floating diffusion in the plurality of synthesis target pixel units common.
The wiring that outputs the output signal of the amplification transistor to the output wiring switching circuit of the synthesis target pixel unit belonging to the first synthesis pixel unit becomes the first vertical read wiring.
The fourth aspect of claim 4 is instructing the output wiring switching circuit of the synthesis target pixel unit belonging to the second synthesis pixel unit so that the wiring that outputs the output signal of the amplification transistor becomes the second vertical read wiring. The image pickup device described. The image pickup element according to claim 10, wherein the light receiving element includes a plurality of light receiving elements.

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