JP2007189085A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit efficient wiring layout in staggered pixel array and contrive the utilization of CMOS (complementary metal oxide semiconductor) type solid state imaging device. <P>SOLUTION: The pixels 15, constituted of a photoelectric conversion unit and a transistor, are arrayed by staggering two-dimensionally into horizontal direction and/or vertical direction, so as to be arrayed through the repetition of the same layout or so as to have a periodical structure. In this case, a plurality of pixels 15a, 15b, 15c, arrayed in the vertical direction, share a vertical signal line 18 and a well potential supplying wiring 22 while a plurality of pixels 15d, 15b, 15e, 15f, arrayed in the horizontal direction, share the gate pulse wirings 16, 17, 19 of the transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a conversion unit that converts a charge generated by a photoelectric conversion unit into a pixel signal in a pixel, such as a CMOS image sensor. Here, the CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

  A CMOS image sensor is a solid-state imaging device in which a plurality of pixels each including a photoelectric conversion unit and a plurality of MOS transistors are arranged two-dimensionally, and charges generated by the photoelectric conversion unit are converted into pixel signals and read. In recent years, this CMOS image sensor has attracted attention as an imaging device such as a camera for a mobile phone, a digital still camera, or a digital video camera.

  In a solid-state imaging device, pixel miniaturization has been promoted due to demands for improvement in resolution and reduction in chip size. Such miniaturization is an effective means for satisfying the above requirements, but generally deteriorates so-called pixel characteristics such as saturation signal amount and sensitivity. In particular, in the above-described solid-state imaging device called a CMOS image sensor, a plurality of MOS transistors are usually provided in a pixel, and a plurality of wirings are densely laid out in the pixel to drive the MOS transistor. It has been considered that it is disadvantageous for miniaturization as compared with the CCD solid-state imaging device.

  Apart from this, as a technique for improving the resolution, a method of shifting pixels with a certain regularity has been widely known for a long time (see Patent Document 1). Although this technique has been widely used in CCD solid-state imaging devices, attempts have been made to apply it to a CMOS image sensor (see Patent Document 2).

  Certainly, it is possible to improve the resolution conceptually by applying the technology of the CCD image sensor even with the CMOS image sensor, but a CMOS image sensor with a shifted arrangement is not yet available. As shown in FIG. 14, the current CMOS image sensor has a configuration in which a plurality of unit pixels 1 are arranged in a square arrangement in the horizontal and vertical directions, that is, in a two-dimensional square arrangement. In this arrangement, the pixel size is reduced. Has been tried.

Japanese Patent Publication No.59-3066 JP 2003-7995 A

  By the way, in the CMOS image sensor, the layout of the wiring is difficult in the case of the configuration in which the pixels are shifted and arranged at a certain ratio. That is, the CMOS image sensor normally has a plurality of transistors in the pixel as described above, and a plurality of wirings need to be laid out in the pixel for driving the transistors. However, since the pixel portion has a photodiode (PD) that is a photoelectric conversion portion, it is a matter of course that wiring through the photodiode causes a large loss in pixel characteristics, and each wiring can be laid out in a straight line. Can not.

  In order not to cause characteristic loss, it is necessary to lay out the wiring so as not to pass over the photodiode as much as possible and without shorting the wiring for driving each transistor. The reason why the pixel shifted arrangement or the oblique arrangement is not realized in the CMOS image sensor is none other than the lack of a process technology for producing wiring with high accuracy and an efficient layout technology for wiring. Of these, the process technology can be made with high precision by recent progress in miniaturization technology, but there is a problem in how to lay out the wiring without losing the pixel characteristics.

  On the other hand, in a CMOS image sensor in which pixels are obliquely arranged at 45 degrees, a wiring layout as shown in the schematic diagram of FIG. 13 can be considered. In FIG. 13, a group of first pixels 1A arranged at a predetermined pitch in the horizontal direction and the vertical direction, and a group shifted by ½ pitch of the pitch in both the horizontal direction and the vertical direction with respect to the group of first pixels 1A. A group of two pixels 1B is arranged, and so-called pixels 1A and 1B are arranged obliquely. For the diagonally arranged pixels, for example, in the three-transistor type, the transfer pulse wiring 2 and the reset pulse wiring 3 are laid out in a zigzag shape so as to be shared by two adjacent pixels 1A and 1B along the horizontal direction. Further, the vertical signal line (wiring) 4 and the well potential supply wiring 5 for stabilizing the potential of the well region of each pixel are linearly shared by the pixels 1A and 1B arranged in the vertical direction along the vertical direction. Are laid out.

  When the transfer pulse wiring 2 and the reset pulse wiring 3 are laid out in a zigzag manner so as to share the two rows of pixels 1A and 1B, there is an advantage that the number of stages of the drive circuit in the peripheral circuit portion is reduced. A driving circuit having a high capability as a driving circuit is required, such as an increase in resistance of wiring along the horizontal direction and an increase in resistance and parasitic capacitance, which is disadvantageous in implementation.

  In view of the above, the present invention provides a solid-state imaging device in which pixels are arranged in a shifted manner, wiring is efficiently laid out without losing pixel characteristics, and can be practically used.

  In the solid-state imaging device according to the present invention, pixels each including a photoelectric conversion unit and a transistor are two-dimensionally shifted and arranged in the horizontal direction and / or the vertical direction, and the pixels are arranged by repeating the same layout and are arranged in the vertical direction. These pixels share a vertical signal line and well potential supply wiring, and a plurality of pixels arranged in the horizontal direction share a gate pulse wiring of a transistor.

  In the solid-state imaging device according to the present invention, since the pixels are arranged while being shifted in the horizontal direction and / or the vertical direction, the number of recording pixels increases from the actual pixels, and the resolution increases. In a state where the pixels are arranged in the same layout, a plurality of pixels arranged in the vertical direction share the vertical signal line and the well potential supply wiring, and a plurality of pixels arranged in the horizontal direction share the gate pulse wiring of the transistor. This enables wiring that avoids the opening of the photodiode, and enables efficient wiring layout even when miniaturized.

  The solid-state imaging device according to the present invention has an imaging region in which a plurality of pixels including a photoelectric conversion unit and a plurality of transistors are arranged, and the pixels are alternately shifted in the horizontal direction and / or the vertical direction from the lattice points of the matrix. The plurality of pixels arranged in the same periodic structure and arranged in the vertical direction share the output signal line and the well potential supply wiring, and the plurality of pixels arranged in the horizontal direction are predetermined transistors included in the plurality of transistors. The gate pulse wiring of the transistor is shared.

  In the solid-state imaging device of the present invention, in an imaging region where a plurality of pixels including a photoelectric conversion unit and a plurality of transistors are arranged, the pixels are alternately shifted from the lattice points of the matrix in the horizontal direction and / or the vertical direction. As a result, the number of recording pixels increases from the actual pixels, and the resolution increases. The pixels are arranged in the same periodic structure, the plurality of pixels arranged in the vertical direction share the output signal line and the well potential supply wiring, and the plurality of pixels arranged in the horizontal direction are gates of predetermined transistors included in the plurality of transistors. Since the pulse wiring is shared, wiring that avoids the opening of the photodiode is possible, and an efficient wiring layout can be achieved even if it is miniaturized.

  According to the solid-state imaging device according to the present invention, wiring can be efficiently laid out without losing pixel characteristics. Therefore, it is possible to provide a solid-state imaging device using a pixel-shifted CMOS sensor that can be put into practical use.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an example of a pixel configuration applied to the solid-state imaging device of the present invention, that is, a CMOS image sensor. In this example, a unit pixel generally called a three-transistor type has a photodiode (PD) serving as a photoelectric conversion unit and three MOS transistors. In the pixel configuration of FIG. 1, a unit pixel 15 is formed from one photodiode 11 and three MOS transistors, that is, a transfer transistor 12, a reset transistor 13, and an amplification transistor 14.

  The cathode of the photodiode 1 is connected to the gate of the amplification transistor 114 through the transfer transistor 12. A node electrically connected to the amplification transistor 14 is referred to as a floating diffusion FD. The transfer transistor 12 is connected between the photodiode 11 and the floating diffusion FD, and a transfer pulse wiring 16 for applying a transfer pulse to the gate is connected. The reset transistor 13 has a source connected to the floating diffusion FD, a drain connected to the drain terminal td, and a gate connected to a reset pulse wiring 17 that applies a reset pulse. The amplification transistor 14 has a drain connected to the drain terminal td and a source connected to the vertical signal line (wiring) 18. In the CMOS image sensor, a plurality of unit pixels 15 are two-dimensionally arranged.

  The distinction between pixel selection and non-selection is made by the potential of the floating diffusion FD (referred to as FD potential). In the selected row, the FD potential is higher than that of the non-selected pixel. This CMOS image sensor is characterized in that the drain terminal td has a variable voltage and changes between a low level and a high level by a pulse.

  FIG. 2 shows another example of a pixel configuration applied to the solid-state imaging device of the present invention, that is, a CMOS image sensor. In this example, a photodiode (PD) serving as a photoelectric conversion unit and four MOS transistors are provided in a unit pixel called a four-transistor type. In the pixel configuration of FIG. 2, a unit pixel 15 is formed from one photodiode 11 and four MOS transistors, that is, a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 19. In this pixel configuration, in the pixel configuration of FIG. 1, the drain of the selection transistor 19 is further connected to the source of the amplification transistor 14, and the vertical signal line (wiring) 18 is connected to the source of the selection transistor 19. Other connection relationships are the same as those in FIG. In this four-transistor pixel configuration, the voltage at the drain terminal td is always fixed at a high level, and whether the pixel is selected or not is determined by whether the selection transistor 19 is on or off.

Next, an embodiment of a pixel array of a solid-state imaging device, that is, a CMOS image sensor according to the present invention will be described. In the embodiment of the present invention, the pixels 15 described in FIGS. 1 and 2 are two-dimensionally arranged.
FIG. 3 shows an embodiment of a pixel array of a CMOS image sensor according to the present invention. The present embodiment is configured by obliquely arranging pixels 15 having a square shape with a 45 degree shift with respect to the horizontal direction and the vertical direction. That is, a group of the first pixels 15A arranged at predetermined pitches a and b in the horizontal direction and the vertical direction, and a half pitch of the pitches a and b in both the horizontal direction and the vertical direction with respect to the group of the first pixels 1A. A group of second pixels 15B shifted by (a / 2, b / 2) is arranged.

  In other words, the pixel array in FIG. 3 is an array obtained by rotating an angle that is a multiple of 45 degrees from the pixel array in which the pixels in the above-described figure are arrayed in a two-dimensional square shape. In this case, the horizontal pitch (a / 2) is ½ of the horizontal size a of the pixel, and the vertical pitch (b / 2) is ½ of the vertical size b of the pixel. (Hereinafter referred to as an oblique pixel shift arrangement).

  FIG. 4 shows another embodiment of the pixel array of the CMOS image sensor according to the present invention. In the present embodiment, the pixels 15 having a square shape are arranged in the horizontal direction and the vertical direction, but are arranged so as to be shifted by 1/2 of the horizontal size c of the pixels 15 every other row ( Hereinafter, this is referred to as a row pixel shift array).

FIG. 5 shows still another embodiment of the pixel array of the CMOS image sensor according to the present invention. In the present embodiment, the pixels 15 having a square shape are arranged in the horizontal direction and the vertical direction, but are arranged so as to be shifted by ½ of the vertical size d of the pixels 15 every other column ( Hereinafter, it is referred to as a column pixel shift array).
The pixel arrays in FIGS. 3 to 5 are collectively referred to as a shifted array.

  A feature of these pixel arrays in FIGS. 3 to 5 is that the pixels 15 having the same layout are all repeatedly arranged and developed in an array. In other words, the pixel arrangement in the present embodiment is different in two layouts, or another pixel having the same layout but a rotated layout A ′ with respect to a pixel group having a layout A. The group is not configured by two pixel groups that are shifted by a half pitch of the pixel size.

  In the wiring layout according to the embodiment of the present invention, the pixel arrangements shown in FIGS. 3 to 5 can be applied. In the following, an embodiment of a CMOS image sensor having a wiring layout according to the present invention will be described, focusing on the case where the oblique pixel shifting arrangement of FIG. 3 is applied.

  As shown in FIG. 6, in the CMOS image sensor 21 according to the first embodiment of the present invention, a plurality of pixels 15 having pixel centers on the same vertical line are arranged as vertical signal lines in a configuration in which the pixels 15 are arranged obliquely. 18 and the well potential supply wiring 22 are shared, and a plurality of pixels 15 having the pixel center on the same horizontal line are configured to share the gate pulse wiring of the pixel transistor. That is, paying attention to the hatched pixel 15b, the vertical signal line 18 for transmitting a signal to the column signal processing circuit is shared by the pixels 15a and 15c directly above and below the pixel 15b in FIG. Similarly, the well potential supply wiring 22 for stabilizing the well potential is also shared by the pixels 15a and 15c directly above and below the pixel 15b.

  By sharing these wirings 18 and 22 between the pixels directly above and directly below, all the pixels existing directly above and below the pixel 15b, that is, all the pixels 15 existing on the vertical line passing through the pixel center can be obtained. The same vertical signal line 18 and well potential supply wiring 22 are shared.

  On the other hand, when a three-transistor pixel is arranged, a transfer pulse wiring 16 for applying a voltage to the gate of the transfer transistor and a reset pulse wiring 17 for applying a voltage to the gate of the reset transistor are arranged in a four-transistor pixel. In this case, the selection pulse wiring 19 for applying a voltage to the gate of the selection transistor is shared by the pixels 15e, 15f and 15d on the right and left of the pixel 15b in FIG.

  By sharing these gate pulse wirings with the respective right and left pixels, all the pixels existing right and right of the pixel 15b, that is, all existing on the horizontal line passing through the pixel center of the pixel 15b. The pixels 15 share the same transfer pulse wiring 16, reset pulse wiring 17, or the same transfer pulse wiring 16, reset pulse wiring 17, and selection pulse wiring 19.

  The power supply wiring is shared by all the pixels 15 regardless of the adjacent manner. The power supply wiring forms metal on the entire surface, but is opened only on the photodiode 11 in the effective pixel region.

  Here, the well potential supply wiring will be described. In a CMOS image sensor, a pixel region in which a large number of pixels are arranged in an array is formed in a second conductivity type semiconductor well region on a first conductivity type semiconductor substrate. A ground (GND) potential serving as a reference potential, that is, a well potential, is supplied to the semiconductor well region. To prevent the well potential from being different depending on the location in the pixel region, a well potential supply wiring is provided in each pixel. A well contact to be connected to 22 is provided.

  In the CMOS image sensor according to the first embodiment, the vertical signal line 18 and the well potential supply wiring 22 are provided to the plurality of pixels 15a, 15b, and 15c having the pixel center on the same vertical line in the configuration in which the pixels are arranged obliquely. By laying out so as to be shared and laying out such that the gate pulse wirings 16, 17, and 19 of each transistor are shared by a plurality of pixels 15d, 15b, 15e, and 15f having the pixel center on the same horizontal line, it is miniaturized. However, a wiring layout that avoids opening of the photodiode (PD) is possible, and an efficient wiring layout can be achieved without losing pixel characteristics such as the saturation signal amount and sensitivity.

  Therefore, with such a wiring layout, the resistance of the gate pulse wirings 16, 17, and 19 and the parasitic capacitance due to the wiring are reduced as compared with the zigzag wiring as shown in the figure, and the driving can be performed with a driving circuit having a small capacity. This is advantageous.

  FIG. 7 shows an example of a signal readout driving method when the CMOS image sensor 21 having the pixel arrangement and the wiring layout of the first embodiment shown in FIG. 6 is used. In the driving method of the present embodiment, two adjacent pixel rows L1 and L2 are simultaneously read out to the vertical signal line. Then, the signal of each pixel 15A corresponding to the pixel row L1 is read out downward (in the direction of the arrow) in FIG. 7 through the vertical signal line 18A. Further, the signal of each pixel 15B corresponding to the pixel row L2 is read out upward (in the direction of the arrow) in FIG. 7 through the vertical signal line 18B.

  According to the driving method of the present embodiment, two rows can be read simultaneously in the diagonal pixel array. In addition, since the adjacent pixel columns are read in the opposite directions, the column signal processing circuit provided in each pixel column can be laid out with a margin of two columns even if miniaturization progresses. This facilitates manufacturing.

Next, a CMOS image sensor according to a second embodiment of the present invention will be described.
In the pixel region of the CMOS image sensor, a second conductivity type, for example, a p-type semiconductor well region is formed on a first conductivity type, for example, an n-type silicon semiconductor substrate, and a photodiode and a plurality of MOSs are formed in the p-type semiconductor well region. A number of pixels made of transistors are formed in an array, and further, multilayer wiring is formed on the substrate via an interlayer insulating film. In this example, the above-described wiring by the first-layer metal, second-layer metal, and third-layer metal is formed from the substrate side. Formed.

In the second embodiment of the present invention, the metal layer forming each wiring is specified and configured in the first embodiment described with reference to FIG. That is, when the three-transistor type pixels that are selected or not selected by the potential of the floating diffusion (FD) in FIG. 1 are arranged, the vertical signal line 118 and the well potential supply wiring 22 are made of the first layer metal. Then, the transfer pulse wiring 16 and the reset pulse wiring 17 are formed of the second layer metal, and the power supply pulse wiring (not shown) is formed of the third layer metal, thereby laying out each wiring.
2 is arranged, the vertical signal line 118 and the well potential supply wiring 22 are formed of the first layer metal, and the transfer pulse wiring 16 is formed. Then, the reset pulse wiring 17 and the selection pulse wiring 19 are formed of the second layer metal, and the power supply wiring (not shown) is formed of the third layer metal, thereby laying out each wiring.

  For example, Al or Cu can be used as the metal of each layer. Furthermore, it is desirable to form the wiring connecting the floating diffusion (FD) and the gate of the amplification transistor with the first layer metal.

  Although the fine process has a problem that the wiring resistance increases due to the thinning of the wiring, the contact portion connecting the metal layers is also reduced accordingly, and the contact resistance is also increased. Therefore, the vertical signal line 18 for transmitting the signal from the pixel to the column signal processing circuit and the well potential supply wiring 22 for supplying the ground (GND) potential are provided in the first layer metal in order to reduce the load (RC time constant). It is desirable to lay out.

  When the load of the well potential supply wiring is heavy, the wiring and contact resistance cannot be ignored with respect to the resistance of the well region in a fine process. For example, in an image sensor in which three-transistor pixels are arranged, a cup is applied when a power pulse is applied. Care must be taken because the well reference potential is fluctuated by the ring, causing deterioration of image quality such as shading.

  Subsequently, in the case of each of the wirings 16, 17, and 4 transistors for applying a voltage to the gate of each transistor, the gate wiring 19 is further laid out using the second layer metal, and the third power supply wiring common to all the pixels 15 is provided. Lay out with layer metal. The third layer metal needs to open a portion corresponding to the photodiode 11 in the so-called effective pixel region.

  According to the CMOS image sensor of the second embodiment, the vertical signal line 18 and the well potential supply wiring 22 are formed of the first layer metal, thereby minimizing an increase in resistance related to the wiring including the contact resistance. The load due to wiring can be reduced. In particular, image quality deterioration such as shading caused by the well potential supply wiring 22 can be avoided.

Next, a CMOS image sensor according to a third embodiment of the invention will be described.
In the third embodiment of the present invention, each wiring, that is, the vertical signal line 18, the well potential supply wiring 22, the transfer pulse wiring 16, the reset pulse wiring 17, in the pixel array of the first and second embodiments described above, The selection pulse wiring 19 is laid out at a position close to the boundary between adjacent pixels 15 so as not to enter the photodiode (PD) opening of each pixel 15. FIG. 8 schematically shows only the wirings 31 and 32 in the vertical direction, but the wirings in the horizontal direction (transfer pulse wiring, reset pulse wiring, and selection pulse wiring) are similarly avoided on the photodiode to avoid adjacent pixels. It is laid out near the boundary. As described above, the wiring is shared only between adjacent pixels directly above and below a certain pixel or between right and left. Here, the wiring 31 is connected to the pixels 15a, 15b and 15c, and the wiring 32 is connected to the pixels 15r, 15s, 15t and 15u. Each of the wirings 31 and 32 represents the vertical signal line 18 and the well potential supply wiring 22 as described above.

  In this way, each wiring (typically, the wirings 31 and 32) is laid out so as to avoid the opening of the photodiode (PD), thereby preventing a reduction in sensitivity and color mixing caused by light reflection on the metal wiring and irregular reflection. Can do.

  On the other hand, when such a wiring layout is performed, as shown by the dotted circle 33 in FIG. As a result, it is expected to be a place where coupling is particularly easy. In particular, in the case where the wirings 31 and 32 shown in FIG. 8 are vertical signal lines, if there is coupling, a signal with a large output is coupled to a smaller output, and a larger output is obtained as compared with a normal case. May be issued. In the dark, white spots may be detected from normal pixels other than the pixels generating white spots, which is a problem.

  In order to avoid this problem, in the present embodiment, especially when the wirings 31 and 32 are vertical signal lines, a signal shielding between the adjacent wirings 31 and 32 is prevented in the wiring dense part of the dotted circle 33. A layer or another wiring is formed. For example, as shown in FIG. 9A, a conductive layer (wiring) that prevents signal transmission, for example, a metal layer 35 that serves as a shield, is sandwiched between the wirings 31 and 32, or as shown in FIG. And 32 so that another wiring 36 is sandwiched between them. The wiring 36 sandwiched between them uses the one that is not sensitive to coupling. For example, a wiring that does not entangle with a power line, a ground line, or other signal lines is selected. Since the well potential supply wiring is laid out in the vertical direction in addition to the vertical signal line, it is also effective to sandwich the well potential supply wiring serving as the ground (GND) potential between the adjacent vertical signal lines as the wiring 36. .

  Of course, the layouts of FIGS. 9A and 9B are also effective for the wiring arranged in the left-right direction. Further, in order to contact the power supply wiring laid out in the third layer metal to the semiconductor substrate in the pixel region, the contact is dropped from the third layer metal to the second layer metal and the first layer metal. However, the first metal layer contacted from the power supply wiring may be used. A metal layer that is used when contacting the pixel region (pixel active region) from another upper layer may be used.

  As described above, the floating diffusion (FD) shown in the equivalent circuit of FIGS. 1 and 2 and the gate of the amplification transistor 14 are connected by the wiring of the first layer metal. The potential applied to the floating diffusion (FD) changes in synchronization with the signal output to the vertical signal line 18 connected via the amplification transistor 14. This connection wiring can also be included in the vertical signal line. Accordingly, in the wiring dense portion 33, if there is a connection wiring 37 between the floating diffusion (FD) of another pixel column and the gate of the amplification transistor adjacent to the vertical signal line 32 of a certain pixel column (see FIG. 10). The coupling between the vertical signal line 32 and the connection wiring 37 is transmitted to the vertical signal line 31 through the connection wiring 37.

  In the present embodiment, as shown in FIG. 10, in the wiring dense portion 33, the shield layer 35 described above or another wiring for preventing signal transmission is provided between the adjacent vertical signal line 32 and the connection wiring 37. Layout.

  According to the third embodiment, pixel characteristics such as saturation signal amount, sensitivity, and color mixing prevention can be improved by laying out each wiring while avoiding the opening of the photodiode (PD). In addition, even when the wiring of adjacent pixels is concentrated in one place due to miniaturization, the above-mentioned problem caused by coupling can be obtained by sandwiching a shield layer or another wiring between the wirings. Can be avoided.

  In the above example, the present invention is applied to the diagonal pixel shift arrangement shown in FIG. 3, but can be similarly applied to the row pixel shift arrangement of FIG. 4 and the column pixel shift arrangement of FIG. 11 and 12 show the respective wiring layouts. Although detailed description is omitted, the same effects as those of the above-described embodiment can be obtained.

  It should be noted that the pixel shift arrangement according to the embodiment of the present invention is shifted by 1/2 pitch of the horizontal / vertical direction size of the pixel described in the above embodiment (see FIG. 3), and 1 / of the horizontal size of the pixel. It is not limited to shifting by 2 pitches (see FIG. 4) or shifting by 1/2 pitch of the vertical size of the pixels (see FIG. 5), but it is predetermined in the horizontal / vertical direction, horizontal direction, or vertical direction, respectively. The arrangement may be shifted by a distance.

  In addition, the pixel arrangement according to the embodiment of the present invention is such that pixels having the same layout in the photodiode, the arrangement of each transistor, the direction of each wiring including the vertical signal line, etc. are repeatedly arranged. The pixel is not limited to this, and so-called pixels may be arranged in a periodic structure. For example, a set of a plurality of pixels may be periodically arranged. For example, when two adjacent pixels are arranged so as to target the layout in the pixel, the two pixels may be periodically arranged as a set. In this case, two adjacent pixels may have a configuration including a photodiode and a plurality of transistors, or a configuration in which a required transistor among a plurality of transistors is shared.

  That is, the solid-state imaging device according to the embodiment of the present invention has an imaging region in which a plurality of pixels including photodiodes that are photoelectric conversion units and a plurality of transistors are arranged, and the pixels are alternately arranged from lattice points of the matrix. The plurality of pixels arranged in the horizontal direction and / or the vertical direction and arranged in the same periodic structure, and arranged in the vertical direction share the output signal line and the well potential supply line, and the plurality of pixels arranged in the horizontal direction The present invention can also be applied to a configuration in which gate pulse wirings of predetermined transistors included in a plurality of transistors are shared. Even in this configuration, the same effect as described in the above embodiment can be obtained.

  According to the above-described embodiment, the resolution is improved as compared with a CMOS image sensor having a square pixel arrangement which has been conventionally used. In addition, compared with a square pixel array CMOS image sensor having the same pitch, the same or better pixel characteristics can be obtained. The wiring layout according to this embodiment makes it possible to put a CMOS image sensor having a pixel shift arrangement into practical use.

It is an equivalent circuit diagram which shows an example of the unit pixel applied to the solid-state imaging device which concerns on this invention. It is an equivalent circuit diagram which shows the other example of the unit pixel applied to the solid-state imaging device which concerns on this invention. It is a schematic diagram which shows one Embodiment of the pixel arrangement | sequence of the solid-state imaging device concerning this invention. It is a schematic diagram which shows other embodiment of the pixel arrangement | sequence of the solid-state imaging device which concerns on this invention. It is a schematic diagram which shows other embodiment of the pixel arrangement | sequence of the solid-state imaging device which concerns on this invention. It is a schematic diagram which shows the wiring layout of 1st Embodiment of the solid-state imaging device which concerns on this invention. It is the schematic which shows one Embodiment of the drive method of the solid-state imaging device which concerns on this invention. It is a schematic diagram which shows the wiring layout of 3rd Embodiment of the solid-state imaging device which concerns on this invention. A, B It is an enlarged view of the principal part of FIG. It is an enlarged view of the other example of the principal part of FIG. It is a schematic diagram which shows the wiring layout of other embodiment of the solid-state imaging device concerning this invention. It is a schematic diagram which shows the wiring layout of other embodiment of the solid-state imaging device concerning this invention. It is a schematic diagram of the wiring layout which shows the comparative example of the CMOS image sensor of the diagonal pixel shifting arrangement | sequence. It is a schematic diagram which shows the square pixel arrangement | sequence which concerns on the conventional CMOS image sensor.

Explanation of symbols

  11 .. Photodiode, 12 .... Transfer transistor, 13 .... Reset transistor, 14 .... Amplification transistor, FD ..., Floating / Diffusion part, 15 .... Unit pixel, 16 .... Transfer pulse wiring, 17 .... Reset Pulse wiring, 18 ... vertical signal line, 19 ... selection transistor, 20 ... selection pulse wiring, 21 ... CMOS image sensor, 22 ... well potential supply wiring, 31, 32 ... wiring, 33 ... wiring dense 35, Shield layer, 36 ... Separate wiring, 37 ... Connection wiring

Claims (7)

Pixels composed of photoelectric conversion units and transistors are two-dimensionally shifted and arranged in the horizontal direction and / or vertical direction,
The pixels are arranged by repeating the same layout,
A plurality of the pixels arranged in the vertical direction share a vertical signal line and a well potential supply wiring,
A plurality of the pixels arranged in the horizontal direction share the gate pulse wiring of the transistor. The vertical signal line and the well potential supply wiring are formed of a first layer metal,
The gate pulse wiring of the transistor is formed of a second layer metal,
The solid-state imaging device according to claim 1, wherein the power supply wiring is formed of a third layer metal. The solid-state imaging device according to claim 2, wherein a wiring connecting the floating diffusion portion of the pixel and the gate portion of the amplification transistor is formed of a first layer metal. The pixels are arranged diagonally;
4. The solid-state imaging device according to claim 1, wherein a shield layer or another wiring for preventing signal transmission is formed between the wirings connected to adjacent pixels. 5. The solid-state imaging device according to claim 4, wherein a shield layer or a separate wiring for preventing signal transmission is formed between the vertical signal lines connected to adjacent pixels. A shield layer or another wiring for preventing signal transmission is formed between the vertical signal line connected to the pixels adjacent to each other and the wiring connecting the floating diffusion portion and the gate portion of the amplification transistor. The solid-state imaging device according to claim 4. An imaging region in which a plurality of pixels including a photoelectric conversion unit and a plurality of transistors are arranged;
The pixels are alternately shifted from the lattice points of the matrix in the horizontal direction and / or the vertical direction, and arranged in the same periodic structure,
The plurality of pixels arranged in the vertical direction share an output signal line and a well potential supply wiring,
The solid-state imaging device, wherein the plurality of pixels arranged in a horizontal direction share gate pulse wirings of predetermined transistors included in the plurality of transistors.

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