KR20170010214A - Nonvolatile memory module and storage system having the same - Google Patents

Abstract

According to an embodiment of the present invention, a non-volatile memory module includes: at least one non-volatile memory; a random access memory (RAM) for storing data exchanged between the host and the at least one non-volatile memory; and a dual in-line memory module (DIMM) controller for controlling data exchange between the RAM and the at least one non-volatile memory. The allocation to the access area upon access to the RAM is performed in a write transaction that writes data to the RAM and the release of the allocation is performed in a read transaction of the written data. According to the embodiment of the present invention, the performance of the non-volatile memory module can be improved by efficiently using the RAM provided in a physical layer of a non-volatile memory module having a relatively small capacity.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory module and a storage system including the same,

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory module and a storage system including the same.

The semiconductor memory device may be classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. Although volatile semiconductor memory devices have advantages of high read and write speed, there is a disadvantage that the stored data disappears when the power supply is cut off. On the other hand, the nonvolatile semiconductor memory device preserves the stored data even if the power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be stored regardless of whether power is supplied or not.

Recently, much research has been done to improve the communication speed between host and data storage. For example, there is a study to improve the communication speed by mounting a flash memory in a memory (e.g., a DRAM, etc.) slot. However, in this case, it is essential to maintain compatibility with existing interfaces and to ensure data reliability. Therefore, it is important to develop a flash memory device capable of maintaining compatibility with existing interfaces and ensuring data reliability.

The technical idea of the present invention provides a method of efficiently using a RAM provided in a physical layer of a nonvolatile memory module having a relatively small capacity.

A non-volatile memory module according to an embodiment of the present invention includes at least one non-volatile memory, a RAM in which data exchanged between the host and the at least one non-volatile memory is stored, A device controller comprising a DIMM controller for controlling the exchange of data between the memories, wherein access to the access area upon access to the RAM is performed in a write transaction that writes data to the RAM, May be performed in a read transaction of the recorded data.

In an embodiment, the host may allocate an area where the data is to be stored when the host stores the data in the RAM in a write operation to the nonvolatile memory module, and when the DIMM controller reads the data from the RAM, The allocation for the area in which the data was stored can be released.

In another embodiment, the DIMM controller allocates an area in which the data is to be stored when the DIMM controller stores the data in the RAM, and when the host reads the data from the RAM And can release the allocation for the area in which the data was stored.

In another embodiment, the DIMM controller may include a region manager that generates state information as to whether the DIMM controller has read the data stored in the RAM.

In another embodiment, the RAM may include a status area for storing status information.

As another embodiment, the allocated area is prohibited from being overwritten, and the released area may be allowed to be overwritten.

In yet another embodiment, the host and the non-volatile memory module may communicate via a dual data rate (DDR) interface.

In yet another embodiment, the non-volatile memory module may be a dual in-line memory module (DIMM).

In yet another embodiment, the at least one non-volatile memory may comprise a three-dimensional memory array.

A storage system according to an embodiment of the present invention includes a host and at least one non-volatile memory, a RAM in which data exchanged between the host and the at least one non-volatile memory is stored, A nonvolatile memory module including a device controller including a DIMM controller for controlling data exchange between memories, wherein allocation to an access area when accessing the ram is performed in a write transaction that writes data to the ram And release of the allocation may be performed in a read transaction of the recorded data.

As an embodiment, in a write operation to a nonvolatile memory module, the host allocates the area in which the data is to be stored when storing the data in the RAM, and when the DIMM controller reads the data from the RAM, Can be released from the allocation to the area where the < RTI ID = 0.0 >

In another embodiment, the DIMM controller may include a first area manager for generating status information regarding whether the DIMM controller has read the data stored in the RAM.

In another embodiment, the DIMM controller allocates an area where the data is to be stored when the DIMM controller stores the data in the RAM, and the host reads the data from the RAM in a read operation to the nonvolatile memory module The allocation for the area in which the data was stored can be released.

In another embodiment, the host may include a second area manager that generates status information regarding whether the host has read the data stored in the RAM.

As another embodiment, the allocated area is prohibited from being overwritten, and the released area may be allowed to be overwritten.

According to the embodiment of the present invention, a RAM provided in a physical layer of a nonvolatile memory module having a relatively small capacity can be efficiently used.

1 is a block diagram illustrating a storage system according to an embodiment of the present invention.
2 is a block diagram illustrating an exemplary non-volatile memory module and software layer shown in FIG.
3 is a detailed block diagram illustrating the structure of the RAM shown in FIG.
4 is a block diagram illustrating a method of operating a storage system according to an embodiment of the present invention.
5 is a block diagram illustrating a method of operating a storage system in accordance with another embodiment of the present invention.
6 is a flowchart illustrating a write operation for a nonvolatile memory module according to an embodiment of the present invention.
7 is a block diagram illustrating a method of operating a storage system in accordance with another embodiment of the present invention.
8 is a flowchart illustrating a write operation to a nonvolatile memory module according to another embodiment of the present invention.
FIG. 9 is a block diagram exemplarily showing any one of the non-volatile memories shown in FIG. 1. FIG.
10 is a circuit diagram showing an example of any one of the memory blocks included in the memory cell array of FIG.
FIG. 11 is a block diagram illustrating a computing system to which a non-volatile memory module according to the present invention is applied.
FIG. 12 is a block diagram illustrating one of the non-volatile memory modules of FIG. 11; FIG.
FIG. 13 is a block diagram illustrating one of the non-volatile memory modules of FIG. 11 by way of example.
FIG. 14 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied.
15 is a block diagram illustrating an exemplary nonvolatile memory module of FIG.
FIG. 16 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 14;
17 is a block diagram illustrating an exemplary nonvolatile memory module of FIG.
18 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

When an element or layer is referred to as being "connected," "coupled", or "adjacent" to another element or layer, it may be directly connected, joined, or adjacent to another element or layer, It is to be understood that there may be elements or layers interposed therebetween. As used herein, the term "and / or" will include one or more possible combinations of the listed elements.

Although the terms "first "," second "and the like can be used herein to describe various elements, these elements are not limited by these terms. These terms may only be used to distinguish one element from the other. Accordingly, terms such as first element, section, and layer used in this specification may be used as a second element, section, layer, etc. without departing from the spirit of the present invention.

The terms "lower "," lower ", "upper "," upper ", and like terms encompass both directly and indirectly. It should be understood that these terms spatially relative include directions in addition to those shown in the figures. For example, if the device is upside down, the component described as "below" will be "up".

The terminology described herein is used for the purpose of describing a specific embodiment only, and is not limited thereto. Terms such as "one" should be understood to include plural forms unless explicitly referred to as " one ". The terms "comprising" or "comprising" are used to specify the presence of stated features, steps, operations, components, and / or components and may include additional features, steps, operations, components, And / or does not exclude the presence of their group.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a block diagram illustrating a storage system 10 in accordance with an embodiment of the present invention. The storage system 10 may include a host 100 and a non-volatile memory module 200.

The host 100 may perform a read operation or a write operation with respect to the nonvolatile memory module 200. The host 100 can access the physical layer 230 of the device controller 210 to write data to the nonvolatile memory module 200 or to read the stored data. For example, the host 100 can access the RAM 234 included in the physical layer 230 and write commands and addresses and the like for accessing the nonvolatile memory 280. [

The storage system 10 according to an embodiment of the present invention may include a second area manager 110 and a first area manager 242. [ For example, the second area manager 110 may be provided in the host 100, and the first area manager 242 may be provided in the device controller 240.

The second area manager 110 can manage the area where the host 100 reads data from the RAM 234. More specifically, when the DIMM controller 240 writes data (e.g., read data, etc.) to the RAM 234, the DIMM controller 240 determines whether the data is to be stored in the RAM 234 . Thereafter, when the host 100 reads the data stored in the RAM 234, the host 100 can release the area allocation. With this release, the released area is ready for overwriting. The second area manager 110 may generate status information indicating that the data stored in the released area has been processed and update the status information in the RAM 234. [ The DIMM controller 240 can perform the next write operation to the RAM 234 by referring to the updated status information.

The first area manager 242 can manage the area where the DIMM controller 242 reads data from the RAM 234. More specifically, when the host 100 writes data (e.g., storage command, storage address, read data, etc.) to the RAM 234, the host 100 sends data to the RAM 234 Allocate the area to be saved. Thereafter, when the DIMM controller 242 reads the data stored in the RAM 234, the DIMM controller 242 can release the area allocation. With this release, the released area is ready for overwriting. The first area manager 242 may then generate state information indicating that the data stored in the released area has been processed and update the state information in the RAM 234. [ The host 100 can execute the next write operation to the RAM 234 by referring to the updated status information.

According to the embodiment of the present invention, when the host 100 or the DIMM controller 240 transmits data to the RAM 234 provided in the physical area 230 of the nonvolatile memory module 200, Area is allocated. When the processing of the data stored in the allocated area is completed, the host 100 or the DIMM controller 240 releases the area allocation. That is, the area is allocated at the moment when data is stored in the RAM 234, and the area is released at the moment when the data is read from the RAM 234, so that the RAM 234 having a relatively small capacity can be efficiently used have.

The non-volatile memory module 200 may include a device controller 210, a plurality of non-volatile memories 280, and a buffer 290. The device controller 210 includes at least one processor 220, a physical layer (i.e., DIMM PHY) 230, a DIMM controller 240, a non-volatile memory interface 250, a ROM 260, and a buffer manager 270 ).

The processor 220 may control the overall operation of the device controller 210. For example, the processor 220 may perform various functions such as data exchange operations, error correction, scrambling, etc., between the host 100 and the nonvolatile memory module 200, which are executed in the device controller 210 You can run the firmware. For example, the processor 220 may be multi-core, and each core may perform at least one of the operations described above.

DIMM PHY 230 may include a RAM controller 232 for receiving a RAM command CMD_R, a RAM address ADDR_R, and a clock CK from host 100. The DIMM PHY 230 may include a RAM 234 for storing data exchanged with the host 100 using the data DQ and the data strobe signal DQS. At this time, the data DQ can be stored in the space of the RAM 234 designated according to the RAM address ADDR_R received from the host 100. [ The data DQ may include at least one of a storage command CMD_S for accessing the nonvolatile memory 280, a storage address ADDR_S, data DATA, and status information STI. The status information (STI) may include information about the status of the data stored in the RAM 234 (e.g., whether the process has been completed, whether an error occurred during the process, etc.).

The RAM 234 can be divided into an area for storing the storage command CMD_S and a storage address ADDR_S, an area for storing data DATA, and an area for storing status information STI. For example, the RAM 234 may be implemented as a ring buffer, a serial buffer, or the like.

DIMM controller 240 may access RAM 234 to read data stored in RAM 234. [ For example, the DIMM controller 240 can read write data to be stored in the nonvolatile memory 280 and transmit it to the nonvolatile memory 280. [ The DIMM controller 240 can then transfer the data read from the non-volatile memory 280 to the RAM 234. [

According to an embodiment of the present invention, the DIMM controller 240 manages the area of the RAM 234 in which data (e.g., storage command, storage address, write data, etc.) received from the host 100 is stored And may include a first zone manager 242. For example, when the write data received from the host 100 according to the write command is written to the RAM 234, the host 100 can allocate a specific area of the RAM 234 where the write data is to be stored. When the DIMM controller 240 reads the write data stored in the area allocated by the DIMM controller 240, the DIMM controller 100 can release the area allocation. That is, the released area becomes a state in which overwriting is possible. Then, the first area manager 242 generates state information (STI) about the released area and transfers it to the RAM 234. [ The host 100 can execute the next write operation with reference to the updated status information (STI).

The non-volatile memory interface 250 may provide an interface between the device controller 210 and the non-volatile memory 280. For example, the device controller 210 can transmit and receive data to and from the nonvolatile memory 280 via the nonvolatile memory interface 250.

The ROM 260 may store various operations or firmware necessary for operating the device controller 210 and the like. For example, the ROM 260 may store firmware that corrects errors detected by the error detector 244. The ROM 260 may store code data for performing interfacing with the host 100.

The buffer manager 270 may provide an interface between the device controller 210 and the buffer 290.

Non-volatile memory 280 may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithical means that layers of each level in a three-dimensional array are deposited directly on the lower-level layers of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between the levels, a configuration suitable for a three-dimensional memory array is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466 U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, which are incorporated herein by reference. However, it is not limited thereto, and the non-volatile memory 280 may include a planar type memory array.

The non-volatile memory 280 may be coupled to the non-volatile memory interface 250 via a plurality of channels CH. The nonvolatile memory 280 may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a PRAM (Phase-change RAM), a ReRAM (Resistor RAM), a FRAM (Ferroelectric RAM), a STT- Torque Magnetic RAM), and the like.

The buffer 290 can be used as a buffer memory, a working memory, or a cache memory of the device controller 210. For example, the buffer memory 290 may include various random access memories such as dynamic random access memory (DRAM), static random access memory (SRAM), phase-change RAM (PRAM)

2 is a block diagram illustrating an exemplary non-volatile memory module and software layer shown in FIG. Referring to FIG. 1, a host layer software 100 'may be run at a host. And the nonvolatile memory module 200 may be operated with software or firmware 200 'of the nonvolatile memory layer.

Various software may be run in the host layer 100 '. For example, the application 101 'and the operating system 102' may be included in the host upper layer HL1. The application 101 'may be either a basic service or an upper layer software driven by a user. The operating system 102 'may perform overall control operations on the storage system 10, such as executing programs, accessing files, running applications, controlling non-volatile memory modules 200, and the like.

The RAM driver 103 'and the DIMM layer 104' may constitute a host lower layer HL2 for accessing the non-volatile memory module 200. [ The RAM driver 103 'or the DIMM layer driver 104' may be substantially included in the kernel of the operating system. For an access request provided by the host upper layer HL1, the RAM driver 103 'may perform a control operation for accessing the RAM 234' of the nonvolatile memory module 200. [ For example, the RAM driver 103 'may be a control module for controlling the RAM 234' of the non-volatile memory module 200 at the operating system 102 'level. When an access request is made in the application 101 'or the operating system 102' to the RAM 234 ', the RAM driver 103' can be called. The DIMM layer driver 104 'may then be invoked with the ramdriver 103' to support a substantial physical layer level of access to the RAM 234 '.

The non-volatile memory layer 200 'may include a memory upper layer ML1 and a memory lower layer ML2. Access to the nonvolatile memory 280 'in accordance with the upper instruction CMD_R or the upper address ADDR_R recorded in the RAM 234' is controlled in the memory upper layer ML1. The memory upper layer ML1 can be accessed by the control layer 240 'and the memory management operation can be performed to the nonvolatile memory 280'. For example, control over garbage collection, wear leveling, stream control, etc., for the non-volatile memory 280 'may be performed by the control layer 240'. On the other hand, in the memory lower layer ML2, interfacing between the RAM 234 'and the host 100 can be performed. That is, the memory lower layer ML2 may perform an operation of reading or writing data of the RAM 234 'to the RAM command (CMD_R) or the RAM address (ADDR_R) provided through the RAM controller 232. The memory lower layer ML2 may access the RAM 234 'at the request of the memory upper layer ML1.

The host can access the nonvolatile memory 280 by software or firmware having the above-described hierarchical structure. That is, the access to the nonvolatile memory 280 of the nonvolatile memory module formed in the DIMM form can be performed by decoding the command, the address (CMD_R, ADDR_R) provided via the RAM 234 as an intermediary.

3 is a detailed block diagram illustrating the structure of the RAM shown in FIG. 3, the RAM 234 may include a command area 234a, a writing area 234b, a reading area 234c, and a status area 234d. The data received from the host 100 or the DIMM controller 240 are written into the command area 234a and the write area 234b in accordance with the RAM command ADDR_R and the clock CK received from the host 100 Area 234b, read area 234c, and status area 234d. For example, the RAM 234 may be a dual port SRAM that can be accessed by the host and the DIMM controller 240 simultaneously.

The command area 234a can store the storage command CMD_S and the storage address ADDR_S received from the host 100 under the control of the RAM controller 232. [ The DIMM controller can read the storage command CMD_S and the storage address ADDR_S stored in the command area 234a.

The write area 234b may store the write data (DATA_W) received under the control of the RAM controller 232. The DIMM controller 240 can read the write data (DATA_W) stored in the write area 234b of the RAM 234.

The read area 234c may store read data (DATA_R) received under the control of the DIMM controller 232. [ The DIMM controller 240 can read the write data (DATA_R) stored in the read area 234c of the RAM 234. [

Status area 234d may store status information (STI) as to whether data stored in RAM 234 has been processed. The storage command CMD_S and the storage address ADDR_S stored in the command area 234a and the write data DATA_W stored in the write area 234b or the read area 234c, May be read by the host 100 or the DIMM controller 240. In this case, The state information stored in the state area 234d may be transmitted to the host 100 or to the DIMM controller 240. [ For example, the host 100 may transmit the next storage command CMD_S or write data DATA_W to the RAM 234 by referring to the state information (STI). Or the DIMM controller 240 can refer to the status information (STI) and forward the next read data (DATA_R) to the RAM 234.

4 is a block diagram illustrating a method of operating the storage system 10 in accordance with an embodiment of the present invention. In this embodiment, a description will be given of the operation of area allocation and release of area allocation for the storage command CMD_S and the storage address ADDR_S stored in the RAM 234, and updating of the state information (STI).

The host 100 may write the storage command CMD_S and the storage address ADDR_S to the RAM 234 when performing a specific operation on the nonvolatile memory module 200 . At this time, the host 100 can allocate the specific area CA1 of the command area 234a for storing the storage command CMD_S and the storage address ADDR_S (1). That is, data recording and allocation of the command area 234a can occur at the same timing. The area CA1 allocated by the host 100 is an area for only the storage command CMD_S and the storage address ADDR_S and is not overwritten by other data. As will be described in detail later, in accordance with the update of the state information (STI), overwriting is possible only after the allocation of the area CA1 is released.

The DIMM controller 240 can access the RAM 234 and read the data stored in the RAM 234 (2). Then, at the same time, the DIMM controller 234 releases the allocation of the specific area CA1 in which the data was stored. According to the release by the DIMM controller 240, the area CA1 in which data is stored becomes overwritable (2). That is, the reading of data in the command area 234a and the release of the area allocation can occur at the same timing.

The first area manager 242 may generate state information regarding the area released by the DIMM controller 240 (3 & cir &). For example, the status information generated by the first area manager 242 includes an identification mark (e.g., a flag, etc.) indicating that the area CA1 in which data was stored has been unallocated and is overwritable .

The first area manager 242 can update the state information (STI) (4). For example, the status information (STI) may be stored in the status area 234d of the RAM 234. In the embodiment of the present invention, the state information STI_CA1 relating to the released area CA1 may be stored in the state area 234d.

The host 100 can access the status area 234d of the RAM 234 and read out the status information STI_CA1 (5). For example, the host 100 may periodically poll the RAM 234 to access the status area 234d, or access the RAM 234 using an interrupt method.

According to this operation method, the RAM 234 having a relatively small capacity can be efficiently used. That is, a subject storing data (i. E. Host 100 or DIMM controller 240) may actually store data in RAM 234 without pre-allocating the area to be stored in RAM 234 And allocates the area at the moment when it is done. As soon as the data stored in the RAM 234 is read, the area allocation is released by the subject (that is, the DIMM controller 240 or the host 100) available area can be used more flexibly.

5 is a block diagram illustrating a method of operating the storage system 10, in accordance with another embodiment of the present invention. In this embodiment, a description will be given of movement of data in accordance with a write operation, allocation of an area to a specific area of the RAM 234, release of area allocation, and update of the state information (STI).

First, the storage command CMD_S and the storage address ADDR_S relating to the write operation can be transferred from the host 100 to the RAM 234 (1). At this time, the host 100 can allocate the specific area CA1 of the command area 234a for storing the storage command CMD_S and the storage address ADDR_S (1). That is, data recording and allocation of the command area 234a can occur at the same timing. The area CA1 allocated by the host 100 is an area for only the storage command CMD_S and the storage address ADDR_S and is not overwritten by other data.

The DIMM controller 240 accesses the RAM 234 to read the storage command CMD_S and the storage address ADDR_S stored in the RAM 234 (2). Then, at the same time, the DIMM controller 234 releases the allocation of the specific area CA1 in which the storage command CMD_S and the storage address ADDR_S were stored (2). The area CA1 in which the storage command CMD_S and the storage address ADDR_S have been stored becomes a state in which overwriting is possible in accordance with the release by the DIMM controller 240. [ That is, the reading of data in the command area 234a and the release of the area allocation can occur at the same timing.

The first area manager 242 can generate the state information STI_CA1 related to the area CA1 released by the DIMM controller 240 (3). For example, the status information generated by the first area manager 242 includes an identification mark (e.g., a flag, etc.) indicating that the area CA1 in which data was stored has been unallocated and is overwritable . The first area manager 242 can update the state information STI_CA1 (4). For example, the status information STI_CA1 may be stored in the status area 234d of the RAM 234. [

The host 100 can access the status area 234d of the RAM 234 and read out the status information STI_CA1 (5). For example, the host 100 may periodically poll the RAM 234 to access the status area 234d, or access the RAM 234 using an interrupt method.

Write data (DATA_W) may be transferred from the host 100 to the RAM 234 (6) according to the storage command CMD_S related to the write operation. At this time, the host 100 can allocate the specific area WA1 of the write area 234b for storing the write data (DATA_W) (6). That is, the data write to the write area 234b and the allocation of the area can occur at the same timing. The area WA1 allocated by the host 100 is an area for only write data (DATA_W), and is not overwritten by other data.

The DIMM controller 240 can access the RAM 234 and read the write data (DATA_W) stored in the RAM 234 (7). Then, at the same time, the DIMM controller 234 cancels the allocation of the specific area WA1 where the data was stored (7). With the release by the DIMM controller 240, the area WA1 in which the write data (DATA_W) is stored becomes a state in which overwriting is possible. That is, the reading of data in the writing area 234b and the releasing of the area allocation can occur at the same timing.

The first area manager 242 can generate the state information STI_WA1 related to the area WA1 released by the DIMM controller 240 (8). For example, the state information generated by the first area manager 242 includes an identification mark (for example, a flag, etc.) indicating that the area WA1 in which data was stored has been deallocated and is overwritable . The first area manager 242 can update the state information STI_WA1 (9). For example, the status information STI_WA1 may be stored in the status area 234d of the RAM 234. [

The host 100 can access the status area 234d of the RAM 234 and read the status information STI_WA1 (10). For example, the host 100 may periodically poll the RAM 234 to access the status area 234d, or access the RAM 234 using an interrupt method.

The state information STI_CA1 of the area CA1 is updated and transferred to the host 100 and then the write data DATA_W is transferred to the write area 234b of the RAM 234. [ However, this is for convenience of explanation and understanding, and write data (DATA_W) can be transferred to the write area 234b even before the status information (STI_CA1) is updated. Of course, at this time, the write area 234b should have sufficient memory space to receive the write data (DATA_W) from the host 100. [

6 is a flowchart showing a write operation for the non-volatile memory module 200 according to an embodiment of the present invention. For ease of understanding, FIGS. 3 and 5 will be described with reference to FIG.

In step S11, the host 100 transfers the RAM command CMD_R for writing to the command area 234a of the RAM 234 and the RAM address ADDR_R for selecting the command area 234a to the RAM controller 232 ).

In step S12, the host 100 transfers the data signal DQ and the data strobe signal DQS for writing the storage command CMD_S and the storage address ADDR_S to the selected command area 234a in the nonvolatile memory module 200 ). For example, the storage command CMD_S may be a command for a write operation to the nonvolatile memory 280, and the storage address ADDR_S may be an address of the nonvolatile memory 280 where the write data DATA_W is to be stored .

With the transmission of the data signal DQ and the data strobe signal DQS, the host 100 can allocate the area CA1 in which the data signal DQ and the data strobe signal DQS are to be stored. According to the assignment by the host 100, the area CA1 can be in an overwrite impossible state. For example, steps S11 and S12 may be a transaction for the storage command CMD_S.

In step S13, the DIMM controller 240 reads the storage command CMD_S and the storage address ADDR_S stored in the command area 234a, and generates the state information STI_CA1. For example, the first area manager 242 provided in the DIMM controller 240 generates state information STI_CA1 indicating that the allocation of the area CA1 in which the storage command CMD_S and the storage address ADDR_S have been stored is released can do.

The host 100 can transmit the RAM command CMD_R and the RAM address ADDR_R for selecting the status area 234d of the RAM 234 to the nonvolatile memory module 200 in step S14.

In step S15, the host 100 can read the status information STI_CA1 stored in the status area 234d via the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS may include status information STI_CA1. Then, the host 100 can recognize that the area CA1 can be overwritten through the state information STI_CA1. For example, the host 100 may overwrite the next storage command into the area CA1.

In step S16, the host 100 sends a RAM command (CMD_R) for writing to the writing area 234b of the RAM 234 and a RAM address ADDR_R for selecting the writing area 234b to the RAM controller 232 ).

In step S17, the host 100 may transmit the data signal DQ and the data strobe signal DQS for writing the write data (DATA_W) to the non-volatile memory module 200 in the selected write area 234b. Along with the transfer of the data signal DQ and the data strobe signal DQS, the host 100 can allocate the area WA1 in which the data signal DQ and the data strobe signal DQS are to be stored. According to the assignment by the host 100, the area WA1 can be in a state in which it can not be overwritten. For example, steps S16 and S17 may be a transaction for write data (DATA_W).

In step S18, the DIMM controller 240 can read the write data (DATA_W) stored in the write area 234b and generate the state information (STI_WA1). For example, the first area manager 242 provided in the DIMM controller 240 can generate the state information STI_WA1 indicating that the area WA1 in which the write data DATA_W was stored is deallocated.

The host 100 can transmit the RAM command CMD_R and the RAM address ADDR_R for selecting the status area 234d of the RAM 234 to the nonvolatile memory module 200 in step S19.

In step S20, the host 100 can read the status information STI_WA1 stored in the status area 234d via the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS may include status information STI_WA1. Then, the host 100 can recognize that the area WA1 can be overwritten through the state information STI_WA1. For example, the host 100 may store the following write data in the area WA1.

According to the writing operation as described above, the RAM 234 having a relatively small capacity can be efficiently used. That is, by allocating space in which data is to be stored when data is stored in the RAM 234, and allocating the area in which the data was stored when the data is read from the RAM 234, area can be used more flexibly.

FIG. 7 is a block diagram illustrating a method of operating a storage system 10, in accordance with another embodiment of the present invention. In this embodiment, the movement of data in accordance with the read operation, the allocation of the area to the specific area of the RAM 234, the release of the area allocation, and the update of the status information (STI) will be described.

First, the storage command CMD_S and the storage address ADDR_S relating to the read operation can be transferred from the host 100 to the RAM 234 (1). At this time, the host 100 can allocate the specific area CA1 of the command area 234a for storing the storage command CMD_S and the storage address ADDR_S (1). That is, data recording and allocation of the command area 234a can occur at the same timing. The area CA1 allocated by the host 100 is an area for only the storage command CMD_S and the storage address ADDR_S and is not overwritten by other data.

The DIMM controller 240 accesses the RAM 234 to read the storage command CMD_S and the storage address ADDR_S stored in the RAM 234 (2). Then, at the same time, the DIMM controller 234 releases the allocation of the specific area CA1 in which the storage command CMD_S and the storage address ADDR_S were stored (2). The area CA1 in which the storage command CMD_S and the storage address ADDR_S have been stored becomes a state in which overwriting is possible in accordance with the release by the DIMM controller 240. [ That is, the reading of data in the command area 234a and the release of the area allocation can occur at the same timing.

The first area manager 242 can generate the state information STI_CA1 related to the area CA1 released by the DIMM controller 240 (3). For example, the status information generated by the first area manager 242 includes an identification mark (e.g., a flag, etc.) indicating that the area CA1 in which data was stored has been unallocated and is overwritable . The first area manager 242 can update the state information STI_CA1 (4). For example, the status information STI_CA1 may be stored in the status area 234d of the RAM 234. [

The host 100 can access the status area 234d of the RAM 234 and read out the status information STI_CA1 (5). For example, the host 100 may periodically poll the RAM 234 to access the status area 234d, or access the RAM 234 using an interrupt method.

The read data (DATA_R) may be transferred from the DIMM controller 240 to the RAM 234 in accordance with the storage command CMD_S related to the read operation (6). At this time, the DIMM controller 240 can allocate the specific area RA1 of the read area 234c for storing the read data (DATA_R) (6). That is, the recording of data to the read area 234c and the allocation of the area can occur at the same timing. The area RA1 allocated by the DIMM controller 240 is an area for only the read data (DATA_R), and is not overwritten by other data.

The host 100 can access the RAM 234 and read the read data (DATA_R) stored in the RAM 234 (7). Then, at the same time, the host 100 releases the allocation of the specific area RA1 in which the data is stored (7). With the release by the host 100, the area RA1 in which the read data (DATA_R) is stored becomes a state in which overwriting is possible. That is, the reading of data in the reading area 234c and the releasing of the area allocation can occur at the same timing.

The second area manager 110 can generate the state information STI_RA1 related to the area RA1 released by the DIMM controller 240 (8). For example, the status information generated by the second area manager 110 may include an identification mark (e.g., a flag or the like) indicating that overwriting is possible because the area RA1 in which the read data (DATA_R) ). The second area manager 110 can update the state information STI_RA1 (9). For example, the status information STI_RA1 may be stored in the status area 234d of the RAM 234. [

The DIMM controller 240 can access the status area 234d of the RAM 234 and read out the status information STI_RA1 (10). The DIMM controller 240 can perform the next write operation with reference to the state information (STI_RA1). For example, the DIMM controller 240 may overwrite the next write data in the area RA1 in which the write data (DATA_W) was stored.

The state information STI_CA1 of the area CA1 is updated and transferred to the host 100 and then the read data DATA_R is transmitted to the read area 234c of the RAM 234. [ However, this is for convenience and ease of explanation, and the read data (DATA_R) can be transferred to the read area 234c even before the status information (STI_CA1) is updated. Of course, at this time, the read area 234c should have sufficient memory space to receive the read data (DATA_R) from the DIMM controller 240.

FIG. 8 is a flowchart showing a write operation to the non-volatile memory module 200 according to another embodiment of the present invention. For ease of understanding, reference will be made to Figs. 3 and 7 together.

In step S31, the host 100 transfers the RAM command CMD_R for writing to the command area 234a of the RAM 234 and the RAM address ADDR_R for selecting the command area 234a to the RAM controller 232 ).

In step S32, the host 100 transfers the data signal DQ and the data strobe signal DQS for writing the storage command CMD_S and the storage address ADDR_S to the selected command area 234a in the nonvolatile memory module 200 ). For example, the storage command CMD_S is a command for a read operation to the nonvolatile memory 280, and the storage address ADDR_S is an address where the read data (DATA_R) to be read from the nonvolatile memory 280 is stored have.

With the transmission of the data signal DQ and the data strobe signal DQS, the host 100 can allocate the area CA1 in which the data signal DQ and the data strobe signal DQS are to be stored. According to the assignment by the host 100, the area CA1 can be in an overwrite impossible state. For example, steps S31 and S32 may be a transaction for the storage command CMD_S.

In step S33, the DIMM controller 240 reads the storage command CMD_S and the storage address ADDR_S stored in the command area 234a, and generates the state information STI_CA1. For example, the first area manager 242 provided in the DIMM controller 240 generates state information STI_CA1 indicating that the allocation of the area CA1 in which the storage command CMD_S and the storage address ADDR_S have been stored is released can do.

The host 100 can transmit the RAM command CMD_R and the RAM address ADDR_R for selecting the status area 234d of the RAM 234 to the nonvolatile memory module 200 in step S34.

In step S35, the host 100 can read the status information STI_CA1 stored in the status area 234d via the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS may include status information STI_CA1. Then, the host 100 can recognize that the area CA1 can be overwritten through the state information STI_CA1. For example, the host 100 may overwrite the next storage command into the area CA1.

In step S36, the host 100 sends a RAM command (CMD_R) for writing to the reading area 234c of the RAM 234 and a RAM address ADDR_R for selecting the reading area 234c to the RAM controller 232 ).

In step S37, the host 100 can receive the data signal DQ and the data strobe signal DQS from the non-volatile memory module 200 to read the read data (DATA_R) stored in the read area 234c have. Of course, when the read data (DATA_R) read from the nonvolatile memory 280 is stored in the read area 234c, the DIMM controller 240 sets the area RA1 in which the read data (DATA_R) data is stored Will be assigned. According to the allocation, the area RA1 will be in an overwrite impossible state. When the data signal DQ and the data strobe signal DQS are received from the nonvolatile memory module 200, the host 100 can release the allocation of the area RA1 in which the read data DATA_R was stored . With the release by the host 100, the area RA1 can be put in an overwriteable state. For example, steps S36 and S37 may be a transaction on the read data (DATA_R).

In step S38, the host 100 may read the read data (DATA_R) stored in the read area 234c and then generate the status information (STI_RA1). For example, the second area manager 110 provided in the host 100 can generate the state information STI_RA1 indicating that the area RA1 in which the read data (DATA_R) was stored has been deallocated.

The host 100 can transmit the RAM command CMD_R and the RAM address ADDR_R for selecting the status area 234d of the RAM 234 to the nonvolatile memory module 200 in step S39.

In step S40, the host 100 may store the status information STI_RA1 in the status area 234d via the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS may include status information STI_RA1. Then, the DIMM controller 240 can recognize that the area RA1 is overwritable through the state information (STI_RA1). For example, the DIMM controller 240 may store the following read data in the area RA1.

In step S41, the host 100 can determine whether or not the read operation is completed by referring to the read state information (STI_CA1) and the read data (DATA_R). If it is determined that the read operation is completed (Yes), the procedure is ended. On the other hand, if it is determined that the read operation is not completed (No), steps S37 to S40 may be repeatedly performed. That is, the host 100 receives the read data (DATA_W) via the data signal (DQ) and the data strobe signal (DQS), and updates the status data. As a result, in step S41, if all the read data DATA_R is read from the read area 234c, the read operation will end.

According to the writing operation as described above, the RAM 234 having a relatively small capacity can be efficiently used. That is, by allocating space in which data is to be stored when data is stored in the RAM 234, and allocating the area in which the data was stored when the data is read from the RAM 234, area can be used more flexibly.

FIG. 9 is a block diagram exemplarily showing any one of the non-volatile memories shown in FIG. 1. FIG. 9, the non-volatile memory 280 includes a memory cell array 281, an address decoder 282, a page buffer 283, an input / output circuit 284, and control logic and voltage generation circuit 285 can do.

The memory cell array 281 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) storing one bit or a multi level cell (MLC) storing at least two bits.

The address decoder 282 is connected to the memory cell array 281 through a plurality of word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 282 can receive the address ADDR_P from the external device and decode the received physical address ADDR_P to drive the plurality of word lines WL. For example, the address decoder 282 decodes the physical address ADDR_P received from the external device and generates at least one word line of the plurality of word lines WL based on the decoded physical address ADDR_P And may drive at least one selected word line. Illustratively, the physical address ADDR_P may indicate the physical address of the nonvolatile memory 280 to which the storage address ADDR_S is converted. The address conversion operation described above can be performed by the flash conversion layer (FTL) driven by the device controller 230 or the device controller 230. [

The page buffer 283 is connected to the memory cell array 281 through a plurality of bit lines BL. The page buffer 283 controls the bit lines BL so that the data (DATA) received from the input / output circuit 284 is stored in the memory cell array 281 under the control of the control logic and voltage generation circuit 285 . The page buffer 283 can read the data stored in the memory cell array 281 and transmit the read data to the input / output circuit 284 under the control of the control logic and voltage generation circuit 285. [ By way of example, the page buffer 283 may receive data on a page-by-page basis from the input / output circuit 284 or may read data on a page-by-page basis from the memory cell array 281.

The input / output circuit 284 can receive the data (DATA) from the external device and transfer the received data (DATA) to the page buffer 283. Or input / output circuit 284 may receive data (DATA) from page buffer 283 and transfer the received data (DATA) to an external device (e.g., DIMM controller 230). For example, the input / output circuit 284 can transmit and receive data (DATA) with an external device in synchronization with the control signal CTRL.

The control logic and voltage generation circuit 285 receives the storage command CMD_S and the control signal CTRL from the external device and generates an address decoder 282, a page buffer 283, and an input / (284). For example, the control logic and voltage generation circuitry 285 may control other components so that the data (DATA) is stored in the memory cell array 281 in response to signals CMD_S, CTRL. Or control logic and voltage generation circuitry 285 may control other components such that data (DATA) stored in memory cell array 281 is transferred to an external device in response to signals CMD_S and CTRL. For example, the storage command CMD_S received from the external device may be a modified command of the storage command CMD_S of FIG. The control signal CTRL may be a signal that the device controller 230 provides to control the non-volatile memory 280.

The control logic and voltage generation circuit 285 may generate various voltages required for the non-volatile memory 280 to operate. For example, the control logic and voltage generation circuitry 285 may include a plurality of programmable voltages, a plurality of pass voltages, a plurality of selected read voltages, a plurality of unselected read voltages, a plurality of erase voltages, Can generate various voltages such as voltages. The control logic and voltage generation circuit 285 may provide the various voltages generated to the address decoder 282 or to the substrate of the memory cell array 281.

10 is a circuit diagram showing an example of any one of the memory blocks included in the memory cell array of FIG. Illustratively, a memory block BLK1 of a three-dimensional structure will be described with reference to Fig. However, the scope of the present invention is not limited thereto, and other memory blocks included in each of the plurality of nonvolatile memories 280 may have a structure similar to that of the memory block BLK1.

Referring to FIG. 10, the memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row.

For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form a first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes the string selected transistors SSTa and SSTb, the plurality of memory cells MC1 to MC8, the ground selected transistors GSTa and GSTb, And dummy memory cells DMC1, DMC2. Illustratively, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and are stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selected transistors SSTa and SSTb are connected in series and the strings of selected transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selected transistors GSTa and GSTb are connected in series and the grounded selected transistors GSTa and GSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

Illustratively, a first dummy memory cell DMC1 may be provided between a plurality of memory cells MC1 to MC8 and ground selected transistors GSTa and GSTb. Illustratively, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string selected transistors SSTa and SSTb.

The ground selected transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be connected in common to the ground selection line GSL. By way of example, the ground selected transistors in the same row can be connected to the same ground select line, and the ground selected transistors in the other row can be connected to different ground select lines. For example, the first ground selected transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selected transistors GSTa of the cell strings CS21, CS12 of the second row The first ground selected transistors (GSTa) may be connected to the second ground selection line.

Illustratively, although not shown in the drawings, the ground selected transistors provided at the same height from the substrate (not shown) may be connected to the same ground select line, and the ground selected transistors provided at different heights may be connected to another ground select line . For example, the first ground selected transistors (GSTa) of the cell strings (CS11, CS12, CS21, CS22) are connected to a first ground selection line and the second ground selection transistors (GSTb) Line. ≪ / RTI >

Memory cells of the same height from the substrate (or ground selected transistors GSTa, GSTb) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, cell strings The first to eighth memory cells MC8 of the memory cells CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Strings of the same row among the first string selected transistors (SSTa) of the same height are connected to the same string selection line, and the other strings of string selected transistors are connected to another string selection line. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL1a.

Likewise, string selected transistors of the same row of the second string selected transistors (SSTb) of the same height are connected to the same string select line, and the other strings of string selected transistors are connected to different string select lines. For example, the second string selected transistors SSTb of the cell strings CS11, CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21, CS22 of the second row ) Are connected in common with the string selection line SSL2b.

Although not shown in the figure, string selected transistors of cell strings in the same row may be connected in common to the same string select line. For example, the first and second string selected transistors (SSTa, SSTb) of the cell strings CS11, CS12 of the first row may be connected in common to the same string selection line. The first and second string selected transistors (SSTa, SSTb) of the cell strings CS21, CS22 of the second row may be connected in common to the same string selection line.

Illustratively, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

In the memory block BLK1, reading and writing can be performed line by line. For example, one row of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, when the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11, CS12 are connected to the bit lines BL1, BL2. When the turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and the turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row are supplied with bit Connected to the lines BL1 and BL2 and driven. Memory cells of the same height among the memory cells of the cell strings of the row driven by driving the word lines are selected. Read and write operations can be performed on selected memory cells. Selected memory cells may form a physical page unit.

In the first memory block BLK1, erasing may be performed in units of memory blocks or units of subblocks. When erasing is performed in units of memory blocks, all the memory cells MC of the first memory block BLK1 can be erased simultaneously according to one erase request. When performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK1 may be simultaneously erased in response to one erase request, and some of the memory cells MC of the first memory block BLK1 may be erased. A low voltage (e. G., Ground voltage) is applied to the word line connected to the erased memory cells, and the word line connected to the erased memory cells can be floated.

Illustratively, the illustrated memory block BLK1 is exemplary and the number of cell strings may be increased or decreased, and the number of rows and columns comprised by the cell strings may be increased or decreased depending on the number of cell strings have. The number of the cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, and the height of the memory block BLK1 may be increased according to the number of cell transistors Or may be reduced. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

FIG. 11 is a block diagram illustrating a computing system to which a non-volatile memory module according to the present invention is applied. 11, a computing system 1000 includes a processor 1100, non-volatile memory modules 1200 and 1201, RAM modules 1300 and 1301, a chipset 1400, a GPU 1500, an input / 1600, and a storage device 1700.

The processor 1100 may control all operations of the computing system 1000. The processor 1100 may perform various operations performed in the computing system 1000.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may be directly connected to the processor 1100. For example, each of the non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may have the form of a dual in-line memory module (DIMM). Alternatively, each of the non-volatile memory modules 1200, 1201 and the RAM modules 1300, 1301 may be mounted in a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100. Illustratively, the non-volatile memory modules 1200 and 1201 may be the non-volatile memory modules described with reference to FIGS.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate with the processor 1100 via the same interface 1150. For example, the non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate through a DDR (Double Data Rate) interface 1150. Illustratively, processor 1100 may use RAM modules 1300 and 1301 as operational memory, buffer memory, or cache memory of computing system 1000.

The chipset 1400 is electrically connected to the processor 1100 and can control the hardware of the computing system 1000 under the control of the processor 1100. [ For example, the chipset 1400 may be connected to the GPU 1500, the input / output device 1600, and the storage device 1700 via the main buses, respectively, and may serve as a bridge to the main buses.

The GPU 1500 may perform a series of arithmetic operations to output image data of the computing system 1000. Illustratively, GPU 1500 may be implemented within processor 1100 in a system-on-chip form.

The input / output device 1600 includes various devices that input data or instructions to the computing system 1000 or output data to the outside. For example, the input / output device 1600 may include a user input device such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, Liquid Crystal Display), OLED (Organic Light Emitting Diode) display device, AMOLED (Active Matrix OLED) display device, LED, speaker, motor and the like.

The storage device 1700 may be used as a storage medium of the computing system 1000. Storage device 1600 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.

Illustratively, the non-volatile memory modules 1200 and 1201 may be used by the processor 1100 as a storage medium of the computing system 1000. The interface 1150 between the non-volatile memory modules 1200 and 1201 and the processor 1100 may be a higher speed interface than the interface between the storage device 1700 and the processor 1100. [ That is, the performance of the computing system is improved by the processor 1100 using the nonvolatile memory modules 1200 and 1201 as a storage medium.

The non-volatile memory modules 1200 and 1201 may include an SRAM having a structure optimized for an interface protocol with the processor 1100. That is, the processor 1100 can provide instructions, addresses, and data for accessing the non-volatile memory to the non-volatile memory modules 1200 and 1201 through a plurality of RAMs, which are divided into bank groups or bank units will be.

FIG. 12 is a block diagram illustrating one of the non-volatile memory modules of FIG. 11; FIG. Illustratively, FIG. 12 shows a non-volatile memory module 1200 having the form of a Load Reduced DIMM (LRDIMM). 12 may be in the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 1100 .

12, the non-volatile memory module 1200 includes a device controller 1210, a non-volatile memory device 1220, a buffer 1230, and a Serial Presence Detect chip 1240 . The device controller 1210 may include a RAM 1211. Illustratively, non-volatile memory device 1220 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1220 may be implemented as a separate chip, a separate package, a separate device, or a separate module, respectively. Or non-volatile memory device 1220 may be implemented as a single chip or as a single package.

The device controller 1210, the RAM 1211, the nonvolatile memory device 1220 and the buffer 1230 are illustratively connected to the device controller 210, the RAM 234, the buffer 290, And a plurality of non-volatile memories 280, which are the same or similar. The non-volatile memory module 1200 may include an SRAM having a structure optimized for an interface protocol with the processor 1100. That is, the processor 1100 transmits a command, address, and data for accessing the non-volatile memory device 1220 to the non-volatile memory modules 1200 and 1205 through the RAM 1211, which is divided into bank groups or bank units. . ≪ / RTI >

Illustratively, the device controller 1210 can send and receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100, and receives a RAM command CMD_R via separate signal lines. The RAM address ADDR_R, and the clock CK.

SPD 1240 may be a programmable read-only memory (EEPROM). SPD 1240 may include initial information or device information of non-volatile memory module 1200. Illustratively, SPD 1240 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 1300. When the computing system including the non-volatile memory module 1200 is booted, the processor 1100 of the computing system can read the SPD 1240 and recognize the non-volatile memory module 1200 based on the SPD 1240. The processor 1100 may use the nonvolatile memory module 1200 as a storage medium based on the SPD 1240.

Illustratively, the SPD 1240 may communicate with the processor 1100 via a Side-Band Communication Channel. The processor 1100 may exchange a side-band signal (SBS) with the SPD 1240 through an additional communication channel. Illustratively, the SPD 1240 may communicate with the device controller 1210 via an additional communication channel. Illustratively, the supplemental communication channel may be a channel based on I2C communication. Illustratively, SPD 1240, device controller 1210, and processor 1100 may communicate with each other or exchange information based on I2C communications.

FIG. 13 is a block diagram illustrating one of the non-volatile memory modules of FIG. 11 by way of example. Illustratively, FIG. 13 is a block diagram of a non-volatile memory module 2200 in the form of a Registered DIMM (RDIMM). Illustratively, the non-volatile memory module 2200 shown in FIG. 13 is in the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .

13, the non-volatile memory module 2200 includes a device controller 2210, a non-volatile memory device 2220, a buffer 2230, a Serial Presence Detect chip 2240, And a data buffer circuit 2250. The device controller 2210 includes a RAM 2211. Since the device controller 2210, the RAM 2211, the nonvolatile memory device 2220, and the SPD 2240 have been described with reference to FIGS. 1 and 12, a detailed description thereof will be omitted.

The data buffer circuit 2250 receives information or data from the processor 1100 (see FIG. 11) via the data signal DQ and the data strobe signal DQS and forwards the received information or data to the device controller 2250 . Or data buffer circuit 2250 may receive information or data from device controller 2210 and may pass the received information or data to processor 1100 via data signal DQ and data strobe signal DQS.

Illustratively, data buffer circuit 2250 may include a plurality of data buffers. Each of the plurality of data buffers can exchange data signals DQ and data strobe signals DQS with the processor 1100. Or each of the plurality of data buffers can exchange signals with the device controller 2210. Illustratively, each of the plurality of data buffers may operate under the control of a device controller 2210.

By way of example, the device controller 2210 may include a RAM 2211 of a structure optimized for an interface protocol with the processor 1100. That is, the processor 1100 can provide instructions, addresses, and data for accessing the non-volatile memory 2230 to the non-volatile memory module 2200 through the RAM 2211, which is divided into bank groups or bank units There will be.

FIG. 14 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied. For the sake of brevity, a detailed description of the components described above is omitted. 14, a computing system 3000 includes a processor 3100, a non-volatile memory module 3200, a chipset 3400, a GPU 3500, an input / output device 3600, and a storage device 3700 . The processor 3100, the chipset 3400, the GPU 3500, the input / output device 3600, and the storage device 3700 are substantially the same as those described with reference to FIG. 11, and a detailed description thereof will be omitted.

The non-volatile memory module 3200 may be directly coupled to the processor 3100. For example, the non-volatile memory module 3200 may take the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 3100.

The non-volatile memory module 3200 may include a control circuit 3210, a non-volatile memory device 3220, and a ram device 3230. Unlike the non-volatile memory modules 1200 and 2200 of Figures 11-13, the processor 3100 can access the non-volatile memory device 3220 and the RAM 3230 of the non-volatile memory module 3200, respectively . As a more detailed example, the control circuit 3210 may store the received data in the non-volatile memory device 3220 or in the RAM device 3230 under the control of the processor 3100. Or control circuitry 3210 may transfer data stored in non-volatile memory device 3220 to processor 3100 or transmit data stored in RAM 3230 to processor 3100 under the control of processor 3100 . That is, the processor 3100 can recognize the nonvolatile memory device 3220 and the RAM 3230 included in the nonvolatile memory module 3200, respectively. The processor 3100 may store data in the non-volatile memory device 3220 of the non-volatile memory module 3200 or may read the stored data. Or processor 3100 may store data in RAM 3230 or read stored data.

Processor 3100 may use nonvolatile memory device 3220 of nonvolatile memory module 3200 as a storage medium of computing system 3000 and processor 3100 may use nonvolatile memory module 3200 as non- The RAM 3230 of the computing system 3000 can be used as the main memory of the computing system 3000. That is, the processor 3100 can selectively access the nonvolatile memory device or the RAM device included in one memory module mounted in one DIMM socket, respectively.

Illustratively, processor 3100 may communicate with non-volatile memory module 3200 via a double data rate (DDR) interface 3300.

15 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. Referring to FIG. 15, a non-volatile memory module 3200 includes a control circuit 3210, a non-volatile memory device 3220, and a RAM device 3220. By way of example, non-volatile memory device 3220 may comprise a plurality of non-volatile memories, and RAM device 3230 may comprise a plurality of DRAMs. By way of example, a plurality of non-volatile memories may be used by the processor 3100 as storage for the computing system 3000. Illustratively, each of the plurality of nonvolatile memories (NVMs) may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a ReRAM ), STT-MRAM (Spin-Torque Magnetic RAM), and the like.

The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000. By way of example, RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, MRAM, and the like.

The control circuit 3210 includes a device controller 3211 and an SPD 3212. The device controller 3211 can receive the command CMD, the address ADDR, and the clock CK from the processor 3100. [ Device controller 3211 responds to signals received from processor 3100 to transfer data received via data signal DQ and data strobe signal DQS to nonvolatile memory device 3220 or ram device 3230. [ As shown in FIG. Or the device controller 3211 responds to signals received from the processor 3100 to transfer the data stored in the nonvolatile memory device 3220 or the RAM device 3230 to the data signal DQ and the data strobe signal DQS Lt; RTI ID = 0.0 > 3100 < / RTI >

Illustratively, processor 3100 may optionally access non-volatile memory device 3220 or ram device 3230 via command CMD, address ADDR, or a separate signal or separate information. That is, the processor 3100 can selectively access the non-volatile memory device 3220 or the RAM device 3230 included in the non-volatile memory module 3200. [ Illustratively, the device controller 3211 stores the subdata in RAM (not shown) according to the operating method described in Figures 1-12, and stores the subdata in nonvolatile memory device 3220 Can be programmed.

16 is a block diagram exemplarily showing the nonvolatile memory module of FIG. Illustratively, the non-volatile memory module 4200 of FIG. 16 has the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

14 and 16, the non-volatile memory module 4200 includes a control circuit 4100, a non-volatile memory device 4220, and a RAM 4230. The control circuit 4210 includes a device controller 4211, an SPD 4212, and a data buffer circuit 4213.

The device controller 4211 receives the command CMD, the address ADDR, and the clock CK from the processor 3100. The device controller 4211 may control the non-volatile memory device 4220 or the RAM device 4230 in response to the received signals. The processor 3100 may selectively access each of the non-volatile memory device 4220 or the RAM device 4230. The device controller 4231 can control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100. [

The data buffer circuit 4213 can receive the data signal DQ and the data strobe signal DQS from the processor 3100 and provide the received signals to the device controller 4211 and the RAM device 4230. [ Or the data buffer circuit 4213 may provide the data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.

Illustratively, when the processor 3100 stores data in the nonvolatile memory device 4220, the data received via the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 can process the received data and provide it to the nonvolatile memory device 4220. Or the processor 3100 reads data stored in the nonvolatile memory device 4220, the data buffer circuit 4213 supplies the data provided from the device controller 4211 to the data signal DQ and the data strobe signal DQS, Lt; / RTI > to the processor 3100 via the network interface. Or the processor 3100 stores data in the RAM device 4230 the data received by the data buffer circuit 4213 is provided to the RAM device 4230 and the device controller 4231 receives the received command CMD, The address ADDR, and the clock CK to the RAM device 4230. Or when the processor 3100 reads data stored in the RAM device 4230, the device controller 4231 transfers the received command CMD, the address ADDR, and the clock CK to the RAM device 4230 , The RAM device 4230 provides the data to the data buffer circuit 4213 in response to the transmitted signals and the data buffer circuit 4213 supplies the data signal DQ and the data strobe signal DQS, And may provide data to the processor 3100. By way of example, the device controller 3211 can accumulate subdata in a RAM (not shown) according to the operating method described in FIG. 1 and program it into the non-volatile memory device 4220 in accordance with the instructions of the processor 3100 have.

17 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 14, the non-volatile memory module 5200 includes a control circuit 5210, a non-volatile memory device 5220, and a RAM device 5230. [ The control circuit 5210 includes a device controller 5211 and an SPD 5212. The non-volatile memory module 5200 may operate similarly to the non-volatile memory module 4200 of FIG. However, the nonvolatile memory module 5200 does not include the data buffer circuit 4213 unlike the nonvolatile memory module 4200 of FIG. That is, the nonvolatile memory module 5200 of FIG. 17 directly supplies the data received from the processor 3100 via the data signal DQ and the data strobe signal DQS to the device controller 5211 or the RAM device 5230 can do. Alternatively, the data from the device controller 5211 of the nonvolatile memory module 5200 of FIG. 17 or the data from the RAM device 5230 are supplied to the processor 3100 (FIG. 17) via the data signal DQ and the data strobe signal DQS. ).

16 may be a memory module in the form of an LRDIMM (Load Reduced DIMM), and the nonvolatile memory module 5200 in FIG. 17 may be a memory module in the form of a Registered DIMM (RDIMM) .

Illustratively, the device controller 5211 will include a RAM having the configuration and arrangement as described in FIGS. 1-8.

18 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 18, the server system 6000 may include a plurality of server racks 6100. Each of the plurality of server racks 6100 may include a plurality of non-volatile memory modules 6200. The plurality of non-volatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6100. For example, the plurality of non-volatile memory modules 6200 may take the form of a dual in-line memory module and may be mounted in a DIMM socket electrically coupled to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 6200 may be used as storage for the server system 6000.

The nonvolatile memory and / or device controller according to the present invention can be mounted using various types of packages. For example, the non-volatile memory and / or device controller according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) WSP), and the like.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

10: Storage Systems
100: Host
110: First area manager
200: Nonvolatile memory module
210: Device controller
220: Processor
230: physical layer
232: RAM controller
234: RAM
240: DIMM controller
242: Second Zone Manager
250: Nonvolatile memory interface
260: ROM
270: Buffer manager
280: Nonvolatile memory

Claims (10)

At least one non-volatile memory; And
And a DIMM controller for controlling data exchange between the RAM and the at least one nonvolatile memory, wherein the DIMM controller controls data exchange between the host and the at least one nonvolatile memory,
Wherein the allocation to the access area upon access to the RAM is performed in a write transaction that writes data to the RAM and the release of the allocation is performed in a read transaction of the written data. The method according to claim 1,
In a write operation to the nonvolatile memory module,
The host allocates an area in which the data is to be stored when storing the data in the RAM, and the DIMM controller is a non-volatile memory that releases the allocation to the area where the data was stored when the data is read from the RAM. module. The method according to claim 1,
In a read operation for the nonvolatile memory module,
Wherein the DIMM controller allocates an area in which the data is to be stored when the data is stored in the RAM, and the host is a nonvolatile memory that releases the allocation to the area in which the data is stored when the data is read from the RAM. module. The method according to claim 1,
Wherein the DIMM controller includes an area manager for generating status information regarding whether the DIMM controller has read the data stored in the RAM. 5. The method of claim 4,
Wherein the RAM comprises a status area for storing status information. Host; And
And a DIMM controller for controlling data exchange between the RAM and the at least one non-volatile memory, wherein the at least one non-volatile memory is a memory that stores data exchanged between the host and the at least one non-volatile memory, A non-volatile memory module comprising a device controller,
Wherein allocation to the access area upon access to the RAM is performed in a write transaction that writes data to the RAM and release of the allocation is performed in a read transaction of the written data. The method according to claim 6,
In a write operation to the nonvolatile memory module,
Wherein the host allocates the area in which the data is to be stored when the data is stored in the RAM and releases the allocation to the area in which the data is stored when the DIMM controller reads the data from the RAM. 8. The method of claim 7,
Wherein the DIMM controller includes a first area manager for generating status information regarding whether the DIMM controller has read the data stored in the RAM. The method according to claim 6,
In a read operation for the nonvolatile memory module,
Wherein the DIMM controller allocates an area in which the data is to be stored when the data is stored in the RAM and releases the allocation to an area in which the data is stored when the host reads the data from the RAM. 10. The method of claim 9,
Wherein the host includes a second area manager for generating status information about whether the host has read the data stored in the RAM.

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