KR102290988B1 - Nonvolatile memory module and operating method thereof - Google Patents

Abstract

A nonvolatile memory module according to an embodiment of the present invention may include at least one nonvolatile memory and a device controller. The device controller may include a device controller that receives data and an error correction code from a host, detects an error in the data using the error correction code, and corrects an error in the data. The device controller may load and drive an error correction module to correct an error in the data. According to an embodiment of the present invention, the chip size of the nonvolatile memory module can be reduced. Also, by managing error information so that it can be transmitted to the host, reliability of data reception from the host can be improved.

Description

Nonvolatile memory module and operating method thereof

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory module.

The semiconductor memory device may be largely divided into a volatile semiconductor memory device and a non-volatile semiconductor memory device. The volatile semiconductor memory device has an advantage of high read and write speeds, but has a disadvantage in that stored data disappears when power supply is cut off. On the other hand, in the nonvolatile semiconductor memory device, stored data is preserved even when power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be preserved regardless of whether power is supplied or not.

Recently, many studies have been made to improve the communication speed between the host and data storage. For example, there is a study to improve communication speed by mounting a flash memory in a memory (eg, DRAM, etc.) slot. However, in this case, it is essential to maintain compatibility with the existing interface and secure data reliability. Therefore, it is emerging as an important issue to develop a flash memory device capable of maintaining compatibility with an existing interface and ensuring data reliability.

An object of the present invention is to reduce the chip size of a nonvolatile memory module by performing error detection of data received from a host using hardware and error correction using firmware.

Another object of the present invention is to improve reliability of data reception from a host by managing error information so that it can be transmitted to a host.

A nonvolatile memory module according to an embodiment of the present invention receives at least one nonvolatile memory and data and an error correction code from a host, detects an error in the data using the error correction code, and and a device controller for correcting an error, wherein the device controller may correct an error of the data by executing an error correction module.

In an embodiment, the host and the nonvolatile memory module may communicate through a dual data rate (DDR) interface.

In another embodiment, the nonvolatile memory module may be a dual in-line memory module (DIMM).

As another embodiment, the device controller includes a RAM in which the data is stored, a physical layer that interfaces with the host, and a DIMM controller that controls data exchange between the RAM and the nonvolatile memory. may include

As another embodiment, the DIMM controller may include an error detector implemented in hardware for detecting an error in the data.

As another embodiment, the DIMM controller includes a stream packet generator that processes the data in the form of a stream packet and transmits it to the nonvolatile memory, and, when an error in the data is not corrected, the data related to the uncorrected data It may further include a state information generator for updating the state information.

As another embodiment, the DIMM controller may transmit the status information to the RAM.

As another embodiment, the status information may be accessed by the host and referenced for retransmitting the data by the host.

In another embodiment, the data includes a storage command, a storage address, and write data, and the RAM includes a read area in which the storage command and the storage address are stored, a write area in which the write data is stored, and the storage. It may include a status area in which status information regarding whether the execution of the command has been completed is stored.

As another embodiment, the error correction module may be loaded from the nonvolatile memory or a ROM included in the device controller.

A nonvolatile memory module according to an embodiment of the present invention includes at least one nonvolatile memory, and receives data and an error correction code from a host, detects an error in the data using the error correction code, and includes an error correction module a device controller configured to correct an error of the data by executing A physical layer including a RAM, a DIMM controller controlling data exchange between the RAM and the nonvolatile memory, and a processor executing the error correction module may be included.

In an embodiment, the DIMM controller may include an error detector for detecting an error in the data, and a state information generator for updating state information on the uncorrected data when the error in the data is not corrected. .

In another embodiment, the state information may be stored in the RAM, and the state information may be accessed by the host to be referred to by the host to retransmit the data.

In another embodiment, the host and the nonvolatile memory module may communicate through a dual data rate (DDR) interface.

As another embodiment, the nonvolatile memory module may be a dual in-line memory module (DIMM).

According to an embodiment of the present invention, error detection of data received from the host is performed using hardware and error correction is performed using firmware, thereby reducing the chip size of the nonvolatile memory module.

According to another embodiment of the present invention, the reliability of data reception from the host may be improved by managing error information to be transmitted to the host.

1 is a block diagram illustrating a storage system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of the data storage shown in FIG. 1 in more detail.
FIG. 3 is a block diagram exemplarily showing the data storage and software layers shown in FIG. 2 .
FIG. 4 is a block diagram showing in detail the structure of the RAM shown in FIG. 2 .
FIG. 5 is a flowchart illustrating a write operation to the data storage shown in FIG. 2 .
6 is a flowchart illustrating a read operation for the data storage shown in FIG. 2 .
7 is a block diagram exemplarily illustrating data communication between the host 100 and data storage.
8 is a block diagram illustrating a process of detecting and correcting an error according to an embodiment of the present invention.
9 is a block diagram showing the DIMM controller shown in FIG. 8 in more detail.
FIG. 10 is a block diagram showing in more detail another embodiment of the DIMM controller shown in FIG. 8 .
11 is a flowchart illustrating a method of detecting and correcting an error in data received from a host in the storage system of the present invention.
12 is a flowchart illustrating a method of operating a device controller according to an embodiment of the present invention.
13 is a flowchart illustrating a method of operating a device controller according to another embodiment of the present invention.
FIG. 14 is a block diagram exemplarily showing any one of the nonvolatile memories shown in FIG. 2 .
15 is a circuit diagram illustrating an example of any one of memory blocks included in the memory cell array of FIG. 14 .
16 is a block diagram exemplarily showing a computing system to which a nonvolatile memory module according to the present invention is applied.
17 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 16 .
18 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 16 .
19 is a block diagram illustrating another example of a computing system to which a nonvolatile memory module according to the present invention is applied.
20 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 .
21 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 .
22 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 .
23 is a diagram exemplarily illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and it is to be considered that an additional description of the claimed invention is provided. Reference signs are indicated in detail to preferred embodiments of the present invention, examples of which are indicated in the reference drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

When an element or layer is referred to as being “connected”, “coupled to,” or “adjacent to” another element or layer, it may be directly connected to, coupled to, or adjacent to the other element or layer; Alternatively, it will be appreciated that there may be elements or layers sandwiched therebetween. As used herein, the term “and/or” shall include one or more possible combinations of the listed elements.

Although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms may only be used to distinguish one component from others. Accordingly, terms such as a first component, a section, and a layer used in this specification may be used as a second component, a section, a layer, etc. without departing from the spirit of the present invention.

The terms “below,” “below,” “above,” “above,” and similar terms include both directly and indirectly disposed of. And, these spatially relative terms should be understood to include other directions in addition to the directions shown in the drawings. For example, if the device is turned over, elements described as "below" will be "above".

The terminology described herein is only used for the purpose of describing specific embodiments, and is not limited thereto. A term such as “a” is to be understood to include plural forms, unless expressly indicated otherwise. Terms such as “comprising” or “consisting of” specify the presence of a described feature, step, operation, component, and/or component, and include additional one or more features, steps, operations, components, components, and /or do not exclude the existence of their group.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the technical idea of the present invention.

1 is a block diagram illustrating a storage system 10 according to an embodiment of the present invention. Referring to FIG. 1 , a storage system 10 may include a host 100 and a data storage 200 .

The host 100 may access the data storage 200 to perform a read operation or a write operation on the data storage 200 . The host 100 may access the physical layer 230 of the device controller 210 . The host 100 may include an ECC encoder 110 and an ECC decoder 120 . The ECC encoder 120 may encode data transmitted to the data storage 200 . For example, the ECC encoder 120 adds an error correcting code parity (ECC parity) to data (eg, storage command, read data, write data, etc.) transmitted to the data storage 200 . can be transmitted. The ECC parity may be used to correct whether there is an error in the data transmitted to the data storage 200 and correct the error. The ECC decoder 120 may determine whether there is an error by decoding data (eg, read data) transmitted from the data storage 200 .

The data storage 200 may include a device controller 210 that controls the overall operation of the data storage 200 . The device controller 210 may include a DIMM PHY (ie, a physical layer) 230 for interfacing with the host 100 . The data storage 200 may be connected to the host 100 through a high-speed interface such as a dual in-line memory module (DIMM) interface. That is, the DIMM PHY 220 may interface with the host 100 according to a dual data rate (eg, DDR2, DDR3, DDR4, etc.) protocol. The device controller 210 may include a DIMM controller 240 that controls transmission/reception of data between the physical layer 230 and the nonvolatile memory 280 . The DIMM controller 240 may include an error detector 244 that determines whether there is an error in the data received from the host 100 .

According to an embodiment of the present invention, the device controller 210 checks whether there is an error in the data received from the host using hardware (ie, the error detector 244 ). Then, the device controller 210 corrects the detected error by driving the error correction firmware. That is, the chip size can be reduced by performing error detection using hardware and error correction using firmware.

FIG. 2 is a block diagram showing the configuration of the data storage 200 shown in FIG. 1 in more detail. Referring to FIG. 2 , the data storage 200 may include a device controller 210 , a nonvolatile memory 280 , and a buffer 290 .

The device controller 210 includes at least one processor 220 , a DIMM PHY (ie, a physical layer) 230 , a DIMM controller 240 , a nonvolatile memory interface 250 , a ROM 260 , and a buffer manager 270 . ) may be included.

The processor 220 may control the overall operation of the device controller 210 . The processor 220 may drive firmware for driving the device controller 210 . For example, the processor 210 may load and drive firmware for correcting an error detected by the error detector 244 . For example, the firmware may be loaded and driven in various storage spaces such as a cache memory or a buffer 290 provided in the processor 220 .

The DIMM PHY 230 may include a RAM controller 232 that receives a RAM command CND_R, a RAM address ADDR_R, and a clock CK from the host 100 . In addition, the DIMM PHY 230 may include a RAM 234 that stores data exchanged with the host 100 using the data DQ and the data strobe signal DQS. In this case, data CMD_S, ADDR_S, DATA, and STI may be stored in a space of the RAM 234 designated according to the RAM address ADDR_R received from the host 100 . In this case, the data received from the host may be encoded data to which ECC parity is added.

The RAM 234 may be divided into an area storing a storage command CMD_S and a storage address ADDR_S, an area storing data DATA, and an area storing state information STI. However, the present invention is not limited thereto, and the RAM 234 may be implemented as a single ring buffer that stores the storage command CMD_S, the storage address ADDR_S, the data DATA, and the state information STI.

The DIMM controller 240 may access the RAM 234 to process data stored in the RAM 234 . For example, the DIMM controller 240 may read write data to be stored in the nonvolatile memory 280 and transmit it to the nonvolatile memory 280 . In addition, the DIMM controller 240 may transfer data read from the nonvolatile memory 280 to the RAM 234 . For example, the DIMM controller 240 may include an error detector 244 that detects an error in encoded data (eg, CMD_S, ADDR_S, DATA, etc.) transmitted from the host 100 .

The nonvolatile memory interface 250 may provide an interface between the device controller 210 and the nonvolatile memory 280 . For example, the device controller 210 may transmit/receive data to and from the nonvolatile memory 280 through the nonvolatile memory interface 250 .

The ROM 260 may store various operations or firmware required to operate the device controller 210 . For example, ROM 260 may store firmware that corrects errors detected by error detector 244 . In addition, the ROM 260 may store code data for interfacing with the host 100 .

The buffer manager 270 may provide an interface between the device controller 210 and the buffer 290 .

The nonvolatile memory 280 may include a 3D memory array. A three-dimensional memory array may be formed monolithically on one or more physical levels of an array of memory cells having an active area disposed over a silicon substrate and circuitry associated with operation of the memory cells. The circuitry involved in the operation of the memory cells may be located in or on the substrate. The term monolithi234al means that the layers of each level of the three-dimensional array are deposited directly over the layers of the lower level of the three-dimensional array.

As an exemplary embodiment according to the inventive concept, a 3D memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is positioned on another memory cell. At least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor positioned over memory cells. The at least one selection transistor may have the same structure as the memory cells, and may be monolithically formed together with the memory cells.

A three-dimensional memory array is composed of a plurality of levels, has word lines or bit lines shared between the levels, and a configuration suitable for a three-dimensional memory array is described in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466. No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011/0233648, which are incorporated herein by reference. However, the present invention is not limited thereto, and the nonvolatile memory 280 may include a planar type memory array.

The nonvolatile memory 280 may be connected to the nonvolatile memory interface 240 through a plurality of channels CH. For example, the nonvolatile memory 280 may include at least one of nonvolatile memories such as flash memory, phase-change 234cndom access memory (P234cM), resistive 234cM (R234cM), magnetic 234cM (M234cM), and ferroelectric 234cM (Fe234cM). may include

The buffer 290 may be used as a buffer memory, a working memory, or a cache memory of the device controller 210 . For example, the buffer memory 290 may include various random access memories such as dynamic random access memory (DRAM), static random access memory (SRAM), and phase-change RAM (PRAM).

The device controller 210 according to an embodiment of the present invention detects an error in the encoded data received from the host using hardware (ie, the error detector 240 ). Then, the device controller 210 drives the firmware to correct the detected error. That is, the chip size of the semiconductor device can be reduced by correcting the error using firmware instead of using hardware to correct the error.

FIG. 3 is a block diagram exemplarily showing the data storage and software layers shown in FIG. 2 . Referring to FIG. 2 , the host layer software 100 ′ may be driven by the host. In addition, software or firmware 200 ′ of a nonvolatile memory layer may be driven in the data storage 200 .

Various software may be run in the host layer 100'. For example, the application 101 ′ and the operating system 102 ′ may be included in the host upper layer HL1 . The application 101' may be driven as a basic service or may be a higher layer software driven by a user. The operating system 102 ′ may perform overall control operations on the storage system 10 , such as executing a program, accessing a file, driving an application, and controlling the data storage 200 .

The RAM driver 103 ′ and the DIMM layer 104 ′ may constitute a host lower layer HL2 for accessing the data storage 200 . The RAM driver 103' or the DIMM layer driver 104' may be included in the kernel of the operating system. In response to an access request provided from the host upper layer HL1 , the RAM driver 103 ′ may perform a control operation for accessing the RAM 234 ′ of the data storage 200 . For example, the RAM driver 103' may be a control module for controlling the RAM 234' of the data storage 200 at the operating system 102' level. When an access request from the application 101 ′ or the operating system 102 ′ to the RAM 234 ′ occurs, the RAM driver 103 ′ may be called. In addition, the DIMM layer driver 104' is called together with the RAM driver 103' to support access to the RAM 234' at the actual physical layer level.

The nonvolatile memory layer 200 ′ may include a memory upper layer ML1 and a memory lower layer ML2 . In the memory upper layer ML1, access to the nonvolatile memory 280' according to the upper command CMD_R or the upper address ADDR_R written in the RAM 234' is controlled. In the memory upper layer ML1, an access to the nonvolatile memory 280' and a memory management operation may be performed by the control layer 240'. For example, the control layer 240 ′ may control garbage collection, wear leveling, and stream control for the nonvolatile memory 280 ′. On the other hand, in the memory lower layer ML2 , interfacing between the RAM 234 ′ and the host 100 may be performed. That is, the memory lower layer ML2 may perform an operation of reading or writing data of the RAM 234 ′ in response to a RAM command CMD_R or a RAM address ADDR_R provided through the RAM controller 232 . The memory lower layer ML2 may access the RAM 234 ′ according to a request from the memory upper layer ML1 .

The host may access the nonvolatile memory 280 by software or firmware having the above-described hierarchical structure. That is, access to the nonvolatile memory 280 of the data storage configured in the form of a DIMM may be performed by decoding commands and addresses (CMD_R, ADDR_R) provided through the RAM 234 as a medium.

FIG. 4 is a block diagram showing in detail the structure of the RAM shown in FIG. 2 . Referring to FIG. 4 , the RAM 234 may include a command area 234a , a write area 234b , a read area 234c , and a status area 234d . Data received from the host 100 or the DIMM controller 240 is written in the command area 234a according to the RAM command CMD_R, the RAM address ADDR_R, and the clock CK received from the host 100 . It may be stored in any one of the area 234b, the read area 234c, and the status area 234d. For example, the RAM 234 may be a dual port S234cM that can be accessed simultaneously by the host and the DIMM controller 240 .

The command area 234a may store the storage command CMD_S and the storage address ADDR_S received from the host 100 under the control of the RAM controller 232 . The DIMM controller may read the storage command CMD_S and the storage address ADDR_S stored in the command area 234a.

The write area 234b may store write data DATA_W received under the control of the RAM controller 232 . The DIMM controller 240 may read the write data DATA_W stored in the write area 234b of the RAM 234 .

The read area 234c may store read data DATA_R received under the control of the DIMM controller 232 . The DIMM controller 240 may read the write data DATA_R stored in the read area 234c of the RAM 234 .

The status area 234d may store status information STI regarding whether the storage command CMD_S has been completely processed. The status information stored in the status area 234d may be transmitted to the host or to the DIMM controller 240 . For example, the host 100 may transfer the next write data to the write area 234b with reference to the state information STI. Alternatively, the DIMM controller 240 may transfer the next read data to the read area 234c with reference to the state information STI. Also, the state information STI may include information about data for which errors are not corrected. In this case, the host 100 may retransmit the error-corrected data to the device controller 210 by referring to the state information STI.

FIG. 5 is a flowchart illustrating a write operation to the data storage 200 shown in FIG. 2 .

In step S11 , the host 100 may transmit a RAM command CMD_R and a RAM address ADDR_R for selecting the command area 234a of the RAM 234 to the data storage 200 .

In step S12 , the host 100 transmits the data signal DQ and the data strobe signal DQS for writing the storage command CMD_S to the selected command area 234a to the data storage 200 . For example, the data signal DQ and the data strobe signal DQS of step S12 may include a storage command CMD_S for a write operation. For example, steps S11 and S12 may be a transaction for the storage command CMD_S.

In step S13 , the host 100 may transmit a RAM command CMD_R and a RAM address ADDR_R for selecting the write area 234b of the RAM 234 to the data storage 200 .

In operation S14 , the host 100 may transmit the data signal DQ and the data strobe signal DQS for writing the write data DATA_W to the selected write area 234b to the data storage 200 . For example, the data signal DQ and the data strobe signal DQS of step S14 may include write data DATA_W. For example, steps S13 and S14 may be a data transaction for write data.

In step S15 , the host 100 may transmit a RAM command CMD_R and a RAM address ADDR_R for selecting the state area 234d of the RAM 234 to the data storage 200 .

In step S16 , the host 100 may read the state information STI stored in the selected state area 234d through the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS of step S16 may include the state information STI and may be signals provided from the RAM 234 to the host 100 .

In step S17 , the host 100 may determine whether the write operation is complete based on the read state information STI. For example, when the DIMM controller 240 of the data storage 200 completes processing of the write data DATA_W stored in the write area 234b of the RAM 234 , the state area 234d of the RAM 234 is ), the state information STI indicating the completion of the write operation may be written. In this case, in step S16 , status information (STI) indicating completion of the write operation is transmitted to the host 100 . The host 100 may determine whether the operation of writing the received state information STI is completed.

When the received status information STI does not indicate completion of the write operation, the host 100 may repeat steps S15 to S17. When the received state information STI indicates completion of the write operation, the write operation of the user system 10 is terminated. For example, the operations of steps S15 to S17 may be a processing process for checking the completion of the write operation.

If the write operation is not completed, the DIMM controller 240 of the data storage 200 will not write the state information STI to the RAM 234 . In this case, in step S16 , the state information STI may not be transmitted to the host 100 or other state information may be transmitted. When the state information STI is not received or other state information is received, the host 100 determines that the write operation is not completed, and repeats steps S15 to S17.

6 is a flowchart illustrating a read operation on the data storage 200 shown in FIG. 2 .

In operation S21 , the host 100 may transmit a RAM command CMD_R and a RAM address ADDR_R for selecting the command area 234a of the RAM 234 to the data storage 200 .

In operation S22 , the host 100 may transmit the data signal DQ and the data strobe signal DQS to the data storage 200 to write the storage command CMD_S in the selected command area 234a . For example, the data signal DQ and the data strobe signal DQS in step S22 may include a storage command CMD_S for a read operation. For example, the operations of steps S21 and S22 may be processing processes for the storage command CMD_S.

In step S23 , the host 100 may transmit a RAM command CMD_R and a RAM address ADDR_R for selecting the state region 234d to the data storage 200 .

In step S24 , the host 100 may read the state information STI stored in the selected state area 234d through the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS in step S24 may include the state information STI and may be signals provided from the RAM 234 to the host 100 .

In step S25 , the host 100 may determine whether the read operation is complete by referring to the read state information STI. When the read operation is not completed, the host 100 may periodically repeat the operations of steps S23 to S24. For example, the operations of steps S23 to S25 may be a processing process for checking the completion of a read operation.

If the read operation on the data storage 200 is not completed, the DIMM controller 240 of the data storage 200 may not write the state information STI indicating the completion of the read operation to the RAM 234 . In this case, in step S24 , the state information STI may not be transmitted to the host 100 . When the state information STI is not transmitted, the host 100 may repeatedly perform steps S23 to S25.

If the read status information STI does not indicate completion of the read operation, in step S26 , the host 100 uses a RAM command CMD_R and a RAM address ADDR_R to select the read area 234c of the RAM 234 . may be transmitted to the data storage 200 .

In step S27 , the host 100 may read the read data DATA_R stored in the selected read area 234c through the data signal DQ and the data strobe signal DQS. For example, the data signal DQ and the data strobe signal DQS of step S27 may include read data DATA_R and may be signals provided from the RAM 234 to the host 100 .

7 is a block diagram exemplarily illustrating data communication between the host 100 and the data storage 200 . Referring to FIG. 5 , the host 100 and the data storage 200 may transmit/receive data through a queuing method.

The NVM driver 110 of the host 100 may include a submission queuing handler 132 and a completion queuing handler 134 . In response to an access request from the host 100 to the data storage 200 , the submission queuing handler 132 transmits a command CMD_S necessary for controlling the nonvolatile memory of the data storage 200 to the command area 234a. can

When the access request is a write operation, the submission queuing handler 132 may transmit write data to the write area 234b and transmit a storage command CMD_S related to the write operation to the command area 234a. When the access request is a read operation, the submission queuing handler 132 may transmit a storage command CMD_S related to the read operation to the command area 234a.

The completion queuing handler 134 reads status information indicating whether the processing of the storage command CMD_S is completed from the status area 234d, and reads read data according to the read request from the read area 234c. have. The completion queuing handler 134 may transmit read state information or read data to an upper layer as a result value.

8 is a block diagram illustrating a process of detecting and correcting an error according to an embodiment of the present invention. To explain this, an embodiment of the device controller 210 shown in FIG. 2 is illustrated.

First, a storage command CMD_S and a storage address ADDR_S for controlling write data to be stored in the nonvolatile memory 280 may be received from the host 100 (①). In this case, the storage command CMD_S and the storage address ADDR_S may be encoded by the host 100 . That is, it may be data to which ECC parity is added. The storage command CMD_S and the storage address ADDR_S may be stored in the command area 234a.

After the storage command CMD_S and the storage address ADDR_S are transmitted, write data DATA_W corresponding thereto may be received (②). Similarly, write data DATA_W may be encoded by the host 100 . That is, it may be data to which ECC parity is added. The write data DATA_W may be stored in the write area 234b.

The DIMM controller 240 may access the RAM 234 to read the storage command CMD_S and the storage address ADDR_S (③). Then, the DIMM controller 240 may access the RAM 234 to read the write data DATA_W (④).

The error detector 242 may detect whether there are errors in the storage command CMD_S, the storage address ADDR_S, and the write data DATA_W read from the RAM 234 ( ⑤ ). In this case, the error detector 242 may be an IP (Intellectual Property, semiconductor design asset) implemented as hardware. Detection of errors may be performed using ECC parity added when encoded by the host 100 .

If there is an error in the data read from the RAM 234 , the processor 220 may drive the error correction module 222 to correct the error ( ⑥ ). The error correction module 222 may be implemented in the form of firmware, and may be stored in a ROM (see FIG. 2 , 260 ) or a nonvolatile memory 280 provided in the device controller 210 .

If the error is corrected, the error-corrected data (CMD_S, ADDR_S, DATA_W, etc.) may be transmitted to the nonvolatile memory 280 in the form of packet data (WD packet). On the other hand, if the error is not corrected even by the error correction module 222 , the DIMM controller 240 may update the state information STI. In this case, the state information STI may indicate that there is an error in data received from the host.

Thereafter, the host 100 may transmit data (eg, at least one of CMD_S, ADDR_S, and DATA_W) to the RAM 234 with reference to the state information STI stored in the state area 234d.

In this figure, it is shown that the storage command CMD_S, the storage address ADDR_S, and the write data DATA_W are all transmitted to the DIMM controller 240 , and then the detection operation by the error detector 242 is executed. became However, the present invention is not limited thereto, and when the DIMM controller 240 accesses the RAM 234 to read data, the DIMM controller 240 may immediately detect whether there is an error in the read data.

The device controller according to an embodiment of the present invention may detect an error in data received from the host using hardware and correct the detected error using software. As a result, the chip size of the semiconductor device can be reduced.

9 is a block diagram showing the DIMM controller 240 shown in FIG. 8 in more detail. Referring to FIG. 9 , the DIMM controller 240 may include an error detector 242 , a stream packet generator 244 , a status information generator 246 , and an ECC encoder 248 .

The error detector 242 may check whether there is an error in the data read from the RAM 234 . For example, the error detector 242 may check whether there is an error in the data by using the ECC parity added when the data is encoded by the host 100 . As a result of the check, if an error is detected, the processor (refer to FIG. 8 , 220 ) may drive the error correction module 222 . In addition, the processor may correct the detected error using the error correction module 222 .

If the error is corrected by the error correction module 222 , the stream packet generator 244 may process the write data DATA_W in the form of a stream packet. Then, the processed packet data WR packet is transmitted to the nonvolatile memory 280 to be programmed.

On the other hand, if the error is not corrected even when the error correction module 222 is driven, the state information generator 246 may update the state information STI. In this case, the updated state information STI may include information about data in which an error has occurred (eg, CMD_S, DATA_W, etc.). The state information generator 246 may transmit the state information (STI) to the ECC encoder 248 .

The ECC encoder 248 may encode the state information (STI) received from the state information generator 246 . For example, the state information generator 246 may add a parity bit to the state information STI. The ECC encoder 248 may transmit the state information (STI) to the state area (refer to FIG. 8 , 234d) of the RAM. Thereafter, the host 100 may refer to the state information STI stored in the state area 234d and transmit the data in which the error has occurred to the data storage 200 again.

Unlike the embodiment described in this figure, an error detection function for data received from the RAM 234 and a function for encoding data to be transmitted to the RAM 234 may be performed by one IP. This will be described in detail with reference to FIG. 10 .

FIG. 10 is a block diagram showing another embodiment of the DIMM controller 240 shown in FIG. 8 in more detail. Referring to FIG. 10 , the DIMM controller 240 may include an ECC circuit 242 , a stream packet generator 244 , and a state information generator 246 .

The ECC circuit 242 may check whether there is an error in the data read from the RAM 234 . For example, the ECC circuit 242 may check whether there is an error in the data by using the ECC parity added when the data is encoded by the host 100 . As a result of the inspection, if an error is detected, the processor 220 may drive the error correction module 222 . In addition, the processor may correct the detected error using the error correction module 222 .

If the error is corrected by the error correction module 222 , the stream packet generator 244 may process the write data DATA_W in the form of a stream packet. Then, the processed packet data WR packet is transmitted to the nonvolatile memory 280 to be programmed.

On the other hand, if the error is not corrected even when the error correction module 222 is driven, the state information generator 246 may update the state information STI. In this case, the updated state information STI may include information about data in which an error has occurred (eg, CMD_S, DATA_W, etc.). The state information generator 246 may transmit the state information STI to the ECC circuit 242 .

The ECC circuit 242 may encode the state information STI received from the state information generator 246 . For example, the state information generator 246 may add a parity bit to the state information STI. The ECC circuit 242 may transmit the state information STI to the state area (refer to FIG. 8 , 234d) of the RAM. Thereafter, the host 100 may refer to the state information STI stored in the state area 234d and transmit the data in which the error has occurred to the data storage 200 again.

According to an embodiment of the present invention, the DIMM controller may detect whether there is an error in data received from the host using hardware. In addition, the DIMM controller may correct the detected error by driving the firmware. As a result, the chip size of the semiconductor device can be reduced. In addition, when the detected error is not corrected, status information is transmitted to the host so that the host can retransmit data.

11 is a flowchart illustrating a method of detecting and correcting an error in data received from a host in the storage system of the present invention.

In operation S110 , the host 100 may encode the storage command CMD_S, the storage address ADDR_S, and the write data DATA_W. For example, the host 100 may transmit ECC parity by adding ECC parity to data (eg, storage command, read data, write data, etc.) transmitted to the device controller 210 . The ECC parity may be used to determine whether there is an error in data transmitted to the device controller 210 and correct the error.

In operation S120 , the device controller 210 may receive a storage command CMD_S and a storage address ADDR_S from the host. For example, the received storage command CMD_S and the storage address ADDR_S may be stored in the command area 234a of the RAM provided in the physical layer (refer to FIG. 4 , 230 ) of the device controller.

In operation S130 , the device controller 210 may receive write data DATA_W corresponding to the storage command CMD_S and the storage address ADDR_S. For example, the write data DATA_W may be stored in the write area 234b of the RAM provided in the physical layer 230 of the device controller.

In operation S140 , it may be detected whether there is an error in data received from the host 100 . For example, the DIMM controller (see FIG. 8 , 240 ) included in the device controller 210 may read data stored in the command area 234a or the read area 234b and detect whether there is an error. In this step, the detection of the error may be performed by separate hardware (eg, the error detector 242 of FIG. 9 or the ECC circuit 242 of FIG. 10 ) provided in the DIMM controller 240 .

In step S150 , the detected error may be corrected. The error correction may be performed by the processor 210 driving a separate error correction firmware. For example, the firmware for error correction may be stored in the ROM (see FIG. 2 , 260 ) or the nonvolatile memory 280 provided in the device controller 210 , and may be loaded and driven by the processor 210 . have.

In step S160, it may be determined whether the error has been corrected. If the error is corrected as a result of driving the error correction firmware (Yes), the write data will be transmitted to the nonvolatile memory in the form of a stream packet (WR packet). On the other hand, if the error is not corrected (No), the flow moves to step S180.

In operation S180 , the state information STI may be updated. The updated state information STI may be stored in the state area 234d of the RAM 234 . The updated state information STI may include information about data in which an error has occurred. For example, the state information STI may include information on whether an error occurs in which part (ie, logical address) of the write data DATA_W.

In step S190, the state information (STI) may be transmitted to the host. For example, the host 100 may obtain the state information STI by periodically polling the RAM 234 or using an interrupt method. Thereafter, the host 100 retransmits the data in which the error occurred to the device controller 210 again.

12 is a flowchart illustrating a method of operating a device controller according to an embodiment of the present invention.

In operation S210 , an encoded storage command CMD_S and a storage address ADDR_S may be received from the host. For example, the encoded data may include ECC parity. For example, the storage command CMD_S and the storage address ADDR_S may be stored in the state area 234a of the RAM included in the physical layer 220 of the storage controller.

In operation S220 , encoded write data DATA_W corresponding to the storage command CMD_S and the storage address ADDR_S may be received. The write data DATA_W may be stored in the write area 234b of the RAM.

In step S230 , an error in data received from the host may be checked. Detection of errors may be performed using ECC parity added when data is encoded. This step may be executed by the error detector 242 provided in the DIMM controller 240 .

In step S240 , the error may be corrected. This step may be executed by the processor 210 driving a separate firmware for error correction. For example, the firmware for error correction may be stored in the ROM 260 or the nonvolatile memory 280 provided in the device controller 210 , and may be driven by the processor 210 .

In step S250, it may be determined whether the error has been corrected. Depending on the judgment result, an action divergence occurs. If the error is corrected (Yes), the process moves to step S260. On the other hand, if it is not corrected (No), it moves to step S270.

In operation S260 , write data may be transmitted to the nonvolatile memory in the form of a stream packet. Then, the stream packet will be programmed into the non-volatile memory.

In operation S270 , the state information STI may be updated. The state information STI may include information about data in which an error has occurred. The state information STI may be stored in the state area 234d of the RAM 234 . Thereafter, the host will retransmit the error data (eg, CMD_S, ADDR_S, DATA_W, etc.) to the device controller by referring to the status information (STI).

In the present embodiment, it has been described that the storage command CMD_S and the storage address ADDR_S are received (S310) and the read data DATA_W is received (S320), and then an error is checked (S330). However, when the DIMM controller (see FIG. 8 , 240 ) reads the storage command CMD_S and the storage address ADDR_S stored in the read area 234a before reading the write data stored in the write area 234b, the storage command Errors in (CMD_S) and storage address (ADDR_S) may be checked first.

And, in the drawing, it is shown that step S210 is executed after step S270. However, if the state data STI indicates that there is no error in the write data DATA_W, or indicates that there is an error only in the storage command CMD_S and/or the storage address ADDR_S, after step S270 is executed, step S220 is performed. can be executed

13 is a flowchart illustrating a method of operating a device controller according to another embodiment of the present invention. Since the basic operation method is similar to the embodiment described with reference to FIG. 12 , a redundant description will be omitted.

In operation S310 , an encoded storage command CMD_S and a storage address ADDR_S may be received.

In operation S320 , the encoded write data DATA_W may be received.

In step S330, an error of the received data may be checked. This step may be executed by the error detector 242 provided in the DIMM controller 240 .

In operation S340 , it may be determined whether the detected error is correctable. Determining whether an error can be corrected using ECC parity is obvious to a person skilled in the art to which the present invention pertains, so a detailed description thereof will be omitted. An operation branch occurs according to the determination result. If the error is correctable (Yes), the flow moves to step S350. On the other hand, if correction is not possible (No), the process moves to step S370.

In step S350, an error may be corrected. This step may be executed by the processor 210 driving a separate firmware for error correction.

In operation S360 , write data may be transmitted to the nonvolatile memory in the form of a stream packet. Then, the stream packet will be programmed into the non-volatile memory.

In operation S370 , the state information STI may be updated. The state information STI may include information about data in which an error has occurred. The state information STI may be stored in the state area 234d of the RAM 234 . Thereafter, the host will retransmit the error data (eg, CMD_S, ADDR_S, DATA_W, etc.) to the device controller by referring to the status information (STI).

12, in this embodiment, after the storage command CMD_S and the storage address ADDR_S is received (S310) and the read data DATA_W is received (S320), an error is checked (S330) was described as However, when the DIMM controller (see FIG. 8 , 240 ) reads the storage command CMD_S and the storage address ADDR_S stored in the read area 234a before reading the write data stored in the write area 234b, the storage command Errors in (CMD_S) and storage address (ADDR_S) may be checked first.

And, in the drawing, it is shown that step S310 is executed after step S370. However, if the state data STI indicates that there is no error in the write data DATA_W or that there is an error only in the storage command CMD_S and/or the storage address ADDR_S, after step S370 is executed, step S320 is can be executed

According to an embodiment of the present invention, the DIMM controller may detect whether there is an error in data received from the host using hardware. In addition, the DIMM controller may correct the detected error by driving the firmware. As a result, the chip size of the semiconductor device can be reduced. In addition, when the detected error is not corrected, status information is transmitted to the host so that the host can retransmit data. That is, the reliability of data reception from the host can be improved by managing the error information so that it can be transmitted to the host.

FIG. 14 is a block diagram exemplarily showing any one of the nonvolatile memories shown in FIG. 2 . Referring to FIG. 14 , the nonvolatile memory 280 includes a memory cell array 281 , an address decoder 282 , a page buffer 283 , an input/output circuit 284 , and a control logic and voltage generation circuit 285 . can do.

The memory cell array 281 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to the plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) that stores 1-bit or a multi-level cell (MLC) that stores at least 2-bits.

The address decoder 282 is connected to the memory cell array 281 through a plurality of word lines WL, string select lines SSL, and ground select lines GSL. The address decoder 282 may receive the address ADDR_P from the external device, decode the received physical address ADDR_P, and drive the plurality of word lines WL. For example, the address decoder 282 decodes the physical address ADDR_P received from the external device, and selects at least one word line among the plurality of word lines WL based on the decoded physical address ADDR_P. may be selected, and the selected at least one word line may be driven. For example, the physical address ADDR_P may indicate a physical address of the nonvolatile memory 280 to which the storage address ADDR_S is converted. The above-described address translation operation may be performed by the device controller 230 or a flash translation layer (FTL) driven by the device controller 230 .

The page buffer 283 is connected to the memory cell array 281 through a plurality of bit lines BL. The page buffer 283 controls the bit lines BL so that the data DATA received from the input/output circuit 284 is stored in the memory cell array 281 under the control of the control logic and voltage generator circuit 285 . can The page buffer 283 may read data stored in the memory cell array 281 under the control of the control logic and voltage generator circuit 285 and transfer the read data to the input/output circuit 284 . For example, the page buffer 283 may receive data from the input/output circuit 284 on a page-by-page basis or read data from the memory cell array 281 on a page-by-page basis.

The input/output circuit 284 may receive data DATA from an external device and transfer the received data DATA to the page buffer 283 . Alternatively, the input/output circuit 284 may receive the data DATA from the page buffer 283 and transfer the received data DATA to an external device (eg, the DIMM controller 230 ). For example, the input/output circuit 284 may transmit/receive data DATA to and from an external device in synchronization with the control signal CTRL.

The control logic and voltage generator circuit 285 receives the storage command CMD_S and the control signal CTRL from an external device, and responds to the received signals by the address decoder 282 , the page buffer 283 , and the input/output circuit (284) can be controlled. For example, the control logic and voltage generation circuit 285 may control other components such that data DATA is stored in the memory cell array 281 in response to the signals CMD_S and CTRL. Alternatively, the control logic and voltage generator circuit 285 may control other components to transmit data DATA stored in the memory cell array 281 to an external device in response to the signals CMD_S and CTRL. For example, the storage command CMD_S received from the external device may be a modified command of the storage command CMD_S of FIG. 2 . The control signal CTRL may be a signal provided by the device controller 230 to control the nonvolatile memory 280 .

The control logic and voltage generation circuit 285 may generate various voltages required for the nonvolatile memory 280 to operate. For example, the control logic and voltage generator circuit 285 may include a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of non-select read voltages, a plurality of erase voltages, and a plurality of verification voltages. It is possible to generate various voltages such as voltages. The control logic and voltage generation circuit 285 may provide the generated various voltages to the address decoder 282 or a substrate of the memory cell array 281 .

15 is a circuit diagram illustrating an example of any one of memory blocks included in the memory cell array of FIG. 14 . For example, a memory block BLK1 having a three-dimensional structure will be described with reference to FIG. 15 . However, the scope of the present invention is not limited thereto, and other memory blocks included in each of the plurality of nonvolatile memories 280 may also have a structure similar to that of the memory block BLK1 .

Referring to FIG. 15 , the memory block BLK1 includes a plurality of cell strings CS11 , CS12 , CS21 , and CS22 . The plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be disposed along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row.

For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form a first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.

Each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 includes string-selected transistors SSTa and SSTb , a plurality of memory cells MC1 to MC8 , ground-selected transistors GSTa and GSTb , and dummy memory cells DMC1 and DMC2. For example, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, and CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and stacked in a height direction that is perpendicular to a plane formed by a row direction and a column direction. The string-selected transistors SSTa and SSTb are connected in series, and the series-connected string-selected transistors SSTa and SSTb are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground-selected transistors GSTa and GSTb are connected in series, and the series-connected ground-selected transistors GSTa and GSTb are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

For example, the first dummy memory cell DMC1 may be provided between the plurality of memory cells MC1 to MC8 and the ground-selected transistors GSTa and GSTb. For example, the second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string-selected transistors SSTa and SSTb.

The ground-selected transistors GSTa and GSTb of the cell strings CS11 , CS12 , CS21 , and CS22 may be commonly connected to the ground-selection line GSL. Exemplarily, ground-selected transistors in the same row may be connected to the same ground select line, and ground-selected transistors in different rows may be connected to different ground select lines. For example, the first ground-selected transistors GSTa of the cell strings CS11 and CS12 in the first row may be connected to the first ground-selection line, and The first ground-selected transistors GSTa may be connected to the second ground-selected line.

Exemplarily, although not shown in the drawings, ground-selected transistors provided at the same height from the substrate (not shown) may be connected to the same ground selection line, and ground-selected transistors provided at different heights may be connected to different ground selection lines. can be connected For example, the first ground-selected transistors GSTa of the cell strings CS11 , CS12 , CS21 and CS22 are connected to the first ground-selection line, and the second ground-selection transistors GSTb are connected to the second ground-selection line. can be connected to the line.

Memory cells of the same height from the substrate (or ground-selected transistors GSTa and GSTb) are commonly connected to the same wordline, and memory cells of different heights are connected to different wordlines. The first to eighth memory cells MC8 of CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Among the first string-selected transistors SSTa having the same height, string-selected transistors in the same row are connected to the same string select line, and string-selected transistors in different rows are connected to different string select lines. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are commonly connected to the string select line SSL1a, and the cell strings CS21 and CS22 of the second row are connected in common. ) of the first string selected transistors SSTa are commonly connected to the string select line SSL1a.

Similarly, among the second string-selected transistors SSTb having the same height, string-selected transistors in the same row are connected to the same string select line, and string-selected transistors in different rows are connected to different string select lines. For example, the second string selected transistors SSTb of the cell strings CS11 and CS12 of the first row are commonly connected to the string select line SSL1b, and the cell strings CS21 and CS22 of the second row are connected in common. ) of the second string select transistors SSTb are commonly connected to the string select line SSL2b.

Although not shown in the drawings, string-selected transistors of cell strings in the same row may be commonly connected to the same string-selection line. For example, the first and second string-selected transistors SSTa and SSTb of the cell strings CS11 and CS12 of the first row may be commonly connected to the same string select line. The first and second string-selected transistors SSTa and SSTb of the cell strings CS21 and CS22 of the second row may be commonly connected to the same string select line.

For example, dummy memory cells having the same height are connected to the same dummy word line, and dummy memory cells having different heights are connected to different dummy word lines. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1 , and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2 .

In the memory block BLK1 , reading and writing may be performed in units of rows. For example, one row of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, when a turn-on voltage is supplied to the string selection lines SSL1a and SSL1b and a turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11, CS12 is connected to bit lines BL1 and BL2. When a turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and a turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row are bit It is connected to the lines BL1 and BL2 and is driven. Memory cells of the same height among the memory cells of the cell string of the row driven by driving the word line are selected. Read and write operations may be performed on the selected memory cells. The selected memory cells may form a physical page unit.

In the first memory block BLK1 , erasing may be performed in units of memory blocks or sub-blocks. When erasing is performed in units of memory blocks, all memory cells MC of the first memory block BLK1 may be simultaneously erased according to one erase request. When performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK1 may be simultaneously erased according to one erase request, and the remaining portions may be inhibited from being erased. A low voltage (eg, a ground voltage) may be applied to a word line connected to the memory cells to be erased, and the word line connected to the erase-inhibited memory cells may be floated.

For example, the illustrated memory block BLK1 is exemplary, and the number of cell strings may increase or decrease, and the number of rows and columns constituting the cell strings may increase or decrease according to the number of cell strings. have. Also, the number of cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, respectively, and the height of the memory block BLK1 increases according to the number of cell transistors. or it may decrease. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

16 is a block diagram exemplarily showing a computing system to which a nonvolatile memory module according to the present invention is applied. Referring to FIG. 16 , the computing system 1000 includes a processor 1100 , nonvolatile memory modules 1200 and 1201 , RAM modules 1300 and 1301 , a chipset 1400 , a GPU 1500 , and an input/output device ( 1600 ), and a storage device 1700 .

The processor 1100 may control overall operations of the computing system 1000 . The processor 1100 may perform various operations performed by the computing system 1000 .

The nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may be directly connected to the processor 1100 . For example, each of the nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may have the form of a dual in-line memory module (DIMM). Alternatively, each of the nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may be mounted in a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100 . For example, the nonvolatile memory modules 1200 and 1201 may be the nonvolatile memory modules described with reference to FIGS. 1 to 15 .

The nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate with the processor 1100 through the same interface 1150 . For example, the nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate through a double data rate (DDR) interface 1150 . For example, the processor 1100 may use the RAM modules 1300 and 1301 as an operating memory, a buffer memory, or a cache memory of the computing system 1000 .

The chipset 1400 is electrically connected to the processor 1100 , and may control hardware of the computing system 1000 according to the control of the processor 1100 . For example, the chipset 1400 may be connected to each of the GPU 1500 , the input/output device 1600 , and the storage device 1700 through major buses, and may serve as a bridge for the major buses.

The GPU 1500 may perform a series of arithmetic operations for outputting image data of the computing system 1000 . For example, the GPU 1500 may be mounted in the processor 1100 in a system-on-chip form.

The input/output device 1600 includes various devices that input data or commands to the computing system 1000 or output data to the outside. For example, the input/output device 1600 includes user input devices such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, a piezoelectric element, and an LCD ( Liquid Crystal Display), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, and user output devices such as an LED, a speaker, and a motor may be included.

The storage device 1700 may be used as a storage medium of the computing system 1000 . The storage device 1600 may include mass storage media such as a hard disk drive, an SSD, a memory card, a memory stick, and the like.

For example, the nonvolatile memory modules 1200 and 1201 may be used by the processor 1100 as a storage medium of the computing system 1000 . The interface 1150 between the nonvolatile memory modules 1200 and 1201 and the processor 1100 may be a higher-speed interface than the interface between the storage device 1700 and the processor 1100 . That is, since the processor 1100 uses the nonvolatile memory modules 1200 and 1201 as storage media, the performance of the computing system is improved.

The nonvolatile memory modules 1200 and 1201 may include SRAM having a structure optimized for an interface protocol with the processor 1100 . That is, the processor 1100 can provide the nonvolatile memory modules 1200 and 1201 with commands, addresses, and data for accessing the nonvolatile memory through a plurality of RAMs divided in units of bank groups or banks. will be.

17 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 16 . For example, FIG. 17 shows a nonvolatile memory module 1200 having a form of a load reduced DIMM (LRDIMM). Illustratively, the nonvolatile memory module 1200 shown in FIG. 17 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 . can

Referring to FIG. 17 , the nonvolatile memory module 1200 includes a device controller 1210 , a nonvolatile memory device 1220 , a buffer 1230 , and a serial presence detection chip 1240 (Serial Presence Detect chip; SPD). may include The device controller 1210 may include a RAM 1211 . For example, the nonvolatile memory device 1220 may include a plurality of nonvolatile memories NVM. Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1220 may be implemented as a separate chip, a separate package, a separate device, or a separate module. Alternatively, the nonvolatile memory device 1220 may be implemented as one chip or one package.

Exemplarily, the device controller 1210 , the RAM 1211 , the nonvolatile memory device 1220 , and the buffer 1230 include the device controller 210 , the RAM 224 , the buffer 290 described in FIG. 2 , and the plurality of nonvolatile memories 280 may operate the same or similarly. The nonvolatile memory module 1200 may include an SRAM having a structure optimized for an interface protocol with the processor 1100 . That is, the processor 1100 transmits commands, addresses, and data for accessing the nonvolatile memory device 1220 to the nonvolatile memory modules 1200 and 1205 through the RAM 1211 divided by bank group units or bank units. will be able to provide

For example, the device controller 1210 may transmit/receive a plurality of data signals DQ and a plurality of data strobe signals DQS to/from the processor 1100 , and a RAM command CMD_R through separate signal lines. , a RAM address ADDR_R, and a clock CK.

The SPD 1240 may be a programmable read-only memory (EEPROM). The SPD 1240 may include initial information or device information of the nonvolatile memory module 1200 . For example, the SPD 1240 may include initial information or device information such as a module type, a module configuration, a storage capacity, a module type, and an execution environment of the nonvolatile memory module 1300 . When the computing system including the nonvolatile memory module 1200 is booted, the processor 1100 of the computing system may read the SPD 1240 and recognize the nonvolatile memory module 1200 based thereon. The processor 1100 may use the nonvolatile memory module 1200 as a storage medium based on the SPD 1240 .

For example, the SPD 1240 may communicate with the processor 1100 through a side-band communication channel. The processor 1100 may send and receive an additional signal (Side-Band Signal; SBS) with the SPD 1240 through an additional communication channel. For example, the SPD 1240 may communicate with the device controller 1210 through an additional communication channel. Exemplarily, the additional communication channel may be a channel based on I2C communication. For example, the SPD 1240 , the device controller 1210 , and the processor 1100 may communicate with each other or exchange information based on I2C communication.

18 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 16 . For example, FIG. 18 is a block diagram of a nonvolatile memory module 2200 having a registered DIMM (RDIMM) form. Illustratively, the nonvolatile memory module 2200 shown in FIG. 18 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 . can

Referring to FIG. 18 , the nonvolatile memory module 2200 includes a device controller 2210 , a nonvolatile memory device 2220 , a buffer 2230 , a serial presence detection chip 2240 (Serial Presence Detect chip; SPD), and and a data buffer circuit 2250 . The device controller 2210 includes a RAM 2211 . Since the device controller 2210 , the RAM 2211 , the nonvolatile memory device 2220 , and the SPD 2240 have been described with reference to FIGS. 1 and 17 , a detailed description thereof will be omitted.

The data buffer circuit 2250 receives information or data from the processor 1100 (refer to FIG. 16 ) through the data signal DQ and the data strobe signal DQS, and transmits the received information or data to the device controller 2250 . can Alternatively, the data buffer circuit 2250 may receive information or data from the device controller 2210 and transmit the received information or data to the processor 1100 through the data signal DQ and the data strobe signal DQS.

For example, the data buffer circuit 2250 may include a plurality of data buffers. Each of the plurality of data buffers may transmit and receive a data signal DQ and a data strobe signal DQS to and from the processor 1100 . Alternatively, each of the plurality of data buffers may transmit and receive a signal to and from the device controller 2210 . For example, each of the plurality of data buffers may operate under the control of the device controller 2210 .

For example, the device controller 2210 may include a RAM 2211 having a structure optimized for an interface protocol with the processor 1100 . That is, the processor 1100 may provide the nonvolatile memory module 2200 with a command, address, and data for accessing the nonvolatile memory 2230 through the RAM 2211 divided by bank group or bank unit. There will be.

19 is a block diagram illustrating another example of a computing system to which a nonvolatile memory module according to the present invention is applied. For concise description, detailed descriptions of the above-described components are omitted. Referring to FIG. 19 , the computing system 3000 includes a processor 3100 , a nonvolatile memory module 3200 , a chipset 3400 , a GPU 3500 , an input/output device 3600 , and a storage device 3700 . . Since the processor 3100 , the chipset 3400 , the GPU 3500 , the input/output device 3600 , and the storage device 3700 are substantially the same as those described in FIG. 16 , a detailed description thereof will be omitted.

The nonvolatile memory module 3200 may be directly connected to the processor 3100 . For example, the nonvolatile memory module 3200 may have a form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 3100 .

The nonvolatile memory module 3200 may include a control circuit 3210 , a nonvolatile memory device 3220 , and a RAM device 3230 . Unlike the nonvolatile memory modules 1200 and 2200 of FIGS. 16 to 18 , the processor 3100 may access the nonvolatile memory device 3220 and the RAM 3230 of the nonvolatile memory module 3200 , respectively. . As a more detailed example, the control circuit 3210 may store received data in the nonvolatile memory device 3220 or the RAM device 3230 under the control of the processor 3100 . Alternatively, the control circuit 3210 may transmit data stored in the nonvolatile memory device 3220 to the processor 3100 or data stored in the RAM 3230 to the processor 3100 under the control of the processor 3100 . . That is, the processor 3100 may recognize the nonvolatile memory device 3220 and the RAM 3230 included in the nonvolatile memory module 3200 , respectively. The processor 3100 may store data or read stored data in the nonvolatile memory device 3220 of the nonvolatile memory module 3200 . Alternatively, the processor 3100 may store data in the RAM 3230 or read the stored data.

For example, the processor 3100 may use the nonvolatile memory device 3220 of the nonvolatile memory module 3200 as a storage medium of the computing system 3000 , and the processor 3100 may include the nonvolatile memory module 3200 . of RAM 3230 may be used as the main memory of the computing system 3000 . That is, the processor 3100 may selectively access a nonvolatile memory device or a RAM device included in one memory module mounted in one DIMM socket, respectively.

For example, the processor 3100 may communicate with the nonvolatile memory module 3200 through a double data rate (DDR) interface 3300 .

20 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 . Referring to FIG. 20 , the nonvolatile memory module 3200 includes a control circuit 3210 , a nonvolatile memory device 3220 , and a RAM device 3220 . For example, the nonvolatile memory device 3220 may include a plurality of nonvolatile memories, and the RAM device 3230 may include a plurality of DRAMs. For example, the plurality of nonvolatile memories may be used as storage of the computing system 3000 by the processor 3100 . Exemplarily, each of the plurality of nonvolatile memories (NVM) may include an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), and a ferroelectric RAM (FRAM). ) and nonvolatile memory devices such as STT-MRAM (Spin-Torque Magnetic RAM).

The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000 . For example, the RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, and MRAM.

The control circuit 3210 includes a device controller 3211 and an SPD 3212 . The device controller 3211 may receive a command CMD, an address ADDR, and a clock CK from the processor 3100 . In response to signals received from the processor 3100 , the device controller 3211 converts data received through the data signal DQ and the data strobe signal DQS to the nonvolatile memory device 3220 or the RAM device 3230 . can optionally be stored in Alternatively, the device controller 3211 transmits the data stored in the nonvolatile memory device 3220 or the RAM device 3230 to the data signal DQ and the data strobe signal DQS in response to signals received from the processor 3100 . It may be selectively transmitted to the processor 3100 through the

For example, the processor 3100 may selectively access the nonvolatile memory device 3220 or the RAM device 3230 through a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 may selectively access the nonvolatile memory device 3220 or the RAM device 3230 included in the nonvolatile memory module 3200 . For example, the device controller 3211 accumulates sub data in a RAM (not shown) according to the operation method described with reference to FIGS. 1 to 17 , and stores the sub data in the nonvolatile memory device 3220 according to a command of the processor 3100 . can be programmed.

21 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 . For example, the nonvolatile memory module 4200 of FIG. 21 may have a dual in-line memory module (DIMM) form, and may be mounted in a DIMM socket to communicate with the processor 3100 .

19 and 21 , the nonvolatile memory module 4200 includes a control circuit 4100 , a nonvolatile memory device 4220 , and a RAM 4230 . The control circuit 4210 includes a device controller 4211 , an SPD 4212 , and a data buffer circuit 4213 .

The device controller 4211 receives a command CMD, an address ADDR, and a clock CK from the processor 3100 . The device controller 4211 may control the nonvolatile memory device 4220 or the RAM device 4230 in response to the received signals. The processor 3100 may selectively access each of the nonvolatile memory device 4220 and the RAM device 4230 . The device controller 4231 may control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100 .

The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 , and provide the received signals to the device controller 4211 and the RAM device 4230 . Alternatively, the data buffer circuit 4213 may provide data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.

For example, when the processor 3100 stores data in the nonvolatile memory device 4220, data received through the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 may process the received data and provide it to the nonvolatile memory device 4220 . Alternatively, when the processor 3100 reads data stored in the nonvolatile memory device 4220 , the data buffer circuit 4213 converts the data provided from the device controller 4211 into the data signal DQ and the data strobe signal DQS. Through , it may be provided to the processor 3100 . Alternatively, when the processor 3100 stores data in the RAM device 4230 , the data received by the data buffer circuit 4213 is provided to the RAM device 4230 , and the device controller 4231 receives the received command CMD. , the address ADDR, and the clock CK may be transmitted to the RAM device 4230 . Alternatively, when the processor 3100 reads data stored in the RAM device 4230 , the device controller 4231 transfers the received command CMD, the address ADDR, and the clock CK to the RAM device 4230 , , the RAM device 4230 provides data to the data buffer circuit 4213 in response to the transmitted signals, and the data buffer circuit 4213, through a data signal DQ and a data strobe signal DQS, The data may be provided to the processor 3100 . For example, the device controller 3211 may accumulate sub data in a RAM (not shown) according to the operation method described with reference to FIG. 1 , and may program the nonvolatile memory device 4220 according to a command of the processor 3100 . have. .

22 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 19 . Referring to FIG. 19 , the nonvolatile memory module 5200 includes a control circuit 5210 , a nonvolatile memory device 5220 , and a RAM device 5230 . The control circuit 5210 includes a device controller 5211 and an SPD 5212 . The nonvolatile memory module 5200 may operate similarly to the nonvolatile memory module 4200 of FIG. 21 . However, the nonvolatile memory module 5200 does not include the data buffer circuit 4213 unlike the nonvolatile memory module 4200 of FIG. 21 . That is, the nonvolatile memory module 5200 of FIG. 22 directly provides data received from the processor 3100 through the data signal DQ and the data strobe signal DQS to the device controller 5211 or the RAM device 5230 . can do. Alternatively, data from the device controller 5211 of the nonvolatile memory module 5200 of FIG. 22 or data from the RAM device 5230 is transmitted to the processor 3100 through the data signal DQ and the data strobe signal DQS. ) can be provided directly.

For example, the nonvolatile memory module 4200 of FIG. 21 may be a load redued DIMM (LRDIMM) type memory module, and the nonvolatile memory module 5200 of FIG. 22 may be a registered DIMM (RDIMM) type memory module. .

Illustratively, the device controller 5211 may include a RAM having the configuration and arrangement as described in FIGS. 1 to 15 .

23 is a diagram exemplarily illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 23 , the server system 6000 may include a plurality of server racks 6100 . Each of the plurality of server racks 6100 may include a plurality of nonvolatile memory modules 6200 . The plurality of nonvolatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6100 . For example, the plurality of nonvolatile memory modules 6200 may have the form of a dual in-line memory module and may be mounted in a DIMM socket electrically connected to the processor to communicate with the processor. For example, the plurality of nonvolatile memory modules 6200 may be used as storage of the server system 6000 .

The nonvolatile memory and/or the device controller according to the present invention may be mounted using various types of packages. For example, the nonvolatile memory and/or device controller according to the present invention is a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In- Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed Stack Package( WSP), etc. can be mounted using packages such as

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is contemplated that the present invention includes such modifications and variations of the present invention provided that they fall within the scope of the following claims and their equivalents.

10: storage system
100: host
200: data storage
210: device controller
220: processor
230: physical layer
232: ram controller
234: ram
240: DIMM controller
242: error detector
244: Stream Packet Generator
246: state information generator
248: ECC encoder
250: non-volatile memory interface
260: ROM
270: buffer manager
280: non-volatile memory
290: buffer

Claims (10)

non-volatile memories; and
a device controller receiving data and an error correction code from a host, detecting an error in the data using the error correction code, and correcting an error in the data;
The device controller is:
a physical layer including a RAM and a RAM controller configured to control the RAM according to a RAM command and a RAM address provided from the host;
based on a storage command and a storage address provided from the host and stored in the RAM, the data is temporarily stored in the RAM and then stored in locations of the nonvolatile memories corresponding to the storage address; a DIMM controller for controlling nonvolatile memories; and
A processor for correcting an error in the data by executing an error correction module;
and the DIMM controller includes an error detection circuit configured to detect an error in the data. The method of claim 1,
The nonvolatile memory module communicates with the host and the nonvolatile memory module through a dual data rate (DDR) interface. The method of claim 1,
The nonvolatile memory module is a dual in-line memory module (DIMM). delete delete The method of claim 1,
The DIMM controller is:
a stream packet generator which processes the data in the form of a stream packet and transmits it to the nonvolatile memory; and
and a state information generator configured to update state information regarding the uncorrected data when the error of the data is not corrected. 7. The method of claim 6,
The DIMM controller transmits the status information to the RAM. 8. The method of claim 7,
The state information is accessed by the host, and the host is referenced to retransmit the data. 8. The method of claim 7,
The ram is:
a first area for storing the storage command and the storage address;
a second area for storing the data; and
and a third area storing the state information. delete

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