KR20160144560A - Nonvolatile memory module, storage device, and electronic device generating error information accessed by host - Google Patents

Abstract

The present invention provides a non-volatile memory module comprising one or more non-volatile memories and a device controller. The device controller receives the write data with the error correction code from the host, checks the error of the write data with reference to the error correction code, and stores the write data in at least one of the non-volatile memories. The device controller stores the error information in the RAM included in the device controller so that the error information about the error is accessed by the host. According to the present invention, a host can monitor errors in write data and actively respond to errors.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory module, a storage device, and an electronic device that generate error information accessed by a host, a storage device, and an electronic device.

The present invention relates to electronic devices, and more particularly to operations performed between a host and a non-volatile memory module or storage device configured to store data.

A computing system such as a personal computer includes various types of components. For example, the computing system includes various components such as a main processor, a main memory device, a storage device, a graphic processor, an input / output device, and the like. Further, the computing system includes a number of buses configured to connect its components.

Each of the components included in the computing system is connected to the bus and communicates with each other. The bus connecting several components may be different from the bus connecting several other components. In this case, the bandwidth supported by one bus may be different from the bandwidth supported by the other bus. A bus with a higher bandwidth can operate faster than a bus with a lower bandwidth.

By way of example, the main memory device and the graphics processor may be connected to the main processor via a bus operating at a high speed. On the other hand, the storage device and the input / output device can be connected to the main processor through a bus operating at a relatively slow speed. That is, several buses can operate at different performance.

Description of the Related Art [0002] In recent years, a technology related to a storage device is rapidly developing. Semiconductor storage mediums such as solid state drives (SSD) replace mechanical storage media such as hard disk drives (HDDs), thereby improving the performance and reliability of storage devices. However, when the storage device is connected to the main processor through a bus operating at a relatively slow speed, the operation performance of the storage device may be degraded. Particularly, when a storage device having high operation performance such as an SSD is connected to a bus operating at a slow speed, it is difficult to maximize the performance of the storage device.

To solve the above problems and to maximize the performance of the storage device, a storage device is provided that is configured to communicate with the host via a bus operating at high speed. Further, a scheme of a write operation for actively responding to an error of write data is provided.

A non-volatile memory module according to an embodiment of the present invention may include one or more non-volatile memories and a device controller. The device controller can receive write data with an error correction code from the host, check for errors in the write data with reference to the error correction code, and store the write data in at least one of the non-volatile memories. Furthermore, the device controller can store the error information in the RAM included in the device controller so that the error information about the error is accessed by the host.

In the non-volatile memory module according to an embodiment of the present invention, the error information may include information as to whether an error has been detected in the write data.

In the nonvolatile memory module according to an embodiment of the present invention, when an error is detected in the write data, the error information may further include information as to whether or not the detected error is correctable.

In the nonvolatile memory module according to the embodiment of the present invention, when the error information indicates the impossibility of correcting the detected error, the device controller can re-receive the write data from the host based on the error information.

In the nonvolatile memory module according to an embodiment of the present invention, when an error is detected in the write data and the detected error can be corrected, the error information is written to at least one of the nonvolatile memories after the detected error is corrected And may further include information indicating that it has been stored.

In a non-volatile memory module according to an embodiment of the present invention, the device controller may store write data in at least one of the non-volatile memories if no errors are detected or the errors are correctable.

In a non-volatile memory module according to an embodiment of the present invention, the device controller may operate according to an interface specification defined by a DIMM specification.

A storage device according to another embodiment of the present invention may include one or more non-volatile memories and a device controller. The device controller may receive write data with an error correction code from a host and store the write data in at least one of the non-volatile memories. The device controller may include a physical layer and a controller. The physical layer may include a RAM, and a RAM controller configured to control the RAM according to a RAM command and a RAM address provided from the host. The controller controls the physical layer and the nonvolatile memories so that the write data is temporarily stored in the RAM and then stored in the locations of the nonvolatile memories corresponding to the storage addresses based on the storage command and the storage address provided from the host and stored in the RAM can do. The controller may include an error correction block configured to check the error of the write data by referring to the error correction code after the write data is read from the RAM. The device controller can store error information about the error in the RAM.

In the storage apparatus according to another embodiment of the present invention, the error information stored in the RAM can be accessed by the host.

In the storage apparatus according to another embodiment of the present invention, the error correction block can correct the detected error when the error is detected and the detected error is correctable.

An electronic device according to another embodiment of the present invention may include at least one storage device and at least one processor. The processor can send write data with the error correction code to the storage device. The storage device can check the error of the write data by referring to the error correction code, store the error information about the error in the RAM included in the physical layer of the storage device, and store the write data if there is no error or the error is correctable . The processor can access the error information by accessing the RAM.

In an electronic device according to another embodiment of the present invention, the processor can check whether or not error information has been stored at the time of confirmation.

According to an embodiment of the present invention, whether or not an error of write data has occurred in the storage device can be monitored by the host. Therefore, the host can check the status of the data and actively respond to the error. As a result, the reliability of the data can be improved.

1 is a block diagram illustrating a computing system including a storage device according to an embodiment of the present invention.
2 is a conceptual diagram showing a software layer of the computing system of FIG.
FIGS. 3 to 7 are block diagrams showing embodiments of the configuration of the storage apparatus of FIG. 1. FIG.
8 is a block diagram illustrating a storage system including the storage device of FIG.
FIG. 9 is a conceptual diagram showing the configuration of the RAM of FIG. 8 and the communication between the processor, the RAM, and the controller.
10 is a flowchart for explaining a read operation of the storage apparatus of FIG.
11 is a flowchart for explaining a write operation of the storage apparatus of Fig.
12 is a conceptual diagram for explaining a process of notifying an error of write data in the write operation of FIG.
FIG. 13 is a flowchart for explaining a process in which the storage device of FIG. 8 checks errors and generates error information in the write operation of FIG.
FIG. 14 is a flowchart for explaining a process of confirming error information by the host of FIG. 8 in the writing operation of FIG.
FIG. 15 is a conceptual diagram for explaining operations in a case where an error of write data does not occur in the write operation of FIG.
16 is a conceptual diagram for explaining operations when a correctable error of write data occurs in the write operation of FIG.
17 is a conceptual diagram for explaining operations when an uncorrectable error of write data occurs in the write operation of FIG.
Figure 18 is a block diagram showing one of the non-volatile memories of Figure 8;
19 is a conceptual diagram showing one memory block of the memory cell array of FIG.
20 is a conceptual diagram showing a server system including a storage apparatus according to an embodiment of the present invention.

The foregoing features and the following detailed description are exemplary of the invention in order to facilitate a description and understanding of the invention. That is, the present invention is not limited to these embodiments, but may be embodied in other forms. The following embodiments are merely examples for the purpose of fully disclosing the present invention and are intended to convey the present invention to those skilled in the art. Thus, where there are several ways to implement the components of the present invention, it is necessary to make it clear that the implementation of the present invention is possible by any of these methods or any of the equivalents thereof.

It is to be understood that, in the context of this specification, when reference is made to a configuration including certain elements, or when it is mentioned that a process includes certain steps, other elements or other steps may be included. In other words, the terms used herein are for the purpose of describing specific embodiments only, and are not intended to limit the concept of the present invention. Further, the illustrative examples set forth to facilitate understanding of the invention include its complementary embodiments.

The terms used in this specification are meant to be understood by those of ordinary skill in the art to which this invention belongs. Commonly used terms should be construed in a manner consistent with the context of this specification. Also, terms used in the specification should not be construed as being excessively ideal or formal in nature unless the meaning is clearly defined. BRIEF DESCRIPTION OF THE DRAWINGS Fig.

1 is a block diagram illustrating a computing system including a storage device according to an embodiment of the present invention. 1, a computing system 1000 includes a processor 1100, one or more RAM Module devices 1210 and 1212, one or more storage devices 1220 and 1222 of a first type, Chipset 1300, a graphics processing unit (GPU) 1400, an input / output device 1500, and a second type of storage device 1600.

The computing system 1000 may be implemented as an electronic device. By way of example, computing system 1000 may include at least one of a variety of electronic devices such as a personal computer, a notebook, a tablet, a workstation, a blade server, a network storage, However, the present invention is not limited by this example.

The processor 1100 may control the overall operations of the computing system 1000. The processor 1100 may be a host that includes a plurality of storage devices 1210 and 1212, a first type of storage devices 1220 and 1222, a GPU 1400, an input / output device 1500, Services may be provided from the storage device 1600. [

The processor 1100 may perform various arithmetic and / or logic operations to operate the computing system 1000. Processor 1100 may include one or more processor cores configured to perform operations. For example, depending on the type of computing system 1000, the processor 1100 may include at least one of a Central Processing Unit (CPU), an Application Processor (AP), a dedicated processor, and an Application Specific Integrated Circuit (ASICs) .

The RAM module devices 1210 and 1212 may temporarily store data to be processed or processed by the processor 1100. The RAM module devices 1210 and 1212 may be used as an operation memory, a working memory, or a buffer memory of the computing system 1000. For example, each of the RAM module devices 1210 and 1212 may include volatile memory such as DRAM (Dynamic Random Access Memory), SRAM (Static RAM), and SDRAM (Synchronous DRAM) Magneto-resistive RAM), ReRAM (Resistive RAM), and non-volatile memory such as Ferro-electric RAM (FRAM).

The first type of storage devices 1220 and 1222 may store data regardless of the power supply. The first type of storage devices 1220, 1222 can store data permanently or semi-permanently without powering. By way of example, each of the first type of storage devices 1220 and 1222 may include at least one of a flash memory, a PRAM, an MRAM, a ReRAM, and a non-volatile memory such as a FRAM.

The first type of storage devices 1220 and 1222 may be implemented based on embodiments of the present invention. Embodiments of the first type of storage devices 1220 and 1222 will be described in detail with reference to FIGS.

The RAM module devices 1210 and 1212 and the first type of storage devices 1220 and 1222 may be coupled to the processor 1100 through a bus 1230 operating at a high speed. For example, the bus 1230 may support a device implemented as a DIMM (Dual Inline Memory Module), and may employ an interface protocol that operates in a DDR (Double Data Rate) manner. In this example, each of the first type of storage devices 1220 and 1222 may be implemented as a "non-volatile memory module ". The RAM module devices 1210 and 1212 and the first type of storage devices 1220 and 1222 are connected to the processor 1210 through the bus 1230. In this case, 1100).

In Figure 1, a computing system 1000 is shown comprising two RAM module devices 1210, 1212 and two first type storage devices 1220, 1222. However, the number of RAM module devices and the number of storage devices of the first type may be variously modified or modified depending on the configuration of the computing system 1000 and the configuration of the bus 1230.

The chipset 1300 may connect other components of the computing system 1000 to the processor 1100. By way of example, the chipset 1300 may connect a graphics processing unit (GPU) 1400, an input / output device 1500, and a second type of storage device 1600 to the processor 1100. By way of example, chipset 1300 may include a Southbridge chipset.

By way of example, GPU 1400 may perform operations to process image data. To this end, GPU 1400 may include one or more cores and one or more memories. The GPU 1400 may provide the results of operations to the processor 1100 via the chipset 1300 or may be provided with the results of operations of the processor 1100. The GPU 1400 can cause the display device to display an image based on the calculation result.

The input / output device 1500 may provide information provided by a user of the computing system 1000 to the processor 1100 through the chipset 1300. [ Alternatively, the input / output device 1500 may provide services to a user of the computing system 1000 based on data provided from the processor 1100 via the chipset 1300. [ For example, the input / output device 1500 may include an input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, Further, the input / output device 1500 may include an output interface such as a speaker, a motor, and the like.

The second type of storage device 1600 may store data regardless of the power supply. By way of example, the second type of storage device 1600 may include a storage medium such as a solid state drive (SSD), a hard disk drive (HDD), or the like.

Unlike the first type of storage devices 1220 and 1222, the second type of storage device 1600 can be coupled to the processor 1100 via a bus operating at a relatively slow rate. By way of example, if the second type of storage device 1600 includes an SSD, a bus operating at a slower rate may degrade the performance of the second type of storage device 1600. [ Because SSDs include their own processors and fast-running semiconductor non-volatile memory, SSDs can have high operating performance. However, when the SSD is connected to a bus operating at a slow speed, it is difficult to maximize the performance of the SSD.

In an embodiment of the present invention, the first type of storage devices 1220, 1222 coupled to the processor 1100 via the bus 1230 operating at high speed may exhibit high operating performance. That is, a storage device including a semiconductor non-volatile memory, such as an SSD, can operate at higher performance when implemented in the form of first type storage devices 1220, 1222.

In the following, the configuration and operation of the first type of storage devices 1220 and 1222 connected to the processor 1100 through the bus 1230 operating at high speed will be described. Quot; storage device "is a first type of storage device coupled to the processor 1100 via a bus 1230 operating at high speed. It is assumed that the bus 1230 operating at a high speed employs an interface protocol defined on the basis of a DIMM specification. However, this assumption is intended to assist the understanding of the present invention, and the present invention is not limited by this assumption. Here, the DIMM specification refers to a specification regarding the configuration and operation of a device implemented in the form of a DIMM.

2 is a conceptual diagram showing a software layer of the computing system of FIG. In the processor 1100 of FIG. 1, software related to a host layer (HL) may be driven. Further, in the storage device of FIG. 1 (i.e., the "first type" storage device 1220 or 1222), software or firmware related to the storage layer (SL)

The host layer HL may include a first host layer HL1 and a second host layer HL2. The storage layer SL may include a first storage layer SL1 and a second storage layer SL2. The first host layer HL1 and the first storage layer SL1 may be provided as physical layers of the host layer HL and the storage layer SL, respectively.

For example, the first host layer HL1 may include a DIMM layer DL1, and the first storage layer SL1 may include a DIMM layer DL2. In this example, the host layer HL and the storage layer SL can physically access each other through the DIMM layers DL1 and DL2 based on the physical address. By way of example, the host layer HL and the storage layer SL can communicate via the DIMM layers DL1 and DL2 according to an interface protocol defined based on the DIMM specification.

As will be described in more detail with reference to FIG. 8, the first storage layer SL1 may include a RAM RM. The second storage layer SL2 may include a nonvolatile memory NM. The nonvolatile memory NM may permanently or semi-permanently store data provided from the host layer HL under the control of the control layer CL of the second storage layer SL2. Further, according to the control of the control layer CL, management operations such as garbage collection, wear leveling, and the like regarding the nonvolatile memory NM can be performed.

In some embodiments of the present invention, the DIMM layer DL2 may be provided with a RAM command and a RAM address that are used to control the RAM RM from the host layer HL. The RAM (RM) can temporarily store the storage command and the storage address used for controlling the nonvolatile memory (NM) according to the RAM command and the RAM address. In addition, the RAM RM may temporarily store write data to be stored in the nonvolatile memory NM and / or read data read from the nonvolatile memory NM. This embodiment will be described in more detail with reference to Figs. 8 to 17. Fig.

The first host layer HL1 may include a RAM driver RD for interfacing with the RAM RM. The second host layer HL2 may include an operating system (OS) for operating the host layer HL. The operating system (OS) may control and manage the overall operations of the computing system 1000 of FIG. By way of example, an operating system (OS) can handle various operations such as program execution, access to files, activation of applications (AP), control of the storage layer (SL) The second host layer HL2 may execute one or more applications AP to provide various services to the user of the host layer HL.

Depending on the operation of the operating system (OS) and / or the application (AP), the host layer HL may provide write data to be stored in the nonvolatile memory NM to the storage layer SL. Alternatively, the storage layer SL may provide the host layer (HL) with read data used for operation of the operating system (OS) and / or the application (AP) among data stored in the nonvolatile memory (NM). Each of the second host layer HL2 and the second storage layer SL2 can logically recognize the other party based on a logical address.

3 is a block diagram showing an embodiment of the configuration of the storage apparatus of FIG. At least one of the first type of storage devices 1220, 1222 of FIG. 1 may include the storage device 2000 of FIG. As an example, the storage device 2000 may be a non-volatile memory module implemented as an LRDIMM (Load Reduced DIMM). In this example, the storage device 2000 is connected to a DIMM socket of the computing system 1000 of FIG. 1 and is capable of communicating with the processor 1100 of FIG. 1 in accordance with an interface protocol defined based on the DIMM specification.

3, the storage device 2000 may include a device controller 2100, one or more non-volatile memories 2200, a buffer memory 2300, and a Serial Presence Detect (SPD) have. The device controller 2100 can control and manage the overall operations of the storage device 2000.

The non-volatile memories 2200 can store data regardless of the power supply, under the control of the device controller 2100. By way of example, non-volatile memories 2200 may be implemented as a single chip or package. Alternatively, each of the non-volatile memories 2200 may be implemented as a separate chip, package, device, or module. The buffer memory 2300 can buffer the read data to be stored in the non-volatile memories 2200 or the read data to be read from the non-volatile memories 2200 under the control of the device controller 2100.

The device controller 2100 can receive the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK from the processor 1100 through the control signal line. The RAM command CMD_R and the RAM address ADDR_R can be used to control the read / write operation with respect to the RAM 2100b. The device controller 2100 can exchange data signals DQ and data strobe signals DQS with the processor 1100 through a data signal line different from the control signal line.

In an embodiment of the present invention, the data signal DQ may include a storage command and a storage address that are used to control read / write operations with respect to the non-volatile memories 2200. Further, the data signal DQ may include write data to be stored in the non-volatile memories 2200 or read data to be read from the non-volatile memories 2200. In some cases, the data signal DQ may include status information regarding write data and read data. In an embodiment of the present invention, the status information may include error information regarding errors in the write data.

The RAM 2100b may temporarily store the storage command and the storage address according to the RAM command and the RAM address. In addition, the RAM 2100b may temporarily store the write data and the read data according to the RAM command and the RAM address. The device controller 2100 is configured to store write data in the nonvolatile memories 2200 or read data in the nonvolatile memories 2200 according to the storage command and the storage address stored in the RAM 2100b, (2200).

The device controller 2100, the RAM 2100b, the nonvolatile memories 2200, and the buffer memory 2300 can be configured and operated as described with reference to Figs. 8-17. In one embodiment, under control of the device controller 2100, the storage device 2000 may receive write data with an error correction code from a host (e.g., processor 1100 of FIG. 1). The device controller 2100 can check the error of the write data with reference to the error correction code. The device controller 2100 can generate error information on the error of the write data and store the generated error information in the RAM 2100b.

Further, the host can access the error information stored in the RAM 2100b. The host can actively respond to errors in the write data by monitoring the error information. As a result, the reliability of the write data can be improved. Embodiments of the present invention will be described in more detail with reference to Figs. 8 to 17. Fig.

The SPD chip 2500 may store information on the characteristics of the storage device 2000. [ As an example, the SPD chip 2500 may store initialization information or device information such as the module type, module configuration, storage capacity, line layout, operating environment, etc. of the storage device 2000. By way of example, the SPD chip 2500 may include a programmable read-only memory (e.g., an Electrically Erasable Programmable Read Only Memory (EEPROM)).

 The processor 1100 of the computing system 1000 may read information stored in the SPD chip 2500 when the computing system 1000 including the storage device 2000 is booted. The processor 1100 can recognize and operate the storage device 2000 based on the read information. In an embodiment of the present invention, the processor 1100 can recognize and operate the storage device 2000 as a storage medium based on the information read.

As an example, the SPD chip 2500 may communicate with the processor 1100 based on a side-band interface convention. In this embodiment, the SPD chip 2500 and the processor 1100 can send and receive a side-band signal SBS over a communication channel supporting the side-band interface protocol. Further, the SPD chip 2500 may communicate with the device controller 2100 based on a side-band interface convention. By way of example, the side-band interface protocol may support a physical layer defined based on an I2C (Inter-Integrated Circuit) or UART (Universal Asynchronous Receiver / Transmitter) specification.

4 is a block diagram showing an embodiment of the configuration of the storage apparatus of FIG. At least one of the first type of storage devices 1220, 1222 of FIG. 1 may include the storage device 3000 of FIG. By way of example, the storage device 3000 may be a non-volatile memory module implemented in the form of an RDIMM (Registered DIMM). In this example, the storage device 3000 is connected to a DIMM socket of the computing system 1000 of FIG. 1 and is capable of communicating with the processor 1100 of FIG. 1 in accordance with an interface convention defined based on the DIMM specification.

4, the storage device 3000 includes a device controller 3100, one or more non-volatile memories 3200, a buffer memory 3300, a data buffer circuit 3400, and an SPD chip 3500 can do. The device controller 3100, the RAM 3100b, the nonvolatile memories 3200, and the buffer memory 3300 can be configured and operated as described with reference to Figs. 8-17.

In one embodiment, under control of the device controller 3100, the storage device 3000 may receive write data with an error correction code from a host (e.g., processor 1100 of FIG. 1). The device controller 3100 can check the error of the write data with reference to the error correction code. The device controller 3100 can generate error information on errors in the write data and store the generated error information in the RAM 3100b.

Further, the host can access the error information stored in the RAM 3100b. The host can actively respond to errors in the write data by monitoring the error information. As a result, the reliability of the write data can be improved. Embodiments of the present invention will be described in more detail with reference to Figs. 8 to 17. Fig.

The device controller 3100, the RAM 3100b, the nonvolatile memories 3200, the buffer memory 3300 and the SPD chip 3500 correspond to the device controller 2100, the RAM 2100b, the nonvolatile memories The buffer memory 2300, and the SPD chip 2500, respectively. Redundant descriptions of the device controller 3100, the RAM 3100b, the nonvolatile memories 3200, the buffer memory 3300, and the SPD chip 3500 will be omitted.

The data buffer circuit 3400 can exchange the data signal DQ and the data strobe signal DQS with the processor 1100. The data buffer circuit 3400 may provide the received signal to the device controller 3100 or may receive the signal to be transmitted from the device controller 3100. [ That is, the data buffer circuit 3400 can buffer the data between the processor 1100 and the device controller 3100. As an example, the data buffer circuit 3400 may be used to synchronize the timing of data transmission.

By way of example, data buffer circuit 3400 may include one or more data buffers. Each of the data buffers may receive or output a data signal DQ and a data strobe signal DQS via a corresponding data signal line. The data buffers may operate under the control of the device controller 3100.

5 is a block diagram showing an embodiment of the configuration of the storage apparatus of FIG. At least one of the first type of storage devices 1220 and 1222 of FIG. 1 may include the storage device 4000 of FIG. By way of example, the storage device 4000 may be implemented as a non-volatile memory module coupled to a DIMM socket of the computing system 1000 of FIG. In this example, the storage device 4000 may communicate with the processor 1100 of FIG. 1 in accordance with an interface convention defined based on the DIMM specification.

In the embodiment of FIG. 5, the storage device 4000 may include a control circuit 4005, one or more non-volatile memories 4200, and one or more DRAMs 4600. The non-volatile memories 4200 may be utilized as a storage medium of the computing system 1000. The DRAMs 4600 may be used as the main memory of the computing system 1000. That is, the storage apparatus 4000 can perform the function of the main memory together with the function of the storage medium.

By way of example, non-volatile memories 4200 may include at least one of EEPROM, flash memory, PRAM, MRAM, ReRAM, and FRAM. In FIG. 5, the storage device 4000 is shown as including DRAMs 4600. However, in some other embodiments, DRAMs 4600 may be replaced with other memories that are randomly accessed, such as SRAM, SDRM, PRAM, MRAM, ReRAM, and FRAM.

The control circuit 4005 may include a device controller 4100 and an SPD chip 4500. The device controller 4100 and non-volatile memories 4200 may be configured and operative as described with reference to Figures 8-17. In one embodiment, under control of the device controller 4100, the storage device 4000 may receive write data with an error correction code from a host (e.g., processor 1100 of FIG. 1). The device controller 4100 can check the error of the write data with reference to the error correction code. The device controller 4100 can generate error information about errors in the write data and store the generated error information in the RAM 4100b.

Further, the host can access the error information stored in the RAM 4100b. The host can actively respond to errors in the write data by monitoring the error information. As a result, the reliability of the write data can be improved. Embodiments of the present invention will be described in more detail with reference to Figs. 8 to 17. Fig.

The device controller 4100, the RAM 4100b, the nonvolatile memories 4200 and the SPD chip 4500 correspond to the device controller 2100, the RAM 2100b, the nonvolatile memories 2200, and the SPD Chip 2500 may be configured and operated in the same or similar manner, respectively. For convenience of description, redundant descriptions of the device controller 4100, the RAM 4100b, the nonvolatile memories 4200, and the SPD chip 4500 will be omitted.

The device controller 4100 can selectively write data included in the data signal DQ and the data strobe signal DQS to the nonvolatile memories 4200 or DRAMs 4600 on the basis of the signal received from the processor 1100 As shown in FIG. Alternatively, the device controller 4100 may selectively receive data stored in the non-volatile memories 4200 or DRAMs 4600, based on signals received from the processor 1100, as a data signal DQ and a data strobe signal DQS). By way of example, processor 1100 may be coupled to non-volatile memories 4200 or DRAMs 4600 based on at least one of a RAM command CMD_R, a RAM address ADDR_R, a storage command, a storage address, It is selectively accessible.

6 is a block diagram showing an embodiment of the configuration of the storage apparatus of FIG. At least one of the first type of storage devices 1220, 1222 of FIG. 1 may include the storage device 5000 of FIG. By way of example, storage device 5000 may be implemented as a non-volatile memory module coupled to a DIMM socket of computing system 1000 of FIG. In this example, the storage device 5000 may communicate with the processor 1100 of FIG. 1 in accordance with an interface convention defined based on the DIMM specification.

In the embodiment of FIG. 6, the storage device 5000 may include a control circuit 5005, one or more non-volatile memories 5200, and one or more DRAMs 5600. The non-volatile memories 5200 may be utilized as a storage medium of the computing system 1000. The DRAMs 5600 may be utilized as the main memory of the computing system 1000. The nonvolatile memories 5200 and DRAMs 5600 may be configured and operable, respectively, the same or similar to the nonvolatile memories 4200 and DRAMs 4600 of FIG. For purposes of illustration, redundant descriptions of non-volatile memories 5200 and DRAMs 5600 will be omitted.

The control circuit 5005 may include a device controller 5100, a data buffer circuit 5400, and an SPD chip 5500. The device controller 5100 and nonvolatile memories 5200 may be configured and operative as described with reference to Figures 8-17. In one embodiment, under control of the device controller 5100, the storage device 5000 may receive write data with an error correction code from a host (e.g., the processor 1100 of FIG. 1). The device controller 5100 can check the error of the write data with reference to the error correction code. The device controller 5100 can generate error information about errors in the write data and store the generated error information in the RAM 5100b.

Further, the host can access the error information stored in the RAM 5100b. The host can actively respond to errors in the write data by monitoring the error information. As a result, the reliability of the write data can be improved. Embodiments of the present invention will be described in more detail with reference to Figs. 8 to 17. Fig.

The device controller 5100, the RAM 5100b and the SPD chip 5500 can be configured and operated respectively in the same or similar to the device controller 2100, the RAM 2100b, and the SPD chip 2500 in Fig. 3 . The data buffer circuit 5400 may be configured and operated in the same or similar manner as the data buffer circuit 3400 of FIG. For convenience of description, redundant descriptions of the device controller 5100, the RAM 5100b, the data buffer circuit 5400, and the SPD chip 5500 will be omitted.

Device controller 5100 can control non-volatile memories 5200 and DRAMs 5600 based on signals received from processor 1100. [ Processor 1100 may selectively access non-volatile memories 5200 or DRAMs 5600.

For example, when processor 1100 stores data in non-volatile memories 5200, the data to be stored may be transferred to device controller (not shown) via data buffer circuit 5400 as data signal DQ and data strobe signal DQS 5100). The device controller 5100 may provide the provided data to the nonvolatile memories 5200. [ For example, when processor 1100 reads data from non-volatile memories 5200, device controller 5100 writes data read from non-volatile memories 5200 to data signal DQ and data strobe signal DQS, To the processor 1100 through the data buffer circuit 5400.

When the processor 1100 stores data in the DRAMs 5600 as an example, the device controller 5100 transfers the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK to the DRAMs 5600, . The data to be stored may be provided to the DRAMs 5600 through the data buffer circuit 5400 as the data signal DQ and the data strobe signal DQS. For example, when the processor 1100 reads data from the DRAMs 5600, the device controller 5100 transfers the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK to the DRAMs 5600 . The DRAMs 5600 output data based on the provided signals and the data buffer circuit 5400 outputs the data output from the DRAMs 5600 as a data signal DQ and a data strobe signal DQS to the processor 1100 ).

FIG. 7 is a block diagram showing an embodiment of the configuration of the storage apparatus of FIG. 1. FIG. At least one of the first type of storage devices 1220, 1222 of FIG. 1 may include the storage device 6000 of FIG. By way of example, storage device 6000 may be implemented as a non-volatile memory module coupled to a DIMM socket of computing system 1000 of FIG. In this example, the storage device 6000 can communicate with the processor 1100 of FIG. 1 in accordance with an interface convention defined based on the DIMM specification.

In the embodiment of FIG. 7, the storage device 6000 may include a control circuit 6005, one or more non-volatile memories 6200, and one or more DRAMs 6600. The non-volatile memories 6200 may be used as a storage medium of the computing system 1000. The DRAMs 6600 may be used as the main memory of the computing system 1000. The non-volatile memories 6200 and the DRAMs 6600 can be configured and operated respectively in the same or similar manner to the non-volatile memories 4200 and the DRAMs 4600 in Fig. For purposes of illustration, redundant descriptions of non-volatile memories 6200 and DRAMs 6600 will be omitted.

The control circuit 6005 may include a device controller 6100 and an SPD chip 6500. The device controller 6100 and nonvolatile memories 6200 may be configured and operative as described with reference to Figures 8-17. In one embodiment, under control of the device controller 6100, the storage device 6000 may receive write data with an error correction code from a host (e.g., processor 1100 of FIG. 1). The device controller 6100 can check the error of the write data with reference to the error correction code. The device controller 6100 can generate error information about errors in the write data and store the generated error information in the RAM 6100b.

Further, the host can access the error information stored in the RAM 6100b. The host can actively respond to errors in the write data by monitoring the error information. As a result, the reliability of the write data can be improved. Embodiments of the present invention will be described in more detail with reference to Figs. 8 to 17. Fig.

The device controller 6100, the RAM 6100b and the SPD chip 6500 may be constructed and operated respectively in the same or similar manner to the device controller 2100, the RAM 2100b, and the SPD chip 2500 in Fig. 3 . For ease of explanation, redundant descriptions of the device controller 6100, RAM 6100b, and SPD chip 6500 will be omitted.

The device controller 6100 can control the nonvolatile memories 6200 and the DRAMs 6600 based on signals received from the processor 1100. [ Processor 1100 may selectively access non-volatile memories 6200 or DRAMs 6600.

For example, when the processor 1100 stores data in the non-volatile memories 6200, the non-volatile memories 6200 store the data to be stored as a data signal DQ and a data strobe signal DQS in the device controller 6100). For example, when the processor 1100 reads data from the non-volatile memories 6200, the device controller 6100 transfers the data read from the non-volatile memories 6200 to the data signal DQ and the data strobe signal DQS, To the processor 1100 as shown in FIG.

For example, when the processor 1100 stores data in the DRAMs 6600, the device controller 6100 transfers the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK to the DRAMs 6600, . The data to be stored may be provided to the DRAMs 6600 as a data signal DQ and a data strobe signal DQS. For example, when the processor 1100 reads data from the DRAMs 6600, the device controller 6100 transfers the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK to the DRAMs 6600 . The DRAMs 6600 output data based on the provided signals and the output data can be provided to the processor 1100 as a data signal DQ and a data strobe signal DQS.

8 is a block diagram illustrating a storage system including the storage device of FIG. The storage system 10 may include a storage device 100 and a processor 101. The storage device 100 and the processor 101 may correspond to the storage device 1220 or 1222 of the first type and the processor 1100 of FIG. Thus, redundant descriptions of the storage device 100 and the processor 101 will be omitted. With reference to Fig. 8, the configuration and operation of the storage device 100, and the communication between the storage device 100 and the processor 101 will be described.

In one embodiment, the storage device 100 may include a device controller 110, one or more non-volatile memories 120, and a buffer memory 130. The device controller 110 may correspond to one of the device controllers 2100, 3100, 4100, 5100, 6100 of FIGS. 3-7. Non-volatile memories 120 may correspond to one of the non-volatile memories 2200, 3200, 4200, 5200, 6200 of FIGS. 3-7. The buffer memory 130 may correspond to one of the buffer memories 2400 and 3400 of FIGS.

In some alternative embodiments, the storage device 100 may include the data buffer circuits 3400, 5400 of Figures 4 and 6, the SPD chips 2500, 3500, 4500, 5500, 6500 of Figures 3-7, And may further include at least one of the DRAMs 4600, 5600, and 6600 shown in FIGS. FIG. 8 shows an exemplary configuration for facilitating understanding of the present invention, and the configuration of the storage device 100 may be variously modified or modified based on the embodiments described with reference to FIG. 3 to FIG.

In accordance with the control of the device controller 110, the storage device 100 can perform a unique function. For example, when the processor 101 provides write request and write data (DATA_W) to the storage device 100 to store write data (DATA_W) in the storage device 100, Accordingly, the write data (DATA_W) may be stored in the nonvolatile memories 120 or the buffer memory 130. [ For example, when the processor 101 provides a read request to the storage device 100 to read the read data (DATA_R) stored in the storage device 100, under the control of the device controller 110, The read data (DATA_R) stored in the buffer memory (120) or the buffer memory (130) may be transmitted to the processor (101).

The device controller 110 may include a physical layer 111 and a controller 112. The physical layer 111 may include a RAM controller 111a and a RAM 111b. The RAM controller 111a can receive the RAM command CMD_R, the RAM address ADDR_R, and the clock signal CLK provided from the processor 101. [ The RAM controller 111a can control the RAM 111b according to the RAM command CMD_R and the RAM address ADDR_R.

The RAM 111b may store or output data based on the RAM command CMD_R and the RAM address ADDR_R. The RAM 111b may receive the data signal DQ and the data strobe signal DQS provided from the processor 101 and may store data corresponding to the data signal DQ. Alternatively, the RAM 111b may output the data stored therein as the data signal DQ and provide the output data to the processor 101. [

The data signal DQ may include a storage command CMD_S and a storage address ADDR_S provided from the processor 101 to control the nonvolatile memories 120. In this embodiment, Further, the data signal DQ may include write data (DATA_W) to be stored in the nonvolatile memories 120 or read data (DATA_R) read from the nonvolatile memories 2200. In some cases, the data signal DQ may include write data (DATA_W) and status information (STI) regarding read data (DATA_R).

In an embodiment of the present invention, the status information (STI) may include error information. The error information may include information on an error of the write data (DATA_W). The error information will be described in detail with reference to FIG. 11 to FIG.

In the write operation with respect to the nonvolatile memories 120, the RAM 111b can store the storage command CMD_S and the storage address ADDR_S in accordance with the RAM command CMD_R and the RAM address ADDR_R. Further, the RAM 111b may temporarily store the write data (DATA_W) provided from the processor 101 according to the RAM command (CMD_R) and the RAM address (ADDR_R). According to the control of the controller 112, the storage command CMD_S, the storage address ADDR_S, and the write data DATA_W may be provided to the nonvolatile memories 120. Write data DATA_W may be stored in the nonvolatile memories 120 based on the storage command CMD_S and the storage address ADDR_S.

In the read operation with respect to the nonvolatile memories 120, the RAM 111b can store the storage command CMD_S and the storage address ADDR_S according to the RAM command CMD_R and the RAM address ADDR_R. The storage command CMD_S and the storage address ADDR_S may be provided to the nonvolatile memories 120 under the control of the controller 112. [ The read data DATA_R may be read from the nonvolatile memories 120 based on the storage command CMD_S and the storage address ADDR_S and temporarily stored in the RAM 111b and then provided to the processor 101.

That is, data (DATA_W, DATA_R) can be exchanged between the processor 101 and the nonvolatile memories 120 under the control of the controller 112. [ For this purpose, for example, the physical layer 111 is defined based on the DIMM specification and can operate in accordance with the DDR type interface protocol. The device controller 110 may operate in accordance with an interface protocol defined by the DIMM specification. The storage device 100 is implemented in the form of a DIMM and is capable of communicating with the processor 101 in accordance with the interface protocol defined by the DIMM specification.

In the above example, the RAM command CMD_R, the RAM address ADD_R, and the clock signal CLK may be provided through a command pin Pin defined in the DIMM specification. The storage command CMD_S corresponding to the write request or the read request can be transmitted through the data input / output pin defined in the DIMM specification together with the storage address ADDR_S. Write data or read data (DATA) may also be transmitted via the data input / output pins.

For example, the RAM 111b may include a multi-port RAM such as a Dual Port SRAM (DPSRAM), a Shared RAM, or the like. In this example, the RAM 111b may be accessed by the processor 101 and the controller 112, respectively, through different ports. The configuration of the ram 111b will be described in more detail with reference to Fig. Further, the write operation and the read operation will be described in more detail with reference to FIGS. 10 to 17. FIG.

The controller 112 may include various hardware or software components for controlling the physical layer 111 and the non-volatile memories 120. For example, the controller 112 may include an ECC encoding / decoding engine, a scrambler / descrambler, a data buffer, and a Flash Translation Layer .

In the above example, the controller 112 may detect and correct errors in the data by the ECC encoding / decoding engine, and generate and add ECC codes for the data. The controller 112 may scramble or descramble the data by a scrambler / descrambler. The controller 112 may temporarily store the data read from the RAM 111b or the nonvolatile memories 120 in the data buffer. The controller 112 may perform a translation between the logical address and the physical address for the storage address ADDR_S by the flash translation layer. To this end, the buffer memory 130 may store a mapping table between a logical address and a physical address of the non-volatile memories 120. [

In an embodiment of the present invention, the processor 101 may provide an error correction code to the storage device 100 along with write data (DATA_W). As an example, the processor 101 may encode an error correction code based on at least one of various encoding schemes such as a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon code, The error correction code may be transmitted to the storage device 100 via a data input / output pin defined in the DIMM specification.

In an embodiment of the present invention, the controller 112 may include an error correction block 112a. The error correction block 112a may decode the error correction code received from the processor 101. [ The error correction block 112a can check the error of the write data (DATA_W) read from the RAM 111b by referring to the decoded error correction code. Based on the error detection result of the error correction block 112a, the device controller 110 can store the error information in the RAM 111b.

The error information can be accessed and monitored by the processor 101. The processor 101 may access the RAM 111b to obtain error information. The error information can be accessed by the processor 101 via the data input / output pins defined in the DIMM specification. Embodiments of the error correction block 112a and the error information will be described in more detail with reference to FIGS. 11 to 17. FIG.

FIG. 9 is a conceptual diagram showing the configuration of the RAM of FIG. 8 and the communication between the processor, the RAM, and the controller. As an embodiment, the RAM 111b may include a command area CA, a writing area WA, a reading area RA, and a state area STA. The command area CA, the write area WA, the read area RA, and the status area STA can be logically or physically distinguished.

One of the command area CA, the writing area WA, the reading area RA and the state area STA can be selected based on the RAM address ADDR_R (see Fig. 8) provided from the processor 101 have. Further, based on the RAM command (CMD_R, see FIG. 8) provided from the processor 101, a write operation or a read operation can be performed with respect to the selected area. As an example, if a RAM write command is provided as the RAM command CMD_R, a write operation can be performed in the selected area. On the other hand, when a RAM read command is provided as the RAM command CMD_R, a read operation can be performed in the selected area.

The command area CA may store the storage command CMD_S and the storage address ADDR_S provided from the processor 101. [ The controller 112 can read the storage command CMD_S and the storage address ADDR_S stored in the command area CA. The storage command CMD_S may indicate whether a write operation is to be performed in one or more non-volatile memories 120 (see FIG. 8) or whether a read operation is to be performed (i.e., a write request or a read request). The storage address ADDR_S may indicate the location of the non-volatile memories 120 in which a write operation or a read operation is to be performed.

The write area WA and the read area RA can store write data (DATA_W) and read data (DATA_R), respectively. Write data DATA_W provided from the processor 101 may be temporarily stored in the write area WA and then provided to the nonvolatile memories 120 under the control of the controller 112. [ The read data (DATA_R) read from the nonvolatile memories 120 may be provisionally stored in the read area RA under the control of the controller 112 and then provided to the processor 101. [

The status area STA can store the status information STI regarding the write data DATA_W and the read data DATA_R under the control of the RAM controller 111 (see FIG. 8) and the controller 112. FIG. The status information (STI) may include information on the progress of a write operation or a read operation. The processor 101 can recognize whether the write operation or the read operation is completed based on the state information (STI). Further, the controller 112 can recognize whether or not a write operation or a read operation needs to proceed based on the state information (STI).

For example, when the processor 101 desires to store the write data (DATA_W), the processor 101 can provide the write data (DATA_W) in the write area WA. Further, the processor 101 can provide information on the write data (DATA_W) and status information (STI) concerning the request of the write operation to the state area (STA). The controller 112 can control the write operation such that write data (DATA_W) is stored in at least one of the nonvolatile memories 120 based on the status information (STI). The processor 101 can recognize completion of the write operation based on the status information STI when the controller 112 stores the status information STI informing completion of the write operation in the status area STA. To do this, the processor 101 may polle the status area STA at specific times (e.g., periodically).

As will be described with reference to Figs. 11 to 17, in the embodiment of the present invention, the write data (DATA_W) can be received together with an error correction code. The error correction code can be stored in the writing area WA together with the writing data (DATA_W). The error correction block 112a can check the error of the write data (DATA_W) by referring to the error correction code. Based on the error detection result, the error information ERR can be stored in the state area STA as the state information STI. The processor 101 may monitor the error information ERR and actively respond to an error of the write data DATA_W.

For example, if the processor 101 wants to read the read data (DATA_R), the processor 101 sends information about the read data (DATA_R) and status information (STI) As shown in FIG. The controller 112 may control the read operation such that the read data (DATA_R) is read from at least one of the non-volatile memories 120 based on the status information (STI). The processor 101 can recognize the completion of the read operation based on the status information STI when the controller 112 stores the status information STI informing completion of the read operation in the status area STA. Further, the processor 101 may be provided with read data (DATA_R) stored in the read area (RA).

10 is a flowchart for explaining a read operation of the storage apparatus of FIG. The processor 101 may be provided with the read data (DATA_R) stored in the storage device 100 according to the read operation of FIG. To facilitate understanding of the present invention, Figures 8 and 9 will be referred to together.

In operation S110, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a write to the RAM 111b. Furthermore, the processor 101 may provide the RAM address ADDR_R for selecting the command area CA of the RAM 111b to the storage device 100. [

In operation S120, the processor 101 may provide the data signal DQ and the data strobe signal DQS to the storage device 100. [ In operation S120, the data signal DQ may include a storage command CMD_S for requesting a read operation on the storage device 100, and more specifically, a read operation on the non-volatile memories 120 . Further, the data signal DQ may include a storage address ADDR_S indicating the location of the nonvolatile memories 120 in which a read operation is to be performed.

S110 and S120 operations may form a command transaction operation for transferring a read command to non-volatile memories 120 to storage device 100. [ When the S110 and S120 operations are performed, the command area CA of the RAM 111b may store the storage command CMD_S and the storage address ADDR_S.

Here, the storage command CMD_S may indicate that a read operation is performed in the nonvolatile memories 120. [ The read operation can be performed at the position of the nonvolatile memories 120 corresponding to the storage address ADDR_S. As the storage command CMD_S and the storage address ADDR_S are stored in the RAM 111b, the controller 112 can control the reading operation based on the storage command CMD_S and the storage address ADDR_S.

In operation S130, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a read about the RAM 111b. Further, the processor 101 may provide the RAM address ADDR_R for selecting the status area STA of the RAM 111b to the storage device 100. [

In operation S140, the processor 101 may receive the data signal DQ and the data strobe signal DQS from the storage device 100. [ In operation S140, the data signal DQ may include status information (STI) regarding the read operation.

In operation S150, the storage device 100 may store the read data (DATA_R) and the status information (STI) regarding the read operation in the status area (STA). For example, when the read operation is completed in the storage device 100, the operation of S150 may be performed.

In operation S160, the processor 101 can determine whether or not the read operation has been completed. The processor 101 can determine whether or not the read operation is completed based on the state information (STI) stored in the state area STA.

Operations S130 through S160 may form a confirm transaction operation to confirm whether or not the read operation has been completed in the non-volatile memories 120. [ If it is determined that the read operation has not been completed, the processor 101 can continue to poll whether or not the read operation has been completed by repeating S130 and S140 operations. On the other hand, if it is determined that the read operation is completed, operation S170 may be performed.

In operation S170, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a read about the RAM 111b. Furthermore, the processor 101 may provide the RAM address ADDR_R for selecting the read area RA of the RAM 111b to the storage device 100. [

In operation S180, the processor 101 may receive the data signal DQ and the data strobe signal DQS from the storage device 100. [ In operation S180, the data signal DQ may include read data (DATA_R) read from the storage device 100. [

S170 and S180 operations may form a data transaction operation for transferring read data (DATA_R) from the storage device 100 to the processor 101. [ When the S170 and S180 operations are performed, the read data (DATA_R) may be stored in the read area (RA) of the RAM 111b and then provided to the processor 101. [ After the S180 operation is completed, the processor 101 may request the next operation of the storage device 100. [

11 is a flowchart for explaining a write operation of the storage apparatus of Fig. The processor 101 may store the write data (DATA_W) in the storage device 100 according to the write operation of Fig. To facilitate understanding of the present invention, Figures 8 and 9 will be referred to together.

In operation S210, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a write to the RAM 111b. Furthermore, the processor 101 may provide the RAM address ADDR_R for selecting the command area CA of the RAM 111b to the storage device 100. [

In operation S220, the processor 101 may provide the data signal DQ and the data strobe signal DQS to the storage device 100. [ In operation S220, the data signal DQ may include a write command for the storage device 100, and more specifically a storage command CMD_S for requesting a write operation for the non-volatile memories 120 . Further, the data signal DQ may include a storage address ADDR_S indicating the location of the non-volatile memories 120 in which a write operation is to be performed.

S210 and S220 operations may form a command transaction operation to transfer a write command to non-volatile memories 120 to storage device 100. [ When operations S210 and S220 have been performed, the command area CA of the RAM 111b may store the storage command CMD_S and the storage address ADDR_S. Here, the storage command CMD_S may indicate that a write operation is performed in the non-volatile memories 120. [ Write operation may be performed at the location of the nonvolatile memories 120 corresponding to the storage address ADDR_S.

In operation S230, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a write to the RAM 111b. Further, the processor 101 may provide the RAM address ADDR_R for selecting the write area WA of the RAM 111b to the storage device 100. [

In operation S240, the processor 101 may provide the data signal DQ and the data strobe signal DQS to the storage device 100. [ In operation S240, the data signal DQ may include write data (DATA_W) to be stored in the storage device 100. [ Further, the data signal DQ may include an error correction code (ECC) used for checking the error of the write data (DATA_W).

S230 and S240 operations may form a data transaction operation to transfer write data (DATA_W) to be stored in the non-volatile memories 120 to the storage device 100. [ When the operations of S230 and S240 are performed, the writing area WA of the RAM 111b can store the write data (DATA_W) and the error correction code (ECC).

As the storage command CMD_S, the storage address ADDR_S, the write data DATA_W and the error correction code ECC are stored in the RAM 111b, the controller 112 refers to the error correction code ECC, It is possible to check the error of the data (DATA_W). Further, the controller 112 can control the write operation based on the storage command CMD_S and the storage address ADDR_S.

In operation S250, the processor 101 may provide a RAM command (CMD_R) to the storage device 100 for requesting a read about the RAM 111b. Further, the processor 101 may provide the RAM address ADDR_R for selecting the status area STA of the RAM 111b to the storage device 100. [

In operation S260, the processor 101 may receive the data signal DQ and the data strobe signal DQS from the storage device 100. [ In operation S260, the data signal DQ may include status information (STI) regarding the write operation.

In operation S270, the storage apparatus 100 may store write data (DATA_W) and status information (STI) regarding write operations in the status area STA. Particularly, in the embodiment of the present invention, the storage apparatus 100 can determine whether there is an error in the write data (DATA_W) by referring to the error correction code (ECC). Further, the storage apparatus 100 may generate error information ERR as the status information STI based on the error detection result, and store the generated error information ERR in the status area STA. For example, when the write operation is completed in the storage apparatus 100, the write operation is scheduled, the instruction of the write operation enters the queue, or the write data (DATA_W ), The operation S270 can be performed. S270 operation will be described in more detail with reference to FIG.

In operation S280, the processor 101 may determine whether there is an error in the write data (DATA_W) or whether the write operation has been completed. The processor 101 can determine whether or not the write operation is completed based on the state information (STI) stored in the state area STA. Particularly, in the embodiment of the present invention, the processor 101 can acquire the error information ERR stored in the state area STA and actively respond to an error of the write data DATA_W. S280 operation will be described in more detail with reference to FIG.

Operations S250 through S280 may form a confirm transaction operation to confirm whether a write operation has been completed in the non-volatile memories 120. [ 13 and 14, if it is determined that the write operation has not been completed, the processor 101 can continue to poll whether or not the write operation has been completed by repeating S250 and S260 operations. Alternatively, when it is determined that there is an error in the write data (DATA_W), the processor 101 can recognize the error through the error information (ERR). On the other hand, if it is determined that the write operation is completed, the processor 101 may request the next operation of the storage device 100. [

12 is a conceptual diagram for explaining a process of notifying an error of write data in the write operation of FIG. For ease of understanding of the present invention, Fig. 8 will be referred to together.

The processor 101 may provide the storage command CMD_S and the storage address ADDR_S to the controller 112 to store the write data DATA_W in at least one of the non-volatile memories 120 have. The storage command CMD_S and the storage address ADDR_S can be transferred through the command area CA of the RAM 111b (operation 1). Thereafter, the processor 101 may provide the write data (DATA_W) to the controller 112 together with an error correction code (ECC). As an example, the write data (DATA_W) and the error correction code (ECC) can be transmitted through the write area WA of the RAM 111b (operation 2).

The error correction block 112a of the controller 112 may be provided with an error correction code (ECC). The error correction block 112a can check the error of the write data (DATA_W) by referring to the error correction code (ECC) (operation 3). In some cases, the write data (DATA_W) may be error free. On the other hand, in some other cases, there is an error in the write data (DATA_W), but the error may be correctable. In the worst case, the write data (DATA_W) may have an uncorrectable error.

Based on the error detection result of the error correction block 112a, the controller 112 can store the error information ERR in the state area STA of the RAM 111b (operation 4). As an example, the error information ERR may include information as to whether or not an error has been detected in the write data DATA_W. As an example, the error information ERR may include information regarding whether or not the detected error is correctable. As an example, the error information ERR may include information as to whether or not the correctable error has been corrected.

The processor 101 can access the state area STA of the RAM 111b. The processor 101 may access the state area STA at a specific point in time (e.g., periodically) to obtain error information ERR stored in the state area STA. The processor 101 can confirm whether or not the error information ERR is stored in the state area STA at each confirmation time (operation 5). Accordingly, the processor 101 can acquire information on errors of the write data (DATA_W) and actively respond to errors.

FIG. 13 is a flowchart for explaining a process in which the storage device of FIG. 8 checks errors and generates error information in the writing operation of FIG. To facilitate understanding of the present invention, Figures 8, 11 and 12 will also be referred to.

In operation S310, the storage device 100 may receive write data (DATA_W) from the processor 101 by the device controller 110. [ The write data (DATA_W) may be received together with an error correction code (ECC). The S310 operation may be performed according to the operations S210 to S240 of FIG.

In operation S320, the storage apparatus 100 can check the error of the write data (DATA_W) by the error correction block 112a. The error correction block 112a can check the error of the write data (DATA_W) by referring to the error correction code (ECC). The storage device 100 may store write data (DATA_W) in at least one of the non-volatile memories 120 by the device controller 110 if an error is not detected in the S320 operation.

Further, if no error is detected in operation S320, operation S330 may be performed. In operation S330, the storage device 100 may store the status information (STI) in the status area STA of the RAM 111b by the device controller 110. [ Here, the status information STI may indicate that the write data (DATA_W) is normally stored. The processor 101 can recognize the completion of the write operation by referring to the status information (STI).

If an error is detected in operation S320, operation S340 may be performed. In operation S340, the storage apparatus 100 can determine whether or not the error detected by the error correction block 112a is correctable. It is well known to determine whether or not the error is correctable based on the error correction code (ECC), so a detailed description will be omitted.

If the detected error is determined to be correctable in operation S340, the storage device 100 can correct the detected error by the error correction block 112a. After the error is properly corrected, the storage device 100 may store the write data (DATA_W) in at least one of the non-volatile memories 120 by the device controller 110.

Further, if the detected error is determined to be correctable in operation S340, operation S350 may be performed. In operation S350, the storage device 100 may store the error information ERR in the status area STA of the RAM 111b by the device controller 110. [ Here, the error information ERR may indicate that an error is detected in the write data (DATA_W) but the detected error is correctable.

If the detected error is properly corrected, the error information ERR may further indicate that the detected error has been corrected. Further, when the write data (DATA_W) is stored after the detected error is corrected, the error information (ERR) or the status information (STI) may indicate that the write data (DATA_W) is normally stored. The processor 101 can recognize the occurrence of an error, the correction of an error, and the completion of a write operation by referring to the state information (STI) and / or the error information (ERR).

If the detected error is determined to be uncorrectable in operation S340, operation S360 may be performed. In operation S360, the storage device 100 may store the error information ERR in the status area STA of the RAM 111b by the device controller 110. [ Here, the error information ERR may indicate that an error has been detected in the write data (DATA_W) and that the detected error is uncorrectable.

The processor 101 can recognize the occurrence of an error and the impossibility of correcting the error by referring to the error information ERR. Thus, in operation S365, the storage apparatus 100 can re-receive the write data (DATA_W) from the processor 101 based on the error information ERR. S365 operation can be performed in accordance with the operations S210 to S240 in Fig. After the write data (DATA_W) is re-received, in S320 operation, the storage device 100 can check the error of the re-received write data (DATA_W).

14 is a flowchart for explaining the process of the host (i.e., the processor 101) of FIG. 8 in confirming the error information in the write operation of FIG. To facilitate understanding of the present invention, Figures 8, 11 and 12 will also be referred to.

After the processor 101 sends the write data (DATA_W) and the error correction code (ERR) to the storage device 100, the processor 101 can poll the status area STA of the RAM 111b have. Accordingly, in S410 operation, the processor 101 can check whether the state information (STI) or the error information (ERR) is stored in the state area (STA). S410 operation may be performed in accordance with S250 and S260 operations in Fig.

In operation S420, the processor 101 may determine whether or not the write operation has been completed by referring to the status information (STI) and / or the error information (ERR). Write data (DATA_W) may be stored in at least one of the non-volatile memories 120 when an error of the write data (DATA_W) is not detected, as described with reference to Fig. Alternatively, after a correctable error is detected and the error corrected, the write data (DATA_W) may be stored in at least one of the non-volatile memories 120. When the write data (DATA_W) is stored and the write operation is completed, the processor 101 can continue to request the next operation.

On the other hand, if it is determined that the write operation is not completed, operation S430 may be performed. In operation S430, the processor 101 may determine whether or not an uncorrectable error has occurred in the write data (DATA_W). If an uncorrectable error has not occurred, the write data (DATA_W) may not have been completely stored yet. Therefore, the processor 101 can again check whether the status information (STI) or the error information (ERR) is stored in operation S410.

If an uncorrectable error is detected in operation S430, operation S440 may be performed. In operation S440, the processor 101 may retransmit the write data (DATA_W) to the storage device 100. [ Operation S440 may be performed in accordance with operations S210 to S240 of FIG. After the write data DATA_W is retransmitted, the processor 101 can confirm in operation S410 whether the status information (STI) or the error information (ERR) is stored with respect to the retransmitted write data (DATA_W).

According to the embodiment of the present invention, whether or not an error of the write data (DATA_W) has occurred in the storage apparatus 100 can be monitored by the processor 101. [ Therefore, the processor 101 can check the state of the write data (DATA_W) and actively respond to the error. As a result, the reliability of storing the write data (DATA_W) can be improved.

FIG. 15 is a conceptual diagram for explaining operations in a case where an error of write data does not occur in the write operation of FIG.

After the processor 101 provides the write data (DATA_W) and the error correction code (ECC) to the controller 112 via the write area WA, the error correction block 112a refers to the error correction code ECC It is possible to check the error of the write data (DATA_W) (operation 1). In some cases, no error may be detected in the write data (DATA_W). In this case, under the control of the controller 112, write data (DATA_W) may be stored in at least one non-volatile memory (for example, the non-volatile memory 121) among the non-volatile memories 120 (Operation 2).

When the write data DATA_W is stored in the nonvolatile memory 121 and the write operation is completed, the controller 112 can store the state information STI in the state area STA of the RAM 111b (operation 3) . Here, the status information STI may indicate that the write data (DATA_W) is normally stored. The processor 101 may recognize the completion of the write operation by referring to the state information (STI) (operation 4).

16 is a conceptual diagram for explaining operations when a correctable error of write data occurs in the write operation of FIG.

After the processor 101 provides the write data (DATA_W) and the error correction code (ECC) to the controller 112 via the write area WA, the error correction block 112a refers to the error correction code ECC It is possible to check the error of the write data (DATA_W) (operation 1). The error correction block 112a can detect an error in the write data (DATA_W). However, in some cases, the detected error may be correctable.

In one embodiment, the controller 112 may store the error information ERR in the state area STA of the RAM 111b (operation 2) to inform the processor 101 of the detection of a correctable error. Here, the error information ERR may indicate that an error is detected in the write data (DATA_W) but the detected error is correctable. Thereafter, the error correction block 112a can correct the detected error based on the error correction code (ECC) (operation 3). In one embodiment, the controller 112 may store error information ERR in the state area STA of the RAM 111b to inform the processor 101 of the correction of the error (operation 4). Here, the error information ERR may indicate that the detected error has been corrected.

After the detected error is corrected, the write data (DATA_W) is written to at least one nonvolatile memory (for example, the nonvolatile memory 121) of the nonvolatile memories 120 (see FIG. 8) (Operation 5). The controller 112 may store the state information STI and / or the error information ERR in the state area STA of the RAM 111b to notify the processor 101 of the write data (DATA_W) Action ⑥). Here, the status information (STI) and / or the error information (ERR) may indicate that the write data (DATA_W) is normally stored.

The processor 101 may recognize the occurrence of an error, the correction of an error, and the completion of a write operation by referring to the state information (STI) and / or the error information (ERR) (operation 7).

17 is a conceptual diagram for explaining operations when an uncorrectable error of write data occurs in the write operation of FIG.

After the processor 101 provides the write data (DATA_W) and the error correction code (ECC) to the controller 112 via the write area WA, the error correction block 112a refers to the error correction code ECC It is possible to check the error of the write data (DATA_W) (operation 1). The error correction block 112a can detect an error in the write data (DATA_W). In some cases, the detected error may be uncorrectable.

The controller 112 may store the error information ERR in the state area STA of the RAM 111b to inform the processor 101 of the detection of the uncorrectable error (operation 2). Here, the error information ERR may indicate that an uncorrectable error has been detected in the write data (DATA_W). The processor 101 may recognize the occurrence of an error and the impossibility of correcting the error by referring to the error information ERR (operation 3).

Since an uncorrectable error has been detected in the write data (DATA_W), the processor 101 can retransmit the write data (DATA_W) to the controller 112 (operation 4). The controller 112 can check the error of the re-received write data (DATA) by the error correction block 112a. The controller 112 can generate the status information (STI) or the error information (ERR) based on the error detection result.

According to the embodiments described with reference to Figures 8-17, the processor 101 of Figure 8 communicates with the device controller 112 of Figure 8 via a bus operating at high speed, such as the bus 1230 of Figure 1 can do. For example, when the storage device 100 of FIG. 8 is implemented in the form of a DIMM and the processor 101 communicates with the device controller 112 in accordance with an interface protocol operating in DDR mode, ) Is recognized as a DIMM device, and a write operation and a read operation for the RAM 111b of FIG. 8 can be performed according to an interface protocol operating in the DDR scheme. Therefore, according to the embodiment of the present invention, the storage apparatus 100 can exhibit high operation performance.

Figure 18 is a block diagram showing one of the non-volatile memories of Figure 8; At least one of the non-volatile memories 120 of FIG. 8 may include a non-volatile memory 121. FIG. The nonvolatile memory 121 may include a memory cell array 121a, an address decoder 121b, a control logic and voltage generator 121c, a page buffer 121d, and an input / output circuit 121e.

The memory cell array 121a may include a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks may comprise a plurality of cell strings. Each of the cell strings may comprise a plurality of memory cells. Each of the memory cells may be connected to a plurality of word lines (WL). Each of the memory cells may include a single level cell storing one bit or a multi level cell storing at least two bits.

As an example, the memory cell array 121a may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of memory cell arrays having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be disposed within or on the substrate. The term " Monolithical "means that layers of each level of the three-dimensional memory array are deposited directly on the lower level layers of the three-dimensional memory array.

As an example, the three-dimensional memory array may include vertical NAND strings with vertical orientation and at least one memory cell located over the other memory cell. The at least one memory cell may include a charge trap layer. Each of the vertical NAND strings may include at least one select transistor located above the memory cells. At least one select transistor may be constructed in the same structure as the memory cells and monolithically formed with the memory cells.

Suitable configurations for a three-dimensional memory array, such as a three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between levels, are described in U.S. Patent No. 7,679,133, U.S. Patent No. 8,554,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, the disclosures of which are incorporated herein by reference.

The address decoder 121b may be connected to the memory cell array 121a via word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 121b can receive the storage address ADDR_S 'from the device controller 110 (see FIG. 8) and decode the received storage address ADDR_S'. The address decoder 121b may select at least one of the word lines WL based on the decoded storage address ADDR_S 'and may drive the selected at least one word line.

The control logic and voltage generator 121c may receive the storage command CMD_S 'and the control signal CTRL from the device controller 110. [ The control logic and voltage generator 121c can control the address decoder 121b, the page buffer 121d, and the input / output circuit 121e in response to the received signals. As an example, the control logic and voltage generator 121c may be configured such that the write data (DATA) provided from the device controller 110 is stored in the memory cell array 121a in response to the storage command CMD_S 'and the control signal CTRL The decoder 121b, the page buffer 121d, and the input / output circuit 121e so that the read data (DATA) stored in the memory cell array 121a can be read.

The control logic and voltage generator 121c may generate various voltages used to operate the non-volatile memory 121. [ By way of example, control logic and voltage generator 121c may generate a plurality of program voltages, a plurality of pass voltages, a plurality of selected read voltages, a plurality of unselected read voltages, a plurality of erase voltages, and a plurality of verify voltages . The control logic and voltage generator 121c may provide the generated voltages to the address decoder 121b or to the substrate of the memory cell array 121a.

The page buffer 121d may be connected to the memory cell array 121a through a plurality of bit lines BL. The page buffer 121d controls the bit lines BL so that the write data DATA provided from the input / output circuit 121e is stored in the memory cell array 121a under the control of the control logic and the voltage generator 121c . The page buffer 121d may read the read data stored in the memory cell array 121a and provide the read data to the input / output circuit 121e under the control of the control logic and the voltage generator 121c. For example, the page buffer 121d may receive data on a page basis from the input / output circuit 121e, or may read data on a page basis from the memory cell array 121a. As an embodiment, the page buffer 121d may include data latches for temporarily storing data read from the memory cell array 121a or data provided from the input / output circuit 121e.

The input / output circuit 121e may receive write data (DATA) from an external device such as the device controller 110 and provide the supplied write data (DATA) to the page buffer 121d. Alternatively, the input / output circuit 121e may receive the read data (DATA) from the page buffer 121d and provide the received read data (DATA) to an external device such as the device controller 110. For example, the input / output circuit 121e can exchange data (DATA) with an external device in synchronization with the control signal CTRL.

19 is a conceptual diagram showing one memory block of the memory cell array of FIG. Referring to Fig. 19, a first memory block BLK1 of a three-dimensional structure will be described. For example, FIG. 19 shows a case where the memory cell array 121a of FIG. 18 includes a NAND flash memory. However, the present invention is not limited by Fig. Furthermore, other memory blocks may also be configured similar to the first memory block BLK1.

Referring to FIG. 19, the first memory block BLK1 may include a plurality of cell strings CS11, CS12, CS21, and CS22. The cell strings CS11, CS12, CS21, CS22 may be arranged along the row direction and the column direction to form rows and columns. For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row. Furthermore, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form the first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.

Each of the cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. For example, each of the cell strings CS11, CS12, CS21, and CS22 includes a plurality of memory cells MC1 to MC8, a plurality of memory cells MC1 to MC8, a plurality of memory cells MC1 to MC8, (Dummy) memory cells DMC1, DMC2. As an example, each of the plurality of cell transistors included in the cell strings CS11, CS12, CS21, and CS22 may be a charge trap flash memory cell.

The memory cells MC1 to MC8 are connected in series and can be stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selected transistors SSTa and SSTb may be connected in series and the string selected transistors SSTa and SSTb connected in series may be provided between the memory cells MC1 to MC8 and the bit line BL. The grounded selected transistors GSTa and GSTb are connected in series and the grounded selected transistors GSTa and GSTb connected in series may be provided between the memory cells MC1 to MC8 and the common source line CSL.

As an example, a first dummy memory cell DMC1 may be provided between the memory cells MC1 to MC8 and the ground selected transistors GSTa and GSTb. As an example, a second dummy memory cell DMC2 may be provided between the memory cells MC1 to MC8 and the string selected transistors SSTa and SSTb.

The ground selected transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be connected in common to the ground selection line GSL. By way of example, the ground selected transistors of the same row may be connected to the same ground select line, and the ground selected transistors of different rows may be connected to different ground select lines. By way of example, the first ground selected transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selection transistors GSTa of the cell strings CS21, 1 ground selected transistors (GSTa) may be connected to the second ground selection line.

By way of example, not shown, ground selected transistors lying at the same height from a substrate (not shown) may be connected to the same ground select line, and ground selected transistors placed at different heights may be connected to different ground select lines . As an example, the first ground selected transistors GSTa of the cell strings CS11, CS12, CS21, CS22 are connected to a first ground selection line, and the second ground selection transistors GSTb are connected to a second ground selection line Lt; / RTI >

The memory cells placed at the same height from the substrate or ground selected transistors (GSTa, GSTb) are connected in common to the same word line, and the memory cells placed at different heights can be connected to different word lines. For example, the first to eighth memory cells MC1 to MC8 of the cell strings CS11, CS12, CS21, and CS22 may be commonly connected to the first to eighth word lines WL1 to WL8, respectively.

The string selected transistors of the same row among the first string selected transistors SSTa lying at the same height may be connected to the same string select line and the other strings of string selected transistors may be connected to another string select line. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row are connected in common, The first string selected transistors (SSTa) of the memory cell array may be connected in common with the string selection line (SSL1a).

Similarly, string selected transistors in the same row of the second string selected transistors (SSTb) that lie at the same height may be connected to the same string select line, and strings of the other rows may be connected to different string select lines. By way of example, the second string selected transistors SSTb of the cell strings CS11, CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21, CS22 of the second row are connected in common, The second string selected transistors (SSTb) of the second transistor can be connected in common with the string selection line (SSL2b).

Although not shown in the figure, string selected transistors of cell strings in the same row may be connected in common to the same string select line. For example, the first and second string selected transistors (SSTa, SSTb) of the cell strings CS11, CS12 of the first row may be connected in common to the same string selection line. The first and second string selected transistors (SSTa, SSTb) of the cell strings CS21, CS22 of the second row may be connected in common to the same string selection line.

By way of example, dummy memory cells that lie at the same height are connected to the same dummy word line, and dummy memory cells that lie at different heights can be connected to different dummy word lines. For example, the first dummy memory cells DMC1 may be connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 may be connected to the second dummy word line DWL2.

In the first memory block BLK1, reading and writing can be performed line by line. As an example, one row of the first memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, when a turn-on voltage is supplied to the string selection lines SSL1a and SSL1b and a turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, Cell strings CS11 and CS12 of one row may be connected to bit lines BL1 and BL2. On the other hand, when a turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and a turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row, May be connected to the bit lines BL1 and BL2. Among the memory cells of the cell string of the row driven by driving the word line, the memory cells located at the same height can be selected. Read and write operations can be performed on selected memory cells. Selected memory cells may form a physical page unit.

In the first memory block BLK1, erasing may be performed in units of memory blocks or units of subblocks. When erasing is performed in units of memory blocks, all the memory cells MC1 to MC8 of the first memory block BLK1 can be erased simultaneously according to one erase request. When performed in units of subblocks, some of the memory cells MC1 to MC8 of the first memory block BLK1 may be simultaneously erased in response to one erase request, and some of the memory cells MC1 to MC8 may be erased. A low voltage (e. G., Ground voltage) is applied to the word line connected to the erased memory cells, and the word line connected to the erased memory cells may be floated.

The configuration of the first memory block BLK1 shown in Fig. 19 is an example. The number of cell strings may increase or decrease and the number of rows and columns constituted by cell strings may increase or decrease depending on the number of cell strings. Further, the number of the cell transistors (GST, MC, DMC, SST, etc.) of the first memory block BLK1 may increase or decrease, and the height of the first memory block BLK1 Can be increased or decreased. In addition, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may increase or decrease according to the number of cell transistors.

20 is a conceptual diagram showing a server system including a storage apparatus according to an embodiment of the present invention. Referring to FIG. 20, the server system 7000 may include a plurality of server racks. FIG. 20 exemplarily shows one server rack 7100 among a plurality of server racks.

Each of the server racks may include at least one storage device. By way of example, the server rack 7100 may include at least one storage device. The storage device can be implemented based on the embodiments of the present invention described with reference to Figs. 20 shows one storage device 7200 among a plurality of storage devices included in the server rack 7100. FIG.

The server rack 7100 may include at least one processor 1100, one or more RAM module devices 1210 and 1212, and at least one chipset 1300, as shown in FIG. 1, as well as the storage device 7200 have. Further, the server system 7000 can include the GPU 1400, the input / output device 1500, and the at least one second type storage device 1600 shown in FIG.

The storage device 7200 may be connected without the chipset 1300 to at least one processor 1100 included in the server rack 7100. By way of example, storage device 7200 may be a non-volatile memory module implemented in the form of a DIMM. In this example, the storage device 7200 can communicate with the processor 1100 by being coupled to a DIMM socket that is electrically coupled to the processor 1100. By way of example, storage device 7200 may communicate with processor 1100 in accordance with an interface protocol defined based on the DIMM specification and operating in DDR fashion.

The storage device 7200 may be configured and operative based on the embodiments of the invention described with reference to Figures 1-19. According to embodiments of the present invention, the storage device 7200 can communicate with the processor 1100 over a bus operating at a high speed. According to embodiments of the present invention, the storage apparatus 7200 can exhibit high operation performance, and the storage performance of the server system 7000 can be improved.

Circuits, chips, devices, and modules according to embodiments of the present invention may be implemented using various types of semiconductor packages. By way of example, the circuits, chips, devices, and modules according to embodiments of the present invention may be implemented on a variety of devices such as Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carriers Die in Waffer Pack, COB (Chip On Board), CERDIP (Ceramic Dual In-line Package), MQFP (Metric Quad Flat Pack), TQFP (Thin Quad Flat) Packs, Small Outline Integrated Circuits (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP) And can be mounted using a package such as a wafer-level process stack package (WSP).

The configurations shown in the respective conceptual diagrams should be understood from a conceptual viewpoint only. In order to facilitate understanding of the present invention, the shape, structure, size, etc. of each of the components shown in the conceptual diagram have been exaggerated or reduced. The configuration actually implemented may have a physical shape different from that shown in the respective conceptual diagrams. Each conceptual diagram is not intended to limit the physical form of the component.

The device configurations shown in the respective block diagrams are intended to facilitate understanding of the invention. Each block may be formed of blocks of smaller units depending on the function. Alternatively, the plurality of blocks may form a block of a larger unit depending on the function. That is, the technical idea of the present invention is not limited to the configuration shown in the block diagram.

The present invention has been described above with reference to the embodiments of the present invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Accordingly, the above embodiments should be understood in an illustrative rather than a restrictive sense. That is, the technical idea that can achieve the same object as the present invention, including the gist of the present invention, should be interpreted as being included in the technical idea of the present invention.

Therefore, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. The scope of protection of the present invention is not limited to the above embodiments.

10: Storage Systems
100: Storage device 101: Processor
110: device controller 111: physical layer
111a: RAM controller 111b: RAM
112: controller 112a: error correction block
120: Nonvolatile memories 121: Nonvolatile memories
121a: memory cell array 121b: address decoder
121c: Control logic and voltage generator
121d: page buffer 121e: input / output circuit
130: buffer memory
1000: computing system 1100: processor
1210, 1212: RAM module devices 1220, 1222: storage device of the first type
1230: Bus running at high speed
1300: Chipset 1400: GPU
1500 I / O device 1600: second type storage device
2000, 3000, 4000, 5000, 6000: Storage device
4005, 5005, 6005: control circuit
2100, 3100, 4100, 5100, 6100: Device controller
2100b, 3100b, 4100b, 5100b, 6100b: RAM
2200, 3200, 4200, 5200, 6200: non-volatile memories
2300, 3300: buffer memory
3400, 5400: Data buffer circuit
2500, 3500, 4500, 5500, 6500: SPD chip
4600, 5600, 6600: DRAMs
7000: Server system 7100: Server rack
7200: Storage Devices

Claims (10)

One or more non-volatile memories; And
And a device controller configured to receive the write data with the error correction code from the host, to check the error of the write data with reference to the error correction code, and to store the write data in at least one of the non-volatile memories However,
Wherein the device controller is further configured to store the error information in a RAM included in the device controller such that error information about the error is accessed by the host. The method according to claim 1,
Wherein the error information includes information on whether or not the error is detected in the write data. 3. The method of claim 2,
And when the error is detected in the write data, the error information further includes information on whether or not the detected error is correctable. The method of claim 3,
And the device controller is configured to re-receive the write data from the host based on the error information if the error information indicates that the detected error is uncorrectable. The method of claim 3,
If the error is detected in the write data and the detected error is correctable, the error information further includes information indicating that the write data is stored in at least one of the non-volatile memories after the detected error is corrected A non-volatile memory module. The method according to claim 1,
Wherein the device controller is configured to store the write data in at least one of the non-volatile memories if the error is not detected or the error is correctable. The method according to claim 1,
Wherein the device controller is configured to operate in accordance with an interface protocol defined by a DIMM specification. One or more non-volatile memories; And
A device controller configured to receive write data with an error correction code from a host and store the write data in at least one of the non-volatile memories,
The device controller comprising:
A physical layer including a RAM and a RAM controller configured to control the RAM according to a RAM command and a RAM address provided from the host; And
Wherein the write data is temporarily stored in the RAM and is stored in a position of the nonvolatile memories corresponding to the storage addresses based on a storage command and a storage address provided from the host and stored in the RAM, And a controller configured to control the non-volatile memories,
Wherein the controller includes an error correction block configured to check an error of the write data by referring to the error correction code after the write data is read from the RAM,
Wherein the device controller is further configured to store error information regarding the error in the RAM. 9. The method of claim 8,
Wherein the error correction block is further configured to correct the detected error if the error is detected and the detected error is correctable. At least one storage device; And
And at least one processor configured to transmit write data with an error correction code to the storage device,
The storage device checks the error of the write data with reference to the error correction code, stores error information on the error in the RAM included in the physical layer of the storage device, and if there is no error or the error is correctable Said write data being configured to store said write data,
Wherein the processor is further configured to access the RAM to obtain the error information.

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