KR20160144564A - Nonvolatile memory module and operation method thereof - Google Patents

Abstract

A non-volatile memory module according to an embodiment of the present invention includes a plurality of non-volatile memory devices, and a storage controller that receives a storage command from an external device and controls a plurality of non-volatile memory devices in response to the received storage command . The storage controller includes an error correction code (ECC) engine for detecting and correcting an error of a received storage command, and transmits an alarm signal to an external device when an error of the storage command is detected by the ECC engine.

Description

NONVOLATILE MEMORY MODULE AND OPERATION METHOD THEREOF FIELD OF THE INVENTION [0001]

The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory module and an operation method thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

Flash memory, which is a type of nonvolatile memory device, is widely used as a storage device in various fields because of its advantages such as large capacity, low noise and low power. In particular, solid state drives (SSDs) based on flash memory are used as mass storage in personal computers, notebooks, workstations, and server systems. Typical SSD devices are connected to a computing system based on a SATA interface or a PCI-express interface. In recent years, however, as the amount of data processed in the computing system increases, the data throughput becomes larger than the data bandwidth or communication speed of the interface connected to the SSD devices, resulting in a data bottleneck. These phenomena act as a factor that hinders the performance of the computing system, and various performance enhancement techniques for solving the above-mentioned problems are being developed.

As an example, SSD devices using a double data rate (DDR) interface are being developed. DDR interfaces provide faster access speeds than typical PCI or SATA interfaces. However, since the DDR interface is basically an interface based on a DRAM device, there are various problems in applying to the SSD device.

An object of the present invention is to detect and correct an error of information received from an external device (i.e., a processor), and to detect or correct an error in an external device via a notification signal when an error is detected or an error is not corrected And a method of operating the nonvolatile memory module.

A non-volatile memory module according to an embodiment of the present invention includes a plurality of non-volatile memory devices; And a storage controller that receives a storage command from an external device and controls the plurality of non-volatile memory devices in response to the received storage command, wherein the storage controller detects and corrects errors in the received storage command And an error correction code (ECC) engine. When an error of the storage command is detected by the ECC engine, a notification signal is transmitted to the external device.

In an embodiment, when the error is not detected or the error is corrected, the storage controller performs an operation corresponding to the storage command.

In one embodiment, the storage command receives a RAM command, a RAM address, and a clock from the external device, and receives a storage command from the external device according to the received RAM command, the received RAM address, and the received clock .

In an embodiment, the storage controller further comprises a RAM,

The storage controller stores the received command in the RAM according to the received RAM command, the received RAM address, and the received clock.

In an embodiment, the ECC engine detects and corrects errors in the storage commands stored in the RAM.

In an embodiment, the ECC engine detects and corrects an error of the storage command based on an error correction code corresponding to the storage command provided from the external apparatus.

In an embodiment, the storage command further comprises a multipurpose register, and if the error is detected or the error is not corrected, the ECC information for the error is written to the multipurpose register.

As an embodiment, the storage controller transmits the notification signal to the external device, and then transmits the ECC information written in the multi-purpose register to the external device under the control of the external device.

As an embodiment, the storage controller transmits the notification signal to the external device, and then transmits the ECC information on the error to the external device through the serial bus under the control of the external device.

In an embodiment, the storage controller and the external device communicate based on a DDR (Double Data Rate) interface.

In an embodiment, the storage controller further receives write data from the external device, the ECC engine detects and corrects errors in the write data, and the storage controller determines that an error in the write data is detected or not And transmits a notification signal to the external device.

In an embodiment, at least one of the plurality of non-volatile memory devices includes a three-dimensional memory array.

A method of operating a non-volatile memory module including at least one non-volatile memory device and a storage controller controlling the at least one non-volatile memory device according to an embodiment of the present invention includes receiving a storage command from an external device; Detecting and correcting an error of the received storage command through an error correction code (ECC) engine; And performing an operation corresponding to the storage command when an error of the storage command is not detected, and transmitting a notification signal to the external apparatus when an error of the storage command is detected.

As an embodiment, the step of receiving a storage command from the external device includes receiving a RAM command, a RAM address, and a clock from the external device; And storing the storage command received from the external device in a RAM included in the storage controller in response to the RAM command, the RAM address, and the clock.

As an embodiment, the step of detecting and correcting an error of the received storage command through the Error Correction Code (ECC) engine may include detecting an error of the received storage command based on an error correction code provided from the external apparatus, And detecting and correcting the error.

In an embodiment, the non-volatile memory module and the external device communicate based on a DDR (Double Data Rate) interface.

As an embodiment, a method of operating a user system including a processor and a non-volatile memory module electrically coupled to the processor includes the steps of: the processor transmitting a storage command to the non-volatile memory module; The nonvolatile memory module detecting and correcting an error of the received storage command; When the error is detected, the nonvolatile memory module transmits a notification signal to the processor; And in response to the notification signal, the processor resends the storage command to the nonvolatile memory module.

As an embodiment, the step of the processor transmitting a storage command to the non-volatile memory module includes the steps of: the processor transmitting a RAM command, a RAM address, and a clock to the non-volatile memory module; And the processor transmitting the data signal and the data strobe signal including the storage command to the nonvolatile memory module.

According to the present invention, the nonvolatile memory module can detect and correct an error of a storage command received from an external device. At this time, when an error is detected or not corrected, the nonvolatile memory module transmits a notification signal to the external device. The external device recognizes that an error exists in the transmitted storage command in response to the notification signal, and can perform the same operation as the retransmission of the storage command. Accordingly, since the nonvolatile memory module can operate normally, a nonvolatile memory module having improved reliability and an operation method thereof are provided.

1 is a block diagram illustrating a user system in accordance with an embodiment of the present invention.
Fig. 2 is a diagram for explaining the RAM of Fig.
3 is a flow chart illustrating the operation of the nonvolatile memory system of FIG.
FIGS. 4 and 5 are views for explaining the operation of FIG. 3 in detail.
Figure 6 is a flow chart illustrating another operation of the nonvolatile memory system of Figure 1;
7 is a block diagram illustrating a user system according to another embodiment of the present invention.
8 is a flowchart showing the operation of the nonvolatile memory system of FIG.
9 is a block diagram illustrating an exemplary first non-volatile memory device of the plurality of non-volatile memory devices of FIG.
FIG. 10 is a block diagram illustrating a computing system to which a non-volatile memory system according to the present invention is applied.
FIG. 11 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 10 by way of example.
FIG. 12 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 10 by way of example.
13 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied.
14 is a block diagram illustrating an exemplary nonvolatile memory module of FIG.
15 is a block diagram illustrating an exemplary nonvolatile memory module of FIG.
16 is a block diagram illustrating an exemplary non-volatile memory module of FIG.
17 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.

In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, details such as detailed configurations and structures are provided merely to assist in an overall understanding of embodiments of the present invention. Modifications of the embodiments described herein can be performed by those skilled in the art without departing from the spirit and scope of the present invention. Moreover, descriptions of well-known functions and structures are omitted for clarity and brevity. The terms used in the present specification are defined in consideration of the functions of the present invention and are not limited to specific functions. Definitions of terms may be determined based on the description in the detailed description.

Modules in the following figures or detailed description may be shown in the drawings or may be connected to others in addition to the components described in the detailed description. The connections between the modules or components may each be integral or non-direct. The connections between the modules or components may be a communication connection or a physical connection, respectively.

Unless defined otherwise, all terms including technical and scientific meanings used herein have the meaning as understood by one of ordinary skill in the art to which this invention belongs. Generally, terms defined in the dictionary are interpreted to have equivalent meaning to the contextual meaning in the related mood field, and are not interpreted to have ideal or overly formal meaning unless explicitly defined in the text.

1 is a block diagram illustrating a user system in accordance with an embodiment of the present invention. Fig. 2 is a diagram for explaining the RAM of Fig. Referring to FIGS. 1 and 2, the user system 10 includes a processor 101 and a non-volatile memory system 100. Illustratively, the user system 100 may be a computer, a portable computer, an Ultra Mobile PC (UMPC), a workstation, a server computer, a net-book, a PDA, a portable computer, a web tablet A wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, A digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, And may include one of a variety of electronic devices.

The processor 101 may process data or control components included in the user system 100. For example, the processor 101 may be capable of running various operating systems and running various applications on an operating system. The processor 101 can write data (DATA) to the non-volatile memory system 100 or read the data (DATA) stored in the non-volatile memory system 100. [

Illustratively, the processor 101 may send a RAM command CMD_R, a RAM address ADDR_R, and a clock CK to the non-volatile memory system 100. The processor 101 may exchange the data signal DQ and the data strobe signal DQS with the nonvolatile memory system 100. [ Illustratively, the data signal DQ may be a signal including a storage command CMD_S, a storage address ADDR_S, data DATA, and status information STI.

Illustratively, the RAM command CMD_R and the RAM address ADDR_R may be a command and an address for controlling the RAM 111b included in the physical layer 111 of the nonvolatile memory system 100. The storage command CMD_S and the storage address ADDR_S may be commands for controlling the plurality of nonvolatile memory devices 131 to 13n included in the nonvolatile memory system 100.

Illustratively, the RAM command CMD_R, the RAM address ADDR_R, the clock CK, the data signal DQ, and the data strobe signal DQS, which are transmitted and received between the processor 101 and the nonvolatile memory system 100, May follow a predefined convention by an interface between the processor 101 and the non-volatile memory system 100. Illustratively, the interface between the processor 101 and the non-volatile memory system 100 may be based on a Double Data Rate (DDR) interface. For example, the RAM command CMD_R, the RAM address ADDR_R, and the clock CK may be signals conforming to the protocol defined by the DDR interface.

The interface between the processor 101 and the nonvolatile memory system 100 may be a DDR, DDR2, DDR3, DDR4, LPDDR (Low Power DDR), USB (Universal Serial Bus) , MMC (multimedia card), embedded MMC, peripheral component interconnection (PCI), PCI-express (PCI-express), ATA (Advanced Technology Attachment), Serial- ATA, Parallel- an Enhanced Small Disk Interface (IDE), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Nonvolatile Memory Express (NVMe), and the like.

The non-volatile memory system 100 may include a device controller 110, a buffer memory 120, a plurality of non-volatile memory devices 131 to 13n, and an auxiliary power supply 140. Illustratively, the non-volatile memory system 100 is responsive to the storage command CMD_S and the storage address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS, The data DATA received from the processor 101 can be stored in at least one of the plurality of nonvolatile memory devices 131 to 13n through the signal DQ and the data strobe signal DQS. Alternatively, the non-volatile memory system 100 may include a plurality of nonvolatile (non-volatile) memory cells in response to the storage command CMD_S and the storage address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS. (DATA) stored in at least one of the memory devices 131 to 13n to the processor 101 via the data signal DQ and the data strobe signal DQS.

Illustratively, although not shown in the drawings, the non-volatile memory system 100 may have the form of a dual in-line memory module (DIMM) It can be mounted directly on a DIMM socket.

The device controller 110 may include a physical layer 111 (PHY) and a controller 112. The physical layer 111 may include a RAM controller 111a and a RAM 111b. The physical layer 111 may be electrically connected directly to the processor 101 and may provide an interface between the processor 101 and the controller 112. [

The RAM controller 111a receives information received via the data signal DQ and the data strobe signal DQS in response to the RAM command CMD_R, the RAM address ADDR_R, and the clock CK received from the processor 101 Or data may be stored in the RAM 111b or information or data stored in the RAM 111b may be provided to the processor 101 via the data signal DQ and the data strobe signal DQS. Illustratively, the ram 111b may include multiple port RAM, such as a dual port SRAM, a shared RAM, and the like. That is, the processor 101 or the controller 112 can access the RAM 111b through respective independent ports.

2, the RAM 111b includes a command area (CA), a write area (WA), a read area (RA), and a status area (STA; STATA) Area). Each of the command area CA, the write area WA, the read area RA and the state area STA includes a RAM command CMD_R, a RAM address ADDR_R, and a clock CK received from the processor 101, Respectively.

The command area CA of the RAM 111b can store the storage command CMD_S received from the processor 101 via the data signal DQ and the data strobe signal DQS under the control of the RAM controller 111a . The controller 112 can read the storage command CMD_S stored in the command area CA of the RAM 111b. Illustratively, the storage command CMD_S may include a storage address ADDR_S, and the storage command CMD_S and the storage address ADDR_S may be stored in the command area CA.

The write area WA of the ram 111b may store the write data DATA_W received via the data signal DQ and the data strobe signal DQS under the control of the RAM controller 111a. The controller 111b can read the write data (DATA_W) stored in the write area WA of the RAM 111b.

The read area RD of the RAM 111b may store the read data DATA_R under the control of the controller 112. [ The read area RD of the RAM 111b may be transferred to the processor 101 via the data signal DQ and the data strobe signal DQS.

The state area STA of the RAM 111b stores state information STI received from the processor 101 via the data signal DQ and the data strobe signal DQS or stores the stored state information STI into the processor 101 ). The state area STA of the RAM 111b may transmit the stored state information STI to the controller 112 or store the received state information STI from the controller 112 under the control of the controller 112 .

The controller 112 may communicate with the physical layer 111. The controller 112 can control the buffer memory 120 and the plurality of nonvolatile memory devices 131 to 13n, respectively. When the storage command CMD_S is written in the RAM 111b of the physical layer 111, the controller 112 can perform an operation corresponding to the storage command CMD_S written in the RAM 111b. For example, when the storage command CMD_S written in the RAM 111b is a write command, the controller 112 reads the write data (DATA_W) written in the write area WA of the RAM 111b, The data (DATA_W) can be programmed into at least one of the plurality of nonvolatile memory devices 131 to 13n. When the storage command CMD_S written in the RAM 111b is a read command, the controller 112 reads the data corresponding to the storage address ADDR_S from the plurality of nonvolatile memory devices 131 to 13n, (RA) read data (DATA_S) of the RAM 111b. Illustratively, after the write operation and the read operation are completed, the controller 112 may write state information (STI) indicating the completion of operation in the state area STA.

The controller 112 includes an Error Correction Code Engine (ECC engine) 112a. The ECC engine 112a can detect and correct errors of the storage command CMD_S or write data DATA read from the RAM 111b. For example, the storage command (CMD_S) or write data (DATA) provided from the processor 101 may include an error correction code generated by the processor 101. The ECC engine 112a can correct errors of the storage command CMD_S or write data (DATA) based on the error correction code. Or the ECC engine 112a may generate an error correction code for the read data (DATA) to be sent to the processor 101. [ The generated error correction code can be stored in the RAM 111b together with the read data (DATA).

Illustratively, the error detected by the ECC engine 112a is referred to as an ECC error. Illustratively, the ECC error will be different from a cyclic redundancy check (CRC) error. For example, an ECC error indicates an error detected in the ECC engine 112a based on an error correction code generated by the processor 101, and a CRC error indicates an error detected based on a CRC field.

Illustratively, if an ECC error is detected by the ECC engine 112a or if the detected ECC error is not corrected, the controller 112 may provide a notification signal (Alert_n) to the processor 101. The processor 101 may recognize that an ECC error of the storage command CMD_S or the write data DATA provided to the nonvolatile memory system 100 has occurred in response to the alert signal Alert_n. Thereafter, the processor 101 may perform a separate operation in response to the notification signal Alert_n. A separate operation includes retransmission of the storage command (CMD_S) or write data (DATA_W).

Although not shown in the figure, the alert signal Alert_n may be provided to the processor 101 via the RAM controller 111a. Or the alert signal Alert_n may be provided to the processor 101 through a separate driving device. Hereinafter, for ease of explanation and for simplicity of the drawing, it is assumed that the alert signal Alert_n is driven by the controller 112 and provided from the controller 112 to the processor 101. [ It is also assumed that the notification signal Alert_n is activated by the RAM controller 111a to logic low or logic high, but for convenience of explanation, the controller 112 provides or transmits it. That is, when the notification signal Alert_n is provided or transmitted, it means that the alert signal Alert_n is activated for a specific time or repeatedly activated for a specific period. However, the scope of the present invention is not limited thereto.

Although not shown in the figure, the controller 112 can access the RAM 111b through a specific system bus or an internal system bus. Although not shown in the figure, the controller 112 may further include hardware or software components such as a scrambler, a data buffer, a flash translation layer, and the like. The controller 112 can descramble the data read from the RAM 111b through the scrambler or scramble the data to be written into the RAM 111b. The controller 112 may temporarily store data read from the RAM 111b through the data buffer or temporarily store data read from the plurality of nonvolatile memory devices 131-131n.

The controller 112 may perform an address translation operation through the flash translation layer. For example, the storage address ADDR_S may be a logical address. The controller 112 may perform the operation of converting the storage address ADDR_S received from the processor 101 through the flash translation layer to the physical address of the plurality of non-volatile memory devices 131 to 13n. Illustratively, the physical location at which the write data (DATA_W) is written by the address translation operation or the physical location at which the read data (DATA_R) is stored can be determined. Illustratively, the physical location refers to the physical location of the plurality of non-volatile memory devices 131-13n.

The buffer memory 120 may be used as a buffer memory, an operation memory, or a cache memory of the device controller 110. The buffer memory 120 may include various information required for the nonvolatile memory system 100 to operate. Illustratively, the buffer memory 120 may include data for managing a plurality of non-volatile memory devices 131 to 13n. For example, the buffer memory 120 is connected to the non-volatile address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS and the plurality of nonvolatile memory devices 131 through 13n, And a mapping table between the physical addresses of the physical addresses. Illustratively, the buffer memory 120 may include random access memories such as SRAM, DRAM, SDRAM, MRAM, ReRAM, PRAM, FRAM, and the like.

The plurality of nonvolatile memory devices 131 to 13n are connected to the device controller 110 through a plurality of channels CH1 to CHn, respectively. The plurality of nonvolatile memory devices 131 to 131n may program the received data or output the stored data under the control of the device controller 110. [ For example, each of the plurality of nonvolatile memory devices 131 to 13n may include an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a ReRAM (Resistive RAM) (Ferroelectric RAM), STT-MRAM (Spin-Torque Magnetic RAM), and the like. For the sake of brevity, it is assumed that each of the plurality of nonvolatile memory devices 131 to 13n includes a NAND flash memory.

As described above, according to the present invention, when an ECC error is included in the storage command (CMD_S) or write data (DATA_W) received from the processor 101, the nonvolatile memory system 100 notifies the processor 101 Signal Alert_n. The processor 101 can retransmit the storage command CMD_S or the write data DATA_W in response to the alert signal Alert_n. Accordingly, the nonvolatile memory system 100 can operate normally. Thus, a non-volatile memory system with improved reliability is provided.

3 is a flow chart illustrating the operation of the nonvolatile memory system of FIG. FIGS. 4 and 5 are views for explaining the operation of FIG. 3 in detail. Hereinafter, for the sake of brevity, the operation of the non-volatile memory system will be described with reference to the ECC error correcting operation for the storage command CMD_S received from the processor 101. [ However, the scope of the present invention is not limited thereto, and a similar operation can be performed for the ECC error correcting operation on the write data received from the processor 101. [

Further, components unnecessary for explaining transmission / reception of the storage command CMD_S and ECC error detection of the storage command CMD_S are omitted. In addition, a detailed description of the components described above is omitted.

1 to 5, the non-volatile memory system 100 receives a storage command CMD_S from the processor 101. [ 4, in response to the RAM command CMD_R, the RAM address ADDR_R, and the clock CK from the processor 101, the nonvolatile memory system 100 outputs the data signal DQ And the storage command CMD_S received via the data strobe signal DQS to the command area CA of the RAM 111b. (1 in Fig. 4)

In step S120, the nonvolatile memory system 100 can detect an ECC error of the received storage command CMD_S. For example, as shown in FIG. 4, the ECC engine 112a included in the nonvolatile memory system 100 can detect an ECC error of the received storage command CMD_S. (2 in Fig. 4)

In step S130, the nonvolatile memory system 100 can determine whether an ECC error has been detected.

If no ECC error is detected, in step S140, the nonvolatile memory system 100 can perform an operation corresponding to the received storage command CMD_S. For example, the non-volatile memory system 100 may perform a read, write, or erase operation corresponding to the received storage command CMD_S.

If an ECC error is detected, the nonvolatile memory system 100 can transmit the notification signal Alert_n to the processor 101 in step S150. For example, as shown in FIG. 5, when an ECC error is included in the received storage command CMD_S, the nonvolatile memory system 100 can not confirm the operation corresponding to the received storage command CMD_S will be. That is, the non-volatile memory system 100 will not be able to perform the operation corresponding to the received storage command CMD_S. Accordingly, the nonvolatile memory system 100 transmits to the processor 101 a notification signal (Alert_n) indicating that an ECC error is included in the received storage command CMD_S. (3) in Fig. 5)

Illustratively, the processor 101 may recognize that an ECC error has been included in the storage command CMD_S sent to the non-volatile memory system 100 in response to the alert signal Alert_n. Illustratively, the processor 101 may resend the storage command CMD_S to the non-volatile memory system 100 in response to the alert signal Alert_n.

Figure 6 is a flow chart illustrating another operation of the nonvolatile memory system of Figure 1; Referring to FIGS. 1 and 6, the non-volatile memory system 100 may perform operations S210 to S240. The operations of steps S210 to S240 are similar to the operations of steps S110 to S140 of FIG. 3, so that a detailed description thereof will be omitted.

If an error is detected in step S230, the nonvolatile memory system 100 corrects the detected error in step S250. For example, the ECC engine 112a can correct the error of the storage command CMD_S based on the error correction code included in the storage command CMD_S or received together with the storage command CMD_S.

If the ECC error is corrected by the operation of step S250, the nonvolatile memory system 100 performs the operation of step S240.

If the error is not corrected by the operation of step S250, the nonvolatile memory system 100 performs the operation of step S270. Since the operation of step S270 is similar to that of step S150 of FIG. 3, a detailed description thereof will be omitted.

When an error is detected in the storage command CMD_S received from the processor 101 as described above or the error detected is not corrected, the nonvolatile memory system 100 transmits the notification signal Alert_n to the processor 101 . The processor 101 may recognize that the error is included in the storage command CMD_S transmitted to the nonvolatile memory system 100 in response to the received alert signal Alert_n or that the error contained therein is not corrected. Illustratively, the processor 101 may resend the storage command CMD_S to the non-volatile memory device 100 in response to the alert signal Alert_n.

7 is a block diagram illustrating a user system according to another embodiment of the present invention. Referring to FIG. 7, the user system 20 includes a processor 201 and a non-volatile memory system 200. The non-volatile memory system 200 includes a device controller 210, a buffer memory 220, and a plurality of non-volatile memory devices 231 to 23n. The device controller 210 includes a physical layer 211 and a controller 212. The physical layer 211 includes a RAM controller 211a, a RAM 211b, and a multipurpose register (MPR).

A processor 201, a non-volatile memory system 200, a device controller 210, a buffer memory 220, a plurality of non-volatile memory devices 231 to 23n, a physical layer 211, a controller 212, The controller 211a, and the RAM 211b have been described with reference to FIG. 1, so a detailed description thereof will be omitted.

Unlike the nonvolatile memory system 100 of FIG. 1, the nonvolatile memory system 200 of FIG. 7 further includes a multipurpose register (MPR). The multipurpose register (MPR) may include a plurality of registers. A multipurpose register (MPR) can store data patterns, error logs, information about mode registers, or information about the update of state information (STI), etc. For example, a multipurpose register (MPR) (MPR) may include a log record for cyclic redundancy check (CRC) of write data, storage commands, etc. received from the processor 101. The multipurpose register (MPR) May include information on a mode register MRS indicating an operation mode of the physical layer 211. The multipurpose register MPR may include ECC information. The ECC engine 212a detects an error in the storage command CMD_S or write data DATA_W received from the processor 201 or corrects the detected error You can point to information about what you can not do.

Illustratively, the processor 101 may access the multipurpose register (MPR) by changing the operating mode (or mode register) of the physical layer 211 to a multipurpose register (MPR) access mode. Illustratively, the processor 101 may change the operation mode (or mode register) of the physical layer 211 using the RAM command CMD_R and the RAM address ADDR_R.

The nonvolatile memory system 200 according to still another embodiment of the present invention is configured such that when an ECC error is included in the storage command CMD_S or write data DATA_W received from the processor 201, And then transmits the notification signal Alert_n to the processor 201. [ The processor 201 may read the ECC information from the multipurpose register (MPR) in response to the alert signal Alert_n. The processor 201 may recognize that an error (particularly, an ECC error) has been detected in the information transmitted to the nonvolatile memory system 100 based on the read ECC information.

Hereinafter, for the sake of simplicity and ease of explanation, after the ECC error is detected by the ECC engine 212a of the controller 212, the controller 212 writes the ECC information to the multipurpose register (MPR) . However, the scope of the present invention is not limited to this, and the ECC information may be stored in a multipurpose register (MPR) by a RAM controller 211a included in the physical layer 211 or a separate logic circuit or a separate control circuit located outside the physical layer. ). ≪ / RTI >

8 is a flowchart showing the operation of the nonvolatile memory system of FIG. Referring to FIGS. 7 and 8, the non-volatile memory system 100 may perform steps S310 to S340. Operations in steps S310 to S340 are similar to operations in steps S110 to S140 in FIG. 3, so a detailed description thereof will be omitted.

If an error is detected by the operation in step S330, the nonvolatile memory system 100 writes the ECC information (ECC log) in the multipurpose register (MPR) in step S350. For example, the nonvolatile memory system 100 can write ECC information indicating that an ECC error is included in the storage command CMD_S received in a partial area of the multipurpose register (MPR).

In step S360, the nonvolatile memory system 100 transmits the notification signal Alert_n to the processor 201. [

Illustratively, as described above, the processor 201 may read the ECC information from the multipurpose register (MPR) in response to the alert signal Alert_n. This number, the processor 201, can retransmit the storage command CMD_S in accordance with the ECC information.

According to the above-described embodiments, the non-volatile memory system can perform error detection and correction operations on the storage command (CMD_S) or write data (DATA_W) received from the processor. At this time, if an error is detected in the storage command CMD_S or the write data DATA_W, or if the detected error is not corrected, the nonvolatile memory system transmits the notification signal Alert_n to the processor. The processor can recognize that the ECC error is included in the storage command (CMD_S) or the write data (DATA_W) in response to the notification signal. Alternatively, the processor can read ECC information from the multipurpose register (MPR) of the nonvolatile memory system in response to the notification signal and recognize that the ECC error is included in the storage command (CMD_S) or write data (DATA_W) according to the ECC information read . Accordingly, the processor can retransmit the storage command (CMD_S) or write data (DATA_W) to the nonvolatile memory system.

Illustratively, although not shown in the drawings, the processor and non-volatile memory system may communicate with each other via a serial bus such as I2C. The processor may receive ECC information from the non-volatile memory system via the serial bus in response to the alert signal (Alert_n).

9 is a block diagram illustrating an exemplary first non-volatile memory device of the plurality of non-volatile memory devices of FIG. 9, the nonvolatile memory device 131 includes a memory cell array 131a, an address decoder 131b, a control logic and voltage generating circuit 131c, a page buffer 131d, and an input / output circuit 131e .

The memory cell array 131a may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) storing one bit or a multi level cell (MLC) storing at least two bits.

The address decoder 131b is connected to the memory cell array 131a through a plurality of word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 131b receives the physical address ADDR_P from the external device (for example, the device controller 110) and decodes the received physical address ADDR to drive the plurality of word lines WL can do. For example, the address decoder 131b decodes the physical address ADDR_P received from the external device and generates at least one word line of the plurality of word lines WL based on the decoded physical address ADDR_P And may drive at least one selected word line. Illustratively, the physical address ADDR_P indicates the physical address of the first nonvolatile memory 131 to which the storage address ADDR_S (see FIGS. 1 and 2) has been converted. The address translation operation described above may be performed by a flash translation layer (FTL) driven by the device controller 110 or the device controller 110. [

The control logic and voltage generating circuit 131c receives the storage command CMD_S and the control signal CTRL from the external device and supplies the address decoder 131b, the page buffer 131d, and the input / (131e). For example, the control logic and voltage generation circuit 131c may control other components so that the data (DATA) is stored in the memory cell array 131a in response to the signals CMD_S and CTRL. Or the control logic and voltage generation circuit 131c may control other components so that the data (DATA) stored in the memory cell array 131a is transferred to the external device in response to the signals CMD_S and CTRL. Illustratively, the storage command CMD_S received from the external device may be a modified command of the storage command CMD_S of FIG. The control signal CTRL may be a signal that the device controller 110 provides to control the nonvolatile memory 131. [

The control logic and voltage generation circuit 131c may generate various voltages required for the non-volatile memory 131 to operate. For example, the control logic and voltage generation circuit 131c may include a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of unselected read voltages, a plurality of erase voltages, Can generate various voltages such as voltages. The control logic and voltage generation circuit 131c may provide the generated various voltages to the address decoder 131b or to the substrate of the memory cell array 131a.

The page buffer 131d is connected to the memory cell array 131a through a plurality of bit lines BL. The page buffer 131d controls the bit lines BL so that data (DATA) received from the input / output circuit 131e is stored in the memory cell array 131a under the control of the control logic and voltage generation circuit 131c . The page buffer 131d may read the data stored in the memory cell array 110 and transmit the read data to the input / output circuit 131e under the control of the control logic and the voltage generation circuit 131c. Illustratively, the page buffer 131d may receive data on a page-by-page basis from the input / output circuit 131e or may read data on a page-by-page basis from the memory cell array 131a.

The input / output circuit 131a receives the data (DATA) from the external device and can transfer the received data (DATA) to the page buffer 131d. Or the input / output circuit 131e may receive the data (DATA) from the page buffer 131d and transfer the received data (DATA) to an external device (for example, the device controller 110). Illustratively, the input / output circuit 160 can transmit and receive data (DATA) with an external device in synchronization with the control signal CTRL.

Illustratively, as an exemplary embodiment according to the technical concept of the present invention, each of the plurality of non-volatile memory devices 131 to 13n may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithical means that layers of each level in a three-dimensional array are deposited directly on the lower-level layers of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between the levels, a configuration suitable for a three-dimensional memory array is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466 U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, which are incorporated herein by reference.

FIG. 10 is a block diagram illustrating a computing system to which a non-volatile memory system according to the present invention is applied. 10, a computing system 1000 includes a processor 1100, non-volatile memory modules 1200 and 1201, RAM modules 1300 and 1301, a chipset 1400, a GPU 1500, an input / 1600, and a storage device 1700.

The processor 1100 may control all operations of the computing system 1000. The processor 1100 may perform various operations performed in the computing system 1000.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may be directly connected to the processor 1100. For example, each of the non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may have the form of a dual in-line memory module (DIMM) Each of the modules 1200 and 1201 and the RAM modules 1300 and 1301 may be mounted in a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100. Illustratively, the non-volatile memory modules 1200, 1201 may be the non-volatile memory systems 100, 200 described with reference to FIGS. 1-9.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate with the processor 1100 through the same interface 1001. For example, the nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 can communicate through a double data rate (DDR) interface 1001. Illustratively, processor 1100 may use RAM modules 1300 and 1301 as operational memory, buffer memory, or cache memory of computing system 1000.

The chipset 1400 is electrically connected to the processor 1100 and can control the hardware of the computing system 1000 under the control of the processor 1100. [ For example, the chipset 1400 may be connected to the GPU 1500, the input / output device 1600, and the storage device 1700 via the main buses, respectively, and may serve as a bridge to the main buses.

The GPU 1500 may perform a series of arithmetic operations to output image data of the computing system 1000. Illustratively, GPU 1500 may be implemented within processor 1100 in a system-on-chip form.

The input / output device 1600 includes various devices that input data or instructions to the computing system 1000 or output data to the outside. For example, the input / output device 1600 A user input device such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, Display devices, AMOLED (Active Matrix OLED) displays, LEDs, speakers, motors, and the like.

The storage device 1700 may be used as a storage medium of the computing system 1000. Storage device 1600 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.

Illustratively, non-volatile memory modules 1200 and 1201 may be used by the processor 1100 as a mass storage medium of the computing system 1000. The interface 1001 between the non-volatile memory modules 1200 and 1201 and the processor 1100 may be a higher speed interface than the interface between the storage device 1700 and the processor 1100. [ That is, the performance of the computing system is improved by the processor 1100 using the nonvolatile memory modules 1200 and 1201 as a storage medium.

FIG. 11 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 10 by way of example. Illustratively, FIG. 11 is a block diagram of a non-volatile memory module 1200 having the form of a Load Reduced DIMM (LRDIMM). Illustratively, the non-volatile memory module 1200 shown in FIG. 11 is in the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 1100 .

11, a non-volatile memory module 1200 includes a device controller 1210, a buffer memory 1220, a non-volatile memory device 1230, and a serial presence detect chip 1240 (SPD) . The device controller 1210 may include a RAM 1211. Illustratively, non-volatile memory device 1230 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1230 may be implemented as a separate chip, a separate package, a separate device, or a separate module, respectively. Or non-volatile memory device 1230 may be implemented in one chip or in one package.

By way of example, device controller 1210, RAM 1211, buffer memory 1220, and non-volatile memory device 1230 may include a device controller, a RAM, a buffer memory, and a plurality Lt; RTI ID = 0.0 > and / or < / RTI > non-volatile memory devices. That is, the non-volatile memory module 1200 may be any one of the non-volatile memory systems 100 and 200 of FIGS.

Illustratively, the device controller 1210 can send and receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100, and receives a RAM command CMD_R via separate signal lines, The RAM address ADDR_R, and the clock CK. Illustratively, the device controller 1210 may send a notification signal Alert_n to the processor 1100 in accordance with the operating method described with reference to Figs. 1-8.

SPD 1240 may be a programmable read-only memory (EEPROM). SPD 1240 may include initial information or device information of non-volatile memory module 1200. Illustratively, SPD 1240 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 1200. When the computing system including the non-volatile memory module 1200 is booted, the processor 1100 of the computing system can read the SPD 1240 and recognize the non-volatile memory module 1200 based on the SPD 1240. The processor 1100 may use the nonvolatile memory module 1200 as a storage medium based on the SPD 1240.

Illustratively, the SPD 1240 may communicate with the processor 1100 via a serial bus SB. The processor 1100 can exchange the signal SBS with the SPD 1240 via the serial bus SB. Illustratively, the SPD 1240 may communicate with the device controller 1210 via the serial bus SB. Illustratively, the serial bus SB may include at least one of two-line serial buses such as I2C, SMBus, PMBus, IPMI, MCTP, and the like.

FIG. 12 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 10 by way of example. Illustratively, FIG. 12 is a block diagram of a non-volatile memory module 2200 in the form of a Registered DIMM (RDIMM). 12 is in the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 1100 .

12, the non-volatile memory module 2200 includes a device controller 2210, a buffer memory 2220, a non-volatile memory device 2230, a serial presence detect chip (SPD) 2240, And a data buffer circuit 2250. The device controller 2210 includes a RAM 2211. Since the device controller 2210, the RAM 2211, the nonvolatile memory device 2230, and the SPD 2240 have been described with reference to FIGS. 1 and 15, a detailed description thereof will be omitted.

The data buffer circuit 2250 receives information or data from the processor 1100 (see FIG. 10) via the data signal DQ and the data strobe signal DQS and forwards the received information or data to the device controller 2250 . Or the data buffer circuit 2250 may receive information or data from the device controller 2210 and communicate the received information or data to the processor 1100 via the data signal DQ and the data strobe signal DQS.

Illustratively, data buffer circuit 2250 may include a plurality of data buffers. Each of the plurality of data buffers can exchange data signals DQ and data strobe signals DQS with the processor 1100. Or each of the plurality of data buffers can exchange signals with the device controller 2210. Illustratively, each of the plurality of data buffers may operate under the control of a device controller 2210.

Illustratively, the device controller 2210 may send a notification signal Alert_n to the processor 1100 in accordance with the operating method described with reference to Figs. 1-8.

13 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied. For the sake of brevity, a detailed description of the components described above is omitted. 13, a computing system 3000 includes a processor 3100, a non-volatile memory module 3200, a chipset 3400, a GPU 3500, an input / output device 3600, and a storage device 3700 . The processor 3100, the chipset 3400, the GPU 3500, the input / output device 3600, and the storage device 3700 have been described with reference to FIG. 10, and a detailed description thereof will be omitted.

The non-volatile memory module 3200 may be directly coupled to the processor 3100. For example, the non-volatile memory module 3200 may take the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

The non-volatile memory module 3200 may include a control circuit 3210, a non-volatile memory device 3220, and a ram device 3230. Unlike the non-volatile memory modules 1200 and 2200 described with reference to FIGS. 10-12, the processor 3100 includes a non-volatile memory device 3220 and a non-volatile memory device 3220, Respectively. As a more detailed example, the control circuit 3210 may store the received data in the non-volatile memory device 3210 or in the RAM device 3220 under the control of the processor 3100. [ Or control circuitry 3210 may send data stored in non-volatile memory device 3210 to processor 3100 or may transfer data stored in ram device 3220 to processor 3100 under the control of processor 3100 have. That is, the processor 3100 can recognize the nonvolatile memory device 3210 and the RAM device 3220 included in the nonvolatile memory module 3200, respectively. The processor 3100 may store data in the non-volatile memory device 3220 of the non-volatile memory module 3200 or may read the stored data. Or processor 3100 may store data to or read data from RAM device 3230. [

The processor 3100 may use the non-volatile memory module 3200 of the non-volatile memory module 3200 as a storage medium of the computing system 3000, The RAM device 3220 of the computing system 3000 can be used as the main memory of the computing system 3000. That is, the processor 3100 can selectively access the nonvolatile memory device or the RAM device included in one memory module mounted on one DIMM socket, respectively.

Illustratively, the processor 3100 may communicate with the non-volatile memory module 3200 via a double data rate (DDR) interface 3001.

14 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 13 and 14, the non-volatile memory module 3200 includes a control circuit 3210, a non-volatile memory device 3220, and a ram device 3220. [ By way of example, non-volatile memory device 3220 may comprise a plurality of non-volatile memories, and RAM device 3230 may comprise a plurality of DRAMs. Illustratively, the plurality of non-volatile memories may be used by the processor 3100 as storage in the computing system 3000. Illustratively, each of the plurality of nonvolatile memories may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a Resistive RAM (FRAM) Non-volatile memory devices such as spin-torque magnetic RAM (MRAM) and the like.

The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000. By way of example, RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, MRAM, and the like.

The control circuit 3210 includes a device controller 3211 and an SPD 3212. The device controller 3211 can receive the command CMD, the address ADDR, and the clock CK from the processor 3100. [ The device controller 3211 responds to signals received from the processor 3100 to transfer data received via the data signal DQ and the data strobe signal DQS to the non-volatile memory device 3220 or to the ram device 3230. [ As shown in FIG. Or device controller 3211 responds to signals received from processor 3100 to transfer data stored in non-volatile memory device 3220 or RAM device 3230 to data signal DQ and data strobe signal DQS Lt; RTI ID = 0.0 > 3100 < / RTI >

Illustratively, the processor 3100 may optionally access the non-volatile memory device 3220 or the RAM device 3230 via a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 can selectively access the non-volatile memory device 3220 or the RAM device 3230 included in the non-volatile memory module 3200. [ Illustratively, the device controller 3211 may send a notification signal Alert_n to the processor 3100 in accordance with the operating method described with reference to Figs. 1-8.

15 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. By way of example, the nonvolatile memory module 4200 of FIG. 15 has the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

Referring to Figures 13 and 15, the non-volatile memory module 4200 includes a control circuit 4100, a non-volatile memory device 4220, and a ram device 4230. The control circuit 4210 includes a device controller 4211, an SPD 4212, and a data buffer circuit 4213.

The device controller 4211 receives the command CMD, the address ADDR, and the clock CK from the processor 3100. The device controller 4211 may control the non-volatile memory device 4220 or the RAM device 4230 in response to the received signals. For example, as described with reference to FIG. 28, the processor 3100 may selectively access each of the non-volatile memory device 4220 or the RAM device 4230. The device controller 4231 can control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100. [

The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 and provide the received signals to the device controller 4211 and the RAM device 4230. Or the data buffer circuit 4213 may provide the data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.

Illustratively, when the processor 3100 stores data in the nonvolatile memory device 4220, the data received via the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 can process the received data and provide it to the nonvolatile memory device 4220. [ Or the processor 3100 reads data stored in the nonvolatile memory device 4220, the data buffer circuit 4213 supplies the data provided from the device controller 4211 to the data signal DQ and the data strobe signal DQS, Lt; / RTI > to the processor 3100 via the network interface. Or the processor 3100 stores data in the RAM device 4230 the data received by the data buffer circuit 4213 is provided to the RAM device 4230 and the device controller 4231 receives the received command CMD, The address ADDR, and the clock CK to the RAM device 4230. Or when the processor 3100 reads data stored in the RAM device 4230, the device controller 4231 transfers the received command CMD, the address ADDR and the clock CK to the RAM device 4230 , The RAM device 4230 provides the data to the data buffer circuit 4213 in response to the transmitted signals and the data buffer circuit 4213 supplies the data signal DQ and the data strobe signal DQS, And may provide data to the processor 3100.

Illustratively, the device controller 4211 may send a notification signal Alert_n to the processor 3100 in accordance with the operating method described with reference to Figs. 1-8.

16 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 13 and 16, the non-volatile memory module 5200 includes a control circuit 5210, a non-volatile memory device 5220, and a RAM device 5230. The control circuit 5210 includes a device controller 5211 and an SPD 5212.

The non-volatile memory module 5200 of FIG. 16 may operate similarly to the non-volatile memory module 4200 of FIG. The nonvolatile memory module 5200 of FIG. 16 does not include the data buffer circuit 4213 unlike the nonvolatile memory module 4200 of FIG. That is, the nonvolatile memory module 5200 of FIG. 16 directly supplies the data received from the processor 3100 via the data signal DQ and the data strobe signal DQS to the device controller 5211 or the RAM device 5230 can do. The data from the device controller 5211 of the nonvolatile memory module 5200 of Figure 20 or the data from the RAM device 5230 is supplied to the processor 3100 through the data signal DQ and the data strobe signal DQS. Can be provided directly.

For example, the non-volatile memory module 4200 in FIG. 15 is a memory module in the form of an LRDIMM (Load Reduced DIMM), and the non-volatile memory module 5200 in FIG. 16 may be a memory module in the form of an RDIMM .

Illustratively, the device controller 5211 may send a notification signal Alert_n to the processor 3100 in accordance with the operating method described with reference to Figs. 1-8.

17 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 17, the server system 6000 may include a plurality of server racks 6110 to 61n0. Each of the plurality of server racks 6110 to 61n0 may include a plurality of nonvolatile memory modules 6200. [ The plurality of nonvolatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6110 to 61n0. For example, a plurality of non-volatile memory modules 6200 may take the form of dual in-line memory modules and may be mounted in a DIMM socket electrically connected to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 6200 may be used as storage for the server system 6000. Illustratively, the plurality of non-volatile memory modules 6200 may operate in accordance with the method described with reference to Figures 1-23.

According to embodiments of the invention described above, the non-volatile memory system performs error detection and correction operations on the storage command or write data received from the processor. At this time, if an error is detected or if the detected error is not corrected, the non-volatile memory system sends a notification signal (Alert_n) to the processor. The processor may resend the storage command or write data to the non-volatile memory system in response to the alert signal (Alert_n). Therefore, the nonvolatile memory system can be normally operated even if an error is included in the storage command, so that a nonvolatile memory system having improved reliability is provided.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

100: non-volatile memory system 110: device controller
111: physical layer 111a: RAM controller
111b: RAM 111c: storage signal driver
112: controller 112a: ECC engine
120: buffer memories 131 to 13n: a plurality of nonvolatile memory devices
CMD_R: RAM command ADDR_R: RAM address
CK: clock DQ: data signal
DQS: Data strobe signal CMD_S: Storage command
ADDR_S: Storage address DATA: Data
STI: Status information Alert_n: Notification signal

Claims (10)

A plurality of non-volatile memory devices; And
A storage controller that receives a storage command from an external device and controls the plurality of non-volatile memory devices in response to the received storage command,
Wherein the storage controller includes an error correction code (ECC) engine for detecting and correcting an error of the received storage command, and when an error of the storage command is detected by the ECC engine, A nonvolatile memory module that transmits signals. The method according to claim 1,
Wherein the storage controller performs an operation corresponding to the storage command if the error is not detected or the error is corrected. The method according to claim 1,
Wherein the storage command is configured to receive a RAM command, a RAM address, and a clock from the external device, and to store the received RAM command, the received RAM address, and a nonvolatile Memory modules. The method of claim 3,
Wherein the storage controller further comprises a RAM,
Wherein the storage controller stores the received command in the RAM according to the received RAM command, the received RAM address, and the received clock. 5. The method of claim 4,
And the ECC engine detects and corrects an error of the storage command stored in the RAM. The method according to claim 1,
Wherein the ECC engine detects and corrects an error of the storage command based on an error correction code corresponding to the storage command provided from the external device. The method according to claim 1,
Wherein the storage command further comprises a multipurpose register,
And writes ECC information on the error to the multipurpose register when the error is detected or the error is not corrected. 8. The method of claim 7,
Wherein the storage controller transmits the notification signal to the external device, and then transmits the ECC information written in the multi-purpose register to the external device under the control of the external device. The method according to claim 1,
Wherein the storage controller transmits the notification signal to the external device and then transmits ECC information on the error to the external device via the serial bus under the control of the external device. The method according to claim 1,
Wherein the storage controller and the external device communicate based on a double data rate (DDR) interface.

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