KR20230068240A - Storage device including the same and method of operating the same - Google Patents

Abstract

A storage device and a method of operating the same are disclosed. The storage device includes a storage controller including a non-volatile memory including a plurality of memory areas, a performance path, and a buffer memory that controls the non-volatile memory and stores recovery data through a performance path and at least one direct path. , When power is cut off and a failure is detected in the performance path, recovery data is written to a non-volatile memory through at least one direct path, and the performance path is a path for performing a write operation, a read operation, and an erase operation for data, At least one direct path may be a path that performs only a write operation on data.

Description

Storage device and its operating method {STORAGE DEVICE INCLUDING THE SAME AND METHOD OF OPERATING THE SAME}

The technical idea of the present disclosure relates to a storage device and an operating method thereof, and more particularly, to a storage device performing a power off recovery operation and an operating method thereof.

As a non-volatile memory, flash memory can retain stored data even when power is cut off. Recently, storage devices including flash memories such as embedded multi-media cards (eMMC), universal flash storage (UFS), solid state drives (SSDs), and memory cards have been widely used, and storage devices store large amounts of data. It is useful for moving or moving. Demands for methods and devices capable of improving the reliability of storage devices are continuously raised.

When power is suddenly turned off by an external factor, for example, a power failure occurs, data existing in a buffer memory inside the storage device may be lost. To prevent this, power loss protection (PLP) may be applied. When the PLP is applied, in case of power loss, data existing in the buffer memory may be moved to the non-volatile memory by supplying reserve power.

An object to be solved by the technical idea of the present disclosure is to provide a storage device and an operating method thereof capable of preventing an error state even when an error occurs during power fail processing.

A storage device according to the technical idea of the present disclosure for achieving the above technical problem is to control the nonvolatile memory and store recovery data through a nonvolatile memory including a plurality of memory areas, a performance path, and at least one direct path. A storage controller including a buffer memory, wherein the storage controller writes recovery data to a non-volatile memory through at least one direct path when power is cut off and a failure is detected in the performance path, and the performance path is A path for performing a write operation, a read operation, and an erase operation, and at least one direct path may be a path for performing only a write operation on data.

In an operating method of a storage device including a storage controller and a non-volatile memory according to the technical idea of the present disclosure for achieving the above technical problem, when power is cut off and a failure in a performance path is detected, a core is selected and written to a buffer memory. Collecting recovery data, and writing the recovery data to a non-volatile memory through a direct path corresponding to the selected core, and the performance path is a path for performing a write operation, a read operation, and an erase operation for data. , the direct path may be a path that performs only a write operation on data.

A method of operating a storage device including a storage controller and a non-volatile memory according to the technical idea of the present disclosure for achieving the above technical problem includes setting write information for writing recovery data written in a buffer memory to a non-volatile memory. Step, when power is cut off and a failure is detected in the performance path, selecting a core and collecting recovery data, and writing recovery data to a non-volatile memory through a direct path corresponding to the selected core, A path may include a plurality of cores, and a direct path may include a corresponding one core.

In the storage device according to the technical idea of the present disclosure, when a fault is detected in the performance path, recovery data stored in the buffer memory may be stored in the non-volatile memory through a direct path through which the core directly accesses the non-volatile memory. . Accordingly, even if an error occurs after a sudden power failure, ie, an error occurs during power failure processing, the storage device is prevented from entering an error state, and the storage device can be continuously used.

Effects that can be obtained in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned above can be obtained from the description of the exemplary embodiments of the present disclosure below. It can be clearly derived and understood by those skilled in the art to which they belong. That is, unintended effects according to the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a storage system according to an exemplary embodiment of the present disclosure.
2 is a block diagram illustrating a storage controller of a storage device according to an exemplary embodiment of the present disclosure.
3 to 5 are diagrams for describing an operation of writing data to a nonvolatile memory when power is cut off to a storage device according to an exemplary embodiment of the present disclosure.
FIG. 6 is a block diagram illustrating one memory device among a plurality of memory devices included in the nonvolatile memory of FIG. 1 .
FIG. 7 is a diagram for explaining recovery data stored in the buffer memory of FIG. 2 .
8 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
9 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
10 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
11 is a diagram illustrating a system to which a storage device according to an exemplary embodiment of the present disclosure is applied.
12 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a storage system 10 according to an exemplary embodiment of the present disclosure.

The storage system 10 may be implemented as, for example, a personal computer (PC), a data server, a network-attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, portable multimedia players (PMPs), and PNDs. (personal navigation device), MP3 player, handheld game console, e-book, wearable device, and the like.

The storage system 10 may include a storage device 100 and a host 200 . The host 200 may control the operation of the storage device 100 . In an example embodiment, the storage device 100 may include one or more solid state drives (SSDs). When the storage device 100 includes a solid state drive, the storage device 100 may include a plurality of flash memory devices (eg, NAND memory devices) that store data.

The storage device 100 may correspond to a flash memory device including one or more flash memory devices. In an exemplary embodiment, the storage device 100 may be an embedded memory built into the storage system 10 . For example, the storage device 100 may be an embedded multi-media card (eMMC) or an embedded universal flash storage (UFS) memory device. In an exemplary embodiment, the storage device 100 may be an external memory removable from the storage system 10 . For example, the storage device 100 may include a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), extreme Digital (xD), or It may be a memory stick.

Referring to FIG. 1 , a storage system 10 may include a storage device 100 and a host 200 . The host 200 and the storage device 100 may communicate with each other through various interfaces. The storage device 100 may exchange signals with the host 200 through a signal connector 140 and receive power through a power connector 150 .

The host 200 may transmit a request (REQ) such as a read request and a program request to the storage device 100 . In an exemplary embodiment, the host 200 may be implemented as an Application Processor (AP) or System-On-a-Chip (SoC).

The storage device 100 may include a storage controller 110 , a non-volatile memory 120 and an auxiliary power supply 130 .

The storage controller 110 may exchange signals with the host 200 through the signal connector 140 . Here, the signals may include a request (REQ), data (DATA), and an error signal (ES).

The storage controller 110 may control the operation of the nonvolatile memory 120 through a channel CH. The storage controller 110 reads data DATA stored in the nonvolatile memory 120 in response to a read request from the host 200, or reads data DATA stored in the nonvolatile memory 120 in response to a write request from the host 200. The non-volatile memory 120 may be controlled to write data DATA to .

In an exemplary embodiment, the non-volatile memory 120 may include a plurality of memory devices 121 that store data. Each of the plurality of memory devices may be a semiconductor chip or a semiconductor die. Each of the plurality of memory devices may be connected to a corresponding channel. For example, the plurality of memory devices 121 include first memory devices connected to the storage controller 110 through a first channel, second memory devices connected to the storage controller 110 through a second channel, and m th memory devices connected to the storage controller 110 through an m th channel. In this case, m may be a natural number of 2 or more. A plurality of memory devices connected to the same channel among the plurality of memory devices 121 may perform a write operation, a read operation, and an erase operation in an interleaved manner.

Each of the plurality of memory devices 121 may include a memory cell array, and in an exemplary embodiment, the memory cell array may include flash memory cells, for example, the flash memory cells may include NAND may be flash memory cells. However, the present disclosure is not limited thereto, and the memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), and magnetic RAM (MRAM).

The auxiliary power supply 130 may be connected to the host 200 through the power connector 150 . The auxiliary power supply 130 may receive power (PWR) from the host 200 and may be charged. However, the auxiliary power supply 130 may be located within the storage device 100 or outside the storage device 100 . The auxiliary power supply 130 may generate an internal power voltage based on the power supply PWR and provide the internal power voltage to the storage controller 110 and the nonvolatile memory 120 .

In an exemplary embodiment, the auxiliary power supply 130 may include a Power-Loss Protection Integrated Circuit (PLP IC). When the power of the storage device 100 is suddenly cut off (off) (ie, sudden power off or power fail), the power loss protection integrated circuit generates an auxiliary power supply voltage for a predetermined time, and the storage controller 110 And it can be provided to the non-volatile memory 120.

The storage controller 110 may write data into the nonvolatile memory 120 through a performance path (PP) during normal operation, that is, while power is supplied. On the other hand, when power is suddenly cut off and a fault is detected in the performance path (PP), data may be written into the nonvolatile memory 120 through a direct path (DP). At this time, in the performance path (PP), the core included in the storage controller 110 passes through several modules to perform operations on the non-volatile memory 120, such as a program operation, a read operation, and an erase operation. may be a path that performs On the other hand, the direct path DP may be a path through which a core included in the storage controller 110 directly writes data into the nonvolatile memory 120 without going through another module. That is, the direct path DP may be a separate path defined to perform an operation of moving data written in the buffer memory of the storage controller 110 to the non-volatile memory 120 when power is cut off.

In an exemplary embodiment, the storage controller 110 may determine whether a failure of the performance path (PP) has occurred from an assert or a core hang. Alternatively, in an exemplary embodiment, the storage controller 110 determines that a failure has occurred in the performance path (PP) when it is determined that each step of the power-off processing operation through the performance path (PP) is not processed within a specified time. can do.

In the storage device 100 according to the present disclosure, when a failure is detected in the performance path (PP), recovery data stored in the buffer memory is retrieved through a direct path (DP) through which a specific core directly accesses the nonvolatile memory 120. It can be stored in non-volatile memory. Accordingly, even if an error occurs during power fail processing, the storage device is prevented from falling into an error state, and the storage device can be continuously used. The configuration of recovery data will be described later in detail with reference to FIG. 7 .

The storage device 100 may transmit an error signal ES to the host 200 when user data cannot be written to the nonvolatile memory 120 due to sudden power cutoff. For example, the error signal ES may be transmitted to the host 200 as a rebuild assist.

2 is a block diagram illustrating the storage controller 110 of the storage device 100 according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 2 , the storage controller 110 may include a processor 111 , a host interface 114 and a memory interface 115 . In addition, the storage controller 110 may include a flash translation layer (FTL) 112 and a buffer memory 113 . The storage controller 110 may further include a working memory into which the flash conversion layer 112 is loaded, and the processor 111 executes the flash conversion layer 112 to write data into the non-volatile memory 120. and a read operation may be controlled. Components of the storage controller 110 may communicate with each other through the bus 116 .

The processor 111 may include a central processing unit or a microprocessor, and may control overall operations of the storage controller 110 . The processor 111 may include one or more cores capable of executing an instruction set of program code configured to perform a specific operation. For example, the processor 111 may execute command codes of firmware stored in the working memory.

The processor 111 writes data to the non-volatile memory 120, reads data from the non-volatile memory 120, or erases data from each component of the storage controller 110 included in the performance path PP. can control. When a power cut is detected, the processor 111 first controls each component of the storage controller 110 included in the performance path (PP) to transfer data written in the buffer memory 113 to the non-volatile memory 120 with power. A block processing operation can be performed.

In an exemplary embodiment, the processor 111 may include one core. When power is cut off and a failure is detected in the performance path (PP), the core of the processor 111 executes a dedicated context to store the recovery data stored in the buffer memory 113 in the non-volatile memory 120. can be done For example, the core of the processor 111 may perform the operation by executing an interrupt context or processing a real time operating system (RTOS) task, and the core of the processor 111 may perform the operation. A path may be defined as a direct path (DP). Alternatively, in an exemplary embodiment, the processor 111 may include a plurality of cores, and operations of the processor 111 including the plurality of cores will be described later in detail with reference to FIGS. 3, 4, and 5.

The host interface 114 may transmit and receive packets with the host 100 . A packet transmitted from the host 100 to the host interface 114 may include a request (REQ in FIG. 1) or data to be written to the non-volatile memory 220 (DATA in FIG. 1), etc. ) to the host 100 may include a response to the request REQ or data DATA read from the nonvolatile memory 220 . For example, the host interface 114 may be Universal Serial Bus (USB), MMC, PCI Express (PCI-E), AT Attachment (ATA), Serial AT Attachment (SATA), Parallel AT Attachment (PATA), Small Computer (SCSI) System Interface), SAS (Serial Attached SCSI), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), etc.

The memory interface 115 may transmit data to be written in the nonvolatile memory 220 to the nonvolatile memory 220 or may receive data read from the nonvolatile memory 220 . This memory interface 115 may be implemented to comply with standard protocols such as Toggle or ONFI.

The flash translation layer 112 may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the host into a physical address used to actually store data in the nonvolatile memory 220 . Wear-leveling is a technology for preventing excessive deterioration of a specific block by uniformly using blocks in the non-volatile memory 220, exemplarily a firmware technology for balancing erase counts of physical blocks can be implemented through Garbage collection is a technique for securing usable capacity in the non-volatile memory 220 by copying valid data of a block to a new block and then erasing the old block.

The buffer memory 113 may temporarily store data to be written to the nonvolatile memory 220 or data to be read from the nonvolatile memory 220 . The buffer memory 113 may be included in the storage controller 110 or may be disposed outside the storage controller 110 .

In an exemplary embodiment, the buffer memory 113 may be Dynamic Random Access Memory (DRAM). However, it is not limited thereto, and the buffer memory 113 may be implemented as static random access memory (SRAM), phase-change random access memory (PRAM), or flash memory.

3 to 5 are diagrams for describing an operation of writing data into the nonvolatile memory 120 when power to the storage device 100 is cut off according to an exemplary embodiment of the present disclosure. When power to the storage device is cut off, the storage device may operate using the auxiliary voltage. The processors 111, 111a, and 111b of FIGS. 3 to 5 may be the processor 111 of FIG. 2 and may include a plurality of cores.

Referring to FIG. 3 , the processor 111 may include a first core 111_1 and a second core 111_2. The first core 111_1 and the second core 111_2 may be cores that process different tasks. In an exemplary embodiment, the first core 111_1 may be a host core that performs an operation related to an interface with a host (eg, 200 in FIG. 1 ), and the second core 111_2 may be a flash conversion layer (eg, 200 in FIG. 1 ). For example, it may be an FTL core (NAND core) that drives 112 of FIG. 2 and performs an operation related to an interface with the non-volatile memory 120, but the present disclosure is not limited thereto.

In the performance path PP, the first core 111_1 and the second core 111_2 may be organically connected to each other, and the first core 111_1 and the second core 112_2 may operate together. On the other hand, the first core 111_1 can directly write data into the non-volatile memory 120 through the first direct path DP1, and the second core 111_2 can write data through the second direct path DP2. Data may be directly written into the volatile memory 120 . Unlike the performance path (PP), each of the first direct path (DP1) and the second direct path (DP2) may be configured to perform only an operation of writing data into the non-volatile memory 120, and only a designated core It can be configured to work. Therefore, when a power failure occurs and a failure is detected in the performance path (PP), the recovery data stored in the buffer memory 113 is transferred to the non-volatile memory through the first direct path (DP1) or the second direct path (DP2). (120). Even if a failure occurs in the performance path PP, the storage device 100 may be prevented from falling into an error state.

The nonvolatile memory 120 may include a plurality of memory areas, for example, first to kth memory areas MR1 to MRk. In this case, k may be a natural number of 3 or greater. Among the first to kth memory areas MR1 to MRk, the first memory area MR1 may be designated to be accessed by the first core 111_1 through the first direct path DP1, and the second memory area MR2 ) may be designated to be accessed by the second core 111_2 through the second direct path DP2. However, it is not limited thereto, and the first memory area MR1 may be designated to be accessed by the first core 111_1 through the first direct path DP1, and the second core 111_2 may access the second direct path (DP1). It can also be specified to be accessed via DP2). In an exemplary embodiment, a memory area corresponding to a specific core may be previously designated as data write information for writing data into the nonvolatile memory 120 when a failure occurs in the performance path (PP).

3 exemplarily, a failure occurs in the performance path PP, and the first core 111_1 accesses the first memory area MR1 of the nonvolatile memory 120 through the first direct path DP1. An example of writing data (eg, recovery data) is shown. However, the present disclosure is not limited thereto, and if a failure does not occur in the second core 111_2 during the performance path (PP), the second core 111_2 passes through the second direct path DP2 to the second memory. Recovery data can also be written in the area MR2.

Referring to FIG. 4 , the processor 111a may include a plurality of first cores 111_1a and a plurality of second cores 111_2a. The plurality of first cores 111_1a may be cores that process the same task, and the plurality of second cores 111_2a may be cores that process the same task. In an exemplary embodiment, the plurality of first cores 111_1a may be host cores that perform an operation related to an interface with the host 200, and the plurality of second cores 111_2a may include a non-volatile memory 120 It may be an FTL core (NAND core) that performs an operation related to an interface with. The first direct paths DP11 and DP12 may correspond to each of the plurality of first cores 111_1a, and the second direct paths DP21 and DP22 may correspond to each of the plurality of second cores 111_2a. It can be.

Each of the plurality of first cores 111_1a may be assigned a memory area accessible through first direct paths DP11 and DP12, and each of the plurality of second cores 111_2a may use second direct paths ( Accessible memory areas can be designated through DP21 and DP22). For example, one of the plurality of first cores 111_1a may write recovery data in the first memory area MR1 through the first direct path DP11, and the plurality of first cores ( The other core of 111_1a) may write recovery data into the kth memory area MRk through the first direct path DP12.

When a power cut occurs and a failure is detected in the performance path (PP), the plurality of first cores 111_1a may be selected as cores for performing the following operation, and the plurality of first cores ( 111_1a) may store the recovery data stored in the buffer memory 113 in the non-volatile memory 120 (mirroring operation) through the first direct paths DP11 and DP12. Since the plurality of first cores 111_1a write the same data to the non-volatile memory 120, a failure occurs in some of the first direct paths DP11 and DP12 or the first memory area MR1 and the second direct paths DP11 and DP12 fail. Even if a failure occurs in some of the k memory areas MRk, the storage device 100 may be prevented from falling into an error state.

Referring to FIG. 5 , the processor 111b may include a first core 111_1, a second core 111_2, and a third core 111_3. The first core 111_1, the second core 111_2, and the third core 111_3 may be cores that process different tasks. In an exemplary embodiment, the first core 111_1 may be a host core that performs an operation related to an interface with the host 200, and the second core 111_2 performs an operation related to an interface with the nonvolatile memory 120. The third core 111_3 may be an FTL core (NAND core) that performs operations of the first core 111_1 and the second core 111_3 between the first core 111_1 and the second core 111_3. can assist Alternatively, the third core 111_3 may perform an operation different from that of the first core 111_1 and the second core 111_2. Each of the first core 111_1, the second core 111_2, and the third core 111_3 may be composed of one core, or as described in FIG. 4, they may be composed of a plurality of cores. may be

The first core 111_1, the third core 111_3, and the second core 111_2 may be sequentially included in the performance path PP. Each of the first core 111_1, the second core 111_2, and the third core 111_3 may correspond to the first direct path DP1, the second direct path DP2, and the third direct path DP3. there is.

The first core 111_1 may be assigned a memory area accessible through the first direct path DP1, for example, the first memory area MR1. The second core 111_2 may be assigned a memory area accessible through the second direct path DP2, for example, the second memory area MR2. A memory area accessible to the third core 111_3 through the third direct path DP3, for example, a kth memory area MRk, may be designated.

When power is cut off and a failure is detected in the performance path (PP), the first core 111_1 and the third core 111_3 may be exemplarily selected as cores for performing the following operations. The first core 111_1 and the third core 111_3 store the recovery data stored in the buffer memory 113 in the nonvolatile memory 120 through the first direct path DP1 and the third direct path DP3 ( mirroring operation). Since the first core 111_1 and the third core 111_3 write the same data to the non-volatile memory 120, respectively, even if a failure occurs in some of the first direct path DP1 and the third direct path DP3, , the storage device 100 may be prevented from falling into an error state.

FIG. 6 is a block diagram illustrating one memory device 121 among a plurality of memory devices included in the nonvolatile memory 120 of FIG. 1 .

1 and 6 , the memory device 121 includes a memory cell array 122, an address decoder 123, a control logic block 124, a page buffer 125, an input/output circuit 126, and a voltage generator. (127) may be included. Although not shown, the memory device 121 may further include an input/output interface.

The memory cell array 122 may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array 122 is connected to the address decoder 123 through word lines WL, string select lines SSL, and ground select lines GSL, and a page buffer through bit lines BL. (125). The memory cell array 122 may include a plurality of memory blocks BLK1 to BLKn.

Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells and a plurality of selection transistors. Memory cells may be connected to word lines WL, and select transistors may be connected to string select lines SSL or ground select lines GSL. Each of the memory cells of the plurality of memory blocks BLK1 to BLKn may be composed of single level cells storing 1-bit data or multi-level cells storing 2 or more-bit data. can

The address decoder 123 may select one of the plurality of memory blocks BLK1 to BLKn of the memory cell array 122, select one of the word lines WL of the selected memory block, and select a plurality of strings. One of the selection lines SSL may be selected.

The control logic block 124 (or control logic circuit) is configured to perform write, read, and erase operations on the memory cell array 122 based on the command CMD, the address ADDR, and the control signal CTRL. Various control signals can be output. The control logic block 124 may provide a row address (X-ADDR) to the address decoder 123, may provide a column address (Y-ADDR) to the page buffer 125, and may provide a voltage generator 127 A voltage control signal (CTRL_Vol) may be provided.

Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of pages. The control logic block 124 may perform an erase operation in units of each of the plurality of memory blocks BLK1 to BLKn. The control logic block 124 may perform a read operation and a write operation in units of each of a plurality of pages.

The page buffer 125 may operate as a light driver or as a sense amplifier according to an operation mode. During a read operation, the page buffer 125 may sense the bit line BL of the selected memory cell according to the control of the control logic block 124 . The sensed data may be stored in latches provided inside the page buffer 125 . The page buffer 125 may dump data stored in the latches to the input/output circuit 126 under the control of the control logic block 124 .

The input/output circuit 126 may temporarily store a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from the outside of the memory device 121 through an input/output line I/O. . The input/output circuit 126 may temporarily store read data of the memory device 121 and output it to the outside through the input/output line (I/O) at a designated time point.

The voltage generator 127 may generate various types of voltages for performing a write operation, a read operation, and an erase operation on the memory cell array 122 based on the voltage control signal CTRL_Vol. Specifically, the voltage generator 127 may generate the word line voltage VWL, eg, a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage. Also, the voltage generator 127 may generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_Vol. Also, the voltage generator 127 may generate an erase voltage to be provided to the memory cell array 122 .

FIG. 7 is a diagram for explaining recovery data stored in the buffer memory 113 of FIG. 2 .

Referring to FIGS. 1 and 7 , recovery data may be stored in the buffer memory 113 . The recovery data may be data required to restore the storage device 100 when power is restored after power is cut off. Accordingly, the storage device 100 may move and store the recovery data stored in the buffer memory 113 to the non-volatile memory 120 when power is cut off.

Recovery data may include user data, debug data, user data digest, device metadata, map data, and the like. Device metadata may be information about the storage device 100 . For example, it may include smart data, security data, and metadata about characteristics of the non-volatile memory 120 . The map data is L2P data and may be map data for user data written in the non-volatile memory 120 .

Some of the recovery data may be minimal recovery data. The minimum recovery data may be data required to prevent the storage device 100 from entering an unusable state, that is, a power failure state. Minimum recovery data may include user data digest, device metadata, map data, and the like. At this time, the user data digest may be required to mark a data defect when all user data cannot be written to the nonvolatile memory 120 .

When power is cut off, the storage device 100 may move recovery data from the buffer memory 113 to the non-volatile memory 120, but may preferentially move minimum recovery data.

8 is a flowchart illustrating a method of operating the storage device 100 according to an exemplary embodiment of the present disclosure. The operation method of steps S10 to S50 illustrated in FIG. 8 may be performed time-sequentially in the storage device 100 of FIG. 1 .

Referring to FIGS. 1 and 8 , write information for writing recovery data may be set in step S10. In an exemplary embodiment, step S10 may be performed when power is supplied to the storage device 100 . The data write information may include information about the location and memory address of the non-volatile memory 120 where the recovery data will be written in step S50 or S60.

For example, in step S10, write information for writing data when a failure occurs in the performance path PP may be set. As described in FIGS. 3 to 5 , a specific core may form a corresponding direct path, and a memory area corresponding to the specific direct path may be set in step S10 .

In step S20, power provided to the storage device 100 may be cut off, and in step S30, failure of the performance path (PP) may be detected. For example, the storage device 100 may determine whether a failure of the performance path (PP) has occurred from an assert or a core hang. Alternatively, in an exemplary embodiment, as described later with reference to FIG. 8 , when the storage device 100 determines that each step of a power-off processing operation through the performance path PP is not processed within a specified time, the performance path ( It can be determined that a failure has occurred in PP).

If a failure is not detected in the performance path PP, that is, if the performance path PP is determined to be normal, the storage device 30 may perform a power cut process through the performance path PP in step S60. For example, the storage device 30 may perform a power cut-off process of writing recovery data written in the buffer memory to the non-volatile memory through the performance path PP.

If a failure is detected in the performance path (PP), in step S40 , the storage device 100 may select a core to perform subsequent steps and collect recovery data written in the buffer memory. For example, if the processor is configured with a single core, the single core may be selected. Alternatively, for example, when a processor is composed of a plurality of cores, a core that has not failed may be selected from among cores having direct paths for directly accessing the nonvolatile memory 120 . Also, the storage device 100 may reset various setting values set in the nonvolatile memory 120 in step S40.

In step S50 , the storage device 100 may write recovery data into the non-volatile memory 120 through a direct path DP corresponding to the selected core. The storage device 100 may write recovery data into the nonvolatile memory 120 based on the write information set in step S10 .

The selected core may write recovery data in a corresponding memory area among a plurality of memory areas included in the non-volatile memory 120 . The write information may include location information of a memory area corresponding to the selected core. For example, when the first core is selected as shown in FIG. 3 , in step S50 , the storage device 100 may write recovery data into the first memory area MR1 through the first direct path DP1. .

Therefore, in the storage device 100 according to the present disclosure, when a failure is detected in the performance path (PP), the recovery stored in the buffer memory is performed through the direct path (DP) through which the selected core directly accesses the non-volatile memory 120. Data can be stored in non-volatile memory. Accordingly, even if an error occurs during power fail processing, the storage device may be prevented from falling into an error state.

9 is a flowchart illustrating a method of operating the storage device 100 according to an exemplary embodiment of the present disclosure. Step S30 shown in FIG. 9 may be an example of step S30 of FIG. 8 and may include steps S31 to S34.

Referring to FIGS. 1 and 9 , in step S31, the storage device 100 may determine whether the writing operation on the first data of the recovery data is completed within a specified time, and in step S32, the storage device 100 determines whether the specified time has elapsed. It may be determined whether the write operation for the i-th data of the recovery data has been completed within the period. That is, in steps S31 and S32 , the storage device 100 may determine whether each write operation for the first to i-th data included in the recovery data has been completed within a specified time. In this case, the write operation may refer to an operation of writing to the non-volatile memory 120, and i may be a natural number of 2 or more. For example, the specified time may be 10 ms. 9 shows that step S32 is performed after step S31, but is not limited thereto, and the order of performing steps S31 and S32 can be freely modified.

The first through i-th data may include user data, device metadata, map data, and debug data. For example, the first data may be user data, the second data may be part of device metadata, and the third data may be another part of device metadata.

When each of the write operations for the first to i-th data is completed within a specified time, the storage device 100 may determine that the performance path PP is normal in step S33. On the other hand, if any one of the write operations for the first to i-th data is not completed within a specified time, it may be determined that the performance path PP has a failure.

10 is a flowchart illustrating a method of operating the storage device 100 according to an exemplary embodiment of the present disclosure. 10 is a diagram for explaining a recovery operation after power is supplied to the storage device 100 . Steps S100 to S700 shown in FIG. 10 may be performed after steps S10 to S60 of FIG. 8 are performed.

1 and 10 , power may be supplied to the storage device 100 in step S100, and the storage device 100 may scan a designated location in the nonvolatile memory 120 in step S200. The designated location may be a pre-designated location to store recovery data in order to perform a power-off processing operation. For example, the storage device 100 may scan a predetermined memory area among a plurality of memory areas (eg, MR1 to MRk in FIG. 3 ) of the nonvolatile memory 120 .

In step S300, the storage device 100 may check whether all recovery data has been written to the designated location of the nonvolatile memory 120. can open When the non-volatile memory 120 is opened, the storage controller 110 may control the operation of the non-volatile memory 120 through the performance path PP and may perform a write operation, a read operation, and an erase operation. there is.

When the recovery data is not written to the designated location of the non-volatile memory 120, the storage device 100 may check whether minimum recovery data is written to the designated location in operation S500. Minimum recovery data may include, for example, user data digest, device metadata, and map data.

When the minimum recovery data is written, the storage device 100 may uncormark the user data in step S600. For example, the storage device 100 may indicate data failure in user data corresponding to the user data digest included in the minimum recovery data.

In this case, the user data may be user data stored in the buffer memory (eg, 113 of FIG. 7 ) of the storage controller 110 but not moved to the non-volatile memory 120 . Accordingly, the storage device 100 may indicate that the corresponding user data is defective and transmit an error signal (eg, ES of FIG. 1 ) corresponding to the corresponding user data to the host 200 . When step S600 is completed, the storage device 100 may perform step S400.

When at least some of the minimum recovery data is not written in step S500, the storage device 100 may determine that the storage device 100 is in an unusable state in step S700. Accordingly, the storage device 100 may notify the host 200 that it is in an unusable state.

11 is a diagram illustrating a system to which a storage device according to an exemplary embodiment of the present disclosure is applied.

Referring to FIG. 11, the system 1000 of FIG. 11 is basically a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT). It can be a mobile system, such as a device. However, the system 1000 of FIG. 11 is not necessarily limited to a mobile system, and can be used for vehicles such as a personal computer, a laptop computer, a server, a media player, or a navigation system. (automotive) equipment and the like.

Referring to FIG. 11 , a system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and additionally includes an image capturing device. 1410, user input device 1420, sensor 1430, communication device 1440, display 1450, speaker 1460, power supplying device 1470 and connections It may include one or more of the connecting interfaces 1480 .

The main processor 1100 may control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. Depending on embodiments, the main processor 1100 may further include an accelerator block 1130 that is a dedicated circuit for high-speed data operations such as AI (artificial intelligence) data operations. Such an accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and is physically different from other components of the main processor 1100. It may be implemented as an independent separate chip.

The memories 1200a and 1200b may be used as main memory devices of the system 1000 and may include volatile memories such as SRAM and/or DRAM, but may include non-volatile memories such as flash memory, PRAM, and/or RRAM. may be The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. can The non-volatile memories 1320a and 1320b may include NAND flash memories, but may also include other types of non-volatile memories such as PRAM and/or RRAM.

The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100 or may be implemented in the same package as the main processor 1100 . In addition, the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, so that other components of the system 1000 can be accessed through an interface such as a connection interface 1480 to be described later. It may also be coupled to be detachable with the . The storage devices 1300a and 1300b may be devices to which standard rules such as universal flash storage (UFS) are applied.

The storage devices 1300a and 1300b may be implemented as the storage device 100 described in FIGS. 1 to 10 . Therefore, in the storage devices 1300a and 1300b, recovery data stored in the buffer memory is stored in the buffer memory through a direct path (DP) through which the core directly accesses the internal non-volatile memory even if a sudden power cut occurs and a failure is detected in the performance path. can be stored in non-volatile memory. Accordingly, even if an error occurs due to a power failure, the storage devices 1300a and 1300b can be prevented from falling into an error state, and the storage devices 1300a and 1300b can be continuously used.

The photographing device 1410 may capture a still image or a video, and may be a camera, a camcorder, and/or a webcam.

The user input device 1420 may receive various types of data input from a user of the system 1000, and may use a touch pad, a keypad, a keyboard, a mouse, and/or It may be a microphone or the like.

The sensor 1430 can detect various types of physical quantities that can be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. Such a sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope.

The communication device 1440 may transmit and receive signals with other devices outside the system 1000 according to various communication protocols. Such a communication device 1440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).

The display 1450 and the speaker 1460 may function as output devices that output visual information and auditory information to the user of the system 1000, respectively.

The power supply device 1470 may appropriately convert power supplied from a battery built in the system 1000 and/or an external power source and supply the power to each component of the system 1000 .

The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 and capable of exchanging data with the system 1000. The connection interface 1480 is an Advanced Technology (ATA) Attachment), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVM express (NVMe) , IEEE 1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), universal flash storage (UFS), embedded universal flash storage (eUFS), It can be implemented in various interface methods such as a CF (compact flash) card interface.

12 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 12 , a memory system 3000 may include a memory device 3100 and a memory controller 3200 . The memory system 3000 may be the storage device 100 of FIG. 1 , the memory device 3100 may be the nonvolatile memory 120 of FIG. 1 , and the memory controller 3200 may be the storage controller 110 of FIG. 1 . ) can be.

The memory system 3000 may support a plurality of channels CH1 to CHm, and the memory device 3100 and the memory controller 3200 may be connected through a plurality of channels CH1 to CHm. For example, the memory system 3000 may be implemented as a storage device such as an SSD. The memory device 3100 may be the nonvolatile memory 120 of FIG. 1 , and the memory controller 322 may be the storage controller 110 of FIG. 1 .

The memory device 3100 may include a plurality of nonvolatile memory devices NVM11 to NVMma. Each of the nonvolatile memory devices NVM11 to NVMma may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the nonvolatile memory devices NVM11 to NVM1a are connected to the first channel CH1 through ways W11 to W1a, and the nonvolatile memory devices NVM21 to NVM2a are connected to ways W21 to W21. W2a) may be connected to the second channel CH2. In an exemplary embodiment, each of the nonvolatile memory devices NVM11 to NVMma may be implemented as an arbitrary memory unit capable of operating according to individual commands from the memory controller 3200 . For example, each of the nonvolatile memory devices NVM11 to NVMma may be implemented as a memory chip or die, but the present disclosure is not limited thereto.

The memory controller 3200 may transmit and receive signals to and from the memory device 3100 through a plurality of channels CH1 to CHm. For example, the memory controller 3200 transmits commands ICMD1 to ICMDm, addresses ADDR1 to ADDRm, and data DATA1 to DATAm to the memory device 3100 through channels CH1 to CHm. Data DATA1 to DATAm may be transmitted to the device 3100 or received from the memory device 3100 .

The memory controller 3200 may select one of the nonvolatile memory devices connected to the corresponding channel through each channel and transmit/receive signals with the selected nonvolatile memory device. For example, the memory controller 3200 may select the nonvolatile memory device NVM11 from among the nonvolatile memory devices NVM11 to NVM1a connected to the first channel CH1 . The memory controller 3200 transmits the command ICMD1, the address ADDR1, and the data DATA1 to the selected nonvolatile memory device NVM11 through the first channel CH1, or transmits the selected nonvolatile memory device NVM11. Data DATA1 can be received from

The memory controller 3200 may transmit and receive signals to and from the memory device 3100 in parallel through different channels. For example, while the memory controller 3200 transmits the command ICMD1 to the memory device 3100 through the first channel CH1, the command ICMD2 is sent to the memory device 3100 through the second channel CH2. can transmit. For example, the memory controller 3200 receives data DATA1 from the memory device 3100 through a first channel CH1 while receiving data DATA2 from the memory device 3100 through a second channel CH2. can receive

The memory controller 3200 may control overall operations of the memory device 3100 . The memory controller 3200 may control each of the nonvolatile memory devices NVM11 to NVMma connected to the channels CH1 to CHm by transmitting signals to the channels CH1 to CHm. For example, the memory controller 3200 may control a selected one of the nonvolatile memory devices NVM11 to NVM1a by transmitting the command ICMD1 and the address ADDR1 through the first channel CH1.

Each of the nonvolatile memory devices NVM11 to NVMma may operate under the control of the memory controller 3200 . For example, the nonvolatile memory device NVM11 may write data DATA1 according to the command ICMD1, the address ADDR1, and the data DATA1 provided through the first channel CH1. For example, the non-volatile memory device NVM21 reads data DATA2 according to the command ICMD2 and address ADDR2 provided through the second channel CH2, and transfers the read data DATA2 to a memory controller ( 3200).

12 shows that the memory device 3100 communicates with the memory controller 3200 through m channels and includes a number of non-volatile memory devices corresponding to each channel; The number and number of nonvolatile memory devices connected to one channel may be variously changed.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

a non-volatile memory including a plurality of memory areas;
A storage controller including a buffer memory that controls the non-volatile memory through a performance path and at least one direct path and stores recovery data;
The storage controller writes recovery data into the non-volatile memory through the at least one direct path when power is cut off and a failure is detected in the performance path;
The performance path is a path for performing a write operation, a read operation, and an erase operation for data,
The storage device according to claim 1 , wherein the at least one direct path is a path for performing only a write operation on data. According to claim 1,
The storage controller,
a first core that performs an operation related to an interface with a host; and
A second core performing an operation related to an interface with the non-volatile memory;
The storage device, wherein the first core and the second core are included in the performance path. According to claim 2,
The at least one direct path includes a first direct path and a second direct path,
The first core writes the recovery data into a first memory area among the plurality of memory areas through the first direct path;
The storage device of claim 1 , wherein the second core writes the recovery data into a second memory area among the plurality of memory areas through the second direct path. According to claim 1,
The storage controller,
a plurality of first cores performing operations related to an interface with a host; and
A plurality of second cores performing operations related to an interface with the non-volatile memory;
The first cores and the second cores are included in the performance path,
The storage device, characterized in that, when power is cut off and a failure is detected in the performance path, each of the plurality of first cores writes the same recovery data to the non-volatile memory through the at least one direct path. According to claim 1,
The storage controller includes first to third cores sequentially included in the performance path;
When power is cut off and a failure is detected in the performance path, each of the first core and the second core writes the same recovery data to the nonvolatile memory through the at least one direct path. . According to claim 5,
The at least one direct path includes first to third direct paths,
The first core writes the recovery data into a first memory area among the plurality of memory areas through the first direct path;
The storage device of claim 1 , wherein the third core writes the recovery data into a second memory area among the plurality of memory areas through the third direct path. According to claim 1,
The storage device according to claim 1 , wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data. A method of operating a storage device including a storage controller and a non-volatile memory, comprising:
selecting a core and collecting recovery data written in a buffer memory when power is cut off and a failure is detected in a performance path; and
And writing the recovery data to the non-volatile memory through a direct path corresponding to the selected core,
The performance path is a path for performing a write operation, a read operation, and an erase operation for data,
The method of claim 1 , wherein the direct path is a path for performing only a write operation on data. According to claim 8,
and writing the recovery data to the non-volatile memory through the performance path when power is cut off and the performance path is determined to be normal. According to claim 8,
The recovery data includes user data, debug data, user data digest, device metadata, and map data. According to claim 8,
and determining that the performance path is normal when each of the write operations for writing the first to nth data of the recovery data into the nonvolatile memory is completed within a specified time. According to claim 8,
Further comprising setting write information including location information of the non-volatile memory where the recovery data is to be written;
The method of operating a storage device, wherein the writing of the recovery data includes writing the recovery data into the non-volatile memory based on the write information. According to claim 12,
The non-volatile memory includes a plurality of memory areas,
The writing of the recovery data may include writing the recovery data into a memory area corresponding to the selected core among the plurality of memory areas based on the write information. . According to claim 8,
scanning a designated location in the non-volatile memory when the power is provided; and
and opening the non-volatile memory when all of the recovery data is written in the designated location. According to claim 8,
scanning a designated location in the non-volatile memory when the power is provided; and
and displaying user data corresponding to the minimum recovery data as data failure when minimum recovery data among the recovery data is written in the designated location. According to claim 15,
Wherein the minimum recovery data includes a user data digest, device metadata, and map data. According to claim 15,
and transmitting an error signal to a host as a response signal according to user data corresponding to the minimum recovery data when minimum recovery data among the recovery data is written in the designated location. method. A method of operating a storage device including a storage controller and a non-volatile memory, comprising:
setting write information for writing the recovery data written in the buffer memory to the non-volatile memory;
selecting a core and collecting the recovery data when power is cut off and a failure is detected in a performance path; and
And writing the recovery data to the non-volatile memory through a direct path corresponding to the selected core,
The method of claim 1 , wherein the performance path includes a plurality of cores, and the direct path includes a corresponding core. According to claim 18,
scanning a designated location in the non-volatile memory when the power is provided; and
and opening the non-volatile memory when all of the recovery data is written in the designated location. According to claim 18,
scanning a designated location in the non-volatile memory when the power is provided; and
When minimum recovery data among the recovery data is written in the designated location, displaying data failure in user data corresponding to the minimum recovery data;
Wherein the minimum recovery data includes a user data digest, device metadata, and map data.

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