KR20160144576A - Nonvolatile memory module and user device comprising the same - Google Patents

Abstract

The nonvolatile memory module of the present invention includes a device controller including at least one nonvolatile memory and a RAM for storing control information for accessing the nonvolatile memory from the host and data to be transferred to the nonvolatile memory Wherein the RAM is arranged in an address unit specified in an interface protocol between the host and the device controller.

Description

[0001] NONVOLATILE MEMORY MODULE AND USER DEVICE COMPRISING THE SAME [0002]

The present invention relates to a semiconductor memory device, and more particularly, to a non-volatile memory module and a user device including the same.

Semiconductor memory devices are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices have a fast read / write speed, but their contents are lost when the external power supply is interrupted. On the other hand, the nonvolatile memory device can retain the stored data even if the external power supply is interrupted. Therefore, the nonvolatile memory device is used to store contents to be stored regardless of whether power is supplied or not.

In recent years, there is a growing demand for nonvolatile semiconductor memory devices capable of realizing high integration and large capacity. As such a memory device, flash memory (Flash memory), which is mainly used in portable electronic devices and the like, is typical. However, in the case of a flash memory, the writing unit and the erasing unit are different from each other. Therefore, the flash memory requires a firmware or an interface to hide the erasing operation for interfacing with the CPU of the computer system.

Nonvolatile memories compatible with various interfaces of currently used computer systems are being studied. That is, attempts have been made to use a flash memory as a data storage device or a working memory by attaching the flash memory to the same slot or channel as the main memory (or working memory). Compatibility with volatile RAM (e.g., DRAM) must be considered to implement such a memory device or module. For compatibility, a nonvolatile storage device or nonvolatile memory module capable of meeting the data exchange protocol of the volatile RAM module must be provided.

Various interfacing techniques can be applied to configure non-volatile memory modules compatible with volatile RAM modules. For example, a command, address, or data for accessing a non-volatile memory can be written to the shared memory using the protocol of the volatile RAM. In this case, the nonvolatile memory module will be able to access the nonvolatile memory area intended by the host by reading the command, address, and data stored in the shared memory. This optimal placement or arrangement of shared memory may provide optimal interfacing to the non-volatile memory module.

It is an object of the present invention to provide a nonvolatile memory module having a shared memory optimized for a protocol of a host in order to be compatible with a volatile RAM module. It is another object of the present invention to provide an operation method for managing a shared memory shared for interfacing with a host without conflict between the host and the controller.

According to an aspect of the present invention, there is provided a nonvolatile memory module including at least one nonvolatile memory, a memory for storing control information for accessing the nonvolatile memory from the host, and data to be transferred to the nonvolatile memory, Wherein the RAM is located at an address unit specified in an interface protocol between the host and the device controller.

According to another aspect of the present invention, there is provided a nonvolatile memory module including a plurality of nonvolatile memories, at least one buffer memory, a physical layer for exchanging data with a host in accordance with a first interface protocol, And a DIMM controller for exchanging data between the physical layer and the nonvolatile memory and the buffer memory, wherein the physical layer includes a first instruction, a first address, and a first data for accessing the nonvolatile memory, And the random access memory is arranged in a bank group or a bank unit which is an address division unit of the first interface protocol.

According to an aspect of the present invention, there is provided a user apparatus including a nonvolatile memory, a RAM connected to the outside through an external interface, Address, and data for accessing the non-volatile memory through the external interface, the ram being connected to the external interface, And one address space that can be input / output for each address unit defined in the protocol of FIG.

According to the data management method of the present invention, it is possible to efficiently share the host and the nonvolatile memory module in the shared memory provided for interfacing with the host. In addition, the shared memory of the present invention can provide an interface structure of a nonvolatile memory module optimized for a protocol of a host.

1 is a block diagram illustrating a non-volatile memory module according to an embodiment of the present invention.
Figure 2 is a block diagram illustrating an exemplary software layer of the nonvolatile memory module and host of Figure 1;
FIG. 3 is a diagram showing a logical area classification of the RAM of FIG. 1. FIG.
4 is a block diagram briefly showing the structure of the physical layer of FIG.
5 is a simplified block diagram of a ram controller of the present invention.
6 is a block diagram illustrating an exemplary structure of a plurality of data slices (DS) of the present invention.
FIG. 7 is a block diagram specifically illustrating a function of the serial / deserializer of FIG.
FIG. 8 is a view showing an example of dividing the SRAM of FIG. 6 into bank groups and bank address units.
9 is a block diagram illustrating an example of the structure of the ESRAM assigned to one bank group in FIG.
10 is a circuit diagram showing an exemplary configuration of the ESRAM cell of FIG.
FIG. 11 is a timing chart briefly showing an interface protocol accessing a bank group unit of a host.
FIG. 12 is a flowchart briefly showing a RAM access operation of the DIMM controller of the present invention in the configuration of FIG. 1 described above.
FIG. 13 is a block diagram illustrating one of the non-volatile memories of FIG. 1; FIG.
14 is a circuit diagram showing an example of any one of the memory blocks included in the memory cell array of FIG.
FIG. 15 is a block diagram illustrating a computing system to which a non-volatile memory module according to the present invention is applied.
FIG. 16 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 15 by way of example.
FIG. 17 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 15 by way of example.
18 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied.
FIG. 19 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 18; FIG.
20 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 18;
FIG. 21 is a block diagram showing another example of the nonvolatile memory module of FIG. 18; FIG.
22 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

In the following, a flash memory device as an example of a non-volatile memory device will be used to illustrate the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. The invention may also be embodied or applied in other embodiments. In addition, the detailed description may be modified or modified in accordance with the aspects and applications without departing substantially from the scope, spirit and other objects of the invention.

1 is a block diagram illustrating a non-volatile memory module according to an embodiment of the present invention. Referring to FIG. 1, a nonvolatile memory module 10 according to an embodiment of the present invention may include a device controller 100, a nonvolatile memory device 200, and a buffer memory 300.

The device controller 100 includes a physical layer 110 for lower level interfacing with a host and a DIMM controller 150 for exchanging data between the physical layer 110 and the buffer memory 300 and the nonvolatile memory 200, . ≪ / RTI > The device controller 100 is connected to the CPU 110 executing software or firmware for controlling the storage command CMD_N loaded into the physical layer 110, the storage address ADDR_N, data to be stored in the nonvolatile memory 200, (130).

To access the non-volatile memory module 10, a host (not shown) provides a write request and a read request. The host accesses the physical layer 110 provided in the device controller 100 to write data to the nonvolatile memory module 10. The physical layer 110 receives a RAM command CMD_R, a RAM address ADDR_R, a clock CLK, and the like transmitted from the host. The physical layer 110 may receive the data DQ and the data strobe signal DQS together with the RAM command CMD_R, the RAM address ADDR_R and the clock CLK from the host. The RAM command CMD_R, the RAM address ADDR_R and the clock CLK are signals for storing the data DQ in the RAM 114 provided in the physical layer 110. The data DQ written in the specific area of the RAM 114 is substantially the same as the storage command CMD_N for accessing the nonvolatile memory 200, the storage address ADDR_N, the data DATA, .

The host can write information (CMD_N, ADDR_N, DATA, ST) for accessing the nonvolatile memory 200 or the buffer memory 300 to a specific area of the RAM 114. [ Logical area division for writing the information (CMD_N, ADDR_N, DATA, ST) of the RAM 114 will be described later in detail in FIG. Here, the information (CMD_N, ADDR_N, DATA) written in the RAM 114 is a command, address, and data for accessing the nonvolatile memory 200, respectively. The state information ST is data indicating the state of the command, the address, and the data recorded in the RAM 114 of the data to the host.

As a result, the RAM 114 can perform the shared memory function of the host and the nonvolatile memory module 10 to write the address and data to the nonvolatile memory module 10 according to the interface protocol of the host have. In particular, the RAM 114 of the present invention may have an optimal arrangement and structure for the address protocol of the host. For example, the host may include an interface protocol to support a dual in-line memory module (DIMM) of Double Data Rate 4 (DDR4). The physical layer 110 supports the pin configuration of the DDR4 standard and the DDR4 standard RAM command CMD_R, the RAM address ADDR_R, the clock CLK, the data DQ, (DQS).

In the protocol for supporting the DDR4 standard, the RAM address ADDR_R may include a bank group (BG) address. In the case of DDR4 standard DRAM, it is a structure having 16 banks, which can be divided into four bank groups (x4 / x8 devices). It is also possible to issue individual instructions for each of the four divided bank groups BG. That is, it means that the DDR4 standard can be independently accessed from the host for each of the bank groups (BG). Through such a bank group address structure, the host can access each bank group in a prefetch manner like DDR3. However, to meet the interface speed, the DDR4 specification requires twice the data rate compared to the DDR3 prefetch approach. In the DDR4 scheme, a plurality of banks are simultaneously accessed to meet this speed requirement. Accordingly, the structures for accessing the plurality of banks are divided into a plurality of bank groups in units of a plurality of bank groups that can be independently accessed and controlled.

The RAM 114 of the present invention may have a physical structure, for example, divided into bank groups (BG). Alternatively, the RAM 114 of the present invention may have a physical structure that is divided into bank address (BA) units. With this structure, the nonvolatile memory module 10 optimized for the host interface protocol can be provided. In addition, the physical layer 110 itself can store the access state of the host with respect to the bank group BG or the bank address BA. The access state of the host may be provided to the DIMM controller 150 to prevent an access collision with the RAM 114 driven in a dual port manner.

The CPU 130 may execute firmware for performing various data exchange, error correction, scrambling, and the like, which are performed in the device controller 100. The CPU 130 analyzes the data loaded in the RAM 114 and transfers the data to the nonvolatile memory 200 and the buffer memory 300 or the data stored in the nonvolatile memory 200 and the buffer memory 300 to the RAM 114 to each other. It will be understood by those skilled in the art that the CPU 130 can be provided as a multi-core for performing the above-described control operations on a function-by-function basis.

The DIMM controller 150 transfers data stored in the RAM 114 of the physical layer 110 to the target area of the nonvolatile memory 200 or the buffer memory 300 under the control of the CPU 130. The DIMM controller 150 may refer to the address status information of the physical layer 110 to suspend access to the same bank group as the bank group BG being accessed by the host. Thus, conflicts with the RAM 114 area being accessed by the host can be avoided.

The plurality of nonvolatile memories 200 are connected to the device controller 100 through a plurality of channels CH1 to CHn, respectively. A plurality of non-volatile memories (200) can program the received data or output the stored data under the control of the device controller (100). Each of the plurality of nonvolatile memories 200 may be an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a Resistive RAM (FRAM) , STT-MRAM (Spin-Torque Magnetic RAM), and the like. For the sake of brevity, it is assumed that each of the plurality of nonvolatile memories 200 includes a NAND flash memory.

Illustratively, as an exemplary embodiment according to the technical concept of the present invention, each of the plurality of non-volatile memories 200 may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithical means that layers of each level in a three-dimensional array are deposited directly on the lower-level layers of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between the levels, a configuration suitable for a three-dimensional memory array is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466 U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, which are incorporated herein by reference.

The buffer memory 300 may be used as a buffer memory, an operation memory, or a cache memory of the device controller 100. The buffer memory 300 may include various information required for the nonvolatile memory module 10 to operate. Illustratively, the buffer memory 300 may include data for managing a plurality of nonvolatile memories 200. For example, the buffer memory 300 stores a mapping table between the storage address ADDR_N received from the host via the data signal DQ and the data strobe signal DQS and the physical address of the plurality of nonvolatile memories 200 . Illustratively, the buffer memory 300 may include random access memories such as SRAM, DRAM, SDRAM, MRAM, ReRAM, PRAM, FRAM, and the like.

Illustratively, the non-volatile memory module 10 is in the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with a host. That is, the physical layer 110 may perform the interfacing operation defined according to the dual data rate (DDR, DDR2, DDR3, DDR4) protocol. However, the interface protocol between the host and the nonvolatile memory module 10 is not limited thereto.

For example, the interface between the host and the nonvolatile memory module 10 may be a DDR, DDR2, DDR3, DDR4, LPDDR, USB, MMC, peripheral component interconnection), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI) ), Firewire, Universal Flash Storage (UFS), Nonvolatile Memory Express (NVMe), and the like.

Figure 2 is a block diagram illustrating an exemplary software layer of the nonvolatile memory module and host of Figure 1; Referring to FIG. 2, host layer software 20 will be running at the host. In the non-volatile memory module 10, the software or the firmware 30 of the non-volatile memory layer will be driven.

Various layers of software may be present in the host layer 20. The application program 21 and the operating system 23 may be included in the host upper layer HL1. The application program 21 is software of an upper layer which is driven as a basic service or driven by a user. The operating system 23 will perform overall control operations such as file access, application program activation, control of the nonvolatile memory module 10 as well as program execution.

The RAM driver 25 or the DIMM layer driver 27 constitutes a host lower layer HL2 for accessing the nonvolatile memory module 10. [ The RAM driver 25 or the DIMM layer driver 27 may be substantially included in the kernel of the operating system. The RAM driver 25 performs a control operation for accessing the RAM 114 of the nonvolatile memory module 10 in response to an access request provided from the host upper layer HL1. For example, the RAM driver 25 may be a control module for controlling the RAM 114 of the non-volatile memory module 10 at the operating system 23 level. When an access request from the application program 21 or the operating system 23 to the RAM 114 occurs, the RAM driver 25 will be called. In addition, the DIMM layer driver 27 with the RAM driver 25 will be called to support the physical layer level access to the RAM 114.

The nonvolatile memory hierarchy 30 includes a memory upper layer ML1 and a memory lower layer ML2. The upper layer memory ML1 controls access to the nonvolatile memory 31 in accordance with the upper instruction CMD_N and upper address ADDR_N written in the RAM 114. [ The memory upper layer ML1 will be accessed by the controller layer 33 to the nonvolatile memory 31 and the memory management operation will be performed. For example, control over garbage collection, wear leveling, stream control, etc. for the non-volatile memory 31 may be performed by the controller layer 33. On the other hand, in the memory lower layer ML2, interfacing between the RAM 35 and the host will be performed. That is, the memory lower layer ML2 will perform an operation of reading or writing data of the RAM 35 to the RAM command CMD_R or the RAM address ADDR_R. It will be appreciated that the memory lower layer ML2 may also access the RAM 35 at the request of the memory upper layer ML1.

The host can access the nonvolatile memory module 10 by software or firmware having the above-described hierarchical structure. Access to the nonvolatile memory 200 provided in the nonvolatile memory module 10 formed in the DIMM type is performed by decoding the storage command CMD_N and the storage address ADDR_N provided via the RAM 114 will be.

In the present invention, the structure of the RAM 114 of the nonvolatile memory module 10 accessed by the host will be provided in a structure optimized for the interface protocol of the host. Therefore, improvement of data transfer characteristics between the host and the nonvolatile memory module 10 is expected.

FIG. 3 is a diagram showing a logical area classification of the RAM of FIG. 1. FIG. 3, the RAM 114 is logically divided into a command area (CA), a write area (WA), a read area (RA), and a status area (STA) . ≪ / RTI >

A storage command CMD_N received from the host via the data signal DQ and the data strobe signal DQS may be stored in the command area CA of the RAM 114. [ The DIMM controller 150 can read the storage command CMD_N stored in the command area CA of the RAM 114. [ Illustratively, the storage command CMD_N may include a storage address ADDR_N, and the storage command CMD_N and the storage address ADDR_N may be stored in the command area CA.

Write data (DATA_W) received through the data signal (DQ) and the data strobe signal (DQS) may be stored in the write area (WA) of the RAM (114). The DIMM controller 150 can read the write data (DATA_W) stored in the write area WA of the RAM 114. [

Read data (DATA_R) may be stored in the read area (RD) of the RAM (114). The read area RD of the RAM 114 may be transmitted to the host via the data signal DQ and the data strobe signal DQS.

State information STI received from the host via the data signal DQ and the data strobe signal DQS is stored in the state area STA of the RAM 114 and the stored state information STI can be transmitted to the host have.

According to the function of the RAM 114 described above, it can be said that it is used as a shared memory between the host and the nonvolatile memory module 10. That is, the RAM 114 stores instructions, addresses, and data for accessing the nonvolatile memory devices 200 or the buffer memory 300. [ The RAM 114 may store the write state of the command, address, and data.

4 is a block diagram briefly showing the structure of the physical layer of FIG. Referring to FIG. 4, the physical layer 110 may include a RAM controller 112, a RAM 114, and a serial / deserializer 116. The RAM controller 112 is configured with a control slice CS and the RAM 114 and the serial / deserializer 116 can be configured with a data slice (DS). Here, the data slice DS may be configured with a plurality of data slices DSs according to the input / output data unit.

The RAM controller 112 receives information or data received via the data signal DQ and the data strobe signal DQS in response to the RAM command CMD_R, the RAM address ADDR_R, and the clock CK received from the host And stores it in the RAM 114. Alternatively, the RAM controller 112 may transmit information or data stored in the RAM 114 to the host via the data signal DQ and the data strobe signal DQS.

Illustratively, the RAM controller 112 may generate an address ADDR and an instruction CMD for controlling the RAM 114 from the RAM command CMD_R, the RAM address ADDR_R, and the clock CK . That is, when the RAM 114 is a dual port SRAM, the RAM controller 112 may generate a command CMD, an address ADDR, and a control signal for accessing the ESRAM.

In particular, the RAM controller 112 stores the bank group BG and the bank address BA provided from the host and stores the address status information ADD_Status for the bank group BG and the bank address BA, To the DIMM controller 150. That is, the RAM controller 112 stores the state of the bank group BG and the bank address BA requested by the host. The address status information ADD_Status may be referred to when the DIMM controller 150 accesses the RAM 114 provided in the dual port SRAM. The specific configuration of the RAM controller 112 will be described in detail in FIG. 5 to be described later.

The RAM 114, which constitutes the data slice DS, And may include a plurality of SRAMs divided into bank group (BG) units. That is, the RAM 114 constituting one data slice DS may be divided into two or four bank groups BG according to the bank address. That is, when there are sixteen banks of the RAM 114 corresponding to one data slice DS, the sixteen banks can be managed by two or four bank groups BG. The bank group (BG) is a DDR4-compliant address protocol that is mixed with the prefetch scheme to match the interface speed. The RAM 114 may be configured in such a manner that one slot group is disposed in one bank group BG. The physical structure of the RAM 114 may provide an optimal access environment for the address protocol provided by the host. Here, it is described that one bank group (BG) is allocated to one bank, but the present invention is not limited thereto. That is, the RAM 114 may be configured in such a manner that one Slam is allocated to one bank.

The serial / deserializer 116 parallelizes the data DQ provided from the host and transfers the data DQ to the RAM 114. In contrast, the serial / deserializer 116 will serialize the data stored in the RAM 114 and deliver it to the host. By the operation of the serial / deserializer 116, the synchronization between the host, which is a high-speed interface, and the internal operation, which operates at a relatively low speed, can be easily performed.

As described above, a plurality of data slices DS can be provided. For example, when the data pin structure of the physical layer 110 is such that one data strobe signal DQS is shared by four data signals DQ, one data slice DS per data strobe signal Lt; / RTI >

5 is a simplified block diagram of a ram controller of the present invention. Referring to FIG. 5, the RAM controller 112 may include a delay lock loop 112_1, an instruction generator 112_2, an MRS register 112_3, and an address status register 122_4.

The delay locked loop 112_1 may control the phase of the clock signal CK_t / CK_c provided from the host to provide it to the internal circuits. For example, when data DQ is transmitted on the rising edge and the falling edge of the clock signal CK_t / CK_c, the data bit time by the clock signal CK_t / CK_c provided by the host is relatively short. To satisfy such a strict timing requirement, the RAM controller 112 needs to be configured to synchronize the phase of the clock signal (CK_t / CK_c) with the internal clock. A clock skew due to the internal circuits occurs when the clock signal (CK_t / CK_c) input from the host is used in the RAM controller 112. [ The delay locked loop 112_1 compensates for this time delay and generates an internal clock whose internal clock has the same phase as the clock signal CK_t / CK_c. That is, the delay locked loop 112_1 generates a delay time when an external incoming clock is used internally, and the delay locked loop controls the delay time so that the phase of the clock used therein is the same as the phase of the clock received from the outside It is a role to play.

The instruction generator 112_2 decodes an instruction and an address provided from the host and internally transfers the decoded instruction to the MRS register 112_3 and the address status register 112_4. The instruction generator 112_2 receives the control signals / RAS, / CAS and ACT_n provided by the host's interface protocol and the address ADDR in synchronization with the clock signal provided from the delay synchronization loop 112_1. Then, the input command will be transmitted to the MRS register 112_3. In addition, the instruction generator 112_2 provides the instruction ACT / WR / RD and the address BG, BA, RA, CA to the address status register 112_4. The instruction generator 112_2 may transmit a status signal ALERT_n to the host to transmit a specific status to the nonvolatile memory module 10. [

The MRS register 112_3 is programmed by the MRS instruction CMD_MRS, which is decoded and supplied from the instruction generator 112_2. That is, the MRS register 112_3 is programmed by the MRS instruction CMD_MRS, and the programmed instruction is provided to the instruction CMD_R for driving the RAM 114. [

The address status register 112_4 receives the command ACT / WR / RD and the bank group BG, the bank address BA, the row address RA and the column address CA provided from the instruction generator 112_2 Stores the access state of each bank group (BG) and each bank. The address status register 112_4 will transmit the status of the bank group or bank being accessed by the host, that is, the address status information ADD_Status to the DIMM controller 150 side. Referring to the address status information ADD_Status, the DIMM controller 150 can avoid a conflict in the RAM 114 operating in the dual port mode by suspending access to a bank group or a bank to which the host is accessing.

6 is a block diagram illustrating an exemplary structure of a plurality of data slices (DS) of the present invention. Referring to FIG. 6, each data slice DS may include an esRAM 114, a serial / deserializer 116, and an SRAM control logic 118. Illustratively, the first data slice DS_1 includes a ram address ADDR_R provided from the RAM controller 112 and an esRAM 114_1 accessed in response to the RAM instruction CMD_R. Illustratively, the first data slice DS_1 may include an esRAM 114_, a serial / deserializer 116_1, and an SRAM control logic 118_1. The second data slice DS_2 to the m-th data slice DS_m may also have the same configuration as the first data slice DS_1.

The ESRAM 114_1 will include a plurality of ESRAMs separated by Bank Group under the control of the ESRAM control logic 118_1. The scrambler 114_1 stores k + 1-bit data supplied from the serial / deserializer 116_1 in the selected area. Also, the data stored in the selected area may be output to the DIMM controller 150 side. In addition, data provided on the DIMM controller 150 side is written in a specific area of the esl ramp 114_1, and data written in a specific area can be transferred to the host via the serial / deserializer 116_1 again. The ESRAM 114_1 may be driven by a dual port system which is simultaneously accessible by the host and the DIMM controller 150. [

The serial / deserializer 116_1 parallelizes the data DQ [j: 0] provided through the high-speed interface of the host to provide the data unit MDQ [k: 0] optimized for the scrambler 114_1. In addition, the data read from the ESRAM 114_1 is serialized and transmitted through the high-speed interface on the host side. By the function of the serial / deserializer 116_1, it is possible to solve the problems caused by the difference between the high-speed interface between the physical layer 110 and the host and the internal operation speed.

The SRAM control logic 118_1 may control the word lines, bit lines, or read / write circuits of the SRAM 114_1 by referring to the input RAM command CMD_R or the RAM address ADDR_R.

Here, although the configuration for one data slice DS_1 has been briefly described, it will be understood that the remaining data slices DS_2 to DS_m may include the same configuration. That is, it may be configured to be connected to one data slice DS for each data signal set DQSn, DQ [m: 0] sharing the data strobe signal DQS. That is, each of the data slices DS_1 to DS_m includes independent SRAMs, and SRAMs independent of each other in the bank group (BG) or the bank unit may be arranged in the same data slice. With this structure, it is possible to provide the physical layer 110 optimized for the DDR4 standard interface protocol that overcomes the difference between the channel and the internal operation speed by using the bank group BG.

FIG. 7 is a block diagram specifically illustrating a function of the serial / deserializer of FIG. Referring to FIG. 7, the serial / deserializer 116_1 is configured to perform an array operation of data (DQ0, DQ1, DQ2, DQ3, and DQS0) exchanged with the host side and data (MDQ0 to MDQ31) The problem of the difference in clock frequency can be solved.

For example, when the host uses a DDR4-compliant interface protocol, a data exchange rate of 1600 MHz may be provided between the host and the data slice (DS_1). On the other hand, in the data slice DS_1, data can be transmitted in synchronization with the clock at 200 MHz. In this case, the serial / deserializer 116_1 performs an operation of arranging the data provided from the host in parallel by the clock CLKi provided from the delay synchronization loop 112_1. Through the serial / parallel operation, it is possible to solve the synchronization problem of the signal caused by the difference between the external clock frequency and the internal clock frequency.

FIG. 8 is a view showing an example of dividing the SRAM of FIG. 6 into bank groups and bank address units. Referring to FIG. 8, the esl ram 114_1 corresponding to one data slice DS may be arranged in units of bank groups (BG).

The ESRAM 114_1 included in one data slice DS_1 may be divided into two or four bank group units. That is, the bank group BG0 will include four banks BA0, BA1, BA2, and BA3. In addition, the esRAM 114_1 of the present invention can allocate one esRAM to one bank group BG0. That is, an esRAM device divided into one input / output unit may be allocated to each of the bank groups BG0, BG1, BG2, and BG3. Of course, the manner in which the esram device is deployed may vary. That is, one of the bank units BA0, BA1, BA2, and BA3 may be assigned to one of the SRAM devices. It is possible to provide the physical layer 110 optimized for the interface protocol of the host that reflects the difference of the movement time between the bank groups or between the banks through the assignment of the bank group unit or the bank unit.

9 is a block diagram illustrating an example of the structure of the ESRAM assigned to one bank group in FIG. Referring to FIG. 9, one bank group BG0 may be composed of one ESRAM 400 having one input / output unit (I / O). The SRAM 400 may include a cell array 410, a row decoder 420, a column decoder 430, a read / write circuit 440, an input / output buffer 450, and a control logic 460.

The cell array 410 may provide a memory area corresponding to one bank group BG0. That is, at least four banks BA0 to BA3 are included in one bank group BG0. The cell array 410 may be divided into a plurality of banks. The bank selection in the bank group BG0 provided by the host may be selected by the row decoder 420 and the column decoder 430. [

The read / write circuit 440 writes or reads data requested to be read or written by the host or the DIMM controller 150 to the cell array 410. The read / write circuit 440 may transmit the sensed data in the selected memory area to the input / output buffer 450. The read / write circuit 440 may write write data provided through the input / output buffer 450 to the cell array 410.

The control logic 460 may control the read and write operations to the ESRAM 400 with reference to the control signals (nWE, nOE, CLK) provided by the host side access request.

The configuration of the ESRAM corresponding to one bank group BG0 is shown. However, it will be appreciated that a single bank may be assigned an S-RAM.

10 is a circuit diagram showing an exemplary configuration of the ESRAM cell of FIG. Referring to FIG. 10, the ESRAM cell 411 may be configured as a dual-port ESRAM.

The SRAM cell 411 will be illustratively shown as a two-port SRAM cell consisting of four transistors. The SRAM cell 411 includes a first inverter composed of a PMOS transistor P1 and an NMOS transistor N1. The SRAM cell 411 includes a second inverter composed of a PMOS transistor P2 and an NMOS transistor N2. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. The SRAM cell 411 is connected to the bit lines BL_A and BLB_A and the word line WL_A constituting the A-port by the pass transistors PT1 and PT2. The gates of the pass transistors PT1 and PT2 are connected to the word line WL_A. When the select voltage is applied to the word line WL_A, the pass transistors PT1 and PT2 are turned on and the esflam cell 411 composed of the first inverter and the second inverter is connected to the bit line pair BL_A and BLB_A .

In order to configure the B-port, the SRAM cell 411 is connected to the bit lines BL_B and BLB_B and the word line WL_B by the pass transistors PT3 and PT4. The gates of the pass transistors PT3 and PT4 are connected to the word line WL_B. When the select voltage is applied to the word line WL_B, the pass transistors PT3 and PT4 are turned on and the esflam cell 411 composed of the first inverter and the second inverter is connected to the bit line pair BL_B and BLB_B .

Although the ESRAM cell 411 is described as being configured as a dual port, the ESRAM of the present invention is not limited thereto. The ESRAM cell 411 may be configured as a single-port ESRAM or as a multi-port ESRAM.

FIG. 11 is a timing chart briefly showing an interface protocol accessing a bank group unit of a host. Referring to FIG. 11, when the interface protocol of the host is DDR4 standard, different delay times are applied when changing the bank address in the same bank group and when accessing different bank groups.

For example, it is assumed that the host inputs the read command (RD) command and the bank group BG0, the bank address BA0, and the column address Col1 at time T0 in synchronization with the host clock. Then, the data read from the selected area will be output through the data (DQ, DQS) line. When the host provides the read command RD and the address BG1, BAO, Col1 for accessing the other bank group BG1 while accessing the bank group BG0, at least the command time tCCD_S ) Is the elapsed time T4. On the other hand, when the host provides the read command RD and address BG1, BA1, Col1 for accessing the same bank group BG1 while accessing the bank group BG1, the command time (tCCD_L) is required.

That is, the time tCCD_L for providing an instruction to access the same bank group BG1 → BG1 takes a relatively longer time compared to the case of accessing the different bank groups BG0 → BG1. Depending on the characteristics of such a DRAM, the host will issue instructions and addresses. When accessing another bank group, the transmission bandwidth of DDR4 can be maximized, but when accessing another bank in the same bank group, the bandwidth can not be filled.

The physical layer reflecting the attributes of the DRAM described above can be constituted through the arrangement and configuration of the sram according to the present invention.

FIG. 12 is a flowchart briefly showing a RAM access operation of the DIMM controller of the present invention in the configuration of FIG. 1 described above. Referring to FIG. 12, the DIMM controller 150 can avoid accessing the same bank group or the same bank as the host by referring to the access state of the host to the RAM 114. [

In step S110, the DIMM controller 150 will monitor whether an access request to the RAM 114 has occurred. For example, if a read request is made to the RAM 114 for data to be transferred to the non-volatile memory 200, the DIMM controller 150 will receive such a request.

In step S120, the DIMM controller 150 will receive from the RAM controller 112 of the physical layer 110 access status information (ADD_Status) of the host for the requested bank group BG or bank.

In step S130, the DIMM controller 150 will detect whether the host is accessing the same area as the bank group (BG) or bank requested to access. The access status information (ADD_Status) includes address information for a bank group or a bank to which the host is being accessed. If the bank group of the RAM 114 to be accessed by the DIMM controller 150 is different from the bank group to which the present host is currently accessing, the procedure moves to step S140. On the other hand, if the bank group to be accessed by the DIMM controller 150 is the same as the bank group to which the current host is accessing, the procedure moves to step S150.

In step S140, the DIMM controller 150 will access the bank group BG and the bank BA of the current access requested RAM without any restriction. Since the host and the different bank groups are accessed, the problem of collision does not occur.

In step S150, the DIMM controller 150 will suspend access to the bank group (BG) of the currently requested RAM. When the access to the bank group of the host is later terminated with reference to the access state information ADD_Status, the DIMM controller 150 will retry the requested access.

 In the above description, the technique of avoiding competition between the host and the DIMM controller 150 by referring to the bank group BG and the access state information ADD_Status for the bank has been described. This technique is possible as the RAM 114 is arranged and accessed in bank groups or bank units.

FIG. 13 is a block diagram illustrating one of the non-volatile memories of FIG. 1; FIG. 13, the non-volatile memory device 200 includes a memory cell array 210, an address decoder 220, a page buffer 230, an input / output circuit 240, and a control logic and voltage generation circuit 250 .

The memory cell array 210 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) storing one bit or a multi level cell (MLC) storing at least two bits.

The address decoder 220 is connected to the memory cell array 210 through a plurality of word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 220 can receive the address ADDR_P from the external device and decode the received physical address ADDR_P to drive the plurality of word lines WL. For example, the address decoder 220 decodes the physical address ADDR_P received from the external device and generates at least one word line of the plurality of word lines WL based on the decoded physical address ADDR_P And may drive at least one selected word line. Illustratively, the physical address ADDR_P indicates the physical address of the nonvolatile memory 200 to which the storage address ADDR_N (see FIG. 1) has been converted. The above-described address conversion operation can be performed by the flash conversion layer (FTL) driven by the device controller 100 or the device controller 100. [

The page buffer 230 is connected to the memory cell array 210 through a plurality of bit lines BL. The page buffer 230 controls the bit lines BL so that data (DATA) received from the input / output circuit 240 is stored in the memory cell array 210 under the control of the control logic and the voltage generating circuit 250 . The page buffer 230 may read the data stored in the memory cell array 110 and transmit the read data to the input / output circuit 240 under the control of the control logic and the voltage generation circuit 250. By way of example, the page buffer 230 may receive data on a page-by-page basis from the input / output circuit 240 or may read data on a page-by-page basis from the memory cell array 210.

The input / output circuit 240 may receive data (DATA) from an external device and may transfer the received data (DATA) to the page buffer 230. Or the input / output circuit 240 may receive the data (DATA) from the page buffer 230 and transfer the received data (DATA) to an external device (for example, the DIMM controller 150). Illustratively, the input / output circuit 160 can transmit and receive data (DATA) with an external device in synchronization with the control signal CTRL.

The control logic and the voltage generating circuit 250 receive the storage command CMD_S and the control signal CTRL from the external device and generate the address decoder 220, the page buffer 230, and the input / (240). For example, the control logic and voltage generation circuit 250 may control other components such that data (DATA) is stored in the memory cell array 210 in response to signals CMD_N and CTRL. Or control logic and voltage generation circuit 250 may control other components such that data (DATA) stored in memory cell array 210 is transferred to an external device in response to signals CMD_N and CTRL. Illustratively, the storage command CMD_N received from the external device may be a modified command of the storage command CMD_N of FIG. The control signal CTRL may be a signal that the device controller 100 provides to control the nonvolatile memory 131. [

The control logic and voltage generation circuit 250 may generate various voltages required for the non-volatile memory 131 to operate. For example, the control logic and voltage generation circuit 250 may include a plurality of programmable voltages, a plurality of pass voltages, a plurality of selected read voltages, a plurality of unselected read voltages, a plurality of erase voltages, Can generate various voltages such as voltages. The control logic and voltage generation circuit 250 may provide the various voltages generated to the address decoder 220 or to the substrate of the memory cell array 210.

14 is a circuit diagram showing an example of any one of the memory blocks included in the memory cell array of FIG. Illustratively, with reference to Fig. 14, a memory block BLK1 of a three-dimensional structure will be described. However, the scope of the present invention is not limited thereto, and other memory blocks included in each of the plurality of nonvolatile memories 200 may have a structure similar to that of the memory block BLK1.

Referring to Fig. 14, the memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row.

For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form a first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes the string selected transistors SSTa and SSTb, the plurality of memory cells MC1 to MC8, the ground selected transistors GSTa and GSTb, And dummy memory cells DMC1, DMC2. Illustratively, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and are stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selected transistors SSTa and SSTb are connected in series and the strings of selected transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selected transistors GSTa and GSTb are connected in series and the grounded selected transistors GSTa and GSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

Illustratively, a first dummy memory cell DMC1 may be provided between a plurality of memory cells MC1 to MC8 and ground selected transistors GSTa and GSTb. Illustratively, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string selected transistors SSTa and SSTb.

The ground selected transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be connected in common to the ground selection line GSL. By way of example, the ground selected transistors in the same row can be connected to the same ground select line, and the ground selected transistors in the other row can be connected to different ground select lines. For example, the first ground selected transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selected transistors GSTa of the cell strings CS21, CS12 of the second row The first ground selected transistors (GSTa) may be connected to the second ground selection line.

Illustratively, although not shown in the drawings, the ground selected transistors provided at the same height from the substrate (not shown) may be connected to the same ground select line, and the ground selected transistors provided at different heights may be connected to another ground select line Can be connected. For example, the first ground selected transistors (GSTa) of the cell strings (CS11, CS12, CS21, CS22) are connected to a first ground selection line and the second ground selection transistors (GSTb) Line. ≪ / RTI >

Memory cells of the same height from the substrate (or ground selected transistors GSTa, GSTb) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, cell strings The first to eighth memory cells MC8 of the memory cells CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Strings of the same row among the first string selected transistors (SSTa) of the same height are connected to the same string selection line, and the other strings of string selected transistors are connected to another string selection line. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL1a.

Likewise, string selected transistors of the same row of the second string selected transistors (SSTb) of the same height are connected to the same string select line, and the other strings of string selected transistors are connected to different string select lines. For example, the second string selected transistors SSTb of the cell strings CS11, CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21, CS22 of the second row ) Are connected in common with the string selection line SSL2b.

Although not shown in the figure, string selected transistors of cell strings in the same row may be connected in common to the same string select line. For example, the first and second string selected transistors (SSTa, SSTb) of the cell strings CS11, CS12 of the first row may be connected in common to the same string selection line. The first and second string selected transistors (SSTa, SSTb) of the cell strings CS21, CS22 of the second row may be connected in common to the same string selection line.

Illustratively, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

In the memory block BLK1, reading and writing can be performed line by line. For example, one row of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, when the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11, CS12 are connected to the bit lines BL1, BL2. When the turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and the turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row are supplied with bit Connected to the lines BL1 and BL2 and driven. Memory cells of the same height among the memory cells of the cell strings of the row driven by driving the word lines are selected. Read and write operations can be performed on selected memory cells. Selected memory cells may form a physical page unit.

In the first memory block BLK1, erasing may be performed in units of memory blocks or units of subblocks. When erasing is performed in units of memory blocks, all the memory cells MC of the first memory block BLK1 can be erased simultaneously according to one erase request. When performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK1 may be simultaneously erased in response to one erase request, and some of the memory cells MC of the first memory block BLK1 may be erased. A low voltage (e. G., Ground voltage) is applied to the word line connected to the erased memory cells, and the word line connected to the erased memory cells can be floated.

Illustratively, the illustrated memory block BLK1 is exemplary and the number of cell strings may be increased or decreased, and the number of rows and columns comprised by the cell strings may be increased or decreased depending on the number of cell strings have. The number of the cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, and the height of the memory block BLK1 may be increased according to the number of cell transistors Or may be reduced. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

FIG. 15 is a block diagram illustrating a computing system to which a non-volatile memory module according to the present invention is applied. 15, a computing system 1000 includes a processor 1100, RAM modules 1200 and 1250, non-volatile memory modules 1300 and 1305, a chipset 1400, a GPU 1500, an input / 1600, and a storage device 1700.

The processor 1100 may control all operations of the computing system 1000. The processor 1100 may perform various operations performed in the computing system 1000.

The RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may be directly connected to the processor 1100. For example, each of the RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may have the form of a dual in-line memory module (DIMM). Each of the RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may be mounted on a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100. Illustratively, the non-volatile memory modules 1300 and 1305 may be the non-volatile memory module 10 described with reference to FIGS.

The RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 can communicate with the processor 1100 through the same interface 1150. [ For example, the non-volatile memory modules 1300 and 1305 and the RAM modules 1200 and 1250 can communicate through the DDR (Double Data Rate) interface 1150. Illustratively, processor 1100 may use RAM modules 1200 and 1250 as operational memory, buffer memory, or cache memory of computing system 1000.

The chipset 1400 is electrically connected to the processor 1100 and can control the hardware of the computing system 1000 under the control of the processor 1100. [ For example, the chipset 1400 may be connected to the GPU 1500, the input / output device 1600, and the storage device 1700 via the main buses, respectively, and may serve as a bridge to the main buses.

The GPU 1500 may perform a series of arithmetic operations to output image data of the computing system 1000. Illustratively, GPU 1500 may be implemented within processor 1100 in a system-on-chip form.

The input / output device 1600 includes various devices that input data or instructions to the computing system 1000 or output data to the outside. For example, the input / output device 1600 may include a user input device such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, Liquid Crystal Display), OLED (Organic Light Emitting Diode) display device, AMOLED (Active Matrix OLED) display device, LED, speaker, motor and the like.

The storage device 1700 may be used as a storage medium of the computing system 1000. Storage device 1600 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.

Illustratively, non-volatile memory modules 1300 and 1305 may be used by the processor 1100 as a storage medium of the computing system 1000. The interface 1150 between the non-volatile memory modules 1300 and 1305 and the processor 1100 may be a higher speed interface than the interface between the storage device 1700 and the processor 1100. [ That is, the performance of the computing system is improved by the processor 1100 using the nonvolatile memory modules 1300 and 1305 as the storage medium.

The non-volatile memory modules 1300 and 1305 may include an architecture that is optimized for the interface protocol with the processor 1100. That is, the processor 1100 can provide instructions, addresses, and data for accessing the non-volatile memory to the non-volatile memory modules 1300 and 1305 through a plurality of RAMs, which are divided into bank groups or bank units will be.

FIG. 16 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 15 by way of example. Illustratively, FIG. 16 shows a non-volatile memory module 1300 in the form of a Load Reduced DIMM (LRDIMM). 16 illustrates a non-volatile memory module 1300 in the form of a dual in-line memory module (DIMM), which is mounted in a DIMM socket to communicate with the processor 1100 .

16, the non-volatile memory module 1300 includes a device controller 1310, a buffer memory 1320, a non-volatile memory device 1330, and a serial presence detect chip 1340 (SPD) . The device controller 1310 may include a RAM 1311. Illustratively, non-volatile memory device 1330 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1330 may be implemented as a separate chip, a separate package, a separate device, or a separate module, respectively. Or non-volatile memory device 1330 may be implemented as a single chip or as a single package.

By way of example, the device controller 1310, the RAM 1311, the buffer memory 1320, and the non-volatile memory device 1330 correspond to the device controller 100, the RAM 114, the buffer memory 300 ), And a plurality of non-volatile memories (200). The non-volatile memory module 1300 may include an architecture that is optimized for the interface protocol with the processor 1100. That is, the processor 1100 transmits instructions, addresses, and data for accessing the nonvolatile memory 1330 to the nonvolatile memory modules 1300 and 1305 through the RAM 1311, which is divided into bank groups or bank units .

Illustratively, the device controller 1310 can send and receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100, and receives a RAM command CMD_R via separate signal lines, The RAM address ADDR_R, and the clock CK.

SPD 1340 may be a programmable read only memory (EEPROM). SPD 1340 may include initial information or device information of non-volatile memory module 1300. Illustratively, SPD 1340 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 1300. When the computing system including the non-volatile memory module 1300 is booted, the processor 1100 of the computing system can read the SPD 1340 and recognize the non-volatile memory module 1300 based on the SPD 1340. The processor 1100 may use the nonvolatile memory module 1300 as a storage medium based on the SPD 1340.

Illustratively, the SPD 1340 may communicate with the processor 1100 via a Side-Band Communication Channel. The processor 1100 can exchange a side-band signal (SBS) with the SPD 1340 through an additional communication channel. By way of example, the SPD 1340 may communicate with the device controller 1310 via an additional communication channel. Illustratively, the supplemental communication channel may be a channel based on I2C communication. Illustratively, SPD 1340, device controller 1310, and processor 1100 may communicate with each other or exchange information based on I2C communications.

FIG. 17 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 15 by way of example. Illustratively, FIG. 17 is a block diagram of a non-volatile memory module 2300 in the form of a Registered DIMM (RDIMM). Illustratively, the non-volatile memory module 2300 shown in FIG. 17 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .

17, the non-volatile memory module 2300 includes a device controller 2310, a buffer memory 2320, a non-volatile memory device 2330, a serial presence detect chip (SPD) 2340, And a data buffer circuit 2350. The device controller 2310 includes a RAM 2311. Since the device controller 2310, the RAM 2311, the nonvolatile memory device 2330, and the SPD 2340 have been described with reference to FIGS. 1 and 16, a detailed description thereof will be omitted.

The data buffer circuit 2350 receives information or data from the processor 1100 (see FIG. 15) via the data signal DQ and the data strobe signal DQS and forwards the received information or data to the device controller 2350 . Or the data buffer circuit 2350 may receive information or data from the device controller 2310 and transfer the received information or data to the processor 1100 via the data signal DQ and the data strobe signal DQS.

Illustratively, the data buffer circuit 2350 may include a plurality of data buffers. Each of the plurality of data buffers can exchange data signals DQ and data strobe signals DQS with the processor 1100. Or each of the plurality of data buffers can exchange signals with the device controller 2310. [ Illustratively, each of the plurality of data buffers may operate under the control of a device controller 2310.

By way of example, the device controller 2310 may include a RAM 2311 of a structure optimized for an interface protocol with the processor 1100. That is, the processor 1100 can provide instructions, addresses, and data for accessing the non-volatile memory 2330 to the non-volatile memory module 2300 through the RAM 2311, which is divided into bank groups or bank units There will be.

18 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied. For the sake of brevity, a detailed description of the components described above is omitted. 18, a computing system 3000 includes a processor 3100, a non-volatile memory module 3200, a chipset 3400, a GPU 3500, an input / output device 3600, and a storage device 3700 . The processor 3100, the chipset 3400, the GPU 3500, the input / output device 3600, and the storage device 3700 are substantially the same as those of FIG. 21, and thus a detailed description thereof will be omitted.

The non-volatile memory module 3200 may be directly coupled to the processor 3100. For example, the non-volatile memory module 3200 may take the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

The non-volatile memory module 3200 may include a control circuit 3210, a non-volatile memory device 3220, and a ram device 3230. Unlike the non-volatile memory modules 1300 and 2300 of FIGS. 21-23, the processor 3100 can access the non-volatile memory device 3220 and the ram device 3230 of the non-volatile memory module 3200, have. As a more detailed example, the control circuit 3210 may store the received data in the non-volatile memory device 3220 or in the RAM device 3230 under the control of the processor 3100. Or control circuitry 3210 may transfer data stored in non-volatile memory device 3220 to processor 3100 or transmit data stored in ram device 3230 to processor 3100 under the control of processor 3100 have. That is, the processor 3100 can recognize the nonvolatile memory device 3220 and the RAM device 3230 included in the nonvolatile memory module 3200, respectively. The processor 3100 may store data in the non-volatile memory device 3220 of the non-volatile memory module 3200 or may read the stored data. Or processor 3100 may store data to or read data from RAM device 3230. [

The processor 3100 may use the non-volatile memory module 3200 of the non-volatile memory module 3200 as a storage medium of the computing system 3000, The RAM device 3230 of the computing system 3000 can be used as the main memory of the computing system 3000. That is, the processor 3100 can selectively access the nonvolatile memory device or the RAM device included in one memory module mounted on one DIMM socket, respectively.

Illustratively, processor 3100 may communicate with non-volatile memory module 3200 via a double data rate (DDR) interface 3300.

FIG. 19 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 18; FIG. Referring to Figure 25, a non-volatile memory module 3200 includes a control circuit 3210, a non-volatile memory device 3220, and a ram device 3220. By way of example, non-volatile memory device 3220 may comprise a plurality of non-volatile memories, and RAM device 3230 may comprise a plurality of DRAMs. By way of example, a plurality of non-volatile memories may be used by the processor 3100 as storage for the computing system 3000. Illustratively, each of the plurality of nonvolatile memories (NVMs) may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a ReRAM ), STT-MRAM (Spin-Torque Magnetic RAM), and the like.

The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000. By way of example, RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, MRAM, and the like.

The control circuit 3210 includes a device controller 3211 and an SPD 3212. The device controller 3211 can receive the command CMD, the address ADDR, and the clock CK from the processor 3100. [ The device controller 3211 responds to signals received from the processor 3100 to transfer data received via the data signal DQ and the data strobe signal DQS to the non-volatile memory device 3220 or to the ram device 3230. [ As shown in FIG. Or device controller 3211 responds to signals received from processor 3100 to transfer data stored in non-volatile memory device 3220 or RAM device 3230 to data signal DQ and data strobe signal DQS Lt; RTI ID = 0.0 > 3100 < / RTI >

Illustratively, the processor 3100 may optionally access the non-volatile memory device 3220 or the RAM device 3230 via a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 can selectively access the non-volatile memory device 3220 or the RAM device 3230 included in the non-volatile memory module 3200. [ Illustratively, the device controller 3211 stores the subdata in a RAM (not shown) in accordance with the operating method described in Figures 1-19, and stores the subdata in nonvolatile memory device 3220 Can be programmed.

20 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 18; Illustratively, the non-volatile memory module 4200 of FIG. 20 has the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

Referring to Figures 18 and 20, the non-volatile memory module 4200 includes a control circuit 4100, a non-volatile memory device 4220, and a ram device 4230. The control circuit 4210 includes a device controller 4211, an SPD 4212, and a data buffer circuit 4213.

The device controller 4211 receives the command CMD, the address ADDR, and the clock CK from the processor 3100. The device controller 4211 may control the non-volatile memory device 4220 or the RAM device 4230 in response to the received signals. The processor 3100 may selectively access each of the non-volatile memory device 4220 or the RAM device 4230. The device controller 4231 can control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100. [

The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 and provide the received signals to the device controller 4211 and the RAM device 4230. Or the data buffer circuit 4213 may provide the data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.

Illustratively, when the processor 3100 stores data in the nonvolatile memory device 4220, the data received via the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 can process the received data and provide it to the nonvolatile memory device 4220. [ Or the processor 3100 reads data stored in the nonvolatile memory device 4220, the data buffer circuit 4213 supplies the data provided from the device controller 4211 to the data signal DQ and the data strobe signal DQS, Lt; / RTI > to the processor 3100 via the network interface. Or the processor 3100 stores data in the RAM device 4230 the data received by the data buffer circuit 4213 is provided to the RAM device 4230 and the device controller 4231 receives the received command CMD, The address ADDR, and the clock CK to the RAM device 4230. Or when the processor 3100 reads data stored in the RAM device 4230, the device controller 4231 transfers the received command CMD, the address ADDR, and the clock CK to the RAM device 4230 , The RAM device 4230 provides the data to the data buffer circuit 4213 in response to the transmitted signals and the data buffer circuit 4213 supplies the data signal DQ and the data strobe signal DQS, And may provide data to the processor 3100. By way of example, device controller 3211 can accumulate subdata in a RAM (not shown) in accordance with the operating method described in FIG. 1 and program it into nonvolatile memory device 4220 in accordance with instructions of processor 3100 have. .

FIG. 21 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. 18; 21, the non-volatile memory module 5200 includes a control circuit 5210, a non-volatile memory device 5220, and a ram device 5230. The control circuit 5210 includes a device controller 5211 and an SPD 5212. The non-volatile memory module 5200 may operate similarly to the non-volatile memory module 4200 of Fig. However, the non-volatile memory module 5200 does not include the data buffer circuit 4213 unlike the non-volatile memory module 4200 of Fig. That is, the nonvolatile memory module 5200 in FIG. 27 directly supplies the data received from the processor 3100 via the data signal DQ and the data strobe signal DQS to the device controller 5211 or the RAM device 5230 can do. The data from the device controller 5211 of the nonvolatile memory module 5200 in FIG. 27 or the data from the RAM device 5230 are supplied to the processor 3100 (FIG. 27) via the data signal DQ and the data strobe signal DQS. ).

Illustratively, the non-volatile memory module 4200 of FIG. 20 is a memory module in the form of an LRDIMM (Load Reduced DIMM), and the non-volatile memory module 5200 of FIG. 21 may be a memory module in the form of a Registered DIMM .

Illustratively, the device controller 5211 will include a ram having the configuration and arrangement as described in FIGS. 1-12.

22 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 22, the server system 6000 may include a plurality of server racks 6100. Each of the plurality of server racks 6100 may include a plurality of non-volatile memory modules 6200. The plurality of non-volatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6100. For example, the plurality of non-volatile memory modules 6200 may take the form of a dual in-line memory module and may be mounted in a DIMM socket electrically coupled to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 6200 may be used as storage for the server system 6000.

The nonvolatile memory and / or device controller according to the present invention can be mounted using various types of packages. For example, the non-volatile memory and / or the device controller according to the present invention may be implemented as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) WSP), and the like.

The embodiments have been disclosed in the drawings and specification as described above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

At least one non-volatile memory; And
And a device controller including a RAM for storing control information for accessing the nonvolatile memory from the host and data to be transferred to the nonvolatile memory,
Wherein the RAM is disposed at an address unit specified in an interface protocol between the host and the device controller. The method according to claim 1,
The interface protocol may be one of DDR, DDR2, DDR3, DDR4, LPDDR, USB, MMC, embedded MMC, PCI (Peripheral Component Interconnection) , Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI ), And Nonvolatile Memory Express (NVMe). The method according to claim 1,
Wherein the address unit corresponds to a bank group unit and the ram is provided to each of the bank group units as one ESRAM device. The method according to claim 1,
Wherein the address unit corresponds to a bank unit and the ram is provided to each of the bank units as one ESRAM device. The method according to claim 1,
The device controller comprising:
A physical layer for containing the RAM and for providing physical interfacing with the host; And
And a DIMM controller for transferring the control information or the data stored in the RAM to the at least one nonvolatile memory device. 6. The method of claim 5,
Wherein the physical layer includes a RAM controller for controlling the RAM to store the control information or the data provided to the RAM with reference to a RAM address and a RAM command provided from the host,
Wherein the RAM controller provides the access status of the RAM to a specific address unit by the host to the DIMM controller. The method according to claim 6,
Wherein the DIMM controller refers to access state information of the host and holds a request for access to a bank group or a bank to which the host is accessing. 6. The method of claim 5,
Wherein the physical layer includes a plurality of data slices separated according to a data signal or a data strobe signal, and each of the plurality of data slices includes a serial / deserializer for serializing or parallelizing the data signals. The method according to claim 1,
Wherein the non-volatile memory device comprises a three-dimensional memory array. A plurality of nonvolatile memories;
At least one buffer memory; And
A physical layer for exchanging data with a host according to a first interface protocol;
And a DIMM controller for exchanging data between the physical layer and the nonvolatile memory and the buffer memory in a second interface protocol manner,
Wherein the physical layer includes a random access memory for storing a first instruction, a first address, and first data for accessing the nonvolatile memory,
Wherein the random access memory is arranged in a bank group or a bank which is an address division unit of the first interface protocol.

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