KR20170007803A - Mixer and method for generating an output signal from an input signal - Google Patents

Abstract

The present invention relates to a mixer (100) for generating an analog output signal X _OUT from an analog input signal X _IN using a mixing signal having a mixing frequency f _MIX , wherein the mixer (100) comprises a sampled analog input signals X _iN [k] to the sampled analog input signal based on the sampling of the analog input signal X _iN at a plurality of discrete time k with a sampling frequency f _S to obtain, and a plurality of scaling factors to a [k] X _iN [ k], and the scaling coefficient A [k] is a time discrete expression of the mixed signal. The scaling factor A [k] is configured to generate an analog output signal X _OUT having a continuous signal value.

Description

TECHNICAL FIELD [0001] The present invention relates to a mixer and a method for generating an output signal from an input signal.

The present invention relates to a mixer for generating an output signal from an input signal using a mixed signal, as well as a method for generating an output signal from an input signal.

Mobile wireless communication devices, such as cellular telephones, smart phones, personal digital assistants (PDAs), etc., may be configured to communicate with other devices over a number of different frequencies. As such, a mobile wireless communications device needs to include a receiver capable of receiving communication signals at a number of different frequencies. In some situations, it is desirable to receive and demodulate two or more communication signals in different frequency bands using a technique called multi-carrier aggregation. In this way, greater bandwidth is available, which allows more information to be sent per second to provide a more enjoyable user experience. To this end, the receiver often includes a mixer for performing frequency up-conversion or frequency down-conversion of the received communication signal using a sinusoidal mixed signal of the desired frequency. Typically, such a mixer includes a PLL for all frequency bands, but significantly increases area and power consumption. A similar problem occurs in frequency division duplexing (FDD) where mobile wireless communication devices receive and transmit at the same time but at different frequencies, resulting in the need for two PLLs.

Thus, there is a need for improved mixers.

It is an object of the present invention to provide an improved mixer.

This object is achieved by the claims of the independent claims. Additional implementations are provided in the dependent claims, the description and the drawings.

According to a first aspect of the present invention there is provided a mixer for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having a mixing frequency f _MIX , analog input signals X _iN [k] to the sampled analog input signal based on the sampling of the analog input signal X _iN at a plurality of discrete time k with a sampling frequency f _S to obtain, and a plurality of scaling factors to a [k] X _iN [ by scaling the k] comprises a scaler that is configured to produce an analog output signal X _OUT having consecutive signal values, the scaling factor a [k] are the discrete-time representation of the mixed signal.

The mixer produces an analog output signal from the analog input signal by scaling, i.e., multiplying the time-sampled analog input signal by a plurality of scaling factors A [k]. The scaling factor A [k] may be provided by the scaler based on the control code n stored in the scaler. Thus, an improved mixer is provided.

According to a first embodiment of the first aspect of the present invention, the sampling frequency f _S is at least twice the mixing frequency f _MIX of the mixed signal.

According to sampling theory, the sampling frequency f _S is preferably at least twice as large as the mixing frequency f _MIX so that the mixed signal can be expressed without aliasing effect. This facilitates the use of a mixer.

According to such a second embodiment of the first aspect of the invention or a first embodiment thereof, the mixed signal is a sinusoidal mixed signal.

The scaling factor A [k] is, for example, T _S = 1 / f _S is the sampling period and θ is an arbitrary phase angle,

. ≪ / RTI >

According to such a third or first or second embodiment of the first aspect of the present invention, the ratio of the mixing frequency f _MIX to the sampling frequency f _S is given by A / B, where A and B are integers .

For such a mixer the mixed signal will be periodic when sampled at f _S and may be stored in a finite-size periodic shift register or look-up table (LUT) in the memory of the scaler.

According to an advantageous implementation of the third embodiment of the first aspect of the present invention, the integers A and B are the number

Is selected to be an integer multiple of 4, and gcd (A, B) represents the greatest common divisor of A and B.

According to a fourth aspect of the first aspect of the first aspect of the present invention, or one of the first to third aspects, the scaler is adapted to convert the local oscillator signal f _LO of the local oscillator signal provided by the local oscillator to a sampling frequency f _S a is configured to derive a sampling frequency f _S is an integer times the frequency f _LO of the local oscillator, in particular the same as four times the local oscillator frequency f _LO.

In such a mixer, a system including a mixer, that the mixer is in a system having a transmitter and a receiver which is part of the receiver and the transmitter includes a local oscillator for providing a local oscillator signal, the local oscillator (LO) signal already available f _{LO Lt;} RTI ID = 0.0 > f _MIX. &_Lt; / RTI >

According to the fifth embodiment or the first to fourth embodiments of the first aspect of the present invention, the analog input signal X _IN is an analog voltage signal V _IN or an analog current signal I _IN , X _OUT is the analog voltage signal V _OUT or the analog current signal I _OUT .

Anti-aliasing filtering is provided in favor of the current input signal.

According to a sixth or first to fifth embodiments of the first aspect of the present invention, the mixer includes an input terminal and an output terminal, and the scaler includes a plurality of Wherein each unit cell comprises a unit cell capacitor, the unit cell capacitor of the ith unit cell has a capacitance C _ui , the sum of the capacitances of the unit cells defines a total capacitance C _s , The unit cell includes a charge transfer switch for connecting the unit cell capacitor of each unit cell to the output terminal, and the scaler scales the sampled analog input signal X _IN [k] based on the plurality of scaling coefficients A [k] To control the charge transfer switches of each unit cell.

This implementation provides an efficient mixer that uses unit cells with unit capacitors where given k can contribute differently to the scaling factor A [k].

According to a seventh implementation of the sixth aspect of the first aspect of the present invention, the plurality of unit cells comprises N unit cells, and the unit cell capacitors have the same capacitance C _ui = C _u and C _u is a constant capacitance, the total capacitance C _s is given by C _s = NC _u .

This advantageous implementation of the mixer having the same unit cell with the same capacitance provides optimal matching characteristics.

According to an eighth embodiment of the sixth aspect of the first aspect of the present invention, the plurality of unit cells includes b unit cells, and the unit cell capacitors of the i-th unit cell have a capacitance C _ui = 2 ^{i - 1} C _u , C _u is a constant capacitance, and the total capacitance C _s is given by C _s = (2 ^b -1) C _u , where i can range from 1 to b.

This advantageous implementation of the mixer with unit cells increasing by a factor of 2 is smaller in terms of layout and therefore produces better parasitic components.

According to a ninth embodiment of the sixth aspect of the first aspect of the present invention, the plurality of unit cells includes (b + K) unit cells, and the i-th unit cell among the b unit cells of the plurality of unit cells The unit cell capacitors of the plurality of unit cells may have a capacitance C _ui = 2 ^{i- 1} C _u , i may range from 1 to b, C _u is a constant capacitance, _{Has the} same capacitance C _ui = 2 ^b C _u and is given by the total capacitance C _s = (2 ^b K + 2 ^b -1) C _u .

This advantageous implementation of a mixer with a combination of binary and unary cells provides an optimal trade-off between parasitic components and matching characteristics.

According to a tenth implementation of one of the sixth to ninth aspects of the first aspect of the present invention, the input terminal includes a positive input terminal and a negative input terminal for differentially implementing the mixer, Wherein each of the unit cells of the plurality of unit cells includes a plurality of inversion switches, and the scaler is a unit cell capacitor of one unit cell of the plurality of unit cells And is configured to control the plurality of inverting switches so that each side can be connected to a positive output terminal and / or a negative output terminal.

This advantageous differential implementation of the mixer allows the negative scaling factor A [k] to be realized.

According to an eleventh implementation of one of the sixth to tenth implementations of the first aspect of the present invention, the scaler comprises a memory, wherein the memory is configured to store a plurality of control codes n, n determines the total capacitance C _s fraction α [k] connected to an output terminal of the mixer.

In such a mixer, the control code n may determine the fraction of the total capacitance C _s contributing to the scaling factor A [k].

According to a twelfth implementation of one of the sixth to eleventh aspects of the first aspect of the present invention, the scaler comprises a ^2M block of unit cells, M is an integer, and each block of unit cells Are configured to sample the sampled analog input signal _XIN [k] in different phases, each block using a possible different set of scaling factors A [k].

This embodiment is advantageous for current transistor technology, for example, by using a quadrature mixer with four unit cell blocks. In this way, the sampling rate required in each block is only f _S / 2 ^M , allowing a higher combined sampling rate f _S.

According to a thirteenth implementation of one of the sixth to twelfth implementations of the first aspect of the present invention, each unit cell of the scaler further comprises a reset switch for discharging the unit cell capacitor, So that the reset switch of the unit cell of the unit cell is opened and closed.

According to a fourteenth embodiment of one of the sixth to thirteenth aspects of the first aspect of the present invention, the scaler is configured to sample the analog input signal X _IN by the first clock signal < RTI ID = _0.0 > And to control the input control switch.

According to a fifteenth embodiment of one of the sixth to fourteenth aspects of the first aspect of the present invention, the scaler further comprises a transfer capacitor having a capacitance C _t , And is connected to the connection between the switch and the output terminal of the mixer.

According to a sixteenth embodiment of one of the sixth to fifteenth aspects of the first aspect of the present invention, each unit cell of the scaler further comprises a dummy capacitor having a capacitance C _ui , The dummy capacitor is connected to the connection between the charge transfer switch of each unit cell and the output terminal of the mixer through the dummy control switch and the scaler closes the charge transfer switch of a part of the plurality of unit cells and opens the dummy control switch, The charge transfer switch of the remaining unit cells of the plurality of unit cells is opened and the dummy control switch is closed based on the control code n stored in the memory.

According to a second aspect of the present invention, the present invention relates to a method of generating an analogue output signal X _OUT from an analogue input signal X _IN using a mixed signal having a mixing frequency f _MIX , on the basis of the analog input signal X _iN [k] a plurality of sampling an analog input signal X _iN at discrete time k, a plurality of scaled coefficients to a sampling frequency f _S to obtain a [k] samples having the sampled And generating an analog output signal X _OUT having a continuous signal value by scaling the analog input signal X _IN [k], wherein the scaling factor A [k] is a time-discrete representation of the periodic mixed signal.

The method according to the second aspect of the present invention can be carried out by the mixer according to the first aspect of the present invention. A further feature of the method according to the second aspect of the invention results directly from the functionality of the mixer according to the first aspect of the invention.

According to a third aspect, the present invention relates to a computer program comprising program code for performing the method according to the second aspect of the present invention when executed on a computer.

The present invention may be implemented in hardware and / or software.

Embodiments of the present invention will be described with reference to the following drawings.
1 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
2 shows a schematic diagram of a method for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
3 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
4 shows a schematic diagram of a plurality of clock signals for driving a mixer to produce an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
5 shows a schematic diagram of a quadrature mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
FIG. 6 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
7 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
FIG. 8 shows a schematic diagram of a quadrature mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
Figures 9a-c schematically illustrate the operational principles implemented in the mixer embodiments shown in Figures 6, 7 and 8 by showing selected components during different clock phases.
10A to 10D show a schematic view showing the operation principle of the mixer according to the embodiment.
11 (a) to 11 (c) show a schematic view showing the operation principle of the mixer according to the embodiment.
12 shows a schematic diagram of a quadrature mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
13 shows a schematic diagram of a quadrature mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
14 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
15 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
Figure 16 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
17 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
18 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
19 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
20 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.
Figure 21 shows a schematic diagram of a mixer for generating an analog output signal from an analog input signal using a mixing signal having a mixing frequency f _MIX according to an embodiment.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and illustrate, by way of example, specific embodiments in which the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It should be understood that the disclosure relating to the described method is also valid for a corresponding device or system configured to perform the method and vice versa. For example, if a particular method step is described, the corresponding device may include a unit for performing the described method steps, even if such unit is not explicitly described or illustrated in the figures. It is also to be understood that, unless specifically stated otherwise, the features of the various exemplary aspects described herein may be combined with one another.

1 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX , according to an embodiment. Mixer 100, the sampled analog input has a continuous signal value signals X _IN [k] the analog input signal at a plurality of discrete time k in the input terminal 120 of the mixer 100 to obtain a sampling frequency f _S Sampling the X _IN and scaling the sampled analog input signal X _IN [k] based on the plurality of scaling coefficients A [k], i.e. X _OUT = A [k] X _IN [k] And a scaler 110 configured to generate an analog output signal X _OUT at an output terminal 130 of the mixer 100 having the output signal X _OUT . The scaling factor A [k] is a time discrete representation of the mixed signal.

In one embodiment, the mixing signal used by mixer 100 may be, for example,

T _S = 1 / f _S is the sampling period and θ is an arbitrary phase angle,

Is a sinusoidal mixed signal having a scaling factor A [k] given by.

In one embodiment, the scaler 110 includes a plurality of unit cells 140 connected in parallel to the input terminal 120. Each unit cell 140 includes a unit cell capacitor C _ui , the unit cell capacitor of the ith unit cell has a capacitance C _ui , and the sum of the capacitances of the unit cells defines the total capacitance C _s . Each unit cell 140 includes a charge transfer switch that connects the unit cell capacitor C _ui of each unit cell 140 to the output terminal 130. The scaler 110 is configured to control the charge transfer switch of each unit cell 140 to scale the sampled analog input signal X _IN [k] based on the plurality of scaling coefficients A [k].

In one embodiment, the plurality of unit cells 140 comprise N unit cells, and the unit cell capacitors C _ui comprise the same capacitances C _ui = C _u , C _u is a constant capacitance, and the total capacitance C _s is given by C _s = NC _u .

In one embodiment, the plurality of unit cells 140 comprise b unit cells, the unit cell capacitors of the ith unit cell have a capacitance C _ui = 2 ^{i- 1} C _u , C _u a constant capacitance, The total capacitance C _s is given by C _s = (2 ^b -1) C _u , where i can range from 1 to b.

In one embodiment, the plurality of unit cells 140 include (b + K) unit cells, and the unit cell capacitors of the i-th unit cells among the b unit cells of the plurality of unit cells 140 are capacitances C _ui = 2 ^{i- 1} C _u where i is in the range of 1 to b and C _u is a constant capacitance and the unit cell capacitors of the K remaining unit cells of the plurality of unit cells 140 have the same capacitance C _ui = 2 ^b C _{u and is given} by the total capacitance C _s = (2 ^b K + 2 ^b -1) C _u .

2 shows a schematic diagram of a method 200 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having a mixing frequency f _MIX according to an embodiment. The method 200 includes a step 201 of sampling an analog input signal X _IN at a plurality of discrete time points k at a sampling frequency f _S to obtain a sampled analog input signal X _IN [k] having successive signal values, And a step 203 of generating an analog output signal X _OUT having a continuous signal value by scaling the sampled analog input signal X _IN [k] based on the scaling coefficients A [k]. The scaling factor A [k] is a time discrete representation of the periodic mixed signal.

In the following, further implementations and embodiments of the mixer 100 and method 200 are described.

FIG. 3 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX , in accordance with one embodiment. 3, only one half of the differential mixer 100 is shown in FIG. 3 for the sake of simplicity and the analog input signal X _{IN has} a positive input signal X _{IN , p} and produces a positive output signal X _{OUT , p} of the analog output signal X _OUT . The mixer 100 samples the analog input signal at a plurality of discrete time points k from the input terminal 120 of the mixer 100 to a sampling frequency f _S to obtain a sampled analog input signal having a continuous signal value, By scaling the sampled analog input signal based on the scaling factor A [k], i.e. X _OUT = A [k] X _IN [k] And a scaler 110 configured to generate an output signal. The scaling factor A [k] is a time discrete representation of the mixed signal.

In one embodiment, the mixer 100 shown in Fig. ₃ is configured to operate using four clock signals phi ₀ through phi ₃ . These clock signals can control the different switches of the mixer 100, which will be described in further detail below. In one embodiment, the clock signals phi ₀ through phi ₃ have a frequency corresponding to the frequency f _LO of the local oscillator LO and have a phase difference of 90 degrees with a duty cycle of 25%. In one embodiment, the clock signals phi ₀ through phi ₃ have the form shown in Fig.

Referring again to the mixer embodiment shown in FIG. 3, the scaler 110 includes four blocks 350 of N unit cells 140. Each unit cell 140 includes a unit cell capacitor C _u having a capacitance C _u . The sum of the capacitances C _u of the unit cell capacitors C _u of the N unit cells 140 defines the total or total capacitance C _s as C _S = N C _u .

Each unit cell 140 further includes an input control switch referred to as "phi ₀ " in Fig. 3, indicating that the input control switch of each unit cell 140 is controlled by the clock signal phi ₀ . When the clock signal? ₀ is high, the input control switch of each unit cell 140 is switched to the unit cell capacitor C of all the unit cells 140 in a state where the analog input signal X _{IN , p} is supplied to the input terminal 120 by connecting a _u and the node "nsample_p", all the unit cells 140 is the analog input signal X _iN, samples the _p and, as a result, all the unit cell capacitor C _u has the same voltage at the end of the high-phase φ ₀ V _iN And V _IN is the voltage at input terminal 120 (for ground). At this point, the total charge of all unit cell capacitors C _u is given as Q _s = C _s V _IN .

When the clock signal φ ₁ is high, the total number N of unit capacitor portion of the C _u is transmitted through the charge transfer switches referenced in Figure 3 is connected to node "nshare_p" a "φ ₁ and control and the sign""capacitor C _t , and the charge transfer switch of each unit cell 140 is controlled by the clock signal? ₁ by the digital control code n and the inverse of the sign bit, and "& represents a logical AND operation. In the mixer embodiment shown in FIG. 3, the sign bit is assumed to be 0 for positive numbers and 1 for negative numbers.

In one embodiment, the digital control code n determines how many N unit cells 140 are connected to the transfer capacitors C _t while the clock signal? ₁ is high. During this phase, the total charge Q _s of the fraction α = n / N is redistributed over the total capacitance _{C t + n · C u =} C t + α · C s. This means that the voltage across the transfer capacitor C _t (as well as all unit cells 140 connected to the transfer capacitors C _t )

.

The mixer 100 shown in FIG. 3 is configured to change the control code n every time step, i.e., every sampled value of V _IN . In other words, the control code n is a function of the discrete time variable k, n [k]. By using different digital control codes n for different time steps, the mixer 100 shown in FIG. 3 can be used to calculate the scaling factor (or voltage gain)

.

3 can be implemented differentially, the negative voltage gain can be obtained by adding the unit cell capacitors C _u on the positive side of the mixer 100 to the transfer capacitors C on the negative side of the mixer 100 _t , and vice versa in the same manner. To this end, the mixer each of the unit cells 140, each of the unit cell 140 including additional switches referenced in FIG connected to the node "nshare_n" 3 to "φ ₁ and control and the sign" of 100 An additional switch is controlled by the digital control code n and the sign bit by the clock signal? ₁ .

In one embodiment, the mixer 100 shown in FIG. 3 remains idle during the high phase of the clock signal? ₂ because essentially only three different clock signal phases are needed for the mixer 100 shown in FIG. It is possible to have. This embodiment may be advantageous when the clock signal φ ₁ to be delayed by the gated (gating) required for the clock signal, which may cause overlap of the clock signals φ ₁ and φ ₂ clock signal.

During the high phase of the clock signal? ₃ , the voltage of all the unit cells 140 is reset via the reset switch to the common mode DC voltage V _CM of the input and output signals, and the reset switch, in the embodiment shown in FIG. 3, Is referred to as "? ₃ " to indicate that the reset switch of each unit cell 140 in Fig. 3 is controlled by the clock signal? ₃ . Having a reset switch is not necessary in the case of an ideal voltage input signal, but is advantageous for a current input signal, as will be described in further detail below. In addition, when the mixer 100 shown in FIG. 3 is driven by a voltage input signal having an output impedance other than zero, the memory effect is such that some of the unit cells 140 remain fully charged from the previous sample The other unit cell may already be caused by the fact that it has already delivered some of its charge to the transfer capacitor C _t .

As will be appreciated by one of ordinary skill in the art, the portions of mixer 100 described so far can handle one input signal sample per LO cycle. In one embodiment, (scaler (110 or more mixers 100)), the mixer 100 shown in Figure 3, the effective sampling frequency of four times the LO frequency f _LO f _S, that is achieve f _S = 4f _LO to, comprises four blocks 350 of the unit cell 140, each block 350 is passed capacitor input signals of different phases during comprises a C _t and the clock signals φ ₀ through φ ₃ X _{iN, p} . < / RTI > In other words, each block 350 of the unit cell 140 operates at a phase difference of 90 degrees at the LO frequency f _LO providing an effective sampling rate f _S of 4f _LO .

A single hold capacitor C _h is provided at the output terminal 130 to recombine a sample of the input signal X _{IN , p} taken by the four blocks 350 of the mixer 100 shown in Figure 3 back into a single analog signal do. The hold capacitor C _h is connected to all four blocks 350 of the mixer 100 through four hold capacitor switches and thus redistributes the charge to one of the phases during each clock signal phase. The hold capacitor switch of block 350 is referred to as "? ₃ " in Fig. ₃ , indicating that the hold capacitor switch of each block 350 is controlled by the clock signal? ₃ . It will be appreciated by those of ordinary skill in the art that, for this reason, there is no clock signal phase while hold capacitor C _h can be reset.

The four transfer capacitors C _t of the four blocks 350 may be represented as implementing an infinite impulse response (IIR) low pass filter with a hold capacitor C _h , which transfer function

, Where the z conversion should be taken at the sampling rate f _S = 4f _LO . The pole of this filter is

.

In an embodiment in which the mixer 100 is implemented as a component of the receiver, the IIR low-pass filter may be used as the first filtering stage in the receiver lineup. In one embodiment, the hold capacitor C _h may be provided by a tunable capacitor as shown in FIG. 3 to tune the filter pole according to the communication band to be received.

3, each of the four blocks 350 of the mixer 100 uses a control code n to scale the input signal X _{IN , p} sampled at an effective sampling rate f _S = 4f _LO . Since each block 350 scales only every fourth sample of the input signal, control code n must be present in the block with frequency f _LO . When considered together as one signal sampled at f _S = 4f _LO , the control code n of the four blocks 350 provides a mixed signal at frequency f _MIX . If the ratio f _MIX / f _S is a rational number A / B, then only a limited set of control code samples that can be repeated forever is needed, as will be described in further detail below. For cellular bands, the number of control code samples required is generally less than 30, so that samples can be easily stored in the local table (LUT) or shift register of mixer 100.

5 illustrates a schematic diagram of a mixer 500 for generating an analog output signal from an analog input signal using a mixed signal having an adjustable mixing frequency f _MIX , in accordance with one embodiment. In the embodiment of FIG. 5, the mixer 500 is implemented in the form of a quadrature mixer by connecting two of the mixers 100 described above in parallel. Each mixer 100 of quadrature mixer 500 is controlled by a different control code set n that defines a respective mixed signal with a phase difference of 90 degrees.

5 and the following figures include some of the elements described in detail in the context of FIGS. 1 and 4, they are generally meant to have the same meaning as those of the above detailed embodiments of FIGS. 1 and 4 Only when it can not be easily derived from the explanation will be described below.

The embodiment of the mixer 100 shown in Figures 3 and 5 provides a mixer 100 with a uni-mixer implementation, i. E. At least one block 350 of the same unit cell 140 with the same capacitance C _u . This solution includes relatively few layout operations and is most suitable for matching between unit cells 140. [

As already mentioned above, the mixer 100 may be provided in the form of a binary mixer implementation in which the capacitance C _ui of the unit cell capacitor of the i th unit cell 140 is given by the capacitance C _ui = 2 ^{i - 1} C _u , and C _u means a constant capacitance. In the case of a binary implementation of the mixer 100, the total capacitance C _s is given by C _s = (2 ^b -1) C _u , where b is the total number of binary unit cells 140.

By adopting a binary implementation of the mixer, most significant bits (MSBs) can be implemented with much less area and parasitics, which can improve power consumption and input capacitance while sacrificing degraded matching characteristics.

As described above, the mixer 100 may be implemented as a combination of unary and binary implementations having (b + K) unit cells 140, wherein one of the b unit cells of the (b + K) the unit cell capacitors of the ith unit cell have a capacitance C _ui = 2 ^{i- 1} C _u , C _u has a constant capacitance, and the unit cell capacitors of the remaining K unit cells of the (b + K) The capacitance C _ui = 2 ^b C _u , and the total capacitance C _s is given by C _s = (2 ^b K + 2 ^b -1) C _u . The combination of binary and uni-unit cells provides an optimal trade-off between parasitic components and matching characteristics.

In one embodiment, mixer 100 is to process analog input signals X _IN analog voltage signal V _IN, or the analog current signal I _IN, or the analog output signal an analog voltage signal as X _OUT V _OUT or the analog current signal I _OUT as .

In the embodiment in which the analog input signal X _IN is the analog voltage signal V _IN , the total capacitance C _S of the mixer embodiment 100 shown in FIGS. 3 and 5 is maintained until the stuck voltage is equal to the analog voltage signal V _IN And thus the mixer embodiment 100 shown in Figures 3 and 5 will sample the input signal. In this case, the mixer embodiment 100 shown in Figures 3 and 5 is sensitive to variations in the time at which the input control switch controlled by the clock signal < RTI ID = _0.0 > φ ₀ is open, which determines when the input signal is sampled to be. In addition, the resistance of the input control switch of the unit cell 140 of the mixer embodiment shown in FIG. 3 (when conducting) is sufficient to allow good stabilization, i.e. C _s to be charged to the correct voltage for the time the input control switch is closed It should be low enough to do.

In an embodiment where the analog input signal X _IN is an analog current signal I _IN , the current on C _s will be integrated for the time the input control switch is closed. When the input control switch is opened from "high" to "low" by the clock signal φ ₀ , the voltage on C _s will represent the integral of the analog current signal I _IN during this period. With this embodiment, an integral and dump low pass filter is realized, which provides favorable anti-aliasing filtering. In this case, the mixer embodiment 100 shown in FIGS. 3 and 5 is sensitive to changes in both the open and closed times of the input control switch, the difference between these times being the period during which the input signal is integrated And the times also determine when the input signal is correctly sampled.

Capacitor C _s, C _t and / or C _h respectively, it can be implemented by any one of a differential capacitor having a capacitance of one end (single-ended) or capacitor half of the capacitor one end. The use of differential capacitors has the following advantages: The differential capacitor can replace two single-ended capacitors, so a chip area that is four times smaller is used. Implementing the capacitor C _s or C _t as a differential capacitor results in a strong common-mode rejection. The common mode signal can only be passed by sampling against the parasitic capacitance to the substrate or other net (net). The use of a single-ended capacitor has the following advantages. For a single-ended capacitor, the standard deviation on the effective differential capacitance will be doubled because four times as much physical capacitance is used. Implementing the hold capacitor C _h as a single end capacitor has the effect that the IIR filter will also filter out the high frequency common mode signal.

In the embodiment shown in FIG. 5, the hold capacitor C _h is implemented differentially with respect to the save area. The total capacitance C _s of the unit cell 140 or rather the unit capacitor C _u is implemented as a single end capacitor for better matching between unit cells. Since the area of the unit cell 140, a capacitor unit cell C _u is determined by the switch and routing overhead, the unit cell 140 as well as determined by, and its influence area is generally less large.

As can be seen from the above equation (2), in the mixer embodiments shown in Figs. 3 and 5, the maximum value of the scaling coefficient or voltage gain A [k] is achieved when? = 1,

.

The total capacitance of the selected size of the capacitances of the transfer capacitors C _t to C _s is a trade-off between quantization noyijeugwa voltage loss. This can be seen as follows.

When C _t is infinite, the term α · C _s in the denominator of Equation 2 becomes negligible and the scaling factor A [k]

.

This means that the scaling factor A [k] is directly proportional to?. This is useful because the quantization levels for a are arranged at equidistant intervals, and so it will also be applied to the scaling factor A [k]. However, as C _t increases infinitely, the maximum value of the scaling factor A _max will be zero.

As C _t decreases, the α · C _s term of the denominator becomes dominant and A _max will increase. At the same time, the dependence of the scaling factor A [k] on a will be progressively non-linear, with more quantization levels closer to 1 and closer to zero. This is most likely to result in an increase in quantization noise.

If C _t decreases to 0, it can be ignored in the denominator

.

This is the largest scaling factor that can be achieved with a passive structure, but is now independent of α. This means that all the quantization levels for A [k] are consistent and can no longer achieve mixing.

Optimal values for C _s and C _t depend on the given environment of the application in which the mixer 100, such as noise, quantization noise, voltage gain, as well as area and power consumption, will be used. In one embodiment, the capacitances C _s and C _t are similar in magnitude. In the case of C _s = C _t , the dependence of A [k] on α is not too far from a straight line and A _max is equal to 0.5.

FIG. 6 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX , in accordance with one embodiment. 6, the mixer 100 is implemented as differential and for simplicity only one half of the differential mixer 100 is shown in FIG. 6 and the positive input signal X _IN of the analog input signal X _{IN , p} and produces a positive output signal X _{OUT , p} of the analog output signal X _OUT . The mixer 100 samples the analog input signal at a plurality of discrete time points k from the input terminal 120 of the mixer 100 to a sampling frequency f _S to obtain a sampled analog input signal having a continuous signal value, By scaling the sampled analog input signal based on the scaling factor A [k], i.e. X _OUT = A [k] X _IN [k] And a scaler 110 configured to generate an output signal. The scaling factor A [k] is a time discrete representation of the mixed signal.

In general, the main difference between the mixer embodiment shown in FIG. 6 and the mixer embodiment shown in FIG. 3, which will be described in more detail hereinafter, is that the transfer capacitors C _t are removed in the mixer embodiment shown in FIG. 6, The unit cell 140 of the scaler 110 of the mixer 100 shown in FIG. 6 includes a dummy unit capacitor C _d in addition to the unit capacitor C _u . In one embodiment, the capacitance of the dummy unit capacitor C _d is essentially equal to the capacitance of the unit cell capacitor C _u (i.e., C _d = C _u ).

To illustrate the operation of the mixer embodiment 100 shown in FIG. 6, it will be helpful to first describe a slightly modified embodiment of the mixer 100 shown in FIG. The mixer embodiment shown in FIG. 7 differs from the mixer embodiment shown in FIG. 6 in that the mixer embodiment shown in FIG. 7 includes additional output switches at the output of each block 750 of the scaler 110, Do. An additional output switch at the output of each block 750 of scaler 110 is referred to as "phi _1b " in FIG. 7 so that the additional output switch of each block 750 of scaler 110 is coupled to another clock signal & _1b . ≪ / RTI > In one embodiment, the clock signal φ _1b the clock signal φ ₁ at a later point in time than the transition from "low" to "high", but returns to the "low" at the same time as the clock signal φ _1. For example, the "high" phase of the clock signal? _1b may be half of the "high" phase of the clock signal? ₁ . During the "high" phase of the clock signal φ ₀ , all of the unit cells 140 of the mixer embodiment 100 shown in FIG. 7 sample the analog input signal X _{IN , p} on its unit capacitor C _u , _The total charge on the voltages V _IN and C _s on _u is Q _s = C _s · V _IN . Dummy capacitor C _d has no charge since it is referenced as "? ₃ " in Fig. 7 and reset during the previous "high" phase of clock signal? ₃ through the reset switch connected to each dummy capacitor C _d .

During the "high" phase of the clock signal? ₁ , only n of the N unit cells 140 (defined as n by the digital control code) couple that unit capacitor C _u to the node Or a node referred to as "nshare_n" in Fig. 7 when the sign is negative) through respective switches controlled by the clock signal? ₁ , the digital control code n and the inverse of the sign bit. The remaining (Nn) unit cells 140 connect the "ndummy_p" node to the "nshare_p" node. Thus, the charge α · Q _s (α = n / N as before) is redistributed over the total capacitance n · C _u + (Nn) · C _d = C _s . The voltage

And thus the scaling factor A [k] (or voltage gain), which is directly proportional to a,

. In the embodiment shown in Figs. 6 and 7, the maximum value A _max of the scaling factor is now equal to 1, but it is clear that the dependence of A [k] on? Is always linear.

When the charge is redistributed, the clock signal? _1b rises and an additional output switch at the output of each block 750 of the scaler 110, referred to as? _1b in FIG. 7, connects the "nshare_p" node to the output terminal 130, but the switch controlled by the clock signal? ₁ is still closed. In this manner, the total capacitance C _s carrying charge a Q _s is connected to a hold capacitor C _h that carries charge dependent on the previous sample from another block 750. During the "high" phase of the clock signal? ₃ , the unit capacitors C _u and dummy unit capacitors C _d are reset.

As in the case of the mixer embodiment 100 shown in FIG. 3, the arrangement described above provides an IIR low-pass filter with a DC gain of 1, with C _t replaced by C _s in the transfer function:

The pole,

.

Since the sum of all the unit capacitors C _u and dummy unit capacitors C _d connected to the hold capacitor C _h is always equal to C _s , the pole frequency does not depend on?. The input capacitance of the mixer 100 is always equal to C _s, and thus is independent of?. This is useful for preventing non-linearity when the driving signal source has an output impedance other than zero.

Referring back to the mixer embodiment 100 shown in FIG. 6, it can be readily seen that the operation of the mixer embodiment 100 shown in FIG. 7 does not change if the clocks? ₁ and? _1b rise simultaneously . This is because the charge existing in the n unit capacitors C _u and the hold capacitors C _h is redistributed over the capacitance n C _u + (N n) C _d + C _h = C _s + C _h . For the same clock signals? ₁ and? _1b , additional output switches at the output of each block 750 of the scaler 110 referenced as "? _1b " in FIG. 7 can be eliminated. This leads to the mixer embodiment 100 shown in FIG. 6, which is functionally equivalent to the mixer embodiment of FIG. 7, when an ideal switch is used. However, the use of a physical switch, together the mixer embodiment 100 shown in Figure 6. Preferably, this second clock in place of the shorter "high" phase of the clock signal φ _1b does not have the switches in series signals φ ₁ Because it allows redistribution of charge during the complete "high" phase.

FIG. 8 shows a schematic diagram of a mixer 800 for generating an analog output signal from an analog input signal using a mixed signal having an adjustable mixing frequency f _MIX , in accordance with one embodiment. In the embodiment of FIG. 8, the mixer 800 is implemented in the form of a quadrature mixer by connecting two of the mixer embodiments 100 shown in FIG. 6 in parallel. For simplicity, an additional switch for implementing negative sign scaling coefficients is not shown in FIG. Each mixer 100 of quadrature mixer 800 is controlled by a different control code set n that defines a respective mixed signal with a phase difference of 90 degrees.

Figures 9a-c schematically illustrate the operating principle implemented in the mixer embodiment shown in Figures 6, 7 and 8 by showing selected components. For purposes of illustration, dummy unit capacitors C _d are separated into individual dummy unit cells. Each box in Figs. 9A to 9C represents a variable number of unit cells or dummy unit cells depending on?.

Figure 9a shows the "high" phase of the clock signal φ ₀ , where the input is sampled for the total capacitance C _s . Figure 9 b is a (1-α) · a dummy unit cell having a capacitance of C _s and shows the "high" phase of the hold capacitor C _h a clock signal φ ₁ is the charge is delivered to. The dummy unit cell ensures that the pole of the IIR filter stays at the same frequency.

9C shows the "high" phase of the clock signal? ₃ at which all the capacitors are reset.

A further variation of the mixer embodiment 100 shown in FIG. 6 will now be described. Although specific implementations are different, they have the same scaling factor A [k] = alpha and provide the same IIR filter as the mixer embodiment 100 shown in FIG. Although not shown in the drawings for the sake of simplicity, all implementations may have two mixer channels and four mixer blocks per channel.

Figures 10a-d schematically illustrate the operational principle implemented in the further mixer embodiment 100. [ As in the case of Figures 9a-c, only the selected components of the further mixer embodiment 100 are shown in Figures 10a-d for illustration. Each box in Figs. 10A to 10D represents a variable number of unit cells or dummy unit cells depending on?.

The mixer 100 shown in Figs. 10A to 10D uses all four clock signals? ₀ ,? ₁ ,? ₂ and? ₃ without requiring any dummy capacitors.

During the "high" phase of the clock signal φ ₀ , the input is sampled for the unit capacitors C _u , ie, the total capacitances C _s of all N unit cells 140, so that the voltage V _IN and the charge Q _{s of} each of the unit capacitors C _u = C _{s ·} V _IN .

During the "high" phase of the clock signal? ₁ , (Nn) of these unit cells 140 are reset while the unit capacitors C _u of the other unit cells 140 remain at the voltage V _IN . The total charge is now only α · Q _s .

During the "high" phase of the clock signal? ₂ , all N unit cells 140 are connected to the hold capacitor C _h . Thus, the charge? _S Q _s plus the charge already present in the hold capacitor C _h is redistributed across the total capacitance C _s + C _h . In this way, the scaling factor A [k] = a is realized and the same IIR filter as the mixer embodiment shown in Figs. 6 and 7 is implemented.

During the "high" phase of the clock signal? ₃ , all of the unit capacitors C _u are reset.

The main advantage of the mixer embodiment shown in FIGS. 10A-D is that both the transfer capacitor C _t and the dummy unit cell (i.e., the dummy unit capacitor) are not present. However, with respect to the mixer embodiment shown in Figs. 10A to 10D, the following should be considered. All four clock signals must be routed through the matrix of unit cells 140 in each block. This will result in increased power consumption and possibly also the increased area required for the matrix of unit cells 140. The digital control code n, and the sign bit clock signal in addition to requiring a gating of φ _1, from the mixer embodiment 100 shown in Figure 10 a to d, the clock signal φ ₁ is also the clock signal from the OR gate should be combined with φ ₃ . In some situations, since all four clock signals are used, delay due to such gating can be a problem and there is no buffer to delay some clock signals.

Figures 11a-c schematically illustrate the operating principle implemented in the further mixer embodiment 100. [ As in the case of Figures 9a-c and 10a-d, only the selected components of the further mixer embodiment 100 are shown in Figures 11a-c for illustration. As in the case of FIG. 9 a to c, the dummy unit capacitor C _d is separated into the individual unit cells pile. Each box in Figs. 11 (a) to (c) represents a variable number of unit cells or dummy unit cells depending on?.

6, 7, 8 and 9 in a through analogy to the mixer embodiment 100 illustrated in c, the mixer 100 shown in Figure 11, a to c may also include a dummy unit capacitor C _d do. However, in the mixer 100 shown in Figs. 11A to 11C, these dummy unit capacitors C _d are connected to the input terminal 120 through the dummy unit cell input switch rather than the output terminal 130. Consequently, in this embodiment, clock gating is performed on the dummy unit cell input switch.

During the "high" phase of the clock signal φ _0, the input signal is sampled from n unit capacitors C _u and (Nn) dummy capacitors C _d (C _d = C _u ), so the total (sampling) capacitance is always equal to C _s Do. This causes a voltage V _IN and a total charge Q _s = C _s V _IN . The dummy unit cell ensures that the input load is always equal to C _s .

During the "high" phase of the clock signal φ ₁ , all N unit capacitors C _u (n unit capacitors C _u sampling the input signal and (Nn unit capacitors C _u not sampling the input signal) is connected to _h, this embodiment is also obtained by adding an electric charge present in the total electric charge Q · α _s and the hold capacitor C _h is redistributed over the total capacitance C _s + C _h. As in the previous embodiments, this leads to the scaling factor A [k] = a and the same IIR filter implementation.

In this mixer embodiment 100, the clock signal? ₂ is not used. During the high phase of the clock signal? ₃ , all capacitors C _u and C _d are reset.

With respect to the mixer embodiment 100 shown in Figures 11a-c, since the gating determines how long the input signal is integrated at the time of sampling and in the case of the current input signal, clock gating is now only a timing critical lt; RTI ID = 0.0 > timing-critical < / RTI > switch.

As already mentioned above, the mixer embodiment 100 described above may be implemented in the form of a quadrature mixer that provides in-phase output signals and quadrature output signals.

For example, the quadrature mixer embodiment 500 shown in FIG. 5 and the quadrature mixer embodiment 800 shown in FIG. 8 have two identical and independent mixers 100 for the I and Q paths. During each clock cycle, each of the mixer 100 is to sample the input of the capacitance C _S, and generates a total charge _{Q s = C s · V IN} . The only case where all of these charges are to be used (ie, to be connected to the hold capacitor C _h ) is when α = 1 (eg, at the peak of the mixed signal in the case of a sinusoidal mixed signal). In the more general case where? <1, some of the charge remains at the sampling capacitor until it is discarded in the reset phase, which is not related to the charge redistribution process at all. Nevertheless, the total (sampling) capacitance C _s needs to be the same every clock cycle so that the signal source always drives the same impedance.

During each clock cycle, the I and Q phases together take charge 2 · Q _s from the input signal source and store it in total capacitance 2 · C _s . However, not all such charges are used. Because the I and Q mixing signals is the phase difference is 90 degrees, the peak does not match, that is, (referred to hereinafter, α _i) of the I channel α and (referred to below, α _q) of the Q channel α, the same It is impossible to equal 1 at the time.

that is,

. &Lt; / RTI &gt;

To maintain the input impedance of the mixer 100 of the I and Q channels during all clock cycles, the total capacitance &lt; RTI ID = 0.0 &gt;

Lt; / RTI &gt; is sufficient to sample the input signal.

Also,

.

개의 더미 커패시터 C_d만을 포함한다. 따라서 총 커패시턴스는This finding leads to the quadrature mixer embodiment 1200 shown in FIG. 12 based on the mixer embodiment 100 described above. Similar to the mixer embodiment shown in FIGS. 10A-D, both the I-channel mixer and the Q-channel mixer also include N unit capacitors C _u . However,

Dummy capacitor C _d . Therefore, the total capacitance

.

일 경우, 총 커패시턴스는 2.4·C_s만이 실질적으로 감소된 영역으로 변환된다.Compared to the mixer embodiment shown in Figs. 10a-d, for a quadrature implementation, the total capacitance

, Then the total capacitance is converted to the substantially reduced region of only 2.4 · C _s .

만큼 감소되어, 혼합기를 구동시키는 신호 소스의 설계를 용이하게 한다.Further, in the quadrature mixer embodiment 1200 shown in FIG. 12, the input capacitance during the sampling phase may be a factor

Thereby facilitating the design of the signal source driving the mixer.

13 shows a further quadrature mixer embodiment 1300 based on the mixer embodiment 100 described above. Similar to the quadrature mixer embodiment 1200 of FIG. 12, the quadrature mixer embodiment 1300 of FIG. 13 is implemented to share a unit cell 140 between the I and Q channels of a quadrature mixer. However, unlike the quadrature mixer embodiment 1200 of FIG. 12, the clock gating in the quadrature mixer embodiment 1300 of FIG. 13 is performed in the output switch based on the mixer embodiment 100 shown in FIGS. 6 and 7 do.

유닛 커패시터 C_u에 대해 샘플링되어 대략

의 총 커패시턴스가 된다. 다음 클록 신호의 "하이" 위상 동안, 이들 유닛 셀(140)의 n_i는 I 채널의 홀드 커패시터 C_h에 접속되고, 이들 유닛 셀(140)의 n_q는 직교 혼합기 실시예(1300)의 Q 채널의 홀드 커패시터 C_h에 접속되며, 여기서,

,

및

이다. 동시에, 각각의 채널에서 총 커패시턴스 C_s를 달성하기 위해 더미 유닛 셀이 양쪽 채널에 포함된다. 도 13에 도시된 직교 혼합기 실시예(1300)에 대해서, 단지 대략

유닛 커패시터 C_u 및 대략

더미 커패시터 C_d가 요구되며, 이것은 단지 총 커패시턴스

라는 것을 의미한다. 실제로, 전하 공유 페이즈 동안 각각의 채널 I 및 Q가 홀드 커패시터 C_h에 접속될 C_s의 총 커패시턴스를 필요로 하기 때문에, 이는 달성 가능한 최저 총 커패시턴스를 나타낸다. 또한, 도 13에 도시된 직교 혼합기 실시예(1300)에서, 클록 게이팅은 타이밍 감지 입력 스위치들로부터 출력 스위치들로 이동된다.For the quadrature mixer embodiment 1300 shown in FIG. 13, the input signal is approximately

RTI ID = 0.0 &gt; _Cu &lt; / RTI _&gt;

Lt; / RTI &gt; For the next "high" phase of the clock signal, of these unit cells 140, n _i is connected to the hold capacitor C _h of the I-channel, n _q of these unit cells 140 in the quadrature mixer embodiment (1300) Q Is connected to the hold capacitor C _h of the channel,

,

And

to be. At the same time, the pile unit cells are included in both channels to achieve the total capacitance C _s in each channel. For the quadrature mixer embodiment 1300 shown in FIG. 13,

The unit capacitors C _u and approximately

A dummy capacitor C _d is required, which is simply a total capacitance

. Indeed, this represents the lowest total capacitance achievable since each channel I and Q during the charge sharing phase requires the total capacitance of C _s to be connected to the hold capacitor C _h . Also in the quadrature mixer embodiment 1300 shown in FIG. 13, the clock gating is moved from the timing sensing input switches to the output switches.

However, as compared to the quadrature mixer embodiment 1200 shown in FIG. 12, the quadrature mixer embodiment 1300 shown in FIG. 13 is configured such that the unit cell and the dummy cell are connected to the output of either the I channel or the Q channel Additional switches are required. These additional switches can add more parasitic capacitance. Also, signal routing can become more complex.

In the following, a further embodiment of a mixer 100 comprising a unit cell 140 and / or a block of unit cells 140 configured differently compared to the mixer embodiment shown in Figs. 3 and 6 will be described. The unit cell described below may also be implemented using an architecture that includes a transfer capacitor C _t or a dummy unit cell to hold the total capacitance associated with sampling and charge transfer at C _h equal to C _s .

As already mentioned above, the unit cell 140 of the mixer 100 shown in FIG. 3 is controlled by one data bit based on three clock signals and a control code. This means that a sign bit and three clock signals need to be routed to every single unit cell 140 within a given block 350 of the unit cell 140 of the mixer 100 shown in FIG. In addition, each unit cell 140 also requires one of the control code data bits. In an alternative embodiment, the clock signal &lt; RTI ID = 0.0 &gt; ₁ &lt; / RTI &gt; may be gated to the sign bit outside the matrix of the unit cell 140 and its inverse and then distributed. In this case, the two clock signals, i.e., φ ₀ and φ _3, and the two gated clock signals, "φ ₁ and sign" and "φ ₁ and sign" , And each unit cell 140 must still be provided with one of the control code data bits. In both cases, this routing can cause significant parasitic capacitance, thus affecting or even dominating both the power consumption of the clock signal and the data driver and the input impedance of the mixer 100 shown in FIG. This situation can be improved by increasing the spacing between the wires, but this will increase the size of the matrix of unit cells 140, which in turn can increase the capacitance for the substrate on which the mixer 140 is implemented. There are several options for reducing the number of signals routed through the matrix of unit cells 140 of the mixer shown in FIG. All of these options require an additional switch and have at least two switches in series during at least some "high" phases of the clock signal. In order to keep the on-resistance the same, the switches in series need to be wider, followed by the increase in gate capacitance.

14 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX , in accordance with one embodiment. The mixer 100 samples the analog input signal at a plurality of discrete time points k from the input terminal 120 of the mixer 100 to a sampling frequency f _S to obtain a sampled analog input signal having a continuous signal value, (K) of the mixer 100 having a continuous signal value by scaling the sampled analog input signal based on the scaling coefficients A [k], i.e. X _OUT = A [k] X _IN [ And a scaler 110 configured to generate an output signal. The scaling factor A [k] is a time discrete representation of the mixed signal.

The embodiment of the mixer 100 shown in FIG. 14 includes an additional switch in series with the unit capacitor C _u in each unit cell 140. This configuration allows all other switches to be shared by all N unit cells 140 in block 1450 and to be taken out of the unit cell and out of the matrix. In this embodiment of the mixer 100, the unit cell 140 consists of only one switch and a unit capacitor C _u , and is controlled by only one data bit and one gated clock signal based on the control code. The gated clock signal " phi ₀ | phi _{3 &} quot ;, shown as a reference to the switch of the unit cell 140 of Fig. 14, where "|" represents a logical OR operation - can be generated outside the matrix, Can be routed to all of the unit cells 140, so that only one clock signal should be counted.

In this embodiment, not only the sign bit but also other clock signals are needed outside the matrix, i.e. outside the N unit cells 140 only. The clock signal drives the same number of switches (all switches must be twice as large as the two switches in series during all "high" clock phases), but the load capacitance is concentrated in one place rather than spreading across a large matrix, Due to the fact that it can be significantly reduced, the overall load capacitance can still be small.

For the embodiment of the mixer 100 shown in FIG. 14, it should be taken into account that there will be some parasitic capacitance on the node to which all the switches are connected. This parasitic capacitance may be considerably large, since the node is spread over the matrix of unit cells 140 and thus may have a large routing capacitance. This parasitic capacitance will always be present, even if the control code n is set to zero, and will always convey some charge from the input terminal 120 to the output terminal 130, i.e., the embodiment of the mixer 100 shown in FIG. 14 A parasitic charge path exists. This presents the lower limit for the scaling factor or voltage gain A [k]. If this lower limit is low enough that all required mixed signal samples can still be realized, but it is not possible to represent the smallest mixed signal samples, this will result in distortion of the output signal.

This potential problem does not occur, for example, in the unit cell 140 of the mixer 100 shown in FIG. In the embodiment of the mixer 100 shown in FIG. 3, when the control code n is 0, none of the transfer switches will be closed and no charge is delivered to the transfer capacitors C _t and the hold capacitors C _h .

By having separate input and output switches, the potential problems described above do not occur in the embodiment of the mixer 100 shown in FIG. In the embodiment of the mixer 100 shown in FIG. 15, when the control code n is zero, the output switches will all be open and no charge is delivered to the hold capacitor C _h . The additional input switch still allows placing the sampling and reset switch outside the matrix, i. E. Outside of the N unit cells 140. Each unit cell 140 includes three switches (including a sign inversion switch not shown in FIG. 15), and one clock signal ₁ , one control code data bit and sign bit . In an alternative embodiment, the clock signal &lt; RTI ID = 0.0 &gt; ₁ &lt; / RTI &gt; can be gated to the sign bit (and its inverse) at the highest level and then distributed across the matrix of unit cells 140. In this case, one clock signal, two gated clock signals and one control code data bit are required, but this is likely to consume more power because the combined activity of the clock signal is higher than the combined activity of the sign bit have.

16 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX in accordance with a further embodiment.

The configuration of the N unit cells 140 of block 1650 of the embodiment of mixer 100 shown in Figure 16 allows the removal of sign bits from the matrix of unit cells 140. [ In this embodiment, two output switches (only positive signs for the positive and negative signs are shown in FIG. 16) are moved out of the unit cell 140, which is the control within the unit cell 140 By adding an extra switch controlled by the code. Thus, the unit cell 140 now includes two switches, one clock signal? ₁ '(where? ₁ ' is the inverse of the clock signal? ₁ ) and one control code data bit.

FIG. 17 illustrates a method of generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX according to a further embodiment based on a variation of the embodiment of the mixer 100 shown in FIG. 15 Lt; RTI ID = 0.0 &gt; 100 &lt; / RTI &gt; In this embodiment, the unit cell 140 is inverted, but is generally not a problem since the mixer 100 is implemented as a differential mixer. It can be seen that there is still no parasitic charge path for the embodiment of the mixer 100 shown in FIG. As in the case of the embodiment shown in Fig. 15, the unit cell 140 of the mixer 100 shown in Fig. 17 includes two switches, one clock signal? ₁ , one control code data bit, Bit. However, Now that the respective clock signal, two switches (one for each side of the unit cell capacitor C _u) in series during the phase, it is necessary to switch all of the width of the doubled. In addition, an additional clock signal &quot; phi ₁ | phi ₃ "needs to be generated.

18 shows a schematic diagram of a mixer 100 for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX in accordance with a further embodiment. The unit cell 140 of the mixer 100 shown in FIG. 18 provides the advantage of not requiring a clock signal at all. In the embodiment of the mixer 100 shown in FIG. 18, all of the switches controlled by one of the clock signals are moved out of the matrix of unit cells 140. The only signal to the unit cell 140 is the control code bit. The effect of this is that the sampling capacitor is already off during the sampling phase. For this reason, when the output switch is closed (by the clock signal? ₁ ), a dummy capacitor interrupted by the clock signal? ₁ ', that is, by the inverted clock signal? ₁ (to the left of the unit cell 140 of FIG. 1) do.

The unit cell 140 of the embodiment of the mixer 100 shown in Fig. 18 requires that the control code data bits change during the unused clock phase? ₂ . In this way, the capacitor to be used for sampling is already connected and reset correctly during the "high" phase of the clock signal? ₃ .

19 generates an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX according to a further embodiment based on a modification of the embodiment of the mixer 100 shown in Fig. Lt; RTI ID = 0.0 &gt; 100 &lt; / RTI &gt; The unit cell 140 of the embodiment of the mixer 100 shown in Figure 19 includes only a single unit capacitor C _u . However, in this embodiment, the parasitic charge path can now be expected to carry much more charge because it also includes the parasitic capacitance of the unit capacitor C _u , which is generally larger than the parasitic component of the switch.

20 generates an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX according to a further embodiment based on a modification of the embodiment of the mixer 100 shown in Fig. Lt; RTI ID = 0.0 &gt; 100 &lt; / RTI &gt; The configuration of the unit cell 140 in the embodiment of the mixer 100 shown in FIG. 20 still requires only one unit capacitor C _u , but removes the parasitic charge path. However, in this embodiment there are now three switches in series for any clock phase.

21 generates an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having an adjustable mixing frequency f _MIX according to a further embodiment based on a modification of the embodiment of the mixer 100 shown in Fig. Lt; RTI ID = 0.0 &gt; 100 &lt; / RTI &gt; The difference is that the control code no longer controls the replicated version of the input switch, not the output switch. It is particularly interesting that, for the mixer embodiment 100 shown in Figs. 11a-c and 12, the dummy unit cell is connected to the input terminal 120. Fig. The unit cell 140 shown in Fig. 21 makes it possible to take advantage of the mixer embodiment 100 shown in Figs. 11a-c and 12 without having to gating the clock signal controlling the input switch.

The first input switch is now directly controlled by the clock signal, allowing the correct timing of the edge. The second input switch is controlled only by a control code data bit that can be set well before the clock edge of the sampling clock signal, and does not cause any timing problems.

The different effects of the selection of the mixing frequency f _MIX are described below and apply essentially to all of the above-described mixer embodiments. The mixing frequency f _MIX is a rational number for the sampling frequency f _S ,

, Where A and B are integers. In this case, the mixed signal will be periodic when sampled at f _s and may be stored in a limited-sized look-up table (LUT) or periodic shift register of mixer 100.

If the ratio is not rational, the representation of the sampled mixed signal will not be periodic even if the analog mixed signal is periodic. In this case, the mixed signal samples need to be calculated at runtime, requiring more computational resources and thus more area and power.

It can be seen that the period of the mixed signal sampled at f _S is L samples, where L is

, Where gcd (x, y) is the greatest common divisor of x and y. Thus, in the general case, a LUT of the L sample is required, which is sampled at f _S. However, the mixer 100 has a phase of f _LO = f _S / 4 and processing only every fourth sample it is easy for one LUT to be included per mixer block so that the LUT is sampled likewise at f _LO . If L is a multiple of four, the samples can be distributed over four sub-LUTs so that each sub-LUT contains only L / 4 samples. If L is a multiple of 2 but not 4, then each lower LUT contains L / 2 samples, and if L is not a multiple of 2, each lower LUT will contain the same L sample, but in a different order something to do. In summary, each sub-LUT contains M samples,

Generally, when f _MIX is required to match the input signal frequency, the minimum numbers A and B can be large, which is a large value for M. However, there is some flexibility in choosing f _MIX , since a non-zero intermediate frequency (IF) is generally preferred and there is some flexibility in choosing IF. In this case, f _MIX can be selected such that A and B are fairly small numbers and M can be kept low.

Because of the limited number of unit cells 140, the mixed signal samples will have to be rounded, which causes quantization noise. This quantization noise will also be periodic with a LUT length M and will appear as a spur at the discrete frequency of the mixed signal spectrum rather than the noise floor as might be expected. The spacing between the spurs is

, And a spur can occur at all frequencies.

Thus, the choice of the ratio A / B is a trade-off between the LUT length M (usually the least significant effect) and the spur spacing _Afspur and the intermediate frequency IF. Usually the best strategy is to maximize Δf _spur while maintaining IF within the bounds. The higher the gap between the _spur and the desired signal, the easier it is to filter out the _spur after mixing (the _spur and the desired signal will be at f _IF + k · Δf _spur after mixing). The height of the LO spur can be improved by adding more bits, i. E. More unit cells 140 to the mixer 100. In one embodiment, the mixer 100 is configured to mix an input signal with a mixed signal having a frequency f _LO , e.g., for a band where the bi-directional distance is not too large. In the context of Equation 16 above, this means A = 1 and B = 4

이 된다.

.

Then L = 4 and M = 1, and the LO samples stored in the LUT are decremented to the sequence {1, 0, -1, 0}. A big advantage of this is that these samples perfectly represent sinusoids with amplitude 1 without any quantization noise. Therefore, there will be no quantization noise spur.

의 진폭을 갖는 혼합 신호를 구현할 수도 있다. 이는 혼합기 손실을 3dB 만큼 감소시키지만 여전히 임의의 양자화 노이즈는 도입하지 않는다. 이러한 최적화는, LUT가 상이한 시점에서 샘플링된 혼합 신호의 다중 주기를 저장하기 때문에 일반적으로 가능하지 않아서, 샘플들 중 하나는 혼합 신호의 피크에서 또는 근방에서 발생할 것이므로, 1보다 클 필요가 있다. 이는 스케일링 계수 A[k]에 대해 가장 높은 가능한 값이 α = 1이기 때문에 가능하지 않다.In this particular case, by replacing the LUT sample with the sequence {1, 1, -1, -1}, without any quantization noise

Lt; RTI ID = 0.0 &gt; amplitude. &Lt; / RTI &gt; This reduces the mixer loss by 3 dB but still does not introduce any quantization noise. This optimization is generally not feasible because the LUT stores multiple periods of the sampled mixed signal at different points in time, so one of the samples would need to be greater than one, as it would occur at or near the peak of the mixed signal. This is not possible because the highest possible value for the scaling factor A [k] is? = 1.

If f _MIX = f _LO , then all of the unit cells 140 in one block 350 of the mixer 100 are either permanently on (for samples 1 and -1) or permanently off (for sample 0) , Such a mixer 100 operates as a complex implementation of a conventional passive mixer.

Some of the mixer embodiments 100 described above include four mixer blocks (or mixer phases) 350 of the unit cells 140. However, as discussed above, having four mixer blocks is not essential for mixer 100 to operate, but it is only necessary to use an 25% duty cycle clock signal at f _LO to achieve an effective sampling rate of 4f _LO Method.

For low frequency f _LO or high speed transistor technology, it may be possible to implement a mixer 100 having a single mixer block per channel (i. E. One block for the I channel and one block for the Q channel). In this case, four 25% clock signals with a clock frequency f _S = 4f _LO are required. In this way, the different processing steps of the mixer 100 can all be completed for one T _S period, so that the same block of the mixer 100 can be used to process the next sample. This single block mixer 100 differs from the four block mixer 100 in the following points.

The four block mixer 100 connects each block or phase to the input during the entire T _S period. Therefore, except for the moment when the clock signal is switched, the signal source must always drive the same load. Single mixer block 100 is then connected only to an input sampling capacitor of over 25% of the sampling period T _S itself. Therefore, the signal source must be able to handle very variable loads.

The stabilization time available for sampling, charge sharing and resetting is now T _S / 4 instead of T _S for 4 block mixer 100. This means that all switches of the single block mixer 100 will have to be four times larger than in the four block mixer 100 in order to achieve an equally good stabilization.

Due to the increased switch, the input capacitance per mixer block is four times higher. However, this is compensated by the fact that there is only one mixer block instead of four. Thus, four times higher power consumption can be expected because the total clock load is the same and the clock frequency is four times higher.

Similarly, a mixer 100 having two mixer blocks per channel using four 25% clock signals at 2f _LO can be implemented. The implication is similar to that for the single block mixer 100. The two-block mixer 100 should only be able to handle a variable load by connecting one of its sampling capacitors to the input for 50% of the time. The switch of the two-block mixer 100 must be twice as large as the switch of the four-block mixer 100. [ The power consumption will be as high as twice the power consumption in the four block mixer 100. [

The higher power for the mixer 100 with fewer blocks represents an interesting trend that can also be used in other directions, for example, by implementing the mixer 100 with 8 mixer blocks per channel. In this case, eight 25% clock signals are needed at f _LO / 2 where the clock signal pulses in the clock signal phase overlap with the pulses in the adjacent clock signal phases. Because the sampling clock signal is superimposed, the 8 block mixer 100 simultaneously connects two of its blocks to the input at any instant. Thus, the source does not need to handle the variable load, but the load will be higher than the four block mixer 100. In addition, the parasitic input capacitance of the 8 block mixer 100 will now be higher, since the parasitic component of 8 blocks per channel is connected to the input. The switch needs to be only as large as half the number of switches in the four-block mixer 100. [ The power consumption will be only as high as only half of the power consumption in the four block mixer 100. [ This is an interesting way to reduce power consumption while sacrificing the doubled area and input capacitance.

Instead, a non-overlapping 12.5% clock signal phase can be used to control the sampling switch of the 8-block mixer 100 so that the stabilization time is the same as in the 4-block mixer 100 and the switches need to have the same size have. In this way, the source driving the inputs will have to drive the same load as in the four-block mixer 100. [ On the other hand, other switches can be halved and controlled by superposing a 25% clock signal. This still saves power, but is less in the above architecture.

One of ordinary skill in the art will appreciate that the multi-block mixer embodiment 100 may be further extended with a 16 block mixer, a 32 block mixer, and the like.

Also, although specific features or aspects of the present disclosure may be described with respect to only one of several embodiments or examples, it will be appreciated that such features or aspects, as may be desired and advantageous for any given or specific application May be combined with one or more other features or aspects of other implementations or embodiments. Furthermore, to the extent that the terms "comprises", "having", "having", or variations thereof, are used in either the detailed description or the claims, such terms are intended to be inclusive . In addition, the terms "exemplary "," example ", and "example" mean only as an example rather than as optimal or optimal. The terms "connection" and "connection" can be used with derivatives. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether or not they are direct physical or electrical contacts, or are not in direct contact with each other.

While specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. will be. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein.

Although elements in the following claims are described in their specific sequence with corresponding labeling, unless the description of the claims otherwise indicates a particular sequence for implementing some or all of these elements, The present invention is not limited thereto.

Many alternatives, modifications, and variations will be apparent to those of ordinary skill in the art in light of the above teachings. Of course, those of ordinary skill in the art will readily recognize that there are numerous applications of the present invention beyond what is described herein. While the invention has been described with reference to one or more specific embodiments, those skilled in the art will recognize that many changes can be made therein without departing from the scope of the invention. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims (15)

A mixer (100) for generating an analog output signal (X _OUT) from an analog input signal (X _IN) using a mixing signal having a mixing frequency (f _MIX )
The mixer
To obtain the analog input signal X _IN [k] samples having consecutive signal values and sampling the analog input signal X _IN at a plurality of discrete time k with a sampling frequency f _S, based on the plurality of scaled coefficients A [k] (110) configured to generate the analog output signal (X _OUT) having a continuous signal value by scaling the sampled analog input signal (X _IN [k]
Lt; / RTI &gt;
Wherein the scaling factor A [k] is a time discrete representation of the mixed signal. The method according to claim 1,
Wherein the sampling frequency f _S is at least twice the mixing frequency f _MIX of the mixing signal. 3. The method according to claim 1 or 2,
Wherein the mixing signal is a sinusoidal mixing signal. 4. The method according to any one of claims 1 to 3,
_Wherein the ratio of the mixing frequency f _MIX to the sampling frequency f _S is given as A / B, and A and B are integers. 5. The method according to any one of claims 1 to 4,
The scaler 110 is configured to derive the sampling frequency f _S from the local oscillator frequency f _LO of the local oscillator signal provided by the local oscillator, wherein the sampling frequency f _S is an integer multiple of the local oscillator frequency f _LO , Equal to four times the local oscillator frequency f _LO . 6. The method according to any one of claims 1 to 5,
Wherein the analog input signal X _IN is an analog voltage signal V _IN or an analog current signal I _IN and the analog output signal X _OUT is an analog voltage signal V _OUT or an analog current signal I _OUT . 7. The method according to any one of claims 1 to 6,
The mixer 100 includes an input terminal 120 and an output terminal 130 connected to the scaler 110. The scaler 110 includes a plurality of unit cells 120 connected in parallel to the input terminal 120, (140), wherein each unit cell (140) comprises a unit cell capacitor, the unit cell capacitor of the ith unit cell has a capacitance C _ui , and the sum of the capacitances of the unit cells (140) C _s and each unit cell 140 includes a charge transfer switch for connecting the unit cell capacitor of each unit cell 140 to the output terminal 130, Is configured to control the charge transfer switch of each unit cell (140) to scale the sampled analog input signal X _IN [k] based on a plurality of scaling factors A [k]. 8. The method of claim 7,
Wherein said plurality of unit cells (140) comprise N unit cells, said unit cell capacitors having the same capacitance C _ui = C _u , C _u is a constant capacitance, and the total capacitance C _s is given by C _s = NC _u . 8. The method of claim 7,
Wherein said plurality of unit cells (140) comprises b unit cells, said unit cell capacitors of an ith unit cell have a capacitance C _ui = 2 ^{i - 1} C _u , C _u a constant capacitance, C _s is given by C _s = (2 ^b -1) C _u . 8. The method of claim 7,
Wherein the plurality of unit cells 140 includes (b + K) unit cells, and the unit cell capacitors of the i-th unit cells among the b unit cells of the plurality of unit cells 140 have a capacitance C _ui = 2 ^{i- 1} C _u , C _u is a constant capacitance, and the unit cell capacitors of the K remaining unit cells of the plurality of unit cells (140) have the same capacitance C _ui = 2 ^b C _u , C _s is given by C _s = (2 ^b K + 2 ^b -1) C _u . 11. The method according to any one of claims 7 to 10,
The input terminal 120 includes a positive input terminal and a negative input terminal, the output terminal 130 includes a positive output terminal and a negative output terminal, and each of the plurality of unit cells 140 Wherein each unit cell of the plurality of unit cells (140) includes a plurality of inverting switches, each of the sides of the unit cell capacitors of one of the plurality of unit cells (140) And to control the plurality of inversion switches to be connectable to the positive output terminal and / or the negative output terminal for operation. 12. The method according to any one of claims 7 to 11,
Wherein the scaler 110 comprises a memory and the memory is configured to store a plurality of control codes wherein each control code is associated with a sum of the total capacitance C _s connected to the output terminal 130 of the mixer 100 To determine the fraction [alpha] [k]. 13. The method according to any one of claims 7 to 12,
The scaler 110 includes 2 ^M blocks of unit cells 140, where M is an integer and each block of unit cells 140 has the sampled analog input signal X _IN [k] in a different phase Wherein each block uses a possibly different set of scaling factors A [k]. A method (200) for generating an analog output signal X _OUT from an analog input signal X _IN using a mixed signal having a mixing frequency f _MIX ,
The method comprises:
The method comprising: sampling the analog input signal X _IN at a plurality of discrete time k with a sampling frequency f _S to obtain the analog input signal X _IN [k] samples having consecutive signal values,
Generating the analog output signal X _OUT having a continuous signal value by scaling the sampled analog input signal X _IN [k] based on a plurality of scaling coefficients A [k]
Lt; / RTI &gt;
Wherein the scaling factor A [k] is a time discrete representation of a periodic mixed signal. 15. A computer program comprising program code for performing the method of claim 14 when executed on a computer.

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