KR20160145484A - Method for manufacturing solar cell - Google Patents

Abstract

According to an embodiment of the present invention, a manufacturing method of a solar cell comprises a step of forming a protection film on a semiconductor substrate by an insulation film wherein the semiconductor substrate includes a base region formed of crystalline silicon having first conductivity. The step of forming the protection film includes a process of performing thermal treatment at a thermal treatment temperature, which is 600C or higher, in a gas atmosphere including a halogen gas having a halogen element.

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method of manufacturing a solar cell, and more particularly, to a method of manufacturing a solar cell having a protective film formed on a semiconductor substrate or a conductive type region.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. The solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be manufactured so as to maximize the efficiency of the solar cell.

For example, in solar cells, various passivation layers are formed to passivate, physically protect, and electrically isolate a semiconductor substrate or a semiconductor layer. Such a protective film can be formed by a thermal oxidation method, a vapor deposition method, or the like. It is difficult to precisely control the thickness of the protective film formed by the thermal oxidation method and it may be difficult to have excellent film characteristics. In the vapor deposition method, the deposition is carried out in an atmosphere containing a raw material gas containing elements constituting a protective film, and if necessary, a carrier gas. However, a passivation film formed using only a basic substrate such as a raw material gas or a carrier gas may have a high interface trap density and may not have excellent passivation characteristics for passivating a semiconductor substrate or a semiconductor layer. Accordingly, a manufacturing method for forming a protective film having excellent characteristics is required.

The present invention provides a method of manufacturing a solar cell capable of forming a solar cell having excellent efficiency by forming a protective film having excellent characteristics.

A method of manufacturing a solar cell according to an embodiment of the present invention includes forming a protective film with an insulating film on a semiconductor substrate including a base region made of crystalline silicon having a first conductivity type. The forming of the passivation layer may include a heat treatment at a heat treatment temperature of 600 ° C or higher in a gaseous atmosphere containing a halogen gas having a halogen element.

According to an embodiment of the present invention, a protective film such as a control passivation layer, a passivation film and the like can be formed by including a heat treatment process performed at a specific temperature and a gas atmosphere, thereby improving the characteristics and quality of the protective film. Thus, the efficiency of the solar cell can be improved. The formed protective film can subsequently maintain excellent quality and characteristics in a process carried out at a high temperature, thereby improving process stability.

FIG. 1 is a cross-sectional view illustrating an example of a solar cell manufactured by a method of manufacturing a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
3A to 3F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is an example of a heat treatment apparatus in which a heat treatment process can be performed in the method of manufacturing a solar cell according to the present embodiment.
5 is a view showing a temperature cycle of a heat treatment process in a method of manufacturing a solar cell according to an embodiment of the present invention.
6A and 6B are cross-sectional views illustrating steps of forming a control passivation layer in a method of manufacturing a solar cell according to a modification of the present invention.
7 is a cross-sectional view showing another example of a solar cell manufactured by the method for manufacturing a solar cell according to an embodiment of the present invention.
8 is a schematic plan view of the solar cell shown in Fig.
9A to 9D are cross-sectional views illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.
10A to 10D are cross-sectional views illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.
11 is a photoluminescence (PL) photograph of a solar cell according to Experimental Example 1. FIG.
12 is a PL photograph of the solar cell according to Comparative Example 1. Fig.
13 is a PL photograph of the solar cell according to Comparative Example 2. Fig.
FIG. 14 is a graph showing the results of measurement of the implied open-circuit voltage (implied Voc) of the solar cell according to Experimental Example 1 and Comparative Example 1. FIG.
FIG. 15 is a graph showing the result of measuring the open-circuit voltage after performing additional heat treatment at a temperature of 900.degree. C. to the solar cell manufactured according to Experimental Examples 1 and 2 and Comparative Example 1. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described with reference to the accompanying drawings. An example of a solar cell manufactured by the method of manufacturing a solar cell according to an embodiment of the present invention will be described first and then a method of manufacturing a solar cell according to an embodiment of the present invention will be described.

FIG. 1 is a cross-sectional view illustrating an example of a solar cell manufactured by the method of manufacturing a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG.

1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, a semiconductor substrate 10 formed on or in contact with the semiconductor substrate 10, Electrodes 42 and 44 connected to the conductive regions 32 and 34 and a protective film formed on the semiconductor substrate 10 to be in contact with the conductive regions 32 and 34, The control passivation layer 20 located on the semiconductor substrate 10 constitutes the above described protective film and the semiconductor layer 30 including the conductive type regions 32 and 34 is formed on the control passivation layer 20 . Here, the semiconductor layer 30 includes conductive type regions 32 and 34 including a first conductive type region 32 having a first conductive type and a second conductive type region 34 having a second conductive type. And may include a barrier region 36 located between the first conductive type region 32 and the second conductive type region 34 and having intrinsic characteristics. The electrodes 42 and 44 may include a first electrode 42 connected to the first conductive type region 32 and a second electrode 44 connected to the second conductive type region 34. The solar cell 100 may further include another passivation film such as a front passivation film 24, an antireflection film 26, and a rear passivation film 40. Here, the protective film may be an insulating film for protecting the semiconductor substrate 10 or the conductive type regions 32 and 34. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising a second conductive dopant. The electrical characteristics are excellent based on the base region 110 or the semiconductor substrate 10 having high crystallinity and few defects.

The second conductivity type may be p-type or n-type. For example, if the base region 110 has an n-type, then p (pn junction) that forms a carrier by photoelectric conversion with the base region 110 (e.g., a pn junction between the control passivation layer 20) The first conductivity type region 32 of the first conductivity type can be formed wide to increase the photoelectric conversion area. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

The semiconductor substrate 10 may include a front electric field area (or an electric field area) 130 located on the front side of the semiconductor substrate 10. Since the front electric field area 130 has the same conductivity type as the base area 110 and has a higher doping concentration than the base area 110, it can form a conductive type or impurity area.

In this embodiment, the front electric field region 130 is formed in the semiconductor substrate 10 as a doped region formed by doping a dopant having a second conductivity type with a relatively high doping concentration. Accordingly, the front electric field area 130 includes a crystalline (single crystal or polycrystalline) semiconductor having a second conductivity type to constitute a part of the semiconductor substrate 10. For example, the front electric field area 130 can form a part of a single crystal semiconductor substrate having a second conductivity type (for example, a single crystal silicon wafer substrate). At this time, the doping concentration of the front electric field region 130 may be smaller than the doping concentration of the second conductive type region 34 having the same second conductivity type.

However, the present invention is not limited thereto. Therefore, it is also possible to form the front electric field area 130 by doping a second conductive type dopant to a semiconductor layer other than the semiconductor substrate 10 (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) have. Or a region which is similar to that doped by the fixed charge of the layer formed adjacent to the semiconductor substrate 10 (for example, the front passivation film 24 and / or the antireflection film 26) 130). For example, when the base region 110 is n-type, the front passivation film 24 may be formed of an oxide (for example, aluminum oxide) having a fixed negative charge to form an inversion layer ) Can be formed and used as an electric field region. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [ The front electric field area 130 having various structures can be formed by various other methods.

In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. The texturing structure formed in the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (for example, (111) plane) of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

The control passivation layer 20 may be formed on the rear surface of the semiconductor substrate 10 as a protective film formed on the semiconductor substrate 10. [ For example, the control passivation layer 20 may be formed in contact with the back surface of the semiconductor substrate 10 to simplify the structure. The control passivation layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10 and may be formed by a simple process without additional patterning. However, the present invention is not limited thereto, and the shape and the like of the control passivation layer 20 can be variously modified.

The control passivation layer 20 may serve as a diffusion barrier to prevent the dopants of the conductive regions 32 and 34 from diffusing into the semiconductor substrate 10. [ The control passivation layer 20 may include various materials through which a plurality of carriers can pass, for example, oxides, nitrides, and the like. In particular, the control passivation layer 20 may be composed of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which is excellent in passivation characteristics and in which the carrier is easy to move. This control passivation layer 20 may be a layer formed by wet chemical and / or thermal oxidation under specific conditions, which will be described in more detail later.

At this time, the thickness of the control passivation layer 20 may be smaller than the thickness of the rear passivation film 40. As an example, the thickness of the control passivation layer 20 may be 5 nm or less (more specifically, 2 nm or less, for example, 1 nm to 2 nm). If the thickness T of the control passivation layer 20 exceeds 5 nm, the carrier does not move smoothly and the solar cell 100 may not operate. The thickness of the control passivation layer 20 may be less than or equal to 2 nm in order to make the movement of the carrier more smooth. When the thickness of the control passivation layer 20 is as thin as 2 nm or less, the carrier can be smoothly transferred and the fill factor (FF) of the solar cell 100 can be improved. If the thickness of the control passivation layer 20 is less than 1 nm, it may be difficult to form the control passivation layer 20 of desired quality. However, the present invention is not limited thereto, and the thickness of the control passivation layer 20 may have various values.

On the control passivation layer 20, a semiconductor layer 30 including conductive regions 32 and 34 may be located. As an example, the semiconductor layer 30 may be formed in contact with the control passivation layer 20 to simplify the structure. However, the present invention is not limited thereto.

In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, a second conductivity type region 32 having a second conductivity type dopant and exhibiting a second conductivity type, Type region 34. [0040] The first conductive type region 32 and the second conductive type region 34 may be coplanar on the control passivation layer 20. [ That is, no other layers are equally positioned between the first and second conductivity type regions 32 and 34 and the control passivation layer 20, or the first and second conductivity type regions 32 and 34 and the control passivation layer 20, If another layer is located between the layers 20, the other layers in the first and second conductivity type regions 32 and 34 may have the same lamination structure. And a barrier region 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34 on the same plane.

The first conductive type region 32 forms an emitter region for forming a carrier by photoelectric conversion by forming a pn junction (or a pn tunnel junction) with the base region 110 and the control passivation layer 20 interposed therebetween .

At this time, the first conductive type region 32 may include a semiconductor (for example, silicon) including a first conductive type dopant opposite to the base region 110. The first conductive type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the control passivation layer 20) and the first conductive type dopant Doped semiconductor layer. Accordingly, the first conductive type region 32 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first conductive type region 32 can be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the first conductive type dopant. The first conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the first conductive type region 32 may include a first conductive type dopant that can exhibit a conductive type opposite to the base region 110. That is, when the first conductivity type dopant is a p-type, a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. As an example, the first conductivity type dopant may be boron (B) having a p-type.

The second conductivity type region 34 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10) Thereby constituting a rear electric field area.

At this time, the second conductive type region 34 may include a semiconductor (e.g., silicon) including the same second conductive type dopant as the base region 110. The second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the control passivation layer 20) and the second conductivity type dopant 34 is formed on the semiconductor substrate 10 Doped semiconductor layer. Accordingly, the second conductive type region 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the second conductive type region 34 can be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the second conductive type dopant. The second conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the second conductive type region 34 may include a second conductive type dopant that can exhibit the same conductivity type as the base region 110. That is, when the second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. As an example, the second conductivity type dopant may be phosphorus (P) having n-type conductivity.

A barrier region 36 is positioned between the first conductive type region 32 and the second conductive type region 34 to separate the first conductive type region 32 and the second conductive type region 34 from each other. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductive type region 32 and the second conductive type region 34.

The barrier region 36 may comprise a variety of materials that can substantially insulate them between the first conductive type region 32 and the second conductive type region 34. That is, an undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used for the barrier region 36. Alternatively, the barrier region 36 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, , The barrier region 36 may be an i-type (intrinsic) semiconductor material substantially free of dopants. For example, a semiconductor layer containing a semiconductor material may be formed, and then a first conductive type dopant may be doped in a part of the semiconductor layer to form a first conductive type region 32, and a second conductive type dopant A region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 36. In this case, This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36.

However, the present invention is not limited thereto. Therefore, when the barrier region 36 is formed separately from the first conductivity type region 32 and the second conductivity type region 34, the thickness of the barrier region 36 is different from that of the first conductivity type region 32 and the second conductivity type region 34, Conductivity type region 34. [0060] For example, in order to more effectively prevent shorting of the first conductive type region 32 and the second conductive type region 34, a barrier region 36 is formed between the first conductive type region 32 and the second conductive type region 34 ). ≪ / RTI > Alternatively, the thickness of the barrier region 36 may be made smaller than the thickness of the first conductivity type region 32 and the second conductivity type region 34 in order to reduce the raw material for forming the barrier region 36. Of course, various modifications are possible. In addition, the basic constituent material of the barrier region 36 may include a material different from the first conductive type region 32 and the second conductive type region 34.

In this embodiment, the barrier region 36 is entirely spaced apart from the first conductivity type region 32 and the second conductivity type region 34. However, the present invention is not limited thereto. Therefore, the barrier region 36 may be formed to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. According to this, other portions of the boundaries of the first conductivity type region 32 and the second conductivity type region 34 may be in contact with each other.

Here, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 can be wider than the area of the second conductivity type region 34 having the same conductivity type as that of the base region 110 have. Thus, the pn junction formed through the control passivation layer 20 between the base region 110 and the first conductive type region 32 can be made wider. At this time, when the base region 110 and the second conductivity type region 34 have the n-type conductivity and the first conductivity type region 32 has the p-type conductivity, the first conductivity type region It is possible to effectively collect holes having a relatively slow moving speed by the electron beam 32. [ The planar structure of the first conductive type region 32, the second conductive type region 34, and the barrier region 36 will be described later in detail with reference to FIG.

The rear passivation film 40 may be formed on the first and second conductivity type regions 32 and 34 and the barrier region 36 on the rear surface of the semiconductor substrate 10. [ For example, the rear passivation film 40 may be formed in contact with the first and second conductivity type regions 32 and 34 and the barrier region 36 to simplify the structure. However, the present invention is not limited thereto.

The rear passivation film 40 has openings 402 and 404 for electrical connection between the conductive regions 32 and 34 and the electrodes 42 and 42. The openings 402 and 404 include a first opening 402 for connecting the first conductivity type region 32 and the first electrode 42 and a second opening 403 for connecting the second conductivity type region 34 and the second electrode 44, And a second opening 404 for connection with the second opening 404. As a result, the rear passivation film 40 is formed in the same manner as that of the first conductive type region 32 and the second conductive type region 34 in the case of the electrode to which the first conductive type region 32 and the second conductive type region 34 should not be connected 44 in the case of the second conductivity type region 34 and the first electrode 42 in the case of the second conductivity type region 34). In addition, the back passivation film 40 may have the effect of passivating the first and second conductivity type regions 32, 34 and / or the barrier region 36.

The back passivation film 40 may be a single film or a multilayer film including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, and the like.

The rear passivation film 40 may be positioned on the semiconductor layer 30 at a portion not located at the electrodes 42 and 44. [ The back passivation film 40 may have a thickness that is thicker than the control passivation layer 20. As a result, the insulating characteristics and the passivation characteristics can be improved. Various other variations are possible.

For example, in the present embodiment, the front passivation film 24 and / or the antireflection film 26 and the rear passivation film 40 may not include a dopant or the like so as to have excellent insulating properties, passivation properties, and the like.

Electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 include a first electrode 42 electrically and physically connected to the first conductivity type region 32 and a second electrode 42 electrically connected to the second conductivity type region 34 And a second electrode 44 electrically and physically connected.

The first and second electrodes 42 and 44 may include various metal materials. The first and second electrodes 42 and 44 are connected to the first conductive type region 32 and the second conductive type region 34 without being electrically connected to each other, And can have a variety of planar shapes. That is, the present invention is not limited to the planar shapes of the first and second electrodes 42 and 44.

1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 36, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. Barrier regions 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34 as described above. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . Various other variations are possible. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

1, a front passivation film 24 and / or an antireflection film (not shown) are formed on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) 26) can be located. Only the front passivation film 24 may be formed on the semiconductor substrate 10 or only the antireflection film 26 may be formed on the semiconductor substrate 10 or the front passivation film 26 may be formed on the semiconductor substrate 10. [ The antireflection film 24 and the antireflection film 26 may be sequentially disposed. The front passivation film 24 and the antireflection film 26 are sequentially formed on the semiconductor substrate 10 so that the semiconductor substrate 10 is contacted with the front passivation film 24. However, the present invention is not limited thereto, and the semiconductor substrate 10 may be formed in contact with the anti-reflection film 26, and various other modifications are possible.

The front passivation film 24 and the antireflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. [ Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.

The front passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate defects existing in the front surface or bulk of the semiconductor substrate 10. [ Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductive type region 32 can be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. As described above, the open-circuit voltage and the short-circuit current of the solar cell 100 can be increased by the front passivation film 24 and the anti-reflection film 26, thereby improving the efficiency of the solar cell 100.

The front passivation film 24 and / or the antireflection film 26 may be formed of various materials. For example, the front passivation film 24 and / or the antireflection film 26 may include a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO ₂ , ₂ , or a multilayer film structure in which two or more films are combined. For example, the front passivation film 24 may be a silicon oxide layer formed on the semiconductor substrate 10, and the antireflection film 26 may have a structure in which a silicon nitride layer and a silicon carbide layer are sequentially stacked.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by the photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, And electrons pass through the control passivation layer 20 and move to the first and second electrodes 42 and 44 after moving to the first conductivity type region 32 and the second conductivity type region 34, respectively. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front of the display device. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto.

In this embodiment, the control passivation layer 20, which is a protective film located on the semiconductor substrate 10, is formed with good quality. This will be described in detail in the method of manufacturing the solar cell 100 according to the embodiment of the present invention with reference to FIGS. 3A to 3F. The detailed description will be omitted for the ones described above and the details not described will be described in detail.

3A to 3F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 3A, a control passivation layer 20, which is a passivation layer, is formed on the rear surface of a semiconductor substrate 10 including a base region 110 having a second conductive dopant. In this embodiment, the control passivation layer 20 is formed including a step of heat-treating in a gas atmosphere containing a halogen gas having a halogen element at a relatively high temperature.

This will be described in more detail with reference to FIG. 3A and FIG. 4 and FIG. 4 is an example of a heat treatment apparatus in which a heat treatment process can be performed in the method of manufacturing a solar cell according to the present embodiment. 5 is a view showing a temperature cycle of a heat treatment process in a method of manufacturing a solar cell according to an embodiment of the present invention.

The process of forming the control passivation layer 20 in this embodiment can be performed by placing a plurality of semiconductor substrates 10 in the heat treatment apparatus 200 and then performing a heat treatment process together. At this time, the semiconductor substrates 10 are positioned parallel to each other with a distance d in the heat treatment apparatus 200, so that the thermal oxidation process in the heat treatment process can be sufficiently performed. In one example, the distance d between the semiconductor substrates 10 may be 1 mm to 5 mm. If the distance d between the semiconductor substrates 10 is less than 1 mm, the control passivation layer 20 may not be uniformly formed due to stagnation of the gas flow. If the distance d between the semiconductor substrates 10 is more than 5 mm, the number of semiconductor substrates 10 that can be processed in one heat treatment process is not enough, and the productivity may be lowered. However, the present invention is not limited thereto, and the interval d between the semiconductor substrates 10 can be adjusted to have various values.

For example, the heat treatment apparatus 200 may include a step of heat-treating at a heat treatment temperature (T) of 600 ° C. or higher (more specifically, 600 ° C. to 900 ° C.) in a heat treatment apparatus 200 and a gas atmosphere containing a halogen gas and a raw material gas The control passivation layer 20 can be formed. Here, the heat treatment temperature may mean a temperature at which the semiconductor substrate 10 is uniformly held for a predetermined time for forming the control passivation layer 20 after the semiconductor substrate 10 is introduced into the heat treatment apparatus 200. The inflow temperature T 1 when the semiconductor substrate 10 enters the heat treatment apparatus 200 and the outflow temperature T 1 when the semiconductor substrate 10 on which the control passivation layer 20 is formed go out of the heat treatment apparatus 200 T2) may have a temperature different from the heat treatment temperature.

More specifically, the semiconductor substrate 10 is introduced into the interior of the heat treatment apparatus 200 at the inflow temperature T1 and the temperature is raised from the inflow temperature T1 to the heat treatment temperature T in the temperature rise period S1 . Then, heat treatment is performed at the heat treatment temperature T in the main section S2. In the temperature lowering period S3, the temperature decreases from the heat treatment temperature T to the outflow temperature T2, and the semiconductor substrate 10 flows out of the heat treatment apparatus 200 at the outflow temperature T2. The inflow temperature T1 and the outflow temperature T2 can be made lower than the heat treatment temperature T to prevent deterioration in the quality of the semiconductor substrate 10 and the control passivation layer 20 due to the abrupt temperature change.

When the heat treatment is performed with the halogen gas at the heat treatment temperature T that is relatively high in the main section S2 (that is, 600 ° C or more), the halogen gas adsorbs the impurity particles during the heat treatment process, 20) and the interface trap density (Dit) can be reduced and the film density can be improved. Thus, the quality of the control passivation layer 20 formed by the heat treatment process can be improved.

The adsorption effect of the halogen gas on the impurity particles may be large at a heat treatment temperature (T) of 600 ° C or higher and hardly occur at a heat treatment temperature of less than 600 ° C. In addition, at a temperature lower than 600 deg. C, the halogen gas remains without decomposition, and the halogen gas having toxicity may be discharged to the outside after the heat treatment step. If the heat treatment temperature T in the formation of the control passivation layer 20 exceeds 900 캜, there arises a problem such as installation burden and manufacturing cost increase due to a high heat treatment temperature, and it is difficult to control the thickness of the control passivation layer 20 The thickness distribution of the control passivation layer 20 can be increased. At this time, the heat treatment temperature (T) may be 650 ° C or higher so as to further improve the adsorption effect of the impurity particles of the halogen gas and improve the process stability. And the heat treatment temperature (T) may be 850 DEG C or less so as to reduce the burden due to the high temperature process.

In this embodiment, the inflow temperature T1 may be 550 占 폚 or less (for example, 400 占 폚 to 550 占 폚, more specifically, 500 占 폚 to 550 占 폚). If the inflow temperature T1 is less than 400 占 폚, the process time of the temperature rise period S1 may increase or the quality of the semiconductor substrate 10 may deteriorate due to a rapid temperature rise. If the inflow temperature T1 exceeds 550 deg. C, the control passivation layer 20 may be formed on the semiconductor substrate 10 even when the semiconductor substrate 10 is introduced, so that the thickness of the control passivation layer 20 may be controlled It can be difficult. Considering the process time more, the inlet temperature may be 500 ° C to 550 ° C.

And the outflow temperature T2 may be 550 占 폚 or lower (for example, 400 占 폚 to 550 占 폚, more specifically, 500 占 폚 to 550 占 폚). If the outlet temperature T2 is less than 400 DEG C, the process time of the temperature lowering period S3 can be increased. If the outflow temperature T2 exceeds 550 deg. C, the semiconductor substrate 10 and the control passivation layer 20 undergo a large temperature change after they are discharged from the heat treatment apparatus 200, which may cause problems such as quality deterioration . In consideration of the process time, the outlet temperature (T2) may be 500 ° C to 550 ° C.

However, the present invention is not limited thereto, and the inflow temperature T1 and the outflow temperature T2 may have different values.

The halogen element contained in the halogen gas used in the main section S2 may include at least one of fluorine, chlorine, bromine, iodine, astatine, and uninseptium. This is because the halogen element has an excellent effect of adsorbing impurities in the process of forming the control passivation layer 20 as described above. In particular, using chlorine as a halogen element, the halogen gas may contain chlorine. Chlorine-containing halogen gases are readily available and many equipment has been developed to use them. Reactivity is excellent, and relatively safe use is possible. In one example, the halogen gas containing chlorine may include at least one of Cl ₂ , C ₂ H ₂ Cl _2, and HCl, and in particular may be at least one of Cl ₂ , C ₂ H ₂ Cl ₂ . On the other hand, halogen gases containing fluorine may have certain limitations in that they are used because of their etching properties. And halogen gases including bromine, iodine, astatine and uninseptium are difficult to obtain easily, and iodine, asasine and ununsepthium may release radioactivity under certain conditions.

At this time, since the halogen gas may increase the growth rate of the control passivation layer 20, the halogen gas may be contained in an amount equal to or less than the oxygen gas. In one example, the volume ratio of oxygen gas: halogen gas may be 1: 0.01 to 1: 1. If the ratio is less than 1: 0.01, the effect of increasing the purity by the chlorine gas may not be sufficient. If the ratio is more than 1: 1, chlorine gas is contained in an amount larger than the required amount, so that the purity of the control passivation layer 20 may be lowered and the growth rate may be increased to increase the thickness of the control passivation layer 20 . However, the present invention is not limited thereto and various modifications are possible.

In this embodiment, the gas atmosphere in the heat-treating step may include a raw material gas in addition to the halogen gas. Then, the control passivation layer 20 can be formed by thermal oxidation in a heat treatment process performed at a high temperature. Then, the control passivation layer 20 can be formed only by the heat treatment process without adding a separate process, thereby simplifying the manufacturing process. In this embodiment, the raw material gas includes oxygen gas and the control passivation layer 20 may be composed of an oxide layer. That is, a layer of thermal oxide (e.g., a thermal silicon oxide) in which oxygen and a semiconductor material (e.g., silicon) of the semiconductor substrate 10 are formed by reaction at a high temperature can constitute the control passivation layer 20 have.

The gas atmosphere in the heat treatment process may include various gases other than the oxygen gas as the raw material gas. For example, the gas atmosphere may further include nitrogen gas. The nitrogen gas is involved in controlling the growth rate of the control passivation layer 20 and in controlling the uniformity of the control passivation layer 20 associated with leakage current and dopant penetration. The amount of nitrogen gas may be adjusted considering the size of the chamber in which the control passivation layer 20 is formed. The total amount of halogen gas, oxygen gas and nitrogen gas can be adjusted to have the required pressure.

In this embodiment, the heat treatment apparatus 200 for performing the heat treatment process may be a general heat treatment furnace in which the pressure is difficult to control, a chemical vapor deposition (CVD), a heat treatment at a pressure lower than normal pressure Pressure chemical vapor deposition (LPCVD) apparatus capable of carrying out the process.

If the control passivation layer 20 is formed by a thermal annealing process in a general annealing furnace, the control passivation layer 20 can be easily grown to form the control passivation layer 20 in a short time , The process time can be shortened.

The chemical vapor deposition apparatus or the low pressure chemical vapor deposition apparatus may be suitable for maintaining the desired process conditions. For example, when the control passivation layer 20, which is a protective layer, is formed by performing a heat treatment process in a low-pressure chemical vapor deposition apparatus, the heat treatment process can be performed under a pressure lower than the atmospheric pressure, The thickness can be easily adjusted to uniformly form the control passivation layer 20. Here, the pressure may refer to the pressure inside the production apparatus of the control passivation layer 20 as the pressure including all of the other gases together with the raw material gas.

In this case, even when a chemical vapor deposition apparatus or a low-pressure chemical vapor deposition apparatus is used, the raw material gas does not contain all the raw materials constituting the control passivation layer 20, and oxygen contained in the oxide constituting the control passivation layer 20 It contains only gas and does not contain other raw materials. For example, when the control passivation layer 20 is made of a silicon oxide layer, it does not include a gas containing silicon as raw material but only oxygen gas as the raw material gas. The control passivation layer 20 is formed by a thermal oxidation process in which oxygen of the oxygen gas diffuses into the semiconductor substrate 10 and reacts with the semiconductor material. Alternatively, silane (SiH ₄ ) gas containing silicon is supplied together with an oxygen-containing oxygen gas into a raw material gas in a deposition process or the like. Then, oxygen separated from oxygen gas by thermal decomposition and silicon separated from the silane gas chemically react to form silicon oxide.

As described above, when the control passivation layer 20 is formed by a thermal oxidation process at a high temperature, the thickness of the control passivation layer 20 can be easily increased. The formation of the control passivation layer 20 at atmospheric pressure or lower in the chemical vapor deposition equipment or the low pressure chemical vapor deposition equipment prevents the thickness of the control passivation layer 20 from rapidly increasing (the control passivation layer 20) The control passivation layer 20 can have a uniform and thin overall thickness.

At this time, if the pressure is maintained at 760 Torr or less (pressure lower than atmospheric pressure or atmospheric pressure), even if the control passivation layer 20 is formed by a thermal oxidation process at a relatively high temperature, the growth of the control passivation layer 20 The speed can be maintained at a certain level. Thus, the thickness of the control passivation layer 20 can be greatly reduced.

More specifically, the pressure may be from 1 Torr to 760 Torr (e.g., from 100 Torr to 760 Torr). If the temperature is less than 1 Torr in forming the control passivation layer 20, the cost for maintaining the pressure is large and the manufacturing cost of the control passivation layer 20 may be increased. Considering growth rate and cost, the pressure at forming the control passivation layer 20 may be between 1 Torr and 700 Torr, more specifically between 1 Torr and 600 Torr, for example between 100 Torr and 600 Torr. However, the present invention is not limited thereto, and the pressure and the like at the time of forming the control passivation layer 20 may be changed.

On the other hand, in the conventional semiconductor field, there is no need for a thin oxide layer in which a carrier can move like a control passivation layer of a solar cell. That is, in the semiconductor field or the like, it is not necessary to form the oxide layer with a thickness enough to allow the carrier to pass therethrough, only the oxide layer is adjusted in thickness within the range that the carrier does not pass through. In addition, since the purity of the control passivation layer does not significantly affect the characteristics of semiconductor devices and the like, it is difficult to propose a method for increasing the purity.

On the other hand, as described above, the present embodiment includes a heat treatment process performed in a gas atmosphere including a high heat treatment temperature T and a halogen gas (in particular, by a thermal oxidation process performed during the heat treatment process) The film density, the thickness, etc. of the control passivation layer 20 can be adjusted by forming the passivation layer 20.

At this time, if the thermal oxidation is performed at atmospheric pressure or lower pressure in the chemical vapor deposition apparatus or the low pressure chemical vapor deposition apparatus, the control passivation layer 20 can be formed thinly and uniformly by controlling the growth rate of the control passivation layer 20 have. In addition, since the semiconductor layer (reference numeral 300 in FIG. 3B) formed on the control passivation layer 20 is formed by the deposition equipment according to the embodiment, when the control passivation layer 20 is formed in the deposition equipment, the control passivation layer 20 And the semiconductor layer 300 may be formed by an in-situ process that is performed continuously in the same deposition equipment (e.g., low-pressure chemical vapor deposition equipment). If the control passivation layer 20 and the semiconductor layer 300 are formed by the in-situ process, the manufacturing process can be greatly simplified, and manufacturing cost, manufacturing time, and the like can be greatly reduced.

The temperature in the deposition equipment is controlled by heating for a long period of time or by cooling the heat and it takes a long time to stabilize the temperature while the gas atmosphere and pressure are controlled by the type, amount and so on of the gas supplied into the deposition equipment . Therefore, the gas atmosphere and the pressure can be controlled more easily than the temperature.

In consideration of this, in this embodiment, the temperature difference between the formation temperature of the control passivation layer 20 and the deposition process of the semiconductor layer 300 may be within 200 ° C. (ie, 0 ° C. to 200 ° C.). More specifically, the temperature difference between the formation temperature of the control passivation layer 20 and the deposition process of the semiconductor layer 300 can be set to be within 100 ° C. (ie, from 00 ° C. to 100 ° C.). This is because the formation of the control passivation layer 20 at an atmospheric pressure or a lower pressure can relatively increase the formation temperature of the control passivation layer 20, thereby reducing the temperature difference between the semiconductor passivation layer 20 and the deposition process. In this way, the relatively difficult temperature can be maintained without a large change, and the efficiency of the in-situ process for continuously forming the control passivation layer 20 and the semiconductor layer 300 can be further improved. On the other hand, the gas atmosphere in the deposition process of the semiconductor layer 300 is different from the gas atmosphere in the formation of the control passivation layer 20, and the pressure in the deposition process of the semiconductor layer 300 is different from that in the formation of the control passivation layer 20 It may be equal to or different from the pressure.

However, the present invention is not limited thereto, and the control passivation layer 20 and the semiconductor layer 300 may be formed in a separate process, apparatus, or the like.

Although the control passivation layer 20 is formed only on the rear surface of the semiconductor substrate 10, the present invention is not limited thereto. A control passivation layer 20 may also be additionally formed on the front and / or sides of the semiconductor substrate 10, depending on the method of fabricating the control passivation layer 20. The control passivation layer 20 formed on the front surface of the semiconductor substrate 10 can be removed at a later stage.

In the temperature cycle of FIG. 5, the heat treatment process for forming the protective film is performed alone, but the present invention is not limited thereto. Therefore, it is possible to perform the subsequent process (for example, the process of forming the semiconductor layer 300) or the like without forming the control passivation layer 20 as a protective film and removing the control passivation layer 20 from the thermal processing apparatus 200 have. In this case, the temperature lowering period S3 may not be performed depending on the temperature of the subsequent process. Alternatively, a heat treatment process may be continuously performed in an apparatus in which a process before the formation of the protective film is performed. In this case, the temperature rising period S1 may not be performed depending on the temperature of the previous process.

3B to 3D, a semiconductor layer 30 including the first and second conductive type regions 32 and 34 is formed on the control passivation layer 20, and the semiconductor substrate 10 is formed on the control passivation layer 20, The texturing structure and the front electric field area 130 may be formed on the entire surface of the substrate 110. [ This is formed more specifically.

First, a semiconductor layer 300 having a crystalline structure and having intrinsic properties is formed on the control passivation layer 20 formed on the rear surface of the semiconductor substrate 10, as shown in FIG. 3B. The semiconductor layer 300 may be composed of a microcrystalline, amorphous, or polycrystalline semiconductor. The semiconductor layer 300 may be formed, for example, by a thermal growth method, a chemical vapor deposition method (for example, a plasma chemical vapor deposition method, a low pressure chemical vapor deposition method), or the like. However, the present invention is not limited thereto, and the semiconductor layer 300 may be formed by various methods.

As an example, in this embodiment, intrinsic semiconductor layer 300 may be formed by chemical vapor deposition, and more specifically by low pressure chemical vapor deposition. Accordingly, the intrinsic semiconductor layer 300 can be formed by the in-situ process with the control passivation layer 20 as described above. However, the present invention is not limited thereto, and the in-situ process may not be applied to the control passivation layer 20 and the semiconductor layer 300.

The gas used in the deposition process of the semiconductor layer 300 may include a gas (for example, a silane gas) including a semiconductor material constituting the semiconductor layer 300. In this embodiment, since the semiconductor layer 300 is deposited so as to have intrinsic properties, the gas atmosphere can be composed only of a gas containing a semiconductor material. Thus, the supply gas can be simplified and the purity of the semiconductor layer 300 to be formed can be improved. However, the present invention is not limited thereto. A separate gas or the like may be further used to promote the deposition process of the semiconductor layer 300 or to improve the characteristics of the semiconductor layer 300. In addition, when doping the first and second conductive dopants together in the deposition process of the semiconductor layer 300, a gas containing the first or second conductive dopant (for example, B ₂ H ₆ , PH _3, etc.).

In addition, in the deposition process of the semiconductor layer 300, nitrogen dioxide (N ₂ O) gas and / or oxygen (O ₂ ) gas may be injected together with a gas including a semiconductor material to control the grain size, crystallinity, and the like.

The deposition temperature of the semiconductor layer 300 may be equal to or less than the temperature at which the control passivation layer 20 is formed. Particularly, when the deposition temperature of the semiconductor layer 300 is made lower than the temperature at the time of formation of the control passivation layer 20, the characteristics of the semiconductor layer 300 directly involved in photoelectric conversion can be made uniform. Alternatively, the deposition temperature of the semiconductor layer 300 may be 500 ° C to 700 ° C. This is limited to a temperature suitable for depositing the semiconductor layer 300 having a crystal structure different from that of the semiconductor substrate 10. Particularly, in the case where the semiconductor layer 300 is not doped, as in the present embodiment, the deposition rate of the semiconductor layer 300 may be 600 ° C. to 700 ° C. since the reaction rate is relatively lower than that in the case of doping. Accordingly, the deviation from the temperature at the time of forming the control passivation layer 20 can be further reduced.

As described above, since the temperature of the control passivation layer 20 is equal to or similar to the deposition temperature of the semiconductor layer 300, the time for adjusting the temperature and the time for stabilizing the temperature are not required, can do.

Although the semiconductor layer 300 is formed only on the rear surface of the semiconductor substrate 10, the present invention is not limited thereto. The semiconductor layer 300 may be additionally formed on the front surface and / or the side surface of the semiconductor substrate 10 according to the method of manufacturing the semiconductor layer 300. [ The semiconductor layer 300 formed on the front surface of the semiconductor substrate 10 may be removed at a later stage.

3C to 3D, the front surface of the semiconductor substrate 10 is textured to form irregularities on the front surface of the semiconductor substrate 10 and the first and second conductivity type regions 32 and 34, The electric field area 130 can be formed.

For example, as shown in FIG. 3C, a first conductive type dopant is doped in a part of the semiconductor layer 300 to form a first conductive type region 32, and as shown in FIG. 3D, The front conductive layer 130 and the second conductive type region 34 may be formed by texturing the front surface of the semiconductor substrate 10 and doping a second conductive type dopant on the entire surface of the semiconductor substrate 10 and another portion of the semiconductor layer 300 . At this time, an undoped region, which is not doped with a dopant, may be positioned between the first conductive type region 32 and the second conductive type region 34, and this region may constitute the barrier region 36.

Various methods known as a doping process for forming the first and second conductivity type regions 32 and 34 and the front electric field region 130 can be used. For example, various methods such as an ion implantation method, a thermal diffusion method by heat treatment using a gas containing a dopant, a heat treatment method performed after forming the doping layer, and a laser doping method may be applied. The present invention is not limited thereto.

Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be uniformly formed, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

In this embodiment, after the semiconductor layer 300 is formed, the entire surface of the semiconductor substrate 10 having the first conductivity type region 32 is textured, and the front electric field region 130 and the second conductivity type region 34 ) Were formed together in the same doping process. However, the present invention is not limited thereto. Accordingly, the formation order of the first conductive type region 32, the second conductive type region 34, the front electric field region 130, and the texturing structure can be variously modified. The second conductive type region 34 and the front electric field region 130 may be formed by different doping processes.

Next, another protective film is formed on the front and rear surfaces of the semiconductor substrate 10, as shown in Fig. 3E. That is, a front passivation film 24 and an antireflection film 26 are formed on the entire surface of the semiconductor substrate 10, and a rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10.

 More specifically, the front passivation film 24 and the antireflection film 26 are entirely formed on the front surface of the semiconductor substrate 10, and the rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10 as a whole. The front passivation film 24, the antireflection film 26 or the rear passivation film 40 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating. The order of forming the front passivation film 24, the antireflection film 26, and the rear passivation film 40 is not limited.

Next, as shown in FIG. 3F, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed.

For example, the first and second openings 402 and 404 are formed in the rear passivation film 40 by the patterning process, and then the first and second openings 402 and 404 are formed while filling the first and second openings 402 and 404, The second electrodes 42 and 44 are formed. At this time, the first and second openings 402 and 404 may be formed by laser ablation using a laser, or various methods using an etching solution or an etching paste. The first and second electrodes 42 and 44 may be formed by various methods such as a plating method and a deposition method.

Alternatively, the first and second electrode forming pastes may be applied on the rear passivation film 40 by screen printing or the like, and then fire through or laser firing contact may be performed to form the above- The first and second electrodes 42 and 44 may be formed. In this case, since the first and second openings 402 and 404 are formed when the first and second electrodes 42 and 44 are formed, the process of forming the first and second openings 402 and 404 separately You do not need to add it.

The control passivation layer 20 is formed by performing a heat treatment process performed at a heat treatment temperature of 600 ° C to 900 ° C and a gas atmosphere containing a halogen gas to form a control passivation layer 20 having a purity and a film density And the interface trap concentration can be lowered. Accordingly, the passivation property of the control passivation layer 20 can be improved, and the efficiency of the solar cell 100 can be improved by smoothly passing the carriers. In addition, such a control passivation layer 20 can maintain excellent quality and characteristics in a process that is subsequently performed at high temperature. Accordingly, the process temperature of a process (for example, a doping process) performed subsequently at a high temperature can be freely selected, and the efficiency of the solar cell 100 can be further improved. The control passivation layer 20 and the semiconductor layer 30 may be formed of a continuous passivation layer 20 in the case of forming the control passivation layer 20 at a temperature similar to that of the semiconductor layer 30 to be formed after the control passivation layer 20, So that the manufacturing process can be simplified.

A modification of the embodiment of the manufacturing method of the solar cell 100 described above will be described in detail with reference to Figs. 6A and 6B. 3A to FIG. 3F, FIG. 4, and FIG. 5, the detailed description thereof will be omitted and the other portions will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

6A and 6B are cross-sectional views illustrating steps of forming a control passivation layer in a method of manufacturing a solar cell according to a modification of the present invention.

Referring to FIGS. 6A and 6B, the control passivation layer 20, which is a passivation layer formed on the semiconductor substrate 10 in this modification, may be a passivation layer formed by performing a heat treatment process after forming the passivation layer 200.

That is, as shown in FIG. 6A, the preliminary protective film 200 is formed on the semiconductor substrate 10. The preliminary protective film 200 can use various processes that are performed at a temperature equal to or lower than the heat treatment process (i.e., a temperature of 600 DEG C or lower). In this way, the preliminary protective film 200 is formed at a lower temperature than the heat treatment process, thereby preventing a process performed at a high temperature from being added, thereby reducing the burden on the process.

As an example, the preliminary protective film 200 may be formed by a wet chemical process using a wet chemical solution. In the wet chemical process, a wet chemical solution is applied or positioned to form a preliminary protective film 200 having a thinner and / or lower film density on the surface of the semiconductor substrate 10 than the control passivation layer 20. The wet chemical solution may include various solutions capable of reacting with the semiconductor substrate 10 to form the preliminary protective film 200 on the surface of the semiconductor substrate 10. As an example, the wet chemical solution may be hydrochloric acid (HCl), hydrogen peroxide (H ₂ O ₂ ), or a mixture thereof. This is because such a solution reacts with the semiconductor substrate 10 to form the preliminary protective film 200 composed of an oxide easily on the semiconductor substrate 10.

Alternatively, the preliminary protective film 200 may be formed by a dry process (for example, vapor deposition (for example, chemical vapor deposition or low pressure chemical vapor deposition) or the like.

Then, as shown in FIG. 6B, the preliminary protective film 200 is subjected to a heat treatment process to form the control passivation layer 20. Next, as shown in FIG. Since the heat treatment process is the same as or very similar to the heat treatment process described with reference to FIGS. 3A, 4, and 5, the description with reference to FIGS. 3A, 4, and 5 can be applied as it is. However, the heat treatment process with reference to FIG. 6B does not necessarily include oxygen gas, and it is also possible to perform the heat treatment without oxygen gas, unlike the heat treatment process shown in FIG.

As described above, in this modification, the passivation layer 20 is formed by first forming the passivation layer 200 having a thinner thickness and / or a lower film density than the control passivation layer 20, and then performing a heat treatment process. Then, the uniformity of the control passivation layer 20 and the film density can be improved. 6A can be performed together with the step of forming the protective protective film 200 shown in FIG. 6A in the cleaning step of the semiconductor substrate 10 without separately performing the step of forming the protective protective film 200 shown in FIG. 6A. Then, the process of forming the preliminary protective film 200 shown in FIG. 6A can be performed without adding a separate process, so that the process can be performed by a simple manufacturing process.

In the above description and drawings, it is exemplified that a heat treatment process is performed after the process of forming the oxide film 200 to form the control passivation layer 20. However, it is also possible to carry out another heat treatment process (for example, a process of forming the semiconductor layer 300 shown in FIG. 3B, a doping process shown in FIG. 3D, The heat treatment process shown in FIG. 6B may be performed at the time of the heat treatment process performed in the heat treatment process, the electrode formation process, and the like. However, the present invention is not limited thereto.

In the above-described embodiment, when the first and second conductivity type regions 32 and 34 are located separately on the semiconductor substrate 10 from the rear surface of the semiconductor substrate 10, The formation of the control passivation layer 20 including the above-described heat treatment process has been illustrated. However, the present invention is not limited thereto. For example, at least one of the front passivation film 24 formed on the semiconductor substrate 10 and the rear passivation film 40 formed on the semiconductor layer 30 (or the conductive regions 32 and 34) May be a protective film formed by a process including a process. Further, another example of the protective film that can be manufactured including the above-described heat treatment process will be described in detail with reference to FIGS. 7 and 8. FIG. Since the above description can be applied to the same or extremely similar parts as the above description, the detailed description will be omitted and only the different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

7 is a cross-sectional view showing another example of a solar cell manufactured by the method for manufacturing a solar cell according to an embodiment of the present invention. 8 is a schematic plan view of the solar cell shown in Fig.

7, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, conductive regions 32 and 34 formed in the semiconductor substrate 10, Front and rear passivation films 24 and 40 as protection films formed on the semiconductor substrate 10 and electrodes 42 and 44 connected to the conductive type regions 32 and 34 through the rear passivation film 40 . At this time, at least one of the front and rear passivation films 24 and 40, which is a protective film formed on the semiconductor substrate 10, may be formed by a manufacturing method including a heat treatment process according to the present embodiment.

More specifically, the conductive regions 32 and 34 are located on the front side of the semiconductor substrate 10 and include a first conductive type region 32 having a first conductive type and a second conductive type region 32 positioned on the rear side of the semiconductor substrate 10, And a second conductivity type region 34 having a conductivity type. The electrodes 42 and 44 may include a first electrode 42 connected to the first conductive type region 32 and a second electrode 44 connected to the second conductive type region 34. The passivation film formed on the semiconductor substrate 10 is formed on the front passivation film 24 formed on the front surface of the semiconductor substrate 10 on the first conductive type region 32 and on the semiconductor substrate 10 10 formed on the back surface of the passivation film 40. And an antireflection film 26 located on the front passivation film 24. [

In this embodiment, the conductive regions 32 and 34 are formed by doping the semiconductor substrate 10 with a dopant to constitute a doped region constituting a part of the semiconductor substrate 10. [ The base region 110 and the conductive regions 32 and 34 constituting the semiconductor substrate 10 can be defined by the kind and concentration of the dopant included therein. For example, in the semiconductor substrate 10, a region including a first conductive type dopant and having a first conductivity type is defined as a first conductive type region 32, and a second conductive type dopant is included at a low doping concentration A region having a second conductivity type is defined as a base region 110 and a region having a second conductivity type is doped with a doping concentration higher than that of the base region 110 in the second conductivity type region 34 ). ≪ / RTI > That is, the base region 110 and the conductive regions 32 and 34 are regions having a crystal structure of the semiconductor substrate 10 and different conductivity types and doping densities.

The first conductivity type dopant included in the first conductivity type region 32 may be an n type or a p type dopant and the second conductivity type dopant included in the base region 110 and the second conductivity type region 34 May be a p-type or n-type dopant having a conductivity type opposite to the first conductivity type of the first conductivity type region (32). As for the p-type or n-type dopant, the contents described in the above-described embodiments can be applied as they are.

For example, the first conductivity type region 32 may have a p-type, the base region 110 and the second conductivity type region 34 may have an n-type. When the pn junction formed by the first conductivity type region 32 and the base region 110 is irradiated with light, electrons generated by the photoelectric effect move toward the rear surface of the semiconductor substrate 10, And holes are collected toward the front side of the semiconductor substrate 10 and collected by the first electrode 42. Thereby, electric energy is generated. Then, holes having a slower moving speed than electrons can be moved to the front surface of the semiconductor substrate 10, not the rear surface, thereby improving the conversion efficiency. However, the present invention is not limited thereto, and it is also possible that the base region 110 and the second conductivity type region 34 have a p-type and the first conductivity type region 32 has an n-type.

In the drawing, the front and back surfaces of the semiconductor substrate 10 are each provided with concave and convex portions by texturing. However, the present invention is not limited thereto. Therefore, it is possible to form irregularities by texturing on either the front surface or the rear surface of the semiconductor substrate 10, or to prevent the irregularities due to texturing from being formed on the front surface and the rear surface of the semiconductor substrate 10.

In this embodiment, at least one of the front passivation film 24 and the rear passivation film 40, which are protective films formed on the front surface and the rear surface of the semiconductor substrate 10, may be a protective film formed by the heat treatment process according to the present embodiment have. For example, the passivation films 24 and 40 formed on the regions having the n-type conductivity among the conductive regions 32 and 34 may be a protective film including the heat treatment process according to the present embodiment. The protective film formed by the heat treatment process according to this embodiment is formed of a silicon oxide layer because the silicon oxide layer has a fixed positive charge and is suitable for n-type passivation. However, the present invention is not limited thereto.

For example, when the second conductive type region 34 has an n-type, the rear passivation film 40 positioned (e.g., in contact with) the rear surface of the semiconductor substrate 10 includes the heat treatment process according to the present embodiment Or the like. This rear passivation film 40 may have a thickness of 2 nm to 10 nm (for example, 3 nm to 6 nm). If the thickness of the rear passivation film 40 is less than 2 nm, the passivation property may not be excellent, and if it is more than 10 nm, the processing time may be increased. In consideration of the passivation characteristic and the process time, the thickness of the rear passivation film 40 may be 3 nm to 6 nm. However, the present invention is not limited to the thickness of the rear passivation film 40.

The front passivation film 24 and / or the antireflection film 26 may be formed of various materials as described in the above embodiments. A description thereof will be omitted.

However, the present invention is not limited thereto, and the front passivation film 24 having the n-type conductivity of the first conductivity type region 32 may be formed by the heat treatment process according to the present embodiment. Alternatively, the front passivation film 24 and / or the rear passivation film 40 can be formed by the heat treatment process according to the present embodiment regardless of the conductive type. Various other variations are possible.

Referring to FIG. 8, the first and second electrodes 42 and 44 may include a plurality of finger electrodes 42a and 44a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a and 44a are parallel to each other and parallel to the edge of the semiconductor substrate 10, the present invention is not limited thereto. The first and second electrodes 42 and 44 may include bus bar electrodes 42b and 44b formed in a direction crossing the finger electrodes 42a and 44a to connect the finger electrodes 42a and 44a. have. Only one bus electrode 42b or 44b may be provided or a plurality of bus electrodes 42b and 44b may be provided with a larger pitch than the pitch of the finger electrodes 42a and 44a as shown in FIG. At this time, the width of the bus bar electrodes 42b and 44b may be larger than the width of the finger electrodes 42a and 44a, but the present invention is not limited thereto and may have the same or small width.

The finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be formed to penetrate the front passivation film 24 and the antireflection film 26, That is, the first opening 402 may be formed corresponding to both the finger electrode 42a and the bus bar electrode 42b of the first electrode 42. [ The finger electrode 44a and the bus bar electrode 44b of the second electrode 44 may all be formed through the rear passivation film 40. [ That is, the second openings 404 may be formed corresponding to the finger electrodes 44a and the bus bar electrodes 44b of the second electrode 44, respectively. However, the present invention is not limited thereto. As another example, the finger electrode 42a of the first electrode 42 is formed to pass through the front passivation film 24 and the antireflection film 26, and the bus bar electrode 42b is formed through the front passivation film 24 and the anti- (Not shown). A finger electrode 44a of the second electrode 44 may be formed through the rear passivation film 40 and a bus bar electrode 44b may be formed on the rear passivation film 40. [

Since the first and second electrodes 42 and 44 of the solar cell 100 have a certain pattern and the solar cell 100 can receive light from the front and the back of the semiconductor substrate 10, Bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100.

In the drawing, the first electrode 42 and the second electrode 44 have the same shape. The width and pitch of the finger electrode and the bus bar electrode of the first electrode 42 are not limited to the width and pitch of the finger electrode 44a and the bus bar electrode 44b of the second electrode 44, Pitch, and the like. The shapes of the first electrode 42 and the second electrode 44 may be different from each other, and various other modifications are possible. For example, the second electrode 44 may be formed entirely on the rear surface of the semiconductor substrate 10 without a pattern.

A manufacturing process of the solar cell 100 having the rear passivation film 40 according to the present embodiment will be described with reference to FIGS. 9A to 9D. 3A to 3F, FIG. 4, FIG. 5, FIG. 6A and FIG. 6B, detailed description will be omitted and only different portions will be described.

9A to 9D are cross-sectional views illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.

The first and second conductivity type regions 32 and 34 are formed in the semiconductor substrate 10 as shown in Fig. The first and second conductivity type regions 32 and 34 may be formed by various methods such as thermal diffusion, ion implantation, and laser doping.

Next, as shown in Fig. 9B, a rear passivation film 40 is formed on the second conductive type region 34. Then, as shown in Fig. The heat-treatment process for forming the rear passivation film 40 is the same as or very similar to that described with reference to Figs. 3A, 4, and 5. However, in order to form the rear passivation film 40 to have a relatively large thickness, the heat treatment temperature, the heat treatment time, and the like may be somewhat controlled within the temperature range described above. That is, as described above, the heat treatment temperature may be 600 ° C or higher (more specifically, 600 ° C to 900 ° C), and in this embodiment, it may be 800 ° C to 900 ° C. This is because the rear passivation film 40 may have a thickness greater than that of the control passivation layer (reference numeral 20 in FIG. 1), so that the heat treatment temperature T can be somewhat increased. However, the present invention is not limited thereto.

Next, as shown in Fig. 9C, a front passivation film 24 and an antireflection film 26 are formed on the first conductive type region 32. Then, as shown in Fig.

Although the rear passivation film 40 is formed before the front passivation film 24 and the antireflection film 26 in the drawings and the description, the present invention is not limited thereto. The order of forming the rear passivation film 40, the front passivation film 24, and the antireflection film 26 may be variously modified. The rear passivation film 40 and the front passivation film 24 may be formed simultaneously using the above-described process, or the rear passivation film 40 and the antireflection film 26 may be formed simultaneously using the above-described process.

9D, a first electrode 42 passing through the rear passivation film 40 and a second electrode 44 passing through the front passivation film 24 and the antireflection film 26 are formed do.

If the rear passivation film 40 is formed at a certain heat treatment temperature and in a gaseous atmosphere, the purity and the film density of the rear passivation film 40 can be improved and the interfacial trap concentration can be reduced. And may have excellent stability even at a high temperature process to be performed later. The front passivation film 24 or the antireflection film 26 may be formed by the above-described heat treatment temperature T, the gas atmosphere, or the like, although the rear passivation film 40 is formed at a constant temperature and a gas atmosphere in the above- have. Another example of the protective film that can be manufactured including the above-described heat treatment process will be described in detail with reference to FIGS. 10A to 10D. 10A to 10D are the same as or similar to the embodiments with reference to Figs. 1 to 5, so that the description thereof can be applied as it is. Therefore, the same or similar parts will not be described in detail and only different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

10A to 10D are cross-sectional views illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.

In this embodiment, the solar cell 100 as shown in FIGS. 1 and 2 is manufactured, and the rear passivation film 40 and / or the front passivation film 24 are formed by heat treatment in a gas atmosphere containing a halogen gas 3A to 3F differ from FIG.

10A, a semiconductor substrate 10 includes a control passivation layer 20, a semiconductor layer 30 including first and second conductivity type regions 32 and 34, a front surface of the semiconductor substrate 10 And the front electric field area 130 are formed. The control passivation layer 20 may be formed by various known methods, and other forming processes may be performed by the same method as described with reference to FIGS. 3A to 3D.

Next, another protective film is formed on the front surface and / or the rear surface of the semiconductor substrate 10, as shown in Fig. 10B. For example, the front passivation film 24 is formed on the front surface of the semiconductor substrate 10 and the rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10.

In this embodiment, the front passivation film 24 and the rear passivation film 40 are formed by a heat treatment in a gas atmosphere including a halogen gas having a halogen element at a relatively high temperature. The heat treatment process is the same as or very similar to that described with reference to Figs. 3A, 4, and 5. However, in order to form the front and rear passivation films 24 and 40 relatively thick, the heat treatment temperature, the heat treatment time, and the like can be controlled within the above-mentioned temperature range. That is, as described above, the heat treatment temperature may be 600 ° C or higher (more specifically, 600 ° C to 900 ° C), and in this embodiment, it may be 800 ° C to 900 ° C. This is because the front and rear passivation films 24 and 40 may have a thickness greater than that of the control passivation layer (reference numeral 20 in FIG. 1), so that the heat treatment temperature T can be somewhat increased. However, the present invention is not limited thereto.

The front and rear passivation films 24 and 40 can be formed by thermal oxidation in the heat treatment process of this embodiment. The raw material gas may include oxygen gas, so that the front and rear passivation films 24 and 40 may be composed of oxide layers. In one example, a layer of thermal oxide (e.g., a thermal silicon oxide) layer, in which oxygen and a semiconductor material (e.g., silicon) of the semiconductor substrate 10 are reacted to form at high temperatures is deposited on the front and back passivation films 24, ).

In this embodiment, a semiconductor material having a thickness of 1 nm to 3 nm on the surface of the semiconductor layer 30 is combined with oxygen to form front and rear passivation films 24 and 40 having thicknesses of 3 nm to 6 nm, respectively. The passivation characteristics can be greatly improved when the front and rear passivation films 24 and 40 have such a thickness. In other words, if the thicknesses of the front and rear passivation films 24 and 40 are less than 3 nm, it may be difficult to realize sufficient passivation characteristics. If the thicknesses of the front and rear passivation films 24 and 40 exceed 6 nm, respectively, The time is increased, and the characteristics of the semiconductor layer 30 may be deteriorated. The thickness of the semiconductor layer 30 coupled with oxygen, the thicknesses of the front and rear passivation films 24 and 40, and the like can be measured and evaluated through a transmission electron microscope (TEM) or the like.

At this time, when the front passivation film 24 positioned adjacent to the front surface of the semiconductor substrate 10 is formed by the above-described heat treatment process, it has excellent quality. As a result, the passivation characteristic can be greatly improved. At this time, since the inside (bulk) of the semiconductor substrate 10 is exposed by the texturing structure on the front surface of the semiconductor substrate 10, a lot of ions (for example, sodium ions) If the front passivation film 24 has a good quality, the passivation effect can be greatly increased.

In this embodiment, front and rear passivation films 24 and 40 located on both sides of the semiconductor substrate 10 are formed together and used as the front passivation film 24 without patterning on the front surface, Similarly, the rear passivation film 40 is patterned and used. Thus, the process can be simplified. However, the present invention is not limited thereto. The front passivation film 24 and the rear passivation film 40 may be formed by different processes and the heat treatment process described above may be applied to at least one of the front and rear passivation films 24 and 40. [ Alternatively, the front passivation film 24 and the rear passivation film 40 may be formed together and then removed. Alternatively, the antireflection film 26 and the rear passivation film 40 may be formed simultaneously by the above-described heat treatment process. Various other changes are possible.

Next, as shown in Fig. 10C, the antireflection film 26 may be formed on the front passivation film 24 in this embodiment. In one example, an antireflective film 26 may be formed entirely on the front passivation film 24. The antireflection film 26 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating.

Then, as shown in FIG. 10D, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed. The description with reference to FIG. 3F can be applied as it is, so a detailed description will be omitted.

Hereinafter, the present invention will be described in more detail with reference to experimental examples of the present invention. However, the experimental examples of the present invention are only for illustrating the present invention, and the present invention is not limited thereto.

Experimental Example  One

A solar cell having a structure as shown in Fig. 1 was manufactured. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation was included as a control passivation layer in a process of performing heat treatment in a gas atmosphere including Cl ₂ gas, O ₂ gas and N ₂ gas at a temperature of 700 ° C. In the heat-treating step, the ratio of O ₂ gas: Cl ₂ gas was 1: 0.1.

Experimental Example  2

A solar cell having a structure as shown in Fig. 1 was manufactured. At this time, a thin oxide film is formed while cleaning the semiconductor substrate with a mixed solution of HCl and H ₂ O ₂ , and then a heat treatment is performed in a gas atmosphere containing Cl ₂ gas, O ₂ gas and N ₂ gas at a temperature of 700 ° C. Respectively. A 2 nm thick silicon oxide layer thus formed was included as a control passivation layer. In the heat-treating step, the ratio of O ₂ gas: Cl ₂ gas was 1: 0.1.

Comparative Example  One

A solar cell was manufactured in the same manner as in Experimental Example except for the step of forming the control passivation layer. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation was included as a control passivation layer in a process of performing heat treatment in a gas atmosphere including Cl ₂ gas, O ₂ gas and N ₂ gas at a temperature of 500 ° C.

Comparative Example  2

A solar cell was manufactured in the same manner as in Experimental Example except for the step of forming the control passivation layer. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation was included as a control passivation layer in a process of performing heat treatment in a gas atmosphere including O ₂ gas and N ₂ gas at a temperature of 700 ° C.

Photoluminescence (PL) photographs of the solar cells according to Experimental Example 1 and Comparative Examples 1 and 2 were taken. A PL photograph of the solar cell according to Experimental Example 1 is shown in FIG. 11, a PL photograph of the solar cell according to Comparative Example 1 is shown in FIG. 12, and a PL photograph of the solar cell according to Comparative Example 2 is shown in FIG. In the PL photograph, bright light is a part where metal impurities, defects, etc. are not present, and dark parts are parts where metal impurities, defects and the like exist.

Referring to FIG. 11, it can be seen that the solar cell according to Experimental Example 1 has a bright light as a whole, so that metal impurities, defects, and the like are hardly present. On the other hand, referring to FIG. 12, it can be seen that the solar cell according to Comparative Example 1 has a black part in part, and metal impurities, defects, etc. are present in this part. Referring to FIG. 13, the solar cell according to the comparative example 2 has a black part as a whole, indicating that many metallic impurities and defects exist.

As described above, the other manufacturing processes in Experimental Example 1 and Comparative Examples 1 and 2 were all the same and only the process of the control passivation layer was different. Accordingly, it can be seen that the control passivation layer having excellent characteristics is formed in the heat treatment process performed in the gas atmosphere including the heat treatment temperature of 600 ° C or more and the halogen gas as in Experimental Example 1. In Comparative Example 1 in which the heat treatment process was performed at a heat treatment temperature of less than 600 占 폚 even in a gas atmosphere containing a halogen gas and Comparative Example 1 where a heat treatment process was performed in a gas atmosphere containing no halogen gas at a heat treatment temperature of 600 占 폚 or more 2 shows that a control passivation layer with excellent characteristics is not formed.

FIG. 14 shows the result of measuring the implied open-circuit voltage (implied Voc) of the solar cell according to Experimental Example 1 and Comparative Example 1. FIG. Referring to FIG. 14, it can be seen that the open-circuit voltage of the solar cell according to Experimental Example 1 is about 50 mV higher than the open-circuit voltage of the solar cell according to Comparative Example 1. It is expected that the interface trap voltage of the control passivation layer according to Experimental Example 1 in which the annealing process is performed in a gas atmosphere including a halogen gas at a heat treatment temperature of 600 ° C or higher is low and the open-circuit voltage of a solar cell including the control trap passivation layer is high. On the other hand, as in Comparative Example 1, the control passivation layer formed at a heat treatment temperature of 600 ° C or less is expected to have a relatively low applied open-circuit voltage because the surface trap concentration is higher than that of Experimental Example 1.

FIG. 15 shows the result of measuring the open-circuit voltage after performing additional heat treatment at a temperature of 900.degree. C. in the solar cell manufactured according to Experimental Examples 1 and 2 and Comparative Example 1. FIG. It can be seen that the open-circuit voltage of the solar cell according to Experimental Examples 1 and 2 is higher than the open-circuit voltage of the solar cell according to Comparative Example 1 by about 100 mV. Thus, it can be seen that the solar cell according to Experimental Examples 1 and 2 has excellent stability even in the case of a subsequent high-temperature process, while the solar cell according to Comparative Example 1 can be deteriorated in the subsequent high-temperature process.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: control passivation layer
24: front passivation film
26: Antireflection film
32: first conductivity type region
34: second conductivity type region
40: rear passivation film
42; The first electrode
44: Second electrode

Claims (20)

Forming a protective film with an insulating film on a semiconductor substrate including a base region made of crystalline silicon having a first conductivity type
Lt; / RTI >
Wherein the step of forming the protective film comprises a step of heat-treating the substrate at a heat treatment temperature of 600 ° C or higher in a gas atmosphere containing a halogen gas having a halogen element. The method according to claim 1,
In the step of forming the protective film,
Performing a heat treatment in a furnace to form the protective film by thermal oxidation;
Performing the heat treatment process in the low pressure chemical vapor deposition apparatus to form the protective film by vapor deposition; or
A step of forming a protective film by a wet chemical process or a dry process at a temperature of 600 ° C or lower and then subjecting the protective film to a heat treatment at a temperature of 600 ° C or higher by the heat treatment process . The method according to claim 1,
Wherein the halogen gas comprises at least one of fluorine, chlorine, bromine, iodine, astatine, and unminceptium as the halogen element. The method of claim 3,
Wherein the halogen gas contains chlorine as the halogen element. 5. The method of claim 4,
Wherein the halogen gas comprises at least one of Cl ₂ , C ₂ H ₂ Cl _2, and HCl. The method according to claim 1,
Wherein the gas atmosphere further comprises oxygen gas as a raw material gas, the protective film includes a silicon oxide layer,
Wherein the halogen gas is contained in an amount equal to or less than that of the oxygen gas. The method according to claim 6,
Wherein the volume ratio of the oxygen gas: the halogen gas is 1: 0.01 to 1: 1. The method according to claim 1,
Wherein the heat treatment temperature of the heat treatment step is 600 占 폚 to 900 占 폚. The method according to claim 1,
The heat treatment process is performed before the main section maintained at the heat treatment temperature, and is performed after the main section and during the temperature rise period in which the temperature is increased from the inflow temperature to the heat treatment temperature, and the temperature is decreased from the heat treatment temperature to the outflow temperature Temperature rising period,
Wherein the inflow temperature or the outflow temperature is in the range of 400 ° C to 550 ° C. 10. The method of claim 9,
Wherein the inflow temperature or the outflow temperature is 500 ° C to 550 ° C. The method according to claim 1,
Wherein the semiconductor substrate is doped with a dopant so as to have a doping concentration higher than that of the base region and having a second conductivity type opposite to the first conductivity type Forming a conductive type region,
Wherein the protective film is formed on the conductive region in the step of forming the protective film. 12. The method of claim 11,
Wherein the passivation film has a thickness of 3 nm to 6 nm. The method according to claim 1,
Forming a conductive type region having a crystal structure different from that of the semiconductor substrate on one surface of the semiconductor substrate before forming the protective film,
Wherein the protective film is formed on the conductive region in the step of forming the protective film. 14. The method of claim 13,
Forming a first conductive type region having the first conductivity type and a second conductive type region having a second conductive type opposite to the first conductive type on the one surface of the semiconductor substrate; Is formed on a plane,
Wherein the protective film covers the first conductive type region and the second conductive type region together. 15. The method of claim 14,
Wherein the passivation film has a thickness of 3 nm to 6 nm. The method according to claim 1,
In the forming of the passivation layer, a control passivation layer is formed on one surface of the semiconductor substrate as the passivation layer,
And forming a conductive type region on the control passivation layer after forming the passivation layer. 17. The method of claim 16,
Forming a second conductivity type region having a first conductivity type having the first conductivity type and a second conductivity type opposite to the first conductivity type on the control passivation layer, Wherein the method comprises the steps of: 17. The method of claim 16,
Wherein the thickness of the control passivation layer is 1 nm to 2 nm. The method according to claim 1,
Wherein the protective film is at least one of a first passivation film located on one side of the semiconductor substrate and a second passivation film on the other side of the semiconductor substrate. 20. The method of claim 19,
Wherein the first passivation film and the second passivation film are simultaneously formed by the heat treatment process.

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