JP2018186278A - Method of manufacturing solar cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a solar cell capable of forming a protective film having excellent characteristics and capable of manufacturing a solar cell having excellent efficiency.SOLUTION: The method of manufacturing a solar cell includes a step of forming a protective film 20 as an insulating film on a semiconductor substrate 10 including a base region 110 made of crystalline silicon having a first conductivity type. A step of forming the protective film includes a step of performing a heat treatment at a heat treatment temperature of 600°C or higher in a gas atmosphere containing a halogen gas having a halogen element.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a solar cell, and more particularly to a method for manufacturing a solar cell including a protective film formed on a semiconductor substrate or a conductive type region.

  Recently, there is a growing interest in alternative energy to replace existing energy resources such as oil and coal. Among them, solar cells are in the spotlight as next-generation batteries that convert solar energy into electrical energy.

  Such solar cells can be manufactured by forming various layers and electrodes by design. The efficiency of the solar cell can be determined by such various layer and electrode designs. Since low efficiencies must be overcome for commercialization of solar cells, it is required that various layers and electrodes be manufactured to maximize the efficiency of the solar cell.

  As an example, in a solar cell, various protective films are formed to passivate, physically protect, and electrically insulate a semiconductor substrate or semiconductor layer. Such a protective film can be formed by a thermal oxidation method, a vapor deposition method, or the like. The protective film formed by the thermal oxidation method can be difficult to precisely control the thickness, and it can be difficult to have excellent film characteristics. And the vapor deposition method is performed in the atmosphere containing the source gas containing the element which comprises a protective film, and the carrier gas as needed. However, a protective film formed using only a basic gas such as a source gas or a carrier gas has a high interface trap density and does not have excellent passivation characteristics for passivating a semiconductor substrate or semiconductor layer. There is a case. Accordingly, a manufacturing method for forming a protective film having excellent characteristics is required.

  The present invention seeks to provide a method for manufacturing a solar cell, which can form a protective film having excellent characteristics and can manufacture a solar cell having excellent efficiency.

  A method for manufacturing a solar cell according to an embodiment of the present invention includes a step of forming a protective film as an insulating film on a semiconductor substrate including a base region made of crystalline silicon having a first conductivity type. The step of forming the protective film includes a step of performing heat treatment at a heat treatment temperature of 600 ° C. or higher in a gas atmosphere containing a halogen gas containing a halogen element.

  According to the embodiment of the present invention, a protective film such as a control passivation layer and a passivation film can be formed by a method including a heat treatment process performed at a specific temperature and gas atmosphere, and the characteristics and quality of the protective film can be improved. Thereby, the efficiency of the solar cell can be improved. And the formed protective film can maintain the quality and characteristic which were excellent in the process performed at high temperature after that, and can improve process stability.

It is sectional drawing which showed an example of the solar cell manufactured by the manufacturing method of the solar cell which concerns on the Example of this invention. FIG. 2 is a partial rear plan view of the solar cell shown in FIG. 1. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the Example of this invention. It is the figure which showed an example of the heat processing apparatus which can perform the heat processing process in the manufacturing method of the solar cell which concerns on a present Example. It is the figure which showed the temperature cycle of the heat processing process in the manufacturing method of the solar cell which concerns on one Example of this invention. It is sectional drawing which showed the formation step of the control passivation layer in the manufacturing method of the solar cell which concerns on the modification of this invention. It is sectional drawing which showed the formation step of the control passivation layer in the manufacturing method of the solar cell which concerns on the modification of this invention. It is sectional drawing which showed the other example of the solar cell manufactured by the manufacturing method of the solar cell which concerns on the Example of this invention. FIG. 8 is a schematic plan view of the solar cell shown in FIG. 7. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the other Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the other Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the other Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the other Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the further another Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the further another Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the further another Example of this invention. It is sectional drawing which showed the manufacturing method of the solar cell which concerns on the further another Example of this invention. 2 is a photoluminescence (PL) photograph of a solar cell according to Experimental Example 1. FIG. 5 is a PL photograph of a solar cell according to Comparative Example 1. 10 is a PL photograph of a solar cell according to Comparative Example 2. 5 is a graph showing results of measuring implicit open voltage (implied Voc) of solar cells according to Experimental Example 1 and Comparative Example 1. 6 is a graph showing a result of measuring an implicit open-circuit voltage after performing additional heat treatment at a temperature of 900 ° C. on solar cells manufactured according to Experimental Examples 1 and 2 and Comparative Example 1. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to such an embodiment, and can naturally be modified into various forms.

  In the drawings, illustration of portions not related to the description is omitted for the sake of clarity and simplicity, and the same reference numerals are used for the same or very similar portions throughout the specification. In the drawings, the thickness and the width are illustrated in an enlarged or reduced manner for the sake of clarity, but the thickness and the width of the present invention are not limited to those illustrated in the drawings.

  In the entire specification, when one part “includes” another part, it is possible to further include another part instead of excluding the other part unless specifically stated to the contrary. . In addition, when a part such as a layer, a film, a region, or a plate is “on” another part, this is not only when it is “immediately above” the other part, Including the case where it is located. When a part such as a layer, a film, a region, or a plate is “immediately above” another part, it means that the other part is not located in the middle.

  Hereinafter, a method for manufacturing a solar cell according to an embodiment of the present invention will be described with reference to the accompanying drawings. An example of a solar cell manufactured by a method for manufacturing a solar cell according to an embodiment of the present invention will be described first, and then a method for manufacturing a solar cell according to an embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view showing an example of a solar cell manufactured by a method for manufacturing a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG.

  1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, and conductivity type regions 32 and 34 formed on or on the semiconductor substrate 10, It includes electrodes 42 and 44 connected to conductive type regions 32 and 34 and a protective film formed (contacted as an example) on semiconductor substrate 10. In this embodiment, the case where the control passivation layer 20 located on the semiconductor substrate 10 constitutes the protective film described above, and the semiconductor layer 30 including the conductivity type regions 32 and 34 is located on the control passivation layer 20 is exemplified. Here, the semiconductor layer 30 includes conductivity type regions 32 and 34 including a first conductivity type region 32 having a first conductivity type and a second conductivity type region 34 having a second conductivity type. An intrinsic barrier region 36 may be included between the first conductive type region 32 and the second conductivity type region 34. The electrodes 42 and 44 may include a first electrode 42 connected to the first conductivity type region 32 and a second electrode 44 connected to the second conductivity type region 34. The solar cell 100 may further include other protective films such as the front passivation film 24, the antireflection film 26, and the rear passivation film 40. Here, the protective film may be an insulating film that protects the semiconductor substrate 10 or the conductive regions 32 and 34. This will be described in more detail below.

  The semiconductor substrate 10 may include a base region 110 that includes the second conductivity type dopant at a relatively low doping concentration and has the second conductivity type. The base region 110 can be composed of a crystalline semiconductor containing a second conductivity type dopant. For example, the base region 110 may be formed of a single crystal or a polycrystalline semiconductor (for example, single crystal or polycrystalline silicon) including the second conductivity type dopant. In particular, the base region 110 can be composed of a single crystal semiconductor (for example, a single crystal semiconductor wafer, more specifically, a semiconductor silicon wafer) including a second conductivity type dopant. Thus, when the base region 110 or the semiconductor substrate 10 having few defects due to high crystallinity is used as a base, the electrical characteristics are excellent.

  The second conductivity type may be p-type or n-type. As an example, when the base region 110 has an n-type, a p-type first conductivity type region that forms a junction (for example, a pn junction sandwiching the control passivation layer 20) that forms carriers by photoelectric conversion with the base region 110. 32 can be formed widely and the photoelectric conversion area can be increased. Further, in this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively slow moving speed, and can further contribute to improvement in photoelectric conversion efficiency. However, the present invention is not limited to this.

  The semiconductor substrate 10 may include a front surface electric field region (or electric field region) 130 located on the front side of the semiconductor substrate 10. The front electric field region 130 is a region having the same conductivity type as that of the base region 110 but having a doping concentration higher than that of the base region 110. Therefore, a kind of conductivity type region or impurity region can be formed.

  In the present embodiment, the case where the front electric field region 130 is configured as a doping region formed by doping the semiconductor substrate 10 with a dopant having the second conductivity type at a relatively high doping concentration is illustrated. As a result, the front surface electric field region 130 includes a crystalline (single crystal or polycrystalline) semiconductor having the second conductivity type, and constitutes a part of the semiconductor substrate 10. For example, the front surface electric field region 130 may constitute a part of a single crystal semiconductor substrate (for example, a single crystal silicon wafer substrate) having the second conductivity type. At this time, the doping concentration of the front electric field region 130 may be lower than the doping concentration of the second conductivity type region 34 having the same second conductivity type.

  However, the present invention is not limited to this. Therefore, the front electric field region 130 is formed by doping the second conductive type dopant into a separate semiconductor layer (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) different from the semiconductor substrate 10. You can also. Alternatively, a region having a role similar to that of a layer formed adjacent to the semiconductor substrate 10 (for example, the front passivation film 24 and / or the antireflection film 26) doped with a fixed charge constitutes the front electric field region 130. You can also For example, when the base region 110 is n-type, the front passivation film 24 is made of an oxide having a fixed negative charge (for example, aluminum oxide), and an inversion layer is formed on the surface of the base region 110. However, this can be used as an electric field region. In this case, the semiconductor substrate 10 includes only the base region 110 without providing a separate doping region, and defects in the semiconductor substrate 10 can be minimized. The front surface electric field region 130 having various structures can be formed by various other methods.

  In this embodiment, the front surface of the semiconductor substrate 10 is textured and may have irregularities such as a pyramid. The texturing structure formed on the semiconductor substrate 10 may have a certain shape (for example, a pyramid shape) having an outer surface formed along a specific crystal plane (for example, (111) plane) of the semiconductor. it can. When unevenness is formed on the front surface of the semiconductor substrate 10 by such texturing and the surface roughness increases, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Therefore, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

  The rear surface of the semiconductor substrate 10 may be a relatively smooth and flat surface having a lower surface roughness than the front surface by mirror polishing or the like. This is because when the first and second conductivity type regions 32 and 34 are formed on the rear surface side of the semiconductor substrate 10 as in this embodiment, the characteristics of the solar cell 100 are large due to the characteristics of the rear surface of the semiconductor substrate 10. Because it can change. As a result, the unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that the passivation characteristics can be improved, and thereby the characteristics of the solar cell 100 can be improved. However, the present invention is not limited to this, and unevenness by texturing can be formed on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

  A control passivation layer 20 can be formed on the rear surface of the semiconductor substrate 10 as a protective film formed on the semiconductor substrate 10. As an example, the control passivation layer 20 is formed in contact with the rear surface of the semiconductor substrate 10 to simplify the structure. The control passivation layer 20 is formed entirely on the rear surface of the semiconductor substrate 10 and can be formed by a simple process without additional patterning. However, the present invention is not limited to this, and the shape of the control passivation layer 20 can be variously modified.

  The control passivation layer 20 can serve as a diffusion barrier that prevents the dopants in the conductivity type regions 32 and 34 from diffusing into the semiconductor substrate 10. The control passivation layer 20 may include a variety of materials through which a large number of carriers can pass. For example, the control passivation layer 20 may include oxides and nitrides. In particular, the control passivation layer 20 can be configured as a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer is a film having excellent passivation characteristics and allowing carriers to move easily. The control passivation layer 20 may be a layer formed by wet chemical and / or thermal oxidation under specific conditions, which will be described in more detail later. .

  At this time, the thickness of the control passivation layer 20 may be smaller than the thickness of the rear surface passivation film 40. As an example, the thickness of the control passivation layer 20 may be 5 nm or less (more specifically, 2 nm or less, as an example, 1 nm to 2 nm). If the thickness T of the control passivation layer 20 exceeds 5 nm, the movement of carriers does not occur smoothly and the solar cell 100 may not operate. The thickness of the control passivation layer 20 for smoother carrier movement may be 2 nm or less. Thus, when the thickness of the control passivation layer 20 is as thin as 2 nm or less, carrier transmission can be facilitated and the charge density (fill factor, FF) of the solar cell 100 can be improved. If the thickness of the control passivation layer 20 is less than 1 nm, it may be difficult to form the control passivation layer 20 having a desired quality. However, the present invention is not limited to this, and the thickness of the control passivation layer 20 can have various values.

  On the control passivation layer 20, the semiconductor layer 30 including the conductivity type regions 32 and 34 may be located. As an example, the semiconductor layer 30 is formed in contact with the control passivation layer 20, and the structure can be simplified. However, the present invention is not limited to this.

  In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type and having a first conductivity type, and a second conductivity type having a second conductivity type dopant and having a second conductivity type. The conductive type region 34 may be included. The first conductivity type region 32 and the second conductivity type region 34 may be located on the same plane on the control passivation layer 20. That is, no other layer is located between the first conductivity type region 32 and the control passivation layer 20, and no other layer is located between the second conductivity type region 34 and the control passivation layer 20. When another layer is inserted between the first and second conductivity type regions 32 and 34 and the control passivation layer 20, the inserted layer is between the first conductivity type region 32 and the control passivation layer 20. And the second conductive type region 34 and the control passivation layer 20 may have the same stacked structure. And between the 1st conductivity type area | region 32 and the 2nd conductivity type area | region 34, the barrier area | region 36 can be located on the same plane as these.

  The first conductivity type region 32 forms a pn junction (or pn tunnel junction) with the base region 110 and the control passivation layer 20 interposed therebetween, and constitutes an emitter region that generates carriers by photoelectric conversion.

  At this time, the first conductivity type region 32 may include a semiconductor (as an example, silicon) including a first conductivity type dopant opposite to the base region 110. In this embodiment, the first conductivity type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the control passivation layer 20), and is a semiconductor layer doped with the first conductivity type dopant. Configured as Thus, the first conductivity type region 32 can be configured as a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so as to be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (for example, amorphous silicon, microcrystalline silicon, or polycrystalline that can be easily manufactured by various methods such as vapor deposition. Silicon) or the like can be formed by doping the first conductivity type dopant. The first conductivity type dopant may be included in the semiconductor layer in the step of forming the semiconductor layer, or after forming the semiconductor layer, the first conductivity type dopant may be added to the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method. May be included.

  At this time, the first conductivity type region 32 may include a first conductivity type dopant capable of exhibiting a conductivity type opposite to that of the base region 110. That is, when the first conductivity type dopant is p-type, Group 3 elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In) can be used. When the first conductivity type dopant is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. As an example, the first conductivity type dopant may be boron (B) having a p-type.

  The second conductivity type region 34 forms a back surface field and prevents the loss of carriers due to recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10). Configure the area.

  At this time, the second conductivity type region 34 may include a semiconductor (as an example, silicon) containing the same second conductivity type dopant as the base region 110. In this embodiment, the second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the control passivation layer 20), and is a semiconductor layer doped with the second conductivity type dopant. Configured as Thus, the second conductivity type region 34 can be configured as a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so as to be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (for example, amorphous silicon, microcrystalline silicon, or polycrystalline, which can be easily manufactured by various methods such as vapor deposition. Silicon) or the like can be formed by doping the second conductivity type dopant. The second conductivity type dopant may be included in the semiconductor layer in the step of forming the semiconductor layer. Alternatively, after the semiconductor layer is formed, the second conductivity type dopant may be added to the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method. May be included.

  At this time, the second conductivity type region 34 may include a second conductivity type dopant capable of exhibiting the same conductivity type as the base region 110. That is, when the second conductivity type dopant is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) can be used. As an example, the second conductivity type dopant may be phosphorus (P) having n-type.

  A barrier region 36 is located between the first conductivity type region 32 and the second conductivity type region 34, and the first conductivity type region 32 and the second conductivity type region 34 are separated from each other by the barrier region 36. When the first conductivity type region 32 and the second conductivity type region 34 are in contact with each other, a shunt is generated, and the performance of the solar cell 100 may be deteriorated. Thus, in this embodiment, the barrier region 36 is positioned between the first conductivity type region 32 and the second conductivity type region 34, and unnecessary shunts can be prevented.

  The barrier region 36 may include various materials that can substantially insulate between the first conductivity type region 32 and the second conductivity type region 34. That is, for the barrier region 36, an undoped (that is, undoped) insulating material (for example, an oxide or a nitride) can be used. Alternatively, the barrier region 36 may include an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, The barrier region 36 may be an i-type (intrinsic) semiconductor material that is substantially free of dopants. As an example, after a semiconductor layer containing a semiconductor material is formed, a first conductivity type region 32 is formed by doping a first conductivity type dopant in a partial region of the semiconductor layer, and a second region is formed in a part of the other region. When the second conductivity type region 34 is formed by doping the conductivity type dopant, a region where the first conductivity type region 32 and the second conductivity type region 34 are not formed constitutes the barrier region 36. According to this, the manufacturing method of the 1st conductivity type area | region 32, the 2nd conductivity type area | region 34, and the barrier area | region 36 can be simplified.

  However, the present invention is not limited to this. Therefore, when the barrier region 36 is formed separately from the first conductivity type region 32 and the second conductivity type region 34, the thickness of the barrier region 36 is equal to the thickness of the first conductivity type region 32 and the second conductivity type region 34. Can be different. As an example, in order to prevent the first conductivity type region 32 and the second conductivity type region 34 from being short-circuited more effectively, the barrier region 36 is thicker than the first conductivity type region 32 and the second conductivity type region 34. You can also have it. Alternatively, the thickness of the barrier region 36 can be made smaller than the thickness of the first conductivity type region 32 and the second conductivity type region 34 in order to save the raw material for forming the barrier region 36. Naturally, various other modifications are possible. In addition, the basic constituent material of the barrier region 36 may include a material different from the first conductivity type region 32 and the second conductivity type region 34.

  In the present embodiment, the case where the barrier region 36 totally separates the first conductivity type region 32 and the second conductivity type region 34 is illustrated. However, the present invention is not limited to this. Therefore, the barrier region 36 can be formed so as to separate only a part of the boundary portion between the first conductivity type region 32 and the second conductivity type region 34. According to this, other parts of the boundary between the first conductivity type region 32 and the second conductivity type region 34 may contact each other.

  Here, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 can be formed wider than the area of the second conductivity type region 34 having the same conductivity type as the base region 110. As a result, a wider pn junction can be formed between the base region 110 and the first conductivity type region 32 through the control passivation layer 20. At this time, when the base region 110 and the second conductivity type region 34 have an n-type conductivity type and the first conductivity type region 32 has a p-type conductivity type, the first conductivity type region 32 formed widely Holes having a relatively slow moving speed can be collected effectively. The planar structure of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36 will be described in detail later with reference to FIG.

  On the rear surface of the semiconductor substrate 10, the rear surface passivation film 40 can be formed on the first and second conductivity type regions 32 and 34 and the barrier region 36. As an example, the rear passivation film 40 is formed in contact with the first and second conductivity type regions 32 and 34 and the barrier region 36, so that the structure can be simplified. However, the present invention is not limited to this.

  The rear surface passivation film 40 includes openings 402 and 404 for electrical connection between the conductivity type regions 32 and 34 and the electrodes 42 and 44. The openings 402 and 404 are a first opening 402 for connecting the first conductivity type region 32 and the first electrode 42, and a second for connecting the second conductivity type region 34 and the second electrode 44. And an opening 404. As a result, the rear surface passivation film 40 is not connected to the first conductive type region 32 and the second conductive type region 34 (that is, in the case of the first conductive type region 32, the second electrode 44, the second conductive type). In the case of the region 34, it serves to prevent connection with the first electrode 42). Further, the rear surface passivation film 40 may have an effect of passivating the first and second conductivity type regions 32 and 34 and / or the barrier region 36.

  The back surface passivation film 40 may be a single film or a multilayer film including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, and the like.

  The rear passivation film 40 may be located in a portion where the electrodes 42 and 44 are not located on the semiconductor layer 30. The rear passivation film 40 may have a thickness that is thicker than the control passivation layer 20. Thereby, insulation characteristics and passivation characteristics can be improved. Various other variations are possible.

  As an example, in the present embodiment, the front passivation film 24 and / or the antireflection film 26 and the rear passivation film 40 may not include a dopant or the like so as to have excellent insulating characteristics and passivation characteristics.

  The electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 are electrically and physically connected to the first electrode 42 and the second conductivity type region 34 that are electrically and physically connected to the first conductivity type region 32. And the second electrode 44.

  The first and second electrodes 42 and 44 may include various metal materials. The first and second electrodes 42 and 44 are not electrically connected to each other, and are connected to the first conductivity type region 32 and the second conductivity type region 34, respectively, and collect generated carriers and transmit them to the outside. It can have various planar shapes. That is, the present invention is not limited to the planar shape of the first and second electrodes 42 and 44.

  Hereinafter, an example of the planar shape of the first conductivity type region 32, the second conductivity type region 34, the barrier region 36, and the first and second electrodes 42 and 44 will be described in detail with reference to FIGS. 1 and 2. To do.

  Referring to FIGS. 1 and 2, in the present embodiment, the first conductivity type region 32 and the second conductivity type region 34 are formed so as to have a stripe shape, and alternately in a direction crossing the length direction. positioned. A barrier region 36 that separates the first conductivity type region 32 and the second conductivity type region 34 may be located. Although not shown in the drawing, a plurality of first conductivity type regions 32 separated from each other can be connected to each other at one side edge, and a plurality of second conductivity type regions 34 separated from each other can be connected to each other at the other side edge. Can be linked. However, the present invention is not limited to this.

  At this time, as described above, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. As an example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by making their widths different. That is, the width W1 of the first conductivity type region 32 may be larger than the width W2 of the second conductivity type region 34.

  The first electrode 42 can be formed in a stripe shape so as to correspond to the first conductivity type region 32, and the second electrode 44 can be formed in a stripe shape so as to correspond to the second conductivity type region 34. Various other variations are possible. Although not shown in the drawings, the first electrodes 42 can be formed to be connected to each other at one side edge, and the second electrodes 44 can be formed to be connected to each other at the other side edge. However, the present invention is not limited to this.

  Referring to FIG. 1 again, the front passivation film 24 and / or the antireflection film 26 may be located on the front surface of the semiconductor substrate 10 (more precisely, on the front surface electric field region 130 formed on the front surface of the semiconductor substrate 10). . Depending on the embodiment, only the front passivation film 24 may be formed on the semiconductor substrate 10, only the antireflection film 26 may be formed on the semiconductor substrate 10, or the front passivation film 24 and the semiconductor substrate 10 may be formed on the semiconductor substrate 10. The antireflection film 26 can also be sequentially positioned. In the drawing, the front passivation film 24 and the antireflection film 26 are sequentially formed on the semiconductor substrate 10, and the semiconductor substrate 10 is formed in contact with the front passivation film 24. However, the present invention is not limited to this, the semiconductor substrate 10 can be formed in contact with the antireflection film 26, and various other modifications are possible.

  The front passivation film 24 and the antireflection film 26 may be substantially formed entirely on the front surface of the semiconductor substrate 10. Here, the overall formation includes not only a case where all the layers are physically formed completely, but also a case where some parts are inevitably excluded.

  The front passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate defects present in the front surface or bulk of the semiconductor substrate 10. Thereby, a recombination site of a small number of carriers can be removed, and the open circuit voltage of the solar cell 100 can be increased. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. As a result, the amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductivity type region 32 can be increased. Thereby, the short circuit current (Isc) of the solar cell 100 can be increased. Thus, the open-circuit voltage and the short-circuit current of the solar cell 100 can be increased by the front passivation film 24 and the antireflection film 26, and the efficiency of the solar cell 100 can be improved.

The front passivation film 24 and / or the antireflection film 26 can be formed of various materials. For example, the front passivation film 24 and / or the antireflection film 26 may be a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO. Any one single film selected from the group consisting of ₂ and CeO ₂ or a multilayer film structure in which two or more films are combined can be provided. As an example, the front passivation film 24 may be a silicon oxide layer formed on the semiconductor substrate 10. Further, the antireflection film 26 may have a structure in which a silicon nitride layer and a silicon carbide layer are sequentially stacked.

  When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, and are generated. The holes and electrons move through the control passivation layer 20 to the first conductivity type region 32 and the second conductivity type region 34, respectively, and then move to the first and second electrodes 42 and 44. This generates electrical energy.

  In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and no electrode is formed on the front surface of the semiconductor substrate 10 as in this embodiment, the shading loss on the front surface of the semiconductor substrate 10 (Shading loss) can be minimized. Thereby, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited to this.

  In this embodiment, the control passivation layer 20 that is a protective film located on the semiconductor substrate 10 is formed to have excellent quality. This will be described in detail with reference to FIGS. 3A to 3F by a method for manufacturing the solar cell 100 according to the embodiment of the present invention. A detailed description of the above-described contents will be omitted, and portions not described will be described in detail.

  3A to 3F are cross-sectional views illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.

  First, as shown in FIG. 3A, a control passivation layer 20 that is a protective film is formed on the rear surface of the semiconductor substrate 10 constituted by the base region 110 having the second conductivity type dopant. In this embodiment, the control passivation layer 20 is formed by a method including a step of performing a heat treatment in a gas atmosphere containing a halogen gas having a halogen element at a relatively high temperature.

  This will be described in more detail with reference to FIGS. 4 and 5 together with FIG. 3A. FIG. 4 is a diagram showing an example of a heat treatment apparatus capable of performing a heat treatment step in the method for manufacturing a solar cell according to this example. FIG. 5 is a diagram showing a temperature cycle of a heat treatment step in the method for manufacturing a solar cell according to one embodiment of the present invention.

  In this embodiment, the control passivation layer 20 can be formed by positioning a plurality of semiconductor substrates 10 in the heat treatment apparatus 200 and then performing a heat treatment process together. At this time, the semiconductor substrates 10 are positioned parallel to each other in the heat treatment apparatus 200 with a distance d therebetween so that the thermal oxidation process in the heat treatment process is sufficiently performed. As an example, the distance d between the semiconductor substrates 10 may be 1 mm to 5 mm. If the distance d between the semiconductor substrates 10 is less than 1 mm, the control passivation layer 20 may not be formed uniformly due to stagnation of the gas flow. If the distance d between the semiconductor substrates 10 exceeds 5 mm, the number of semiconductor substrates 10 that can be processed in one heat treatment step is not large, and thus productivity can be reduced. However, the present invention is not limited to this, and the distance d between the semiconductor substrates 10 can be adjusted to have various values.

  As an example, the control passivation layer 20 is formed by a method including a heat treatment temperature T in a heat treatment apparatus 200 (more specifically, 600 ° C. to 900 ° C.) and a heat treatment in a gas atmosphere containing a halogen gas and a source gas. Can be formed. Here, the heat treatment temperature may mean a temperature that is uniformly maintained for a certain period of time for forming the control passivation layer 20 after the semiconductor substrate 10 enters the heat treatment apparatus 200. The inflow temperature T1 when the semiconductor substrate 10 enters the inside of the heat treatment apparatus 200 and the outflow temperature T2 when the semiconductor substrate 10 on which the control passivation layer 20 is formed go out of the heat treatment apparatus 200 are different from the heat treatment temperature. Can have.

  More specifically, the semiconductor substrate 10 flows into the heat treatment apparatus 200 at the inflow temperature T1, and the temperature rises from the inflow temperature T1 to the heat treatment temperature T in the temperature rise section S1. Then, heat treatment is performed at the heat treatment temperature T in the main section S2. Then, the temperature decreases from the heat treatment temperature T to the outflow temperature T2 in the temperature decrease section S3, and the semiconductor substrate 10 flows out of the heat treatment apparatus 200 at the outflow temperature T2. In this way, the inflow temperature T1 and the outflow temperature T2 can be made lower than the heat treatment temperature T, and deterioration of the quality of the semiconductor substrate 10 and the control passivation layer 20 due to a rapid temperature change can be prevented.

  When the heat treatment with the halogen gas is performed at a relatively high heat treatment temperature T in the main section S2 (that is, 600 ° C. or higher), the halogen gas adsorbs each impurity particle during the heat treatment step. The purity can be improved, the interface trap density (Dit) can be reduced, and the film density can be improved. Thereby, the quality of the control passivation layer 20 formed by the heat treatment process can be improved.

  Such an impurity particle adsorption effect of a halogen gas appears greatly at a heat treatment temperature T of 600 ° C. or higher, and may hardly appear at a heat treatment temperature of less than 600 ° C. Further, at a temperature lower than 600 ° C., there may be a problem that the halogen gas remains without being decomposed and the toxic halogen gas flows out after the heat treatment step. When the control passivation layer 20 is formed, if the heat treatment temperature T exceeds 900 ° C., there are problems such as equipment burden and an increase in manufacturing costs due to the high heat treatment temperature, and it is difficult to control the thickness of the control passivation layer 20, The thickness non-uniformity of the control passivation layer 20 can increase. At this time, the heat treatment temperature T for improving the impurity particle adsorption effect of the halogen gas and improving the process stability may be 650 ° C. or more. And the heat processing temperature T for reducing the burden by a high temperature process may be 850 degrees C or less.

  In this embodiment, the inflow temperature T1 may be 550 ° C. or lower (for example, 400 ° C. to 550 ° C., more specifically, 500 ° C. to 550 ° C.). If the inflow temperature T1 is less than 400 ° C., the process time of the temperature rise section S1 may increase, or the quality of the semiconductor substrate 10 may deteriorate due to a rapid temperature rise. When the inflow temperature T1 exceeds 550 ° C., the control passivation layer 20 can be formed on the semiconductor substrate 10 even during the inflow of the semiconductor substrate 10, so that it may be difficult to control the thickness of the control passivation layer 20. . Considering the process time further, the inflow temperature can be between 500C and 550C.

  The outflow temperature T2 can be 550 ° C. or lower (as an example, 400 ° C. to 550 ° C., more specifically, 500 ° C. to 550 ° C.). If the outflow temperature T2 is less than 400 ° C., the process time of the temperature decrease section S3 may increase. When the outflow temperature T2 exceeds 550 ° C., a large temperature change is experienced after the semiconductor substrate 10 and the control passivation layer 20 flow out of the heat treatment apparatus 200, so that problems such as quality degradation may occur. Considering the process time further, the outflow temperature T2 may be 500 ° C to 550 ° C.

  However, the present invention is not limited to this, and the inflow temperature T1 and the outflow temperature T2 may have different values.

The halogen element contained in the halogen gas used in the main section S2 can include at least one of fluorine, chlorine, bromine, iodine, astatine, and ununseptium. This is because such a halogen element has an excellent effect of adsorbing impurities during the formation process of the control passivation layer 20 as described above. In particular, chlorine can be used as the halogen element, and the halogen gas can contain chlorine. Halogen gas containing chlorine can be easily obtained, and many devices capable of using it have been developed. The reaction power is extremely excellent and relatively safe use is possible. As an example, the halogen gas including chlorine may include at least one of Cl ₂ , C ₂ H ₂ Cl _2, and HCl, and particularly includes at least one of Cl ₂ and C ₂ H ₂ Cl _2. be able to. On the other hand, halogen gases including fluorine have etching properties and may have certain limitations when used. Further, halogen gases containing bromine, iodine, astatine and ununseptium are not easily available, and iodine, astatine and ununseptium may release radioactivity under specific conditions.

  At this time, since the halogen gas can increase the growth rate of the control passivation layer 20, the halogen gas can be included in the same amount or less than the oxygen gas. As an example, the volume ratio of oxygen gas: halogen gas may be 1: 0.01 to 1: 1. If the ratio is less than 1: 0.01, the effect of improving the purity by chlorine gas may be insufficient. When the ratio exceeds 1: 1, more chlorine gas is contained than necessary, rather, the purity of the control passivation layer 20 is lowered, the growth rate is increased, and as a result, the thickness of the control passivation layer 20 is increased. Can be. However, the present invention is not limited to this, and various modifications are possible.

  In this embodiment, the gas atmosphere in the heat treatment step can contain a source gas in addition to the halogen gas. Then, the control passivation layer 20 can be formed by thermal oxidation in a heat treatment process performed at a high temperature. Then, the control passivation layer 20 can be formed only by a heat treatment process without adding a separate process, and the manufacturing process can be simplified. In the present embodiment, the source gas contains oxygen gas, and the control passivation layer 20 can be configured as an oxide layer. That is, a thermal oxide (eg, thermal silicon oxide) layer formed by a reaction between oxygen and a semiconductor material (eg, silicon) of the semiconductor substrate 10 at a high temperature can constitute the control passivation layer 20.

  And the gas atmosphere at the time of a heat treatment process can contain various gas besides the oxygen gas which is source gas. For example, the gas atmosphere can further include nitrogen gas. Nitrogen gas is involved in adjusting the growth rate of the control passivation layer 20 and is responsible for adjusting the uniformity of the control passivation layer 20 in connection with leakage current and dopant penetration. The amount of nitrogen gas can be adjusted in consideration of the size of the chamber in which the control passivation layer 20 is formed. The total amount of halogen gas, oxygen gas and nitrogen gas can be adjusted to have the required pressure.

  In this embodiment, the heat treatment apparatus 200 for performing the heat treatment process is a general heat treatment furnace (furnace) in which the pressure is difficult to adjust, chemical vapor deposition (CVD), or constant by adjusting the pressure. It may be a low pressure chemical vapor deposition (LPCVD) apparatus capable of performing a heat treatment process at a pressure lower than the pressure.

  When a heat treatment step is performed in a general heat treatment furnace and the control passivation layer 20 as a protective film is formed by a thermal oxidation method, the control passivation layer 20 is easily grown and the control passivation layer 20 is formed within a short time. The process time can be shortened.

  Chemical vapor deposition equipment or low pressure chemical vapor deposition equipment may be appropriate to maintain the desired process conditions. As an example, when the heat treatment process is performed with a low-pressure chemical vapor deposition apparatus and the control passivation layer 20 that is a protective film is formed by vapor deposition, the heat treatment process can be performed in a state where the pressure is lower than the normal pressure. It is possible to easily adjust the thickness and form the control passivation layer 20 uniformly. Here, the pressure is a pressure including all other gases in addition to the raw material gas, and may mean a pressure inside the manufacturing apparatus of the control passivation layer 20.

At this time, even when a chemical vapor deposition apparatus or a low pressure chemical vapor deposition apparatus is used, the source gas does not contain all the source materials constituting the control passivation layer 20 and constitutes the control passivation layer 20. The oxide contains only oxygen gas and no other source material. For example, when the control passivation layer 20 is formed of a silicon oxide layer, the source gas includes only oxygen gas, and does not include gas including silicon that is another source material. Thus, the control passivation layer 20 is formed by a thermal oxidation process in which oxygen in the oxygen gas is diffused into the semiconductor substrate 10 and reacts with the semiconductor material. In contrast, in a vapor deposition process or the like, a silane (SiH ₄ ) gas containing silicon is supplied as a source gas together with an oxygen gas containing oxygen. Then, oxygen separated from the oxygen gas by thermal decomposition and silicon separated from the silane gas chemically react to form silicon oxide.

  As described above, when the control passivation layer 20 is formed by a thermal oxidation process at a high temperature, the thickness of the control passivation layer 20 can be easily increased. When the control passivation layer 20 is formed at the atmospheric pressure or lower pressure in the chemical vapor deposition apparatus or the low pressure chemical vapor deposition apparatus, the thickness of the control passivation layer 20 is prevented from increasing rapidly (the control passivation layer 20). The control passivation layer 20 can have a generally uniform and thin thickness.

  At this time, if the pressure is maintained at 760 Torr or lower (atmospheric pressure or pressure lower than atmospheric pressure), even if the control passivation layer 20 is formed by a thermal oxidation process at a relatively high temperature, the growth of the control passivation layer 20 is performed at a low pressure. The speed can be maintained at a constant level. Thereby, the thickness of the control passivation layer 20 can be greatly reduced.

  More specifically, the pressure may be 1 Torr to 760 Torr (for example, 100 Torr to 760 Torr). When the temperature at the time of formation of the control passivation layer 20 is less than 1 Torr, the cost for maintaining the pressure is increased, and a burden may be imposed on the manufacturing apparatus of the control passivation layer 20. Considering the growth rate and cost, the pressure at the time of forming the control passivation layer 20 may be 1 Torr to 700 Torr, more specifically 1 Torr to 600 Torr, for example, 100 Torr to 600 Torr. However, the present invention is not limited to this, and the pressure during the formation of the control passivation layer 20 may change.

  On the other hand, in the existing semiconductor field and the like, a thin oxide layer capable of moving carriers is not required like a control passivation layer of a solar cell. That is, in the semiconductor field and the like, the oxide layer has only been adjusted within a range in which carriers do not pass, and it is not necessary to form the oxide layer with a thickness through which carriers pass. In addition, since the purity of the control passivation layer does not significantly affect the characteristics of the semiconductor element and the like, it has been difficult to present a method for increasing the purity.

  On the other hand, as described above, in this embodiment, the control passivation layer 20 is a method including a heat treatment step performed in a gas atmosphere containing a high heat treatment temperature T and a halogen gas (particularly by a thermal oxidation step performed during the heat treatment step). By forming, characteristics such as purity, film density, and thickness of the control passivation layer 20 can be adjusted.

  At this time, when the thermal oxidation is performed at atmospheric pressure or lower pressure by the chemical vapor deposition apparatus or the low pressure chemical vapor deposition apparatus, the growth rate of the control passivation layer 20 is adjusted, and the control passivation layer 20 is made thin and uniform. Can be formed. According to the embodiment, since the semiconductor layer (reference numeral 300 in FIG. 3B) formed on the control passivation layer 20 is formed by the vapor deposition apparatus, when the control passivation layer 20 is formed by the vapor deposition apparatus, the control passivation layer 20 and The semiconductor layer 300 can be formed by an in-situ process performed continuously in the same vapor deposition apparatus (for example, a low pressure chemical vapor deposition apparatus). When the control passivation layer 20 and the semiconductor layer 300 are formed by an in-situ process as described above, the manufacturing process can be greatly simplified, and the manufacturing cost and the manufacturing time can be greatly reduced.

  The temperature in the deposition apparatus is adjusted by applying heat for a long time or cooling the heat, and it takes time to stabilize the temperature, while the gas atmosphere and pressure are supplied to the deposition apparatus. It can be adjusted according to the type and amount of gas to be adjusted. Therefore, the gas atmosphere and pressure can be controlled more easily than temperature.

  In consideration of this, in this embodiment, the difference between the formation temperature of the control passivation layer 20 and the temperature of the vapor deposition process of the semiconductor layer 300 can be within 200 ° C. (that is, 0 ° C. to 200 ° C.). More specifically, the difference between the formation temperature of the control passivation layer 20 and the temperature of the deposition process of the semiconductor layer 300 can be within 100 ° C. (that is, 00 ° C. to 100 ° C.). This is because the control passivation layer 20 is formed at atmospheric pressure or lower pressure, so the formation temperature of the control passivation layer 20 can be relatively increased, and the difference from the temperature of the deposition process of the semiconductor layer 300 can be reduced. Because. Thus, the temperature that is relatively difficult to adjust can be maintained without a large change, and the efficiency of the in-situ process for continuously forming the control passivation layer 20 and the semiconductor layer 300 can be further improved. On the other hand, the gas atmosphere in the vapor deposition process of the semiconductor layer 300 is different from the gas atmosphere in the formation of the control passivation layer 20, and the pressure in the vapor deposition process of the semiconductor layer 300 is the same as the pressure in the formation of the control passivation layer 20. And can be different.

  However, the present invention is not limited to this, and the control passivation layer 20 and the semiconductor layer 300 can be formed by separate processes and apparatuses.

  In the drawing, the case where the control passivation layer 20 is formed only on the rear surface of the semiconductor substrate 10 is illustrated, but the present invention is not limited to this. The control passivation layer 20 can be further formed on the front surface and / or the side surface of the semiconductor substrate 10 by the method for manufacturing the control passivation layer 20. Thus, the control passivation layer 20 formed on the front surface of the semiconductor substrate 10 can be removed later in a separate step.

  And in the temperature cycle of FIG. 5, although the case where the heat processing process which forms a protective film was performed independently was illustrated, this invention is not limited to this. Therefore, as described above, after forming the control passivation layer 20 which is a protective film, the subsequent process (for example, the process of forming the semiconductor layer 300) or the like can be performed without taking it out from the heat treatment apparatus 200. In this case, the temperature lowering section S3 may not be performed depending on the temperature of the subsequent process. Alternatively, the heat treatment process may be continuously performed in an apparatus in which a process before forming the protective film is performed. In this case, the temperature increase section S1 may not be performed depending on the temperature of the previous process.

  Subsequently, as illustrated in FIGS. 3B to 3D, the semiconductor layer 30 including the first and second conductivity type regions 32 and 34 is formed on the control passivation layer 20, and the texturing structure and the front surface of the semiconductor substrate 10 are formed. A front electric field region 130 can be formed. In the following, this will be more specifically formed.

  First, as shown in FIG. 3B, the intrinsic semiconductor layer 300 having a crystalline structure is formed on the control passivation layer 20 formed on the rear surface of the semiconductor substrate 10. The semiconductor layer 300 can be formed of a microcrystalline, amorphous, or polycrystalline semiconductor. For example, the semiconductor layer 300 can be formed by a thermal growth method, a chemical vapor deposition method (for example, a plasma chemical vapor deposition method, a low pressure chemical vapor deposition method), or the like. However, the present invention is not limited to this, and the semiconductor layer 300 can be formed by various methods.

  As an example, in the present embodiment, the intrinsic semiconductor layer 300 can be formed by chemical vapor deposition, and more specifically, can be formed by low pressure chemical vapor deposition. As a result, the intrinsic semiconductor layer 300 can be formed by the in-situ process with the control passivation layer 20 as described above. However, the present invention is not limited to this, and the in-situ process may not be applied to the control passivation layer 20 and the semiconductor layer 300.

The gas used in the vapor deposition process of the semiconductor layer 300 may include a gas (for example, silane gas) containing a semiconductor material that forms the semiconductor layer 300. In this embodiment, since the semiconductor layer 300 is vapor-deposited so as to be intrinsic, the gas atmosphere can be composed only of a gas containing a semiconductor material. Accordingly, the supply gas can be simplified and the purity of the formed semiconductor layer 300 can be improved. However, the present invention is not limited to this, and a separate gas or the like for promoting the deposition process of the semiconductor layer 300 or improving the characteristics of the semiconductor layer 300 can be used. In addition, when the first and / or second conductivity type dopants are both doped in the vapor deposition process of the semiconductor layer 300, a gas containing the first or second conductivity type dopant (eg, B ₂ H ₆ , PH _3, etc.) is further added. Can be included.

In the vapor deposition process of the semiconductor layer 300, in addition to the gas containing the semiconductor material, nitrogen dioxide (N ₂ O) gas and / or oxygen (O ₂ ) gas are injected together to determine the crystal grain size and crystallinity. Can be adjusted.

  The deposition temperature of the semiconductor layer 300 can be the same as or lower than the temperature at which the control passivation layer 20 is formed. In particular, when the deposition temperature of the semiconductor layer 300 is lower than the temperature at the time of formation of the control passivation layer 20, the characteristics of the semiconductor layer 300 that directly participate in photoelectric conversion can be made uniform. Alternatively, the deposition temperature of the semiconductor layer 300 may be 500 ° C. to 700 ° C. This is limited to a temperature suitable for depositing the semiconductor layer 300 having a crystal structure different from that of the semiconductor substrate 10. In particular, as in this embodiment, when the semiconductor layer 300 is not doped, the reaction rate is relatively lower than when the semiconductor layer 300 is doped, and thus the deposition temperature of the semiconductor layer 300 can be 600 ° C. to 700 ° C. According to this, the deviation between the temperature of the deposition process of the semiconductor layer 300 and the temperature at the time of forming the control passivation layer 20 can be further reduced.

  As described above, since the temperature of the control passivation layer 20 is the same as or similar to the deposition temperature of the semiconductor layer 300, time for adjusting the temperature and time for stabilizing the temperature are not necessary. The process can be simplified.

  Although the case where the semiconductor layer 300 is formed only on the rear surface of the semiconductor substrate 10 is illustrated in the drawings, the present invention is not limited to this. The semiconductor layer 300 can be further formed on the front surface and / or the side surface of the semiconductor substrate 10 by the method for manufacturing the semiconductor layer 300. Thus, the semiconductor layer 300 formed on the front surface of the semiconductor substrate 10 can be removed later in a separate stage.

  3C to 3D, the front surface of the semiconductor substrate 10 is textured, irregularities are formed on the front surface of the semiconductor substrate 10, and the first and second conductivity type regions 32 and 34 and the front electric field region 130 are formed. Can be formed.

  As an example, as shown in FIG. 3C, a first conductivity type region 32 is formed by doping a part of the semiconductor layer 300 with a first conductivity type dopant, and as shown in FIG. The front electric field region 130 and the second conductivity type region 34 can be formed by textured the front surface and doping the front surface of the semiconductor substrate 10 and the other part of the semiconductor layer 300 with the second conductivity type dopant. At this time, an undoped region that is not doped with a dopant may be located between the first conductivity type region 32 and the second conductivity type region 34, but this region can constitute the barrier region 36.

  Various known methods can be used for the doping process for forming the first and second conductivity type regions 32 and 34 and the front surface electric field region 130. As an example, various methods such as an ion implantation method, a thermal diffusion method by heat treatment in a state where a gas containing a dopant is used, a heat treatment method performed after forming a doping layer, and a laser doping method can be applied. However, the present invention is not limited to this.

  As the texturing of the surface of the semiconductor substrate 10, wet or dry texturing can be used. The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has an advantage that the process time is short. The dry texturing is to cut the surface of the semiconductor substrate 10 using a diamond drill or a laser and the like, and the unevenness can be formed uniformly, while the process time is long and the semiconductor substrate 10 can be damaged. In addition, the semiconductor substrate 10 can be textured by reactive ion etching (RIE) or the like. Thus, in the present invention, the semiconductor substrate 10 can be textured by various methods.

  In this embodiment, after the semiconductor layer 300 is formed, the front surface of the semiconductor substrate 10 on which the first conductivity type region 32 is formed is textured, and the front surface electric field region 130 and the second conductivity type region 34 are formed together in the same doping process. The case where it did was illustrated. However, the present invention is not limited to this. Therefore, the order of forming the first conductivity type region 32, the second conductivity type region 34, the front surface electric field region 130, and the texturing structure can be variously modified. The second conductivity type region 34 and the front electric field region 130 can be formed by different doping processes.

  Subsequently, as illustrated in FIG. 3E, another protective film is formed on the front surface and the rear surface of the semiconductor substrate 10. That is, the front passivation film 24 and the antireflection film 26 are formed on the front surface of the semiconductor substrate 10, and the rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10.

  More specifically, the front passivation film 24 and the antireflection film 26 are entirely formed on the front surface of the semiconductor substrate 10, and the rear passivation film 40 is entirely formed on the rear surface of the semiconductor substrate 10. The front passivation film 24, the antireflection film 26, or the rear passivation film 40 can be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating. The order of forming the front passivation film 24, the antireflection film 26, and the rear passivation film 40 is not limited.

  Subsequently, as shown in FIG. 3F, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed.

  As an example, the first and second openings 402 and 404 are formed in the rear surface passivation film 40 by a patterning process, and then the first and second electrodes 42 and 404 are filled while filling the first and second openings 402 and 404. 44 is formed. At this time, the first and second openings 402 and 404 can be formed by various methods using laser ablation using a laser or an etching solution or an etching paste. The first and second electrodes 42 and 44 can be formed by various methods such as plating and vapor deposition.

  As another example, the first and second electrode forming pastes are applied to the rear surface passivation film 40 by screen printing or the like, and then fire through or laser firing contact is performed. It is also possible to form the first and second electrodes 42 and 44 having the shapes described above. In this case, since the first and second openings 402 and 404 are formed when the first and second electrodes 42 and 44 are formed, an additional step of forming the first and second openings 402 and 404 is added. You don't have to.

  According to the present embodiment, the control passivation layer 20 is formed by performing a heat treatment step in a gas atmosphere containing a heat treatment temperature of 600 ° C. to 900 ° C. and a halogen gas, and the purity and film density of the control passivation layer 20 are improved. The trap concentration can be reduced. Thereby, the passivation characteristics of the control passivation layer 20 can be improved, the carrier can be smoothly passed, and the efficiency of the solar cell 100 can be improved. Further, such a control passivation layer 20 can maintain excellent quality and characteristics as it is in a subsequent process performed at a high temperature. Thereby, the process temperature of the process (for example, doping process) performed subsequently at a high temperature can be freely selected, and the efficiency of the solar cell 100 can be further improved. According to the embodiment, when the control passivation layer 20 is formed at a temperature similar to that of the semiconductor layer 30 formed after the control passivation layer 20, the control passivation layer 20 and the semiconductor layer 30 are formed in a continuous process, and a manufacturing process is performed. Can be simplified.

  The modification of one Example of the manufacturing method of the solar cell 100 mentioned above is demonstrated in detail with reference to FIG. 6A and 6B. With reference to FIGS. 3A to 3F, FIG. 4 and FIG. 5, detailed description will be omitted for parts that are the same as or very similar to those described above, and different parts will be described in detail. And what combined the example mentioned above or the example which changed this, and the following example or the example which changed this also belongs to the range of the present invention.

  6A and 6B are cross-sectional views illustrating a formation step of a control passivation layer in a method for manufacturing a solar cell according to a modification of the present invention.

  Referring to FIGS. 6A and 6B, in this modification, the control passivation layer 20 that is a protective film formed on the semiconductor substrate 10 is formed by performing a heat treatment process after forming the preliminary protective film 200. It can be a protective film.

  That is, as shown in FIG. 6A, the preliminary protective film 200 is formed on the semiconductor substrate 10. The preliminary protective film 200 can be formed by various processes performed at a temperature equal to or lower than that of the heat treatment process (that is, a temperature of 600 ° C. or lower). As described above, the preliminary protective film 200 may be formed at a temperature lower than that of the heat treatment process to prevent the addition of a process performed at a high temperature and reduce the process burden.

As an example, the preliminary protective layer 200 may be formed by a wet chemical process using a wet chemical solution. In the wet chemical process, a wet chemical solution is applied or positioned to form a preliminary protective film 200 having a thickness and / or a lower film density than the control passivation layer 20 on the surface of the semiconductor substrate 10. The wet chemical solution may include various solutions capable of forming the preliminary protective film 200 on the surface of the semiconductor substrate 10 by reaction with the semiconductor substrate 10. As an example, the wet chemical solution may be hydrochloric acid (HCl), hydrogen peroxide (H ₂ O ₂ ), or a mixture thereof. This is because such a solution can easily form the preliminary protective film 200 made of an oxide on the semiconductor substrate 10 by reaction with the semiconductor substrate 10.

  Alternatively, the preliminary protective film 200 can be formed by a dry process (for example, vapor deposition (for example, chemical vapor deposition or low pressure chemical vapor deposition)).

  Subsequently, as shown in FIG. 6B, the control passivation layer 20 is formed by performing a heat treatment process on the preliminary protective film 200. Since such a heat treatment process is the same as or very similar to the heat treatment process described with reference to FIGS. 3A, 4 and 5, the description with reference to FIGS. 3A, 4 and 5 can be applied as it is. . However, unlike the heat treatment step with reference to FIG. 3A, the heat treatment step with reference to FIG. 6B does not necessarily contain oxygen gas, and it is possible to perform the heat treatment without containing oxygen gas.

  Thus, in this modification, after forming the preliminary | backup protective film 200 which has thickness and / or film density lower than the control passivation layer 20 previously, the control passivation layer 20 is formed by performing a heat treatment process. Then, the uniformity and the film density of the control passivation layer 20 can be improved. 6A can be performed together with the process of forming the preliminary protective film 200 shown in FIG. 6A in the cleaning process of the semiconductor substrate 10 without performing the process of forming the preliminary protective film 200 shown in FIG. 6A separately. Then, the step of forming the preliminary protective film 200 shown in FIG. 6A can be performed without adding a separate process, and thus the preliminary protective film 200 can be formed by a simple manufacturing process.

  In the above description and drawings, the case where the heat treatment step is performed after the step of forming the oxide film 200 and the control passivation layer 20 is formed is illustrated. However, another heat treatment process for manufacturing the solar cell 100 (for example, the formation process of the semiconductor layer 300 shown in FIG. 3B, the doping process shown in FIG. 3D or activation for this) is not performed separately. The heat treatment step shown in FIG. 6B can be performed together with the heat treatment step performed in the heat treatment step, the electrode formation step, and the like. However, the present invention is not limited to this.

  In the embodiment described above, when the first and second conductivity type regions 32 and 34 are separately located on the semiconductor substrate 10 on the rear surface of the semiconductor substrate 10, the control passivation layer that is a protective film formed on the semiconductor substrate 10. The case where 20 is formed by the method including the heat treatment step described above is illustrated. However, the present invention is not limited to this. As an example, at least one of the front passivation film 24 formed on the semiconductor substrate 10 and the rear passivation film 40 formed on the semiconductor layer 30 (or the conductivity type regions 32 and 34) includes the above-described heat treatment process. May be a protective film. Further, another example of the protective film that can be manufactured by the method including the heat treatment step described above will be described in detail with reference to FIGS. Since the above description can be applied as it is to the same or very similar part as the above description, a detailed description thereof will be omitted, and only different parts will be described in detail. And what combined the example mentioned above or the example which changed this, and the following example or the example which changed this also belongs to the range of the present invention.

  FIG. 7: is sectional drawing which showed the other example of the solar cell manufactured by the manufacturing method of the solar cell which concerns on the Example of this invention. FIG. 8 is a schematic plan view of the solar cell shown in FIG.

  Referring to FIG. 7, the solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, conductivity type regions 32 and 34 formed on the semiconductor substrate 10, and protection formed on the semiconductor substrate 10. It includes front and rear passivation films 24 and 40 that are films, and electrodes 42 and 44 that pass through the rear passivation film 40 and are connected to the conductivity type regions 32 and 34. At this time, at least one of the front and rear passivation films 24 and 40, which are protective films formed on the semiconductor substrate 10, can be formed by a manufacturing method including a heat treatment process according to the present embodiment.

  More specifically, the conductivity type regions 32 and 34 are located on the front surface side of the semiconductor substrate 10, located on the rear surface side of the first conductivity type region 32 having the first conductivity type, and the second conductivity type. And a second conductivity type region 34 having a mold. The electrodes 42 and 44 may include a first electrode 42 connected to the first conductivity type region 32 and a second electrode 44 connected to the second conductivity type region 34. The protective film formed on the semiconductor substrate 10 includes the front passivation film 24 formed on the front surface of the semiconductor substrate 10 on the first conductivity type region 32 and the semiconductor substrate 10 on the second conductivity type region 34. And a rear surface passivation film 40 formed on the rear surface. Further, an antireflection film 26 located on the front passivation film 24 can be further included.

  In the present embodiment, the conductivity type regions 32 and 34 are formed by doping a dopant into the semiconductor substrate 10 and are configured as doping regions constituting a part of the semiconductor substrate 10. Thus, the base region 110 and the conductivity type regions 32 and 34 constituting the semiconductor substrate 10 can be defined by the type and concentration of the dopant contained. For example, in the semiconductor substrate 10, a region including the first conductivity type and having the first conductivity type is defined as the first conductivity type region 32, the second conductivity type dopant is included at a low doping concentration, and the second conductivity type is defined. The region having the second conductivity type may be defined as the second conductivity type region 34, and the region having the second conductivity type may be defined as the second conductivity type region 34. In other words, the base region 110 and the conductivity type regions 32 and 34 are regions having different conductivity types and doping concentrations while having the crystal structure of the semiconductor substrate 10.

  The first conductivity type dopant contained in the first conductivity type region 32 is an n-type or p-type dopant, and the second conductivity type dopant contained in the base region 110 and the second conductivity type region 34 is the first conductivity type region 32. It may be a p-type or n-type dopant having a conductivity type opposite to the first conductivity type. The contents described in the above-described embodiments can be applied as they are to the p-type or n-type dopant.

  As an example, the first conductivity type region 32 may have a p-type, and the base region 110 and the second conductivity type region 34 may have an n-type. When light is applied to the pn junction formed by the first conductivity type region 32 and the base region 110, electrons generated by the photoelectric effect move to the rear surface side of the semiconductor substrate 10 and are collected by the second electrode 44. The holes move to the front side of the semiconductor substrate 10 and are collected by the first electrode 42. This generates electrical energy. If it does so, the hole which has a moving speed slower than an electron will move to the front surface which is not the rear surface of the semiconductor substrate 10, and it can improve conversion efficiency. However, the present invention is not limited to this, and the base region 110 and the second conductivity type region 34 may have a p-type, and the first conductivity type region 32 may have an n-type.

  In the drawing, the case where unevenness by texturing is formed on the front surface and the rear surface of the semiconductor substrate 10 is shown. However, the present invention is not limited to this. Therefore, it is possible that unevenness due to texturing is formed on any one of the front surface and the rear surface of the semiconductor substrate 10, or unevenness due to texturing is not formed on the front surface and the rear surface of the semiconductor substrate 10.

  In this embodiment, at least one of the front passivation film 24 and the rear passivation film 40 which are protective films respectively formed on the front surface and the rear surface of the semiconductor substrate 10 is formed by a method including a heat treatment process according to this embodiment. It can be a protective film. As an example, the passivation films 24 and 40 formed on the n-type regions of the conductivity type regions 32 and 34 may be protective films formed by a method including a heat treatment process according to the present embodiment. The protective film formed by the method including the heat treatment process according to the present embodiment is configured as a silicon oxide layer. This is because such a silicon oxide layer has a fixed positive charge and passivates the n-type. It is because it is suitable for. However, the present invention is not limited to this.

  As an example, when the second conductivity type region 34 has an n-type, the rear surface passivation film 40 positioned (contacted as an example) on the rear surface of the semiconductor substrate 10 is formed by the method including the heat treatment process according to the present embodiment. It can be a protective film. Such a rear surface passivation film 40 may have a thickness of 2 nm to 10 nm (for example, 3 nm to 6 nm). If the thickness of the rear surface passivation film 40 is less than 2 nm, the passivation characteristics may not be excellent, and if the thickness of the rear surface passivation film 40 exceeds 10 nm, the process time may increase. Considering the passivation characteristics and the process time further, the thickness of the rear surface passivation film 40 may be 3 nm to 6 nm. However, the present invention is not limited to the thickness of the rear surface passivation film 40.

  The front passivation film 24 and / or the antireflection film 26 can be formed of various materials described in the above embodiments. The description for this is omitted.

  However, the present invention is not limited to this, and the first conductivity type region 32 may be n-type, and the front passivation film 24 may be formed by the heat treatment process according to the present embodiment. Alternatively, regardless of the conductivity type, the front passivation film 24 and / or the rear passivation film 40 can be formed by the heat treatment process according to this embodiment. Various other variations are possible.

  Referring to FIG. 8, the first and second electrodes 42 and 44 may include a plurality of finger electrodes 42a and 44a that are spaced apart from each other with a certain pitch. In the drawing, the case where the finger electrodes 42a and 44a are parallel to each other and parallel to the edge of the semiconductor substrate 10 is illustrated, but the present invention is not limited to this. The first and second electrodes 42 and 44 may include bus bar electrodes 42b and 44b that are formed in a direction intersecting with the finger electrodes 42a and 44a and connect the finger electrodes 42a and 44a. Only one bus bar electrode 42b and 44b may be provided, and as shown in FIG. 8, a plurality of bus bar electrodes 42b and 44b may be provided while having a pitch larger than the pitch of the finger electrodes 42a and 44a. At this time, the width of the bus bar electrodes 42b and 44b may be larger than the width of the finger electrodes 42a and 44a, but the present invention is not limited to this, and is the same as or smaller than the width of the finger electrodes 42a and 44a. Can have a width.

  When viewed in cross section, the finger electrodes 42 a and the bus bar electrodes 42 b of the first electrode 42 can all be formed to penetrate the front passivation film 24 and the antireflection film 26. That is, the first opening 402 can be formed so as to correspond to all of the finger electrodes 42a and the bus bar electrodes 42b of the first electrode 42. The finger electrodes 44 a and the bus bar electrodes 44 b of the second electrode 44 can all be formed so as to penetrate the rear surface passivation film 40. That is, the second opening 404 can be formed so as to correspond to all of the finger electrodes 44 a and the bus bar electrodes 44 b of the second electrode 44. However, the present invention is not limited to this. As another example, the finger electrode 42a of the first electrode 42 may be formed to penetrate the front passivation film 24 and the antireflection film 26, and the bus bar electrode 42b may be formed on the front passivation film 24 and the antireflection film 26. it can. The finger electrode 44 a of the second electrode 44 can be formed so as to penetrate the rear surface passivation film 40, and the bus bar electrode 44 b can be formed on the rear surface passivation film 40.

  In this embodiment, the first and second electrodes 42 and 44 of the solar cell 100 have a certain pattern, and the solar cell 100 is a double-sided light receiving type (bi−) in which light can be incident on the front and rear surfaces of the semiconductor substrate 10. (facial) structure. As a result, the amount of light used in the solar cell 100 can be increased, and the efficiency of the solar cell 100 can be improved.

  In the drawing, the case where the first electrode 42 and the second electrode 44 have the same shape is illustrated. However, the present invention is not limited to this, and the width and pitch of the finger electrode and bus bar electrode of the first electrode 42 are the same as the width and pitch of the finger electrode 44a and bus bar electrode 44b of the second electrode 44. Can have different values. Further, the shapes of the first electrode 42 and the second electrode 44 can be different from each other, and various other modifications are possible. For example, the second electrode 44 may be formed entirely on the rear surface of the semiconductor substrate 10 without having a pattern.

  A manufacturing process of the solar cell 100 including the rear surface passivation film 40 according to the present embodiment will be described with reference to FIGS. 9A to 9D. Detailed descriptions for the same or similar descriptions to those described with reference to FIGS. 3A to 3F, 4, 5, 6A and 6B are omitted, and only different portions will be described.

  9A to 9D are cross-sectional views illustrating a method for manufacturing a solar cell according to another embodiment of the present invention.

  As shown in FIG. 9A, first and second conductivity type regions 32 and 34 are formed in the semiconductor substrate 10. The first and second conductivity type regions 32 and 34 may be formed by various methods such as a thermal diffusion method, an ion implantation method, and a laser doping method.

  Subsequently, as shown in FIG. 9B, a rear passivation film 40 is formed on the second conductivity type region 34. The heat treatment process for forming the rear surface passivation film 40 is the same as or very similar to that described with reference to FIGS. 3A, 4 and 5. However, in order to form the rear passivation film 40 with a relatively large thickness, the heat treatment temperature, the heat treatment time, and the like can be slightly adjusted within the above-described temperature range. That is, as described above, the heat treatment temperature may be 600 ° C. or higher (more specifically, 600 ° C. to 900 ° C.), but in the present embodiment, it may be 800 ° C. to 900 ° C. as an example. This is because the rear surface passivation film 40 may have a thickness greater than that of the control passivation layer (reference numeral 20 in FIG. 1), so that the heat treatment temperature T can be somewhat increased. However, the present invention is not limited to this.

  Subsequently, as shown in FIG. 9C, the front passivation film 24 and the antireflection film 26 are formed on the first conductivity type region 32.

  In the drawings and description, the case where the rear passivation film 40 is formed prior to the front passivation film 24 and / or the antireflection film 26 is illustrated, but the present invention is not limited to this. The order of forming the rear surface passivation film 40, the front surface passivation film 24, and the antireflection film 26 can be variously modified. Then, the rear surface passivation film 40 and the front surface passivation film 24 can be formed simultaneously using the above-described steps, or the rear surface passivation film 40 and the antireflection film 26 can be formed simultaneously using the above-described steps.

  Subsequently, as shown in FIG. 9D, a second electrode 44 that penetrates the rear surface passivation film 40 and a first electrode 42 that penetrates the front surface passivation film 24 and the antireflection film 26 are formed.

  When the rear surface passivation film 40 is thus formed at a constant heat treatment temperature and gas atmosphere, the purity and film density of the rear surface passivation film 40 can be improved, and the interface trap concentration can be reduced. And it can have the outstanding stability also in the process of the high temperature performed later. In the above description, the case where only the rear surface passivation film 40 is formed at a constant temperature and gas atmosphere is exemplified, but the front surface passivation film 24 or the antireflection film 26 is formed at the above-described heat treatment temperature T, gas atmosphere, or the like. You can also. Another example of the protective film that can be manufactured by the method including the heat treatment step described above will be described in detail with reference to FIGS. 10A to 10D. The embodiment shown in FIGS. 10A to 10D is the same as or similar to the embodiment shown in FIGS. 1 to 5, and the description thereof can be applied as it is. Accordingly, detailed description of the same or similar parts will be omitted, and only different parts will be described in detail. And what combined the example mentioned above or the example which changed this, and the following example or the example which changed this also belongs to the range of the present invention.

  10A to 10D are cross-sectional views illustrating a method for manufacturing a solar cell according to still another embodiment of the present invention.

  In this embodiment, the solar cell 100 shown in FIGS. 1 and 2 is manufactured, and the rear passivation film 40 and / or the front passivation film 24 is formed by heat treatment in a gas atmosphere containing a halogen gas. Different from FIG. 3F.

  As shown in FIG. 10A, a control passivation layer 20, a semiconductor layer 30 including first and second conductivity type regions 32 and 34, a texturing structure on the front surface of the semiconductor substrate 10, and a front electric field region 130 are formed on the semiconductor substrate 10. To do. The control passivation layer 20 can be formed by various known methods, and other forming steps can be performed by the same method as described with reference to FIGS. 3A to 3D.

  Subsequently, as illustrated in FIG. 10B, another protective film is formed on the front surface and / or the rear surface of the semiconductor substrate 10. For example, the front passivation film 24 is formed on the front surface of the semiconductor substrate 10, and the rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10.

  In the present embodiment, the front passivation film 24 and the rear passivation film 40 are formed by a method including a step of heat-treating in a gas atmosphere containing a halogen gas having a halogen element at a relatively high temperature. The heat treatment process is the same as or very similar to that described with reference to FIGS. 3A, 4 and 5. However, in order to form the front and rear passivation films 24 and 40 relatively thick, the heat treatment temperature and the heat treatment time can be slightly adjusted within the above-described temperature range. That is, as described above, the heat treatment temperature may be 600 ° C. or higher (more specifically, 600 ° C. to 900 ° C.), but in this example, it may be 800 ° C. to 900 ° C. as an example. This is because the heat treatment temperature T can be slightly increased because the front and rear passivation films 24 and 40 may have a thickness greater than that of the control passivation layer (reference numeral 20 in FIG. 1). However, the present invention is not limited to this.

  The front and rear passivation films 24 and 40 can be formed by thermal oxidation in the heat treatment process of this embodiment. The source gas contains oxygen gas, and the front and back passivation films 24 and 40 can be configured as oxide layers. As an example, a thermal oxide (eg, thermal silicon oxide) layer formed by a reaction between oxygen and a semiconductor material (eg, silicon) of the semiconductor substrate 10 at a high temperature constitutes the front and back passivation films 24 and 40. can do.

  In this embodiment, a semiconductor material having a thickness of 1 nm to 3 nm is bonded to oxygen on the surface of the semiconductor layer 30 to form front and rear surface passivation films 24 and 40 having a thickness of 3 nm to 6 nm, respectively. When the front and rear passivation films 24 and 40 have such a thickness, the passivation characteristics can be greatly improved. That is, if the thickness of the front and back passivation films 24 and 40 is less than 3 nm, it is difficult to implement sufficient passivation characteristics. If the thickness of the front and back passivation films 24 and 40 exceeds 6 nm, The time for the heat treatment process is increased, which may deteriorate the characteristics of the semiconductor layer 30. The thickness of the semiconductor layer 30 combined with oxygen, the thickness of the front and back passivation films 24 and 40, and the like can be measured and evaluated through a transmission electron microscope (TEM).

  At this time, when the front surface passivation film 24 positioned adjacent to the front surface of the semiconductor substrate 10 is formed by the above-described heat treatment process, it has excellent quality. Thereby, the passivation characteristics can be greatly improved. At this time, since the inside (bulk) of the semiconductor substrate 10 is exposed on the front surface of the semiconductor substrate 10 due to the texturing structure, there are many ions (for example, sodium ions) that deteriorate the quality from the rear surface, and gettering is not performed. Although it is a region that can occur in many cases, if the front passivation film 24 has excellent quality, the passivation effect can be greatly increased.

  In this embodiment, the front and rear passivation films 24 and 40 located on both sides of the semiconductor substrate 10 are formed together, and the front passivation film 24 is used as it is without patterning on the front surface, and as shown in FIG. 10D on the rear surface. The rear passivation film 40 is used after being patterned. This can simplify the process. However, the present invention is not limited to this. The front passivation film 24 and the rear passivation film 40 may be formed by different processes, and the above-described heat treatment process may be applied to at least one of the front and rear passivation films 24 and 40. Alternatively, after the front passivation film 24 and the rear passivation film 40 are formed together, one of them can be removed and used. Alternatively, the antireflection film 26 and the rear surface passivation film 40 can be simultaneously formed by the heat treatment process described above. Various other changes are possible.

  Subsequently, as shown in FIG. 10C, an antireflection film 26 can be formed on the front surface passivation film 24 in this embodiment. As an example, the antireflection film 26 can be entirely formed on the front surface passivation film 24. The antireflection film 26 can be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.

  Subsequently, as shown in FIG. 10D, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed. For this, the description with reference to FIG. 3F can be applied as it is, and a specific description thereof will be omitted.

  Hereinafter, the present invention will be described in more detail with reference to experimental examples of the present invention. However, the experimental example of the present invention is only for illustrating the present invention, and the present invention is not limited to this.

Experimental example 1

A solar cell having the structure shown in FIG. 1 was manufactured. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation in a process of heat treatment in a gas atmosphere containing Cl ₂ gas, O ₂ gas, and N ₂ gas at a temperature of 700 ° C. was included as a control passivation layer. In the heat treatment step, the ratio of O ₂ gas: Cl ₂ gas was 1: 0.1.

Experimental example 2

A solar cell having the structure shown in FIG. 1 was manufactured. At this time, a thin oxide film is formed while cleaning the semiconductor substrate with a mixed solution of HCl and H ₂ O ₂ , and then heat-treated in a gas atmosphere containing Cl ₂ gas, O ₂ gas, and N ₂ gas at a temperature of 700 ° C. The process was performed. A 2 nm thick silicon oxide layer formed thereby was included as a control passivation layer. In the heat treatment step, the ratio of O ₂ gas: Cl ₂ gas was 1: 0.1.

Comparative Example 1

Except for the step of forming the control passivation layer, a solar cell was manufactured by the same method as in the experimental example. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation in a process of heat treatment in a gas atmosphere containing Cl ₂ gas, O ₂ gas, and N ₂ gas at a temperature of 500 ° C. was included as a control passivation layer.

Comparative Example 2

Except for the step of forming the control passivation layer, a solar cell was manufactured by the same method as in the experimental example. At this time, a silicon oxide layer having a thickness of 2 nm formed by thermal oxidation in a process of heat treatment in a gas atmosphere containing O ₂ gas and N ₂ gas at a temperature of 700 ° C. was included as a control passivation layer.

  Photoluminescence (photoluminescence) (PL) photographs of solar cells according to Experimental Example 1 and Comparative Examples 1 and 2 were taken. The PL photograph of the solar cell according to Experimental Example 1 is shown in FIG. 11, the PL photograph of the solar cell according to Comparative Example 1 is shown in FIG. 12, and the PL photograph of the solar cell according to Comparative Example 2 is shown in FIG. In a PL photograph, a portion that emits bright light is a portion where metal impurities and defects are not present, and a dark portion is a portion where metal impurities and defects are present.

  Referring to FIG. 11, it can be seen that the solar cell according to Experimental Example 1 has bright light as a whole, and there are almost no metal impurities, defects, and the like. On the other hand, referring to FIG. 12, it can be seen that the solar cell according to Comparative Example 1 has a partially black portion, and metal impurities and defects exist in this portion. Then, referring to FIG. 13, it can be seen that the solar cell according to Comparative Example 2 has a black portion as a whole, and there are many metal impurities and defects.

  As described above, in Experimental Example 1 and Comparative Examples 1 and 2, all other manufacturing processes were the same, and only the process of the control passivation layer was different from each other. Therefore, it can be seen that, as in Experimental Example 1, a control passivation layer having excellent characteristics was formed in a heat treatment step performed in a gas atmosphere containing a heat treatment temperature of 600 ° C. or higher and a halogen gas. Moreover, even if it is a gas atmosphere containing halogen gas, it is the comparative example 1 in which the heat treatment process was performed at a heat treatment temperature of less than 600 ° C., and a heat treatment temperature of 600 ° C. or more, but in a gas atmosphere containing no halogen gas. In Comparative Example 2 in which the heat treatment step was performed, it can be seen that a control passivation layer having excellent characteristics was not formed.

  The result of having measured the implicit open circuit voltage (implied Voc) of the solar cell which concerns on Experimental example 1 and Comparative example 1 was shown in FIG. Referring to FIG. 14, it can be seen that the implicit open circuit voltage of the solar cell according to Experimental Example 1 is approximately 50 mV higher than the implicit open circuit voltage of the solar cell according to Comparative Example 1. Since the interface trap concentration of the control passivation layer according to Experimental Example 1 in which the heat treatment process is performed in a gas atmosphere including a heat treatment temperature of 600 ° C. or higher and a halogen gas is low, it is expected that the implicit open-circuit voltage of the solar cell including this is high. The On the other hand, since the control passivation layer formed at a heat treatment temperature of 600 ° C. or lower as in Comparative Example 1 has a higher interface trap concentration than Experimental Example 1, the solar cell including this has a relatively low implicit open circuit voltage. That is expected.

  And after performing additional heat processing at the temperature of 900 degreeC with respect to the solar cell manufactured by Experimental example 1 and 2 and the comparative example 1, the result of having measured the implicit open circuit voltage was shown in FIG. It can be seen that the implicit open circuit voltage of the solar cells according to Experimental Examples 1 and 2 is higher by about 100 mV than the open circuit voltage of the solar cell according to Comparative Example 1. As a result, the solar cells according to Experimental Examples 1 and 2 have excellent stability even when there is a subsequent high-temperature process, while the solar cell according to Comparative Example 1 may deteriorate in characteristics at the subsequent high-temperature process. I understand that.

  The features, structures, effects, and the like described above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc., exemplified in each embodiment can be implemented by combining or modifying other embodiments by those having ordinary knowledge in the field to which each embodiment belongs. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Control passivation layer 24 Front surface passivation film 26 Antireflection film 30 Semiconductor layer 40 Rear surface passivation film 42, 44 Electrode 100 Solar cell 402, 404 Opening

Claims (20)

Forming a protective film as an insulating film on a semiconductor substrate including a base region made of crystalline silicon having the first conductivity type;
The step of forming the protective film includes a step of performing a heat treatment at a heat treatment temperature of 600 ° C. or higher in a gas atmosphere containing a halogen gas containing a halogen element. In the step of forming the protective film,
Performing a heat treatment process in a heat treatment furnace, forming the protective film by a thermal oxidation method,
Performing the heat treatment in a low-pressure chemical vapor deposition apparatus, forming the protective film by vapor deposition, or forming a preliminary protective film by a wet chemical process or a dry process at a temperature of 600 ° C. or lower with respect to the protective film. The method for manufacturing a solar cell according to claim 1, wherein the preliminary protective film is heat-treated at a temperature of 600 ° C. or higher by the heat treatment step.   The method for manufacturing a solar cell according to claim 1, wherein the halogen gas contains at least one of fluorine, chlorine, bromine, iodine, astatine and ununseptium as the halogen element.   The said halogen gas is a manufacturing method of the solar cell of Claim 3 containing chlorine as said halogen element. The method for manufacturing a solar cell according to claim 4, wherein the halogen gas includes at least one of Cl ₂ , C ₂ H ₂ Cl _2, and HCl. The gas atmosphere further includes oxygen gas as a source gas, and the protective film includes a silicon oxide layer,
The method for producing a solar cell according to claim 1, wherein the halogen gas is contained in an amount equal to or less than the oxygen gas.   The method for manufacturing a solar cell according to claim 6, wherein a volume ratio of the oxygen gas to the halogen gas is 1: 0.01 to 1: 1.   The manufacturing method of the solar cell of Claim 1 whose heat processing temperature of the said heat processing process is 600 to 900 degreeC. The heat treatment step is performed before the main section maintained at the heat treatment temperature, and is performed after the main section and the temperature increasing section for increasing the temperature from the inflow temperature to the heat treatment temperature, and from the heat treatment temperature to the outflow temperature. Including a temperature lowering section that lowers
The manufacturing method of the solar cell of Claim 1 whose said inflow temperature or the said outflow temperature is 400 to 550 degreeC.   The method for manufacturing a solar cell according to claim 9, wherein the inflow temperature or the outflow temperature is 500 ° C to 550 ° C. Before the step of forming the protective film, by doping a dopant into the semiconductor substrate, the conductive region of the first conductivity type having a higher doping concentration than the base region, or opposite to the first conductivity type. Forming a conductivity type region having the second conductivity type of:
The method for manufacturing a solar cell according to claim 1, wherein in the step of forming the protective film, the protective film is formed on the conductive type region.   The method for manufacturing a solar cell according to claim 11, wherein the protective film has a thickness of 3 nm to 6 nm. Before the step of forming the protective film, further comprising the step of forming a conductive type region having a crystal structure different from that of the semiconductor substrate on one surface of the semiconductor substrate;
The method for manufacturing a solar cell according to claim 1, wherein in the step of forming the protective film, the protective film is formed on the conductive type region. In the step of forming the conductivity type region, a first conductivity type region having the first conductivity type and a second conductivity type region having a second conductivity type opposite to the first conductivity type are formed on one surface of the semiconductor substrate. On the same plane,
The method for manufacturing a solar cell according to claim 13, wherein the protective film covers both the first conductivity type region and the second conductivity type region.   The method for manufacturing a solar cell according to claim 14, wherein the protective film has a thickness of 3 nm to 6 nm. In the step of forming the protective film, a control passivation layer is formed on one surface of the semiconductor substrate as the protective film,
The method of manufacturing a solar cell according to claim 1, further comprising a step of forming a conductive region on the control passivation layer after the step of forming the protective film.   In the step of forming the conductive type region, a first conductive type region having the first conductive type and a second conductive type region having a second conductive type opposite to the first conductive type are formed on the control passivation layer. The method for manufacturing a solar cell according to claim 16, wherein the solar cell is formed on the same plane.   The method for manufacturing a solar cell according to claim 16, wherein the thickness of the control passivation layer is 1 nm to 2 nm.   2. The sun according to claim 1, wherein the protective film is at least one of a first passivation film located on one surface of the semiconductor substrate and a second passivation film located on another surface of the semiconductor substrate. Battery manufacturing method.   The method for manufacturing a solar cell according to claim 19, wherein the first passivation film and the second passivation film are simultaneously formed by the heat treatment step.