KR20160139679A - Backplane Substrate and Method for the Same, Organic Light Emitting Display Device and Method for the Same - Google Patents

Abstract

The present invention relates to a backplane substrate, a manufacturing method thereof, an organic light emitting display device using the same, and a manufacturing method thereof which adjust a position of a gate electrode to eliminate use of metal, and define a region of a storage capacitor by adjusting a doping region of an active layer to reduce use of a mask and improve reliability. According to the present invention, the backplane substrate comprises: a substrate having a plurality of pixel regions on a matrix, and having a storage capacitor region and a driving thin film transistor region separated from each other in each pixel region; a driving gate electrode crossing the storage capacitor region and the driving thin film transistor region in each pixel region on the substrate; a first active layer having a channel corresponding to an upper portion of the driving gate electrode in the driving thin film transistor region, a low concentration region overlapping a portion of the driving gate electrode around the channel, and a high concentration region in a region away from the driving gate electrode around the low concentration region, and branching from one side of the high concentration region to be overlapped with the driving gate electrode of the storage capacitor region; a driving drain electrode connected to one side of the high concentration region of the first active layer; and a driving current line including a driving source electrode connected to the other side of the high concentration region of the first active layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backplane substrate, a method of manufacturing the same, an organic light emitting display device using the backplane substrate, and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backplane substrate, in particular, by adjusting the position of a gate electrode, omitting the use of a metal below a gate electrode, and defining an area of a storage capacitor by adjusting a doping region of the active layer, A method of manufacturing the same, and an organic light emitting display device using the backplane substrate, and a method of manufacturing the same.

As portable electronic devices such as mobile communication terminals and notebook computers are developed, there is an increasing demand for flat panel display devices applicable thereto.

Examples of the flat panel display include a liquid crystal display device, a plasma display panel device, a field emission display device, an organic or inorganic light emitting diode display Device) have been studied. Among such flat panel display devices, the organic light emitting display devices are being applied to various fields with the advantages of development of mass production technology, ease of driving means, low power consumption, high image quality, large-screen realization and softening.

In addition, such a flat panel display device has a plurality of pixels in a matrix, and at least one TFT (Thin Film Transistor) capable of controlling each pixel is provided in the pixel.

The thin film transistor is divided into a top gate structure and a bottom gate structure according to the position of the gate electrode.

In a general top gate TFT (Thin Film Transistor), an amorphous layer is first formed on a substrate, and crystallized using an eximer laser to form a polycrystalline silicon. Next, a photosensitive film (not shown) is coated on the crystallized polycrystalline silicon, the photosensitive film is exposed and developed to form a photosensitive film pattern, and the polycrystalline silicon is etched using the photosensitive film pattern as a mask, Leaving an active layer. A gate insulating film is formed to cover the active layer, and a gate electrode is formed on the gate electrode to correspond to the upper portion of the active layer.

On the other hand, the TFT of the bottom gate structure reverses the above-described top gate structure, the order of forming the active layer and the gate electrode. However, the crystallization process for polycrystallizing amorphous silicon proceeds at a temperature of 400 ° C or higher. In this process, in the bottom gate structure, a mass flow phenomenon occurs due to the mass flow phenomenon. Particularly, This phenomenon was severe in the tapered portion, and there was a problem in the active layer disconnection at the boundary between the flat portion on the gate electrode and the inclined portion on the taper side of the gate electrode.

Therefore, in recent display devices, a thin film transistor having a top gate structure in which a gate electrode is formed after crystallization is completed is preferred so as to prevent such a problem of disconnection of the active layer.

Hereinafter, a conventional method for manufacturing an organic light emitting display will be described with reference to the drawings.

FIG. 1 is a process flow diagram illustrating a conventional method of manufacturing an organic light emitting display device.

That is, the manufacturing process of a conventional organic light emitting display device includes the steps of forming a lower metal (10S), forming a buffer layer, defining an active layer (20S), forming a gate insulating film, Hole formation 30S, a primary impurity doping process 40S for defining a storage capacitor region by performing primary impurity doping on the active layer, formation of a gate electrode 50S, a high impurity doping process including a low concentration region by a second impurity doping process (70S), formation of a source electrode and a drain electrode (80S), formation of a protective film and formation of a third contact hole in a passivation film (90S), formation of a second contact hole in the interlayer insulating film A first electrode formation 100S and a bank formation 110S which are connected to the third contact hole, and it takes at least 11 mask processes.

Here, the lower metal serves to cover the channel of the active layer with respect to the light entering the substrate side, and is an essential structure in the organic light emitting display device to which the top gate structure is applied. Particularly, in the formation of the lower metal, after the patterning of the lower metal itself and the definition of the active layer, two masks are required to apply a signal to the lower metal, which is a major cause of increasing the mask.

In addition, the storage capacitor of the conventional organic light emitting diode display of the above-described type is defined by a doped active layer and a metal overlapping the doped active layer. When the overlapped metal is used as the metal of the same layer as the gate electrode, Since the active layer functioning as the first electrode of the capacitor is covered, the impurity doping process of the active layer corresponding to the storage capacitor must be performed before formation of the gate electrode, so that a further mask is required.

If the storage capacitor is defined as the overlap of the metals in layers other than the doped active layer, the gate electrode of the two layers is used. In this case, even if the storage capacitor is formed of the same layer metal as the gate electrode of the thin film transistor In addition, the formation of the auxiliary gate electrode is required, and an additional mask for patterning the auxiliary gate electrode is required, so that the addition of the mask is also problematic in this case.

When the above-described conventional top gate structure is applied to a thin film transistor, at least eleven masks are used for a backplane substrate for an organic light emitting display.

On the other hand, when the alignment between the masks is inaccurate, the yield decreases as the number of masks increases, considering that this is a direct cause of reducing the yield. Particularly, when one mask is used, cleaning, exposure, development and etching processes are required before and after the mask application, and a detailed step of 5 times or more is required for each actual mask. It is considered that the increase in mask increases the process load, .

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device which can adjust the position of a gate electrode to omit the use of a lower metal and define a region of a storage capacitor by adjusting a doping region of the active layer, An organic light emitting display device using the backplane substrate, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a backplane substrate including a substrate having a plurality of pixel regions in a matrix, a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region, A gate line and a data line crossing the plurality of pixel regions; a driving gate electrode passing through the storage capacitor region and the driving thin film transistor region in each pixel region on the substrate; A channel region corresponding to an upper portion of the electrode; a low concentration region partially overlapping the drive gate electrode around the channel; and a high concentration region in a region off the drive gate electrode in the periphery of the low concentration region, The storage capacitor region And a drive source electrode connected to one side of the high concentration region of the first active layer and a drive source electrode connected to the other side of the high concentration region of the first active layer, Line. ≪ / RTI >

Here, the first active layer overlapping the driving gate electrode in the region of the storage capacitor is preferably a high-concentration region.

Further, the driving drain electrode and the driving source electrode may be connected to the first active layer around the hole side and the hole through a hole penetrating a portion of the high-concentration region of the first active layer, respectively.

A connection portion between the first active layer and the driving drain electrode may be located at a portion where the driving gate electrode is not overlapped with the driving drain electrode, and the driving drain electrode may be extended to be overlapped with the driving gate electrode.

The switching thin film transistor may further include a switching thin film transistor between the gate line and the data line, the switching thin film transistor being overlapped with the gate line and connected to the data line and the driving gate electrode, And a second active layer overlapping the data line and the driving gate electrode at both ends thereof. In this case, it is preferable that the first and second active layers are located on the same layer.

A method of manufacturing a backplane substrate according to the present invention for achieving the same object comprises the steps of preparing a substrate having a plurality of pixel regions in a matrix form and having a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region Forming a driving gate electrode through the storage capacitor region and the driving thin film transistor region of the substrate using a first mask and forming a gate insulating film and an amorphous silicon layer on the substrate including the driving gate electrode Crystallizing the amorphous silicon and patterning the amorphous silicon using a second mask to form a first active layer on the driving gate electrode, the first active layer being branched to the driving thin film transistor region and the storage region and overlapping the driving gate electrode And a gate electrode Doping is performed using a third mask having a transmissive portion corresponding to the periphery of the driving gate electrode and a transmissive portion corresponding to the periphery of the driving gate electrode around the shielding portion corresponding to the driving gate electrode, A step of forming a low concentration region corresponding to the transflective portion in the first active layer and a high concentration region in the first active layer corresponding to the transparent portion, forming an interlayer insulating film on the gate insulating film including the first active layer, Selectively removing the interlayer insulating film to form source contact holes and drain contact holes in a heavily doped region of the first active layer, and forming source and drain contact holes in the source and drain contact holes, And then patterned using a fifth mask to form driving source electrodes and driving drain electrodes connected to the first active layer May comprise a step.

Here, after the first active layer is formed using the second mask, a supplemental interlayer insulating film is further provided on the surface of the substrate before the impurity doping process using the third mask to protect the back channel in the impurity doping process .

In this case, the step of defining the lightly doped region and the heavily doped region using the third mask may include a step of applying a photoresist film on the gate insulating film including the first active layer, a step of exposing the photoresist film using the third mask, Forming a first photoresist pattern having a first thickness at a position corresponding to the light-shielding portion and having a second thickness lower than the first thickness at a position corresponding to the transflective portion, A step of ashing the first photoresist pattern to remove the second thickness, leaving a second photoresist pattern only in an area corresponding to the light-shielding portion, And a second photoresist pattern which is partially overlapped with the gate electrode and which is adjacent to the heavily doped region It may include the step of defining a concentration zone.

Meanwhile, in the step of forming the source contact hole and the drain contact hole by selectively removing the interlayer insulating film using the fourth mask, a high concentration region of the first active layer under the source contact hole and the drain contact hole Can be removed.

In addition, the organic light emitting diode display of the present invention includes the above-described backplane substrate and organic light emitting diodes. The OLED display device has a plurality of pixel regions as a matrix, a storage capacitor region spaced apart from each other, A gate line and a data line intersecting each other on the substrate to define a pixel region; a driving gate electrode in the driving thin film transistor region; a channel corresponding to an upper portion of the driving gate electrode; A first active layer having a low concentration region partially overlapping the driving gate electrode and a high concentration region in a region outside the driving gate electrode around the low concentration region, and a driving transistor connected to one side of the high concentration region of the first active layer, Electrode and the other active region of the first active layer A storage capacitor in which the drive gate electrode is overlapped with a pattern extending from one side of the high concentration region of the first active layer and a drive capacitor connected to the drive drain electrode, And an organic light emitting diode including an organic light emitting layer on the first electrode and a second electrode on the organic light emitting layer.

In this case, it is preferable that a connecting portion between the first active layer and the driving drain electrode is located at a portion where the driving gate electrode is not overlapped, and the driving drain electrode is extended and overlapped with the driving gate electrode, The bank may further include a bank on which one of the light emitting portions of each pixel region is exposed. In this case, the bank may have a protruding portion with a thick thickness.

The driving source line may include a driving current line integrated with the driving source electrode.

The organic light emitting display device may further include a switching thin film transistor between the gate line and the data line, the switching thin film transistor being overlapped with the gate line and connected to the data line and the driving gate electrode, respectively.

Meanwhile, a method of manufacturing an organic light emitting diode display according to the present invention is a method of manufacturing a backplane substrate described above, wherein a protective film is coated on an interlayer insulating film including the driving source electrode and the driving drain electrode, Exposing a part of the drain electrode; forming a first electrode connected to the drain electrode using a seventh mask; and forming a second electrode on the first electrode by using an eighth mask, Forming a bank by removing the light emitting portion of the bank, and forming an organic light emitting layer and a second electrode sequentially on the first electrode including the bank.

In this case, in the eighth mask, a region excluding the light emitting portion is divided into a first region and a second region, the first region is a light shielding portion, the second region is a transflective portion, And the bank formed using the eighth mask may have a protrusion corresponding to the first region and a thickness lower than the protrusion corresponding to the second region.

INDUSTRIAL APPLICABILITY The backplane substrate of the present invention, the method of manufacturing the same, and the organic light emitting display device using the backplane substrate and the manufacturing method thereof have the following effects.

First, even if the lower metal is omitted, the bottom gate structure is applied to form the gate electrode first, and the active layer is formed later, so that the active layer can prevent the influence of the lower external light, The use of the mask can be reduced more than once.

Second, a storage capacitor is defined in the region of the gate electrode layer and the doped active layer overlapping with the gate electrode layer, so that addition of a mask is not required to form a storage capacitor. That is, in the conventional method, it is possible to simplify the process by preventing addition of a mask required in a process of defining a separate doping region in the storage capacitor region or a process of forming a separate assist gate electrode.

Third, there is an advantage of simplifying the process by going through one mask with the definition of the doped region of the active layer used as the electrode of the storage capacitor and the low concentration region and the high concentration region defined around the channel of the thin film transistor. In this case, a halftone mask or a diffraction exposure mask is used for doping the impurities, the photoresist pattern formed using the halftone mask or the diffraction exposure mask has different thicknesses, and the ashing ) To define a low-concentration region. Thus, it is easy to adjust the length of the low-concentration region according to the shape of the transflective portion provided in the halftone mask or the diffraction exposure mask.

Fourth, by applying the auxiliary interlayer insulating film before the process for defining the impurity doped region, it is possible to prevent the back channel from being damaged, and the reliability of the thin film transistor can be improved.

Fifth, since the channel is defined after the formation of the gate electrode layer, the channel region can be freely formed from the shape of the gate electrode layer, and the structure of the thin film transistor can be easily designed.

1 is a flowchart showing a manufacturing process of a conventional organic light emitting display
2 is a circuit diagram showing one pixel of the organic light emitting diode display of the present invention.
3 is a schematic plan view of one pixel of the organic light emitting diode display of the present invention
4 is a cross-sectional view taken along lines I to I '
5 is a flowchart showing a manufacturing process of the organic light emitting diode display of the present invention
6A to 6H are cross-sectional views showing the steps of a method of manufacturing an organic light emitting display according to the present invention
7 is a cross-sectional view of an OLED display according to another embodiment of the present invention
8A and 8B are cross-sectional views showing a process of doping an impurity in a method of manufacturing a backplane substrate according to another embodiment of the present invention

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products.

In the conventional organic light emitting diode display, the reason why the top gate structure is used is that, in the case of the structure of the bottom gate electrode, an active layer is formed as the taper of the gate electrode is maintained. In the crystallization process, So that a break occurs in the tapered portion of the gate electrode to prevent this point.

The applicant of the present invention has filed an application filed with Application No. 10-2015-0067321 for solving the problem of disconnection of the active layer by changing the shape of the gate electrode even when such bottom gate structure is used.

Thus, the present invention solves the crystalline disconnection in the taper of the gate electrode, such that the angle between the side of the gate electrode and the lower side of the gate electrode, for example, the angle between the substrate surface and the side of the gate electrode, At the same time, the number of masks is reduced during the manufacturing process to improve the yield and simplify the process.

FIG. 2 is a circuit diagram showing one pixel of the organic light emitting diode display according to the present invention, FIG. 3 is a schematic plan view of one pixel of the organic light emitting display according to the present invention, and FIG. 4 is a cross- Sectional view.

The organic light emitting display according to the present invention has a pixel region defined by intersecting a plurality of gate lines GL and data lines DL in a matrix form and includes a switching thin film transistor A driving thin film transistor DT connected to the switching thin film transistor ST and an organic light emitting diode OLED connected to the driving thin film transistor DT. The switching thin film transistor ST is formed in a region where the gate line GL and the data line DL cross each other and functions to select pixels. The storage capacitor Cst is located between the gate electrode DG of the driving thin film transistor DT and the organic light emitting diode OLED.

The driving thin film transistor DT functions to drive the organic light emitting diode OLED of the pixel selected by the switching thin film transistor ST.

More specifically, the structure of the driving thin film transistor DT and the storage capacitor Cst will be described with reference to FIGS. 3 and 4. FIG.

As shown in FIGS. 3 and 4, in each pixel region of the substrate 100 having a storage capacitor region (storage region) and a driving thin film transistor region (DT region) spaced from each other in each pixel region, the driving thin film transistor DT A driving gate electrode 121 passing through the storage capacitor region and a driving thin film transistor region and a channel 150a corresponding to an upper portion of the driving gate electrode 121 in the driving thin film transistor region, A low concentration region 150b partially overlapped with the driving gate electrode 121 and a high concentration region 150c in a region deviated from the driving gate electrode 121 and DG around the low concentration region 150b, A first active layer 150 overlapped with the driving gate electrode 121 of the storage capacitor region through a branch pattern 150d branched from one side of the first active layer 15c, Including driving source electrodes 180 connected to one side of the high concentration region 150c of the first active layer 150 and driving source electrodes DS connected to the other side of the high concentration region 150c of the first active layer 150, Line VDL.

The storage capacitor Cst is defined in a region overlapping the driving gate electrode 121 and the first active layer 150 in the region of the storage capacitor and the first active layer of the overlapping region is doped with a high concentration impurity Concentration region 150d.

The driving source electrode integrated with the driving drain electrode 180 and the driving current line VDL is electrically connected to the interlayer insulating layer 170 and the auxiliary interlayer insulating layer 160 and the heavily doped region of the first active layer 150 The first active layer 150, particularly the high concentration region 150c of the first active layer 150, around the side of the hole and the hole through the first and second contact holes 170a and 170b, As shown in Fig. In this process, a portion of the gate insulating layer 130 under the first and second contact holes 170a and 170b may be over-grazed and removed.

The first and second contact holes 170a and 170b are formed only in the interlayer insulating layer 170 and the auxiliary interlayer insulating layer 160 so that a portion of the high concentration region 150c of the first active layer 150 . In this case, the driving source electrode and the driving drain electrode 180 are in surface contact with the first active layer 150.

The first contact hole 170a connected to the heavily doped region 150c of the first active layer 150 and the driving drain electrode 180 is located at a portion where the driving gate electrode 121 does not overlap do.

The low concentration region 150b of the first active layer 150 partially overlaps the driving gate electrode 121. This is because the low concentration region 150b is formed as a separate mask after the driving gate electrode 121 is formed, . Further, by defining the low-concentration region 150b and the high-concentration region 150c together, it is possible to reduce the mask requirement as described in the manufacturing method described later.

In addition, the driving drain electrode 180 may extend to be overlapped with the driving gate electrode 121, as shown in the drawing. However, the driving drain electrode 180 is not necessarily overlapped with the driving gate electrode 121, and may be formed only to the extent that the driving drain electrode 180 covers the first contact hole 170a.

If the driving drain electrode 180 has an overlap region with the driving gate electrode 121, a storage capacitor is further formed between the driving drain electrode 180 and the driving gate electrode 121 so that the first active layer of the doped high concentration region and the driving gate electrode 121 ), The storage capacitance value can be further improved.

One electrode of the storage capacitor is applied to the driving gate electrode 121, DG by the selection of the switching thin film transistor ST, and the other electrode of the storage capacitor is connected to the first active layer The branching pattern 150d of the first embodiment. In addition, the storage capacitance value can be increased by increasing the area of the branching pattern 150d of the first active layer so as to sufficiently cover the storage capacitor region.

A switching thin film transistor (TFT) is connected between the gate line GL and the data line DL and overlaps the gate line GL and is connected to the data line DL and the driving gate electrodes 121 and DG. The switching thin film transistor ST may overlap the gate line GL and overlap the data line DL and the driving gate electrodes 121 and DG at both ends And a second active layer 155 that connects to the second active layer. In this case, it is preferable that the first and second active layers 150 and 155 are separated from each other and defined together in the same layer.

The second active layer 155 may also define a low concentration region and a high concentration region around the channel.

A portion of the high concentration region of the interlayer insulating film 170, the auxiliary interlayer insulating film 170 and the second active layer 155 is also removed from both ends of the second active layer 155, (170c, 170d) can be formed. In this process, a portion of the gate insulating layer 130 under the third and fourth contact holes 170c and 170d may be over-grazed and removed.

Meanwhile, the structure of the driving thin film transistor and the storage capacitor of the present invention is also referred to as a backplane substrate. Such a backplane substrate can be used not only in organic light emitting devices but also in liquid crystal displays and other display devices.

Particularly, the storage capacitor of the organic light emitting diode display of the present invention is a branch pattern 150d of the first active layer doped with one electrode, and the position of the first contact hole 170a, The first contact hole 170a prevents the branch pattern 150d of the first active layer from shorting with the drive gate electrode 121 by preventing the first contact layer 121 from overlapping. Thereby, the driving gate electrode 121, which is another electrode of the storage capacitor, and the effective storage capacitor can be formed. In this case, the first active layer extends beyond the function of the semiconductor layer of the driving thin film transistor, and the driving gate electrode 121 can be overlapped to be used as a storage electrode.

The organic light emitting diode OLED includes a first electrode 200 connected to the driving drain electrode DD, and a second electrode connected to the driving drain electrode DD of the organic light emitting diode OLED. An organic layer 220 including an organic light emitting layer on the first electrode 200 and a second electrode 230 formed on the entire surface including the organic layer 220.

The layers not illustrated in FIG. 4 are insulating films, 110 is a buffer layer, 130 is a gate insulating film, 160 is an auxiliary interlayer insulating film, 170 is an interlayer insulating film, and 190 is an organic protective film.

Here, the substrate 100 may be made of any one of a glass substrate and a plastic substrate.

The buffer layer 110 may be formed of a single-layer silicon oxide film or a silicon nitride film on the substrate 100, or may be formed of a plurality of layers of these materials.

Further, the auxiliary interlayer insulating film 160 functions to prevent the back channel from being damaged in the impurity doping process. At this time, the thickness of the auxiliary interlayer insulating film 160 is reduced to a thickness of about 1000 ANGSTROM to allow dopants to be doped into a predetermined region.

The organic passivation layer 190 may be formed to planarize the surface of the substrate 100 sufficiently before forming the organic light emitting diode to reduce a step in the light emitting portion of the pixel region.

Reference numeral 210 denotes a bank, which is provided for defining a light emitting portion of a pixel region. An organic layer 220 is deposited inside the bank and a portion of the bank 210 may be formed with a relatively high protrusion. The protrusions are provided in the banks 210 because organic materials corresponding to the organic layers 220 are deposited through separate fine metal masks having openings corresponding to the respective light emitting portions. In this process, the fine metal masks are flat There is a phenomenon in which the height of the bank is not maintained but collapses when the bank corresponds to the bank. That is, the bank 210 is formed at the normal height corresponding to the edge of the actual light emitting portion and a certain width therefrom, and the protruding portion of the bank 210 is provided at the outer periphery thereof.

Hereinafter, a process of consuming a mask in a backplane substrate and a method of manufacturing an organic light emitting display according to the present invention will be described with reference to the drawings.

FIG. 5 is a flow chart showing a manufacturing process of an organic light emitting display according to the present invention, and FIGS. 6A to 6H are sectional views showing a manufacturing method of the organic light emitting display according to the present invention.

6A, a plurality of pixel regions are formed in a matrix shape, and a storage capacitor region (storage region) and a driving thin film transistor region DT Region) is prepared.

Next, a buffer layer 110 is formed on the substrate 100. The buffer layer 110 may be omitted.

Next, as shown in FIG. 5, a driving gate electrode 121 passing through the storage capacitor region and the driving thin film transistor region of the substrate is formed (200S) using a first mask.

Next, a gate insulating layer 130 and an amorphous silicon layer are formed on the buffer layer 110 including the driving gate electrode 121. Next, the amorphous silicon is crystallized and patterned using a second mask to form a first active layer 150 (hereinafter, referred to as " first active layer 150 ") that overlaps the driving gate electrode 121, (210S).

Subsequently, as shown in FIG. 6B, an auxiliary interlayer insulating film 160 is formed on the gate insulating film 130 including the first active layer 150. The reason why the auxiliary interlayer insulating film 160 is further provided after the first active layer is formed using the second mask is to prevent the back channel from being damaged in the impurity doping step, It is for channel protection. That is, the reliability of the thin film transistor can be improved by applying the auxiliary interlayer insulating film 160 before the process for defining the impurity doped region.

Next, a light-shielding portion corresponding to the driving gate electrode 121 of the driving thin film transistor region, a semi-transparent portion corresponding to the periphery of the driving gate electrode 121 around the light-shielding portion, and a light- 3, the photosensitive film 310 is formed by applying the exposure and development process of the photosensitive film on the auxiliary interlayer insulating film 160, as shown in FIG. 6C. In this case, the photoresist layer 310 may be formed by applying a photoresist layer on the auxiliary interlayer insulating layer 160 including the first active layer 150, and exposing and developing the photoresist layer using the third mask. And forming a photoresist layer 310 having a first thickness at a position corresponding to the light-shielding portion and a second thickness lower than the first thickness at a position corresponding to the transflective portion.

As shown in FIG. 6C, a region of the first active layer 150 exposed by the photoresist layer 310 is doped with a high-concentration impurity to define a high-concentration region 150c. Here, the branch pattern 150d of the first active layer 150 is also doped with a high concentration impurity (220S).

As shown in FIG. 6D, ashing is performed to remove the second thickness of the photoresist layer 310, leaving a photoresist pattern 310a only in a region corresponding to the light-shielding portion in the third mask.

6D, a region exposed by the photoresist pattern 310a is doped with a low-concentration impurity to form a low-concentration region 150b (a part of which overlaps the drive gate electrode 121 and is adjacent to the high-concentration region 150c) ).

There is an advantage of simplifying the process by proceeding to a single mask with the definition of the doped region of the active layer used as the electrode of the storage capacitor and the low concentration region and the high concentration region defined around the channel of the thin film transistor. In this case, a halftone mask or a diffraction exposure mask is used for doping the impurities, the photoresist pattern formed using the halftone mask or the diffraction exposure mask has different thicknesses, and the ashing ) To define a low-concentration region. Thus, it is easy to adjust the length of the low-concentration region according to the shape of the transflective portion provided in the halftone mask or the diffraction exposure mask.

Since the channel 150a of the first active layer 150 is defined after the formation of the first active layer 150 separately from the formation of the driving gate electrode 121, The channel region 150a and the lightly doped region 150b can be freely formed, and the structure of the thin film transistor can be easily designed.

6E, a thickness of a part of the interlayer insulating layer 170, the auxiliary interlayer insulating layer 160, the first active layer 150, and the gate insulating layer 130 is selectively removed to form the first active layer 150 A first contact hole (drain contact hole) 170a and a second contact hole (source contact hole) 170b are formed in the heavily-doped regions of the source and drain regions, respectively.

Then, a metal filling the first and second contact holes 170a and 170b is deposited and patterned using a fifth mask to form a driving source electrode DS connected to the first active layer 150, And a drain electrode 180b is formed (240S).

In the meantime, although the above-described manufacturing method has been described mainly on the driving thin film transistor and the storage capacitor, the switching thin film transistor is also formed in the same process.

In addition, in the same process as the driving gate electrode 121, the gate line GL is elongated in one direction, and is integrated with the driving source electrode 170a and is driven in a direction crossing the gate line GL A data line DL may be formed in parallel with the driving current line VDL and integrated with the source electrode of the switching thin film transistor in the same process as the driving current line VDL have.

In addition, the method can be used as a manufacturing method of the backplane substrate up to the formation of the driving thin film transistor, the switching thin film transistor, and the storage capacitor.

The organic light emitting display according to the present invention may be formed by applying a bottom gate structure even if the lower shielding metal is omitted to form the driving gate electrode 121 first and then the first active layer 150 to form the driving gate electrode 121 Can be prevented from affecting the external light of the lower part on the first active layer 150, and the mask can be used more than twice while maintaining the same function as the conventional structure.

In addition, a storage capacitor is defined by the driving gate electrode 121 and the branch pattern 150d of the doped first active layer 150, so that addition of a mask is not required to form a storage capacitor. That is, in the conventional method, it is possible to simplify the process by preventing addition of a mask required in a process of defining a separate doping region in the storage capacitor region or a process of forming a separate assist gate electrode.

6F, the organic passivation layer 190 is coated on the interlayer insulating layer 180 including the driving source electrode DS and the driving drain electrode 180, and then selectively removed to form a sixth mask A protective film contact hole 190a is formed to expose a part of the driving drain electrode 180 (250S).

Next, a first electrode 200 connected to the driving drain electrode 180 is formed using a seventh mask (260S).

6G, the bank 210 is formed on the first electrode 200 except for the light emitting portion of the pixel region by using the eighth mask (270S). The eighth mask includes a first region and a second region except for the light emitting portion, wherein the first region is a light-shielding portion, the second region is a transflective portion, and the region corresponding to the light- .

Accordingly, the bank 210 formed using the eighth mask can have a protruding portion 210b corresponding to the first region and a flat bank portion 210a having a thickness lower than the protruding portion corresponding to the second region have.

6H, an organic layer 220 including an organic light emitting layer and a second electrode 230 are sequentially formed on the first electrode 200 including the bank 210. [

Here, the organic layer 220 including the organic light emitting layer may be deposited on the first electrode 200 by a vapor deposition method using a fine metal mask having an opening. In some cases, the organic layer 220 may be formed over the entire area without distinguishing the areas, and further color filters may be further formed to distinguish the colors of the pixels. In this case, the bank forming step may be omitted.

In the process sectional views, the first to eighth masks are not shown in the drawing, and the remaining patterns are shown so as to be visible after each masking step.

When a fine metal mask is used to form the organic layer 220, the fine metal mask deposits an organic material in the openings in a contact or close contact manner, unlike the mask used in the exposure process. To 8 < th > masks, which are not directly affected by the yield.

Hereinafter, an OLED display according to another embodiment of the present invention will be described.

7 is a cross-sectional view illustrating an OLED display according to another embodiment of the present invention.

The organic light emitting diode display according to another embodiment of the present invention is different from that of FIG. 7 in that the auxiliary insulating layer is omitted in comparison with the previous embodiment.

When the auxiliary interlayer insulating film is omitted, the impurity doping process is performed immediately after the formation of the first active layer 150, and the impurity implantation process is performed immediately after the first active layer 150 of FIG. 6A is defined. The same components as those in the previous embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

8A and 8B are cross-sectional views illustrating an impurity doping process in a method of manufacturing a backplane substrate according to another embodiment of the present invention.

That is, as shown in FIG. 8A, the impurity implantation process is performed on the gate insulating film 130 including the first active layer 150.

A third mask having a light shielding portion corresponding to the driving gate electrode 121 of the driving thin film transistor region, a semi-transparent portion corresponding to the periphery of the driving gate electrode 121 around the light shielding portion, 8A, a photoresist layer 310 is formed by applying a photoresist layer on the gate insulating layer 130 and exposing and developing the photoresist layer. In this case, the photoresist layer 310 may be formed by applying a photoresist layer on the gate insulating layer 130 including the first active layer 150, and exposing and developing the photoresist layer using the third mask And forming a photoresist layer 310 having a first thickness at a position corresponding to the light-shielding portion and a second thickness lower than the first thickness at a position corresponding to the transflective portion.

The heavily doped region 150c is defined by doping a region of the first active layer 150 exposed by the photoresist layer 310 with a high concentration impurity. Here, the branch pattern 150d of the first active layer 150 is also doped with a high concentration impurity (220S).

As shown in FIG. 8B, ashing is performed to remove the second thickness of the photoresist layer 310, leaving a photoresist pattern 310a only in the region corresponding to the light-shielding portion in the third mask.

A low concentration region 150b adjacent to the driving gate electrode 121 and partially overlapping the high concentration region 150c is defined by doping a region exposed by the photoresist pattern 310a with a low concentration impurity.

There is an advantage of simplifying the process by going through one mask with the definition of the doped region of the first active layer used as the electrode of the storage capacitor and the low concentration region and the high concentration region defined around the channel of the thin film transistor.

After the impurity doping process, the same process as in FIGS. 6E to 6H is applied to the method of manufacturing an organic light emitting display according to another embodiment of the present invention.

In the organic light emitting diode display according to another embodiment of the present invention, the auxiliary interlayer insulating film may be omitted when the doping region is easily controlled without diffusion in a region not to be formed during impurity implantation.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

100: substrate 110: buffer layer
GL: gate line 121: driving gate electrode
130: gate insulating film DL: data line
160: auxiliary interlayer insulating film VDL: driving current line
150: first active layer 155: second active layer
170: interlayer insulating film 190: protective film
170a to 170d: Contact hole ST: Switching transistor
SG: switching gate electrode SS: switching source electrode
SD: switching drain electrode DT: driving transistor
DG: driving gate electrode DS: driving source electrode
DD: driving drain electrode 200: first electrode
210: bank 220: organic layer
230: second electrode 190a: protective film contact hole

Claims (22)

A substrate having a plurality of pixel regions in a matrix form and having a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region;
A gate line and a data line crossing each other on the substrate to divide the plurality of pixel regions;
A driving gate electrode passing through the storage capacitor region and the driving thin film transistor region in each pixel region on the substrate;
A channel region corresponding to an upper portion of the driving gate electrode in the driving thin film transistor region, a low concentration region partially overlapping the driving gate electrode around the channel, and a high concentration region in an area outside the driving gate electrode around the low concentration region A first active layer that branches from one side of the high concentration region and overlaps with the driving gate electrode of the storage capacitor region;
A driving drain electrode connected to one side of the high concentration region of the first active layer; And
And a driving current line including a driving source electrode connected to the other side of the high-concentration region of the first active layer. The method according to claim 1,
Wherein the first active layer overlapping the driving gate electrode in the region of the storage capacitor is a high concentration region. The method according to claim 1,
Wherein the driving drain electrode and the driving source electrode are respectively connected to the first active layer around the hole and the side of the hole through a hole penetrating a part of the high concentration region of the first active layer. The method according to claim 1,
The connecting portion between the first active layer and the driving drain electrode is located at a portion where the driving gate electrode is not overlapped,
Wherein the driving drain electrode extends and overlaps with the driving gate electrode. The method according to claim 1,
Further comprising: a switching thin film transistor between the gate line and the data line, the switching thin film transistor being overlapped with the gate line and connected to the data line and the driving gate electrode, respectively. 6. The method of claim 5,
The switching thin film transistor includes a second active layer overlapping the gate line and connected to the data line and the driving gate electrode at both ends. The method according to claim 6,
Wherein the first and second active layers are located in the same layer. Preparing a substrate having a plurality of pixel regions as a matrix and having a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region;
Forming a driving gate electrode through the storage capacitor region and the driving thin film transistor region of the substrate using a first mask;
Forming a gate insulating layer and an amorphous silicon layer on the substrate including the driving gate electrode;
Crystallizing the amorphous silicon and patterning the amorphous silicon using a second mask to form a first active layer on the driving gate electrode, the first active layer being branched to the driving thin film transistor region and the storage region and overlapping the driving gate electrode;
And a third mask having a transmissive portion corresponding to the periphery of the driving gate electrode and a transmissive portion corresponding to the periphery of the driving gate electrode around the shielding portion in correspondence to the driving gate electrode of the driving thin film transistor region, Doping the first active layer to define a lightly doped region corresponding to the transflective portion and a heavily doped region in the first active layer corresponding to the transmissive portion;
An interlayer insulating film is formed on the gate insulating film including the first active layer and the interlayer insulating film is selectively removed by using a fourth mask so that source contact holes are formed in heavily doped regions of the first active layer, And forming a drain contact hole; And
Depositing a metal on the source and drain contact holes and patterning the source and drain contact holes using a fifth mask to form driving source electrodes and driving drain electrodes connected to the first active layer. 9. The method of claim 8,
Wherein the step of defining the low-concentration region and the high-concentration region using the third mask comprises:
Applying a photoresist over the gate insulating film including the first active layer;
And exposing and developing the photoresist using the third mask to form a first photoresist layer having a first thickness at a position corresponding to the light shielding portion and a second thickness at a position corresponding to the transflective portion, Forming a pattern;
Doping a region of the first active layer exposed by the first photoresist pattern with a high concentration impurity;
Ashing the first photoresist pattern to remove the second thickness, leaving a second photoresist pattern only in an area corresponding to the light-shielding portion; And
Doping a region exposed by the second photoresist pattern with a low concentration impurity to define a low concentration region partially overlapped with the gate electrode and adjacent to the high concentration region. 9. The method of claim 8,
Forming a second interlayer insulating film on the gate insulating film including the first active layer before forming the low active region and the high active region by using the third mask after forming the first active layer. 9. The method of claim 8,
In the step of forming the source contact hole and the drain contact hole by selectively removing the interlayer insulating film using the fourth mask,
And removing the high concentration regions of the first active layer under the source contact holes and the drain contact holes, respectively. A substrate having a plurality of pixel regions in a matrix form and having a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region;
A gate line and a data line crossing each other on the substrate to divide the pixel region;
A driving gate electrode in the driving thin film transistor region, a channel corresponding to an upper portion of the driving gate electrode, a low concentration region partially overlapping the driving gate electrode in the periphery of the channel, and a low concentration region overlapping the driving gate electrode in the periphery of the low concentration region A driving thin film transistor including a first active layer having a high concentration region, a driving drain electrode connected to one side of the high concentration region of the first active layer, and a driving source electrode connected to the other side of the high concentration region of the first active layer;
A storage capacitor having a storage capacitor region in which a driving gate electrode overlaps with a pattern extending from one side of a high concentration region of the first active layer; And
An organic light emitting diode including a first electrode connected to the driving drain electrode, and an organic light emitting layer on the first electrode and a second electrode on the organic light emitting layer. 13. The method of claim 12,
Wherein the driving drain electrode and the driving source electrode are respectively connected to the first active layer around the hole and the side of the hole through a hole penetrating a part of the high concentration region of the first active layer. 13. The method of claim 12,
The connecting portion between the first active layer and the driving drain electrode is located at a portion where the driving gate electrode is not overlapped,
Wherein the driving drain electrode is extended and overlapped with the driving gate electrode. 13. The method of claim 12,
Further comprising: a bank on which a light emitting portion of each pixel region is exposed on the first electrode. 13. The method of claim 12,
And a driving current line integrated with the driving source electrode. 16. The method of claim 15,
Wherein the bank has a protrusion thicker at a portion thereof. 13. The method of claim 12,
One side of the high-concentration region of the first active layer and the connection portion of the driving drain electrode are located so as not to overlap with the driving gate electrode,
Wherein the pattern extending from one side of the high-concentration region of the first active layer extends from one side of the first active layer to the connection portion between the driving drain electrode and the driving gate electrode. 13. The method of claim 12,
Further comprising a switching thin film transistor between the gate line and the data line, the switching thin film transistor being overlapped with the gate line and connected to the data line and the driving gate electrode, respectively. Preparing a substrate having a plurality of pixel regions as a matrix and having a storage capacitor region and a driving thin film transistor region spaced apart from each other in each pixel region;
Forming a driving gate electrode through the storage capacitor region and the driving thin film transistor region of the substrate using a first mask;
Forming a gate insulating layer and an amorphous silicon layer on the substrate including the driving gate electrode;
Crystallizing the amorphous silicon and patterning the amorphous silicon using a second mask to form a first active layer on the driving gate electrode, the first active layer being branched to the driving thin film transistor region and the storage region and overlapping the driving gate electrode;
And a third mask having a transmissive portion corresponding to the periphery of the driving gate electrode and a transmissive portion corresponding to the periphery of the driving gate electrode around the shielding portion in correspondence to the driving gate electrode of the driving thin film transistor region, Doping the first active layer to define a lightly doped region corresponding to the transflective portion and a heavily doped region in the first active layer corresponding to the transmissive portion;
An interlayer insulating film is formed on the gate insulating film including the first active layer and the interlayer insulating film is selectively removed by using a fourth mask so that source contact holes are formed in heavily doped regions of the first active layer, And forming a drain contact hole;
Depositing a metal on the source and drain contact holes and patterning the source and drain contact holes using a fifth mask to form a driving source electrode and a driving drain electrode connected to the first active layer;
Exposing a portion of the driving drain electrode using a sixth mask after applying a protective film on the interlayer insulating film including the driving source electrode and the driving drain electrode;
Forming a first electrode connected to the driving drain electrode using a seventh mask;
Forming a bank on the first electrode by using an eighth mask, excluding a light emitting portion of the pixel region; And
And forming an organic light emitting layer and a second electrode sequentially on the first electrode including the bank. 21. The method of claim 20,
The eighth mask may be divided into a first region and a second region except for the light emitting portion, wherein the first region is a light shielding portion and the second region is a transflective portion,
And the region corresponding to the light emitting portion is a transparent portion. 22. The method of claim 21,
The bank formed by using the eighth mask is,
Wherein the protrusion has a thickness corresponding to the first region and a thickness lower than the protrusion corresponding to the second region.

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