KR20160137558A - Testing apparatus for cross over communications jack and methods of operating the same - Google Patents

Abstract

A substrate, a plurality of vias located in the substrate, a plurality of pin traces having a height and a width, each extending from the vias toward a side of the substrate and ending at an end point, a plurality of end points A plurality of end traces each having a height and a width and each extending from an end point of each pin trace to a corresponding end point near the pin trace, a plurality of traces extending from an end of each end point or end point to an edge of the substrate Wherein a pair of adjacent end traces and a pair of adjacent end points are adjacent to each other such that end points and end points of each pin trace are adjacent to each other.

Description

TECHNICAL FIELD [0001] The present invention relates to a test apparatus for a crossover communication jack, and a test apparatus for the crossover communication jack.

The present invention relates to a testing framework of a network connection jack used to connect a network cable to a device.

Telecommunication devices and related applications are becoming more sophisticated and powerful, so their ability to collect information and share information with other devices is becoming even more important. The growth of these intelligent, inter-networked devices has resulted in increased data rates in the networks to which they are connected to provide the increased data rates needed to meet these needs. As a result, existing communication protocol standards are constantly improving or new. Many of these standards require significant or even significant benefits from the communication of high-resolution signals over wired networks. The transmission of high resolution signals, which may be more broadband and correspondingly requiring higher frequencies, needs to be supported in a continuous manner. However, even the latest versions of various standards provide theoretically higher data rates, so high-resolution signals are still limited in speed by the current design of certain physical components. Unfortunately, a lack of understanding of what is needed to achieve sustained signal quality at multi-gigahertz and higher frequencies is hampering the design of these physical elements.

For example, a communication jack is used in a device for connecting a communication device, and a cable used to transmit and receive electrical signals representing the communication data. Registered jack (RJ) is a standardized physical interface for connecting telecommunication and data devices. The RJ interface includes both a jack configuration and a wiring pattern. A commonly used RJ interface for a data device is an RJ45 physical network interface, also referred to as an RJ45 jack. RJ45 jacks are widely used for local networks such as networks that carry the Institute of Electrical and Electronic Engineers (IEEE) 802.3 Ethernet protocol. RJ45 jacks are described in various standards, including those published by the American National Standards Institute (ANSI) / Telecommunication Industry Association (TIA) of ANSI / TIA-1096-A.

All electrical interface configurations, such as cables and jacks, including RJ45 jacks, resist not only the initial flow of current but also any change in current flow. This characteristic is called reactance. Two related types of reactance are the inductive reactance and the capacitive reactance. The inductive reactance is based, for example, on the movement of current through a cable with resistance, and the movement of the current results in a magnetic field which induces a voltage on the cable. Capacitive reactance, on the other hand, is produced by the electrostatic charge appearing when electrons from two opposing surfaces are placed in close proximity.

It is desirable that the various components of the communication circuit have a maching impedance to reduce or avoid degradation of the transmitted signal. Otherwise, a load with one impedance value will echo a portion of the signal carried by the cable with a different impedance level, resulting in signal impairment. Because of this, telecommunications equipment designers and manufacturers such as cable vendors design and test their cables to prove that impedance values, as well as cable resistance and capacity levels, follow certain performance parameters. RJ45 jacks are also important in almost all communication circuits, and jack manufacturers have not had a corresponding level of interest in their performance. Therefore, although the problems associated with conventional RJ45 jacks are also documented in experiments and the negative impact on high-frequency signal lines is well recognized, the industry seems to be passive in solving the problem of critical configuration of the physical layer, There has been a demand for high speed jacks.

One embodiment of the present invention provides a semiconductor device comprising a substrate, a plurality of vias located in the substrate, a plurality of pin traces having a height and width, each extending from the respective vias toward a side of the substrate and ending at an end point, A plurality of end points adjacent to the point, a plurality of end traces each having a height and a width and each extending from an end point of each pin trace to a corresponding end point near the pin trace, Wherein a pair of adjacent end traces and a pair of adjacent end points are each adjacent to a different trace and a test unit in which end points and end points of each pin trace are adjacent to one another.

In another embodiment, each pin trace is spaced from each trace by a first distance.

In another embodiment, each end point is spaced from each trace by a second distance.

In another embodiment, each end point is connected to an end point of the pin trace that is not adjacent to the end point by an end trace.

In another embodiment, adjacent pin traces are spaced a third distance apart.

In another embodiment, the test unit includes a ground plane on the substrate that is spaced from each trace by a certain distance.

In another embodiment, the height and width of adjacent traces and the distance separating adjacent traces are adjusted such that adjacent traces are magnetically coupled.

In another embodiment, the inductance and capacitance of each trace is adjusted by adjusting the first distance between the ground plane and each trace.

In another embodiment, the height and width of the adjacent end traces are adjusted such that the end traces are magnetically coupled.

In another embodiment, the substrate is RO XT8100, Rogers material.

In another embodiment, the capacity of each trace is adjusted to be 0.51 pF to 2 pF.

In another embodiment, the inductance and capacitance of each trace is adjusted by adjusting the distance between the first ground plane and the second ground plane and the distance between the first ground plane and each trace.

In another embodiment, the pins of the RJ45 jack are connected to each via.

In another embodiment, the ends of each trace are magnetically coupled to the connecting unit.

In another embodiment, the connection unit is an RJ59 connector.

In another embodiment, the height and width of adjacent pin traces and the distance separating adjacent pin traces are adjusted to magnetically couple adjacent pin traces.

In another embodiment, the height and width of the adjacent end point and the adjacent end point, and the distance separating the adjacent end point and the end point are adjusted such that the adjacent end point and the adjacent end points are magnetically coupled.

In another embodiment, the inductance and capacitance of each endpoint and endpoint is adjusted by adjusting the distance between the ground plane and each endpoint and the branch trace.

In another embodiment, the inductance and capacitance of each pin trace is adjusted along the length of the trace by adjusting the distance between the ground plane and each end trace.

Figure 1 illustrates a test unit for a high speed communication jack.
Figure 2 illustrates the matching unit of the test unit of Figure 1;
Figure 3 is a schematic diagram of the test framework of Figure 1;
Figure 4 is a diagram of the circuit formed in the test unit of Figure 1;
5 shows an embodiment of a test unit for a high speed communication jack.
Figure 6 shows an embodiment for connection of a test unit for two high speed communication jacks.

Figure 1 illustrates a test unit 100 for a high speed communication jack. The test unit 100, or test framework, includes a pin connection 102 configured to secure to a high speed communication jack, such as, but not limited to, an RJ45 communication jack. The traces 104, 106, 108, 110, 112, 114, 116 and 118 extend radially from the pin connection 102 to the outer edge of the test unit 100. The ends of each trace 104, 106, 108, 110, 112, 114, 116, and 118 terminate at the edge of the test unit 100 to permit the connection of a communication unit (not shown). The connection units 120, 122, 124, 126, 128, 130, 132, and 134 may be any type of connector, including, but not limited to, RJ45 connectors.

2 is an exploded perspective view of another embodiment of the pin connector 102. Fig. The pin connection 102 includes vias 204, 206, 208, 210, 212, 214, 216, and 218 sized to engage pins of a high speed communications jack. The pin traces 220,222,224,226,228,230,232 and 234 extend radially from the vias 204,206,208,210,212,214,216 and 218 towards the traces 104,106,108,110,112,114,116 and 118. Each pin trace 220, 222, 224, 226, 228, 230, 232 and 234 extends to end points 236, 238, 240, 242, 244, 246, 248 and 250. Each pin trace 220, 222, 224, 226, 228, 230, 232, and 234 also matches adjacent pin traces 220, 222, 224, 226, 228, 230, 232, and 234. As illustrated, the pin trace 220 matches the pin trace 222, the pin trace 224 matches the pin trace 226, the pin trace 228 matches the pin trace 230, Trace 232 matches pin trace 234. Each pin trace 220, 222, 224, 226, 228, 230, 232 and 234 has a length L, a height H and a width W and is spaced from the adjacent pin traces by a distance S. The width of each pin trace 220, 222, 224, 226, 228, 230, 232, and 234 is about 35 mil. By adjusting the length, height, and width of adjacent pin traces, the inductance of adjacent pin traces can be matched to each other. End points 236, 238, 240, 242, 244, 246, 248 and 250 of each pin trace are spaced from each trace 102, 104, 106, 108, 110, 112 or 114 by a predetermined distance Se.

The end traces 252,254,256,258,260,263,264 and 266 extend from each end point 236,238,240,242,244,246,248 or 250 of the pin traces 220,222,224,226,228,230,232 and 234 to the end point 268,270,272,274,276,278,280 or 282. [ The end traces 252,254,256,258,260,263,264 and 266 may also extend from the sides of the pin traces 220,222,224,226,228,230,232 and 234 to end points 268,270,272,274,276,278,280 or 282. [ The end points 268, 270, 272, 274, 276, 278, 280, or 282 are spaced from the ends of each trace 102, 104, 106, 108, 110, 112 or 114 by a predetermined distance Se. In one embodiment, the distance Se is constant along the length of the end traces 252, 254, 256, 258, 260, 263, 264 and 266. In another embodiment, the distance Se varies along the length of the end traces 252, 254, 256, 258, 260, 263, 264 and 266. Each end trace 252, 254, 256, 258, 260, 263, 264 and 266 has a length L, a width W and a height H. Different guiding and conduction structures can be obtained by adjusting the length, height and width of each end trace 252, 254, 256, 258, 260, 263, 264, and 266 with spacing Se. The width of each of the branch traces 234, 236, 238, and 240 may be about 35 mils. The width of each end trace 252, 254, 256, 258, 260, 263, 264, and 266 may be about 10 mils.

3 is a cutaway view of the pin connecting portion 102. Fig. The pin connection portion 102 includes an upper surface 304. End points 236 and 238 and end points 268 and 270 are positioned on top surface 304 so as to alternate across the top surface 304 of the substrate. The first ground trace 306 and the second ground trace 308 are located in a dielectric layer beneath the top surface and the first ground trace 306 is formed on the top surface 304 by a first dielectric layer having a height H1. Respectively. The second ground trace 308 is spaced from the first ground trace 306 by a second dielectric layer 310 having a second height H2. The capacitance of each trace, end point, and end point can be adjusted by adjusting the heights (H1, H2) of the dielectric layers (308, 310). The impedance of each end trace 252,254,256,258,260,263,264 and 266, pin traces 220,222,224,226,228,230,232 and 234, endpoints 236,238,240,242,244,246,248 or 250 and endpoints 268,270,272,274,276,278,280 or 282 can be adjusted by varying their length, width and height have. By adjusting the impedance of the adjacent traces, endpoints, and endpoints, adjacent traces and points can be magnetically coupled to each other, eliminating crosstalk or noise. The dielectric layer is made of any material having a dielectric constant of 3.0 or higher, such as, but not limited to RO XT8100, ROGERS material, or any material capable of insulating high frequency electrical signals.

4 is a diagram of a circuit formed in the test unit 100 of FIG. The schematic includes a connection 402, an input stimulus 404, an RJ45 high speed communication jack 406, and an output load 408. RJ45 high speed communications jack 406 includes traces 410 and 412 that are connected to pins 416 and 418 that engage vias 422 and 424. The vias 422 and 424 are electrically connected to the pin traces 424 and 426 of the test unit 100. The length, width, height and spacing of the end traces 252, 254, 256, 258, 260, 263, 264 and 266 and the pin traces 220, 222, 224, 226, 228, 230, 232 and 234 are adjusted to produce different capacitance values along the length of the traces 102, 104, 106, 108, 110, 112 or 114. The inductance of each pin trace is determined by the height H1 of the dielectric layer beneath the pin traces 220,222,224,226,228,230,232 and 234 and the distance between the second ground trace 306 and the first ground trace 304 beneath each of the pin traces 220,222,224,226,228,230,232 and 234 Is changed by adjusting the height H2. The capacitors formed by the pin traces 220, 222, 224, 226, 228 and the ground traces 304, 306 have a size between about 1 pF (picofarad) and about 5 pF. The upper and lower surfaces of the unit 100 are covered with a plastic insulator to further improve the operation of the circuit.

The capacitors produced by the traces 102, 104, 106, 108, 110, 112 or 114 and the ground traces 304, 306 have a size of from about 0.51 pF to about 2 pF. The upper and lower surfaces of the unit 100 are covered with a plastic insulating layer to further improve the operation of the circuit. In one embodiment, the signal is driven through the line using a power of about 4 mW to 20 mW.

5 shows an embodiment of a test unit for a high speed communication jack. The test unit 500 includes an RJ type connector, a universal serial bus (USB) connector and jack, a Fire-wire (1394) connector and jack, a High-Definition Multimedia Interface And a high speed communication link to the connection 102 of the test unit, which may be a jack, a D-subminiature type connector and jack, a ribbon type connector or jack, or any other connector or jack that receives a high speed communication signal Lt; / RTI > The high speed communication jack 502 is connected to the connection portion 102 such that each pin of the high speed communication jack 502 corresponds to one of the vias 204, 206, 208, 210, 212, 214, 216 and 218. The high speed communication jack 502 may be configured such that the pairs of pins are magnetically coupled together.

Each trace 104, 106, 108, 110, 112, 114, 116 and 118 extends from the connection 102 to the connection units 120, 122, 124, 126, 128, 130, 132 and 134. The connection units 120, 122, 124, 126, 128, 130, 132 and 134 are configured such that a cable having a connector such as an RJ45 connector is detachably attached to each of the connection units 120,122,124,126,128,130,132 and 134. The connection units 120, 122, 124, 126, 128, 130, 132 and 134 transmit signals from the associated traces 104, 106, 108, 110, 112, 114, 116 or 118 connected to the connection units 120, The connecting units 104, 106, 108, 110, 112, 114, 116 and 118 are fixed to a connecting plate 504 extending around the periphery of the test unit 500. The connecting plate 504 may be made of a metal such as a steel or a matallized plastic. Each connecting unit 104,106,108,110,112,114,116 and 118 is secured to the side of the connecting plate 504 such that the central axis of the connecting unit 104,106,108,110,112,114,116 and 118 is substantially parallel to the surface of the test unit 500. [

Figure 6 shows a schematic view of a plurality of networked test units. The first test unit 602 and the second test unit 604 are connected by a cable 606 connected to the high-speed communication jack of each test unit 602,604. The cable 606 may be a communication cable such as an Ethernet cable, a category 5, 6 or 7 cable, a serial cable, a wire-wire cable, a USB cable, or any other type of communication cable. The cable 606 includes a connector (not shown) that allows the cable 606 to be releasably connected to the high speed communication jack. In one embodiment, the high speed communication jack of the first test unit 602 is of the same type as the high speed communication jack of the second test unit 604. In another embodiment, the high speed communications jack of the first test unit 602 is of a different type than the high speed communications jack of the second test unit 604. [ The cable may be of any length, including but not limited to 3, 6, 10, 12, 15 or 20 feet.

Each connecting unit 104, 106, 108, 110, 112, 114, 116 or 118 is connected to the signal transmitting and receiving unit 610, 612 via a cable coupled to the signal transmitting and receiving unit 610, 612 on the opposite side to the connecting unit 104, 106, 108, 110, 112, 114, In one embodiment, the signal transmitting and receiving units 610 and 612 transmit signals from the first test suite 602 to the second test unit 604 via the high speed communication jacks of the first and second test units 602 and 604 . Upon receipt of the signal, the second test unit 604 sends a signal to the signal transmitting and receiving unit 612. In one embodiment, the signal transmitting and receiving unit 612 transmits the new signal back to the signal transmitting and receiving unit 610 via the cable 608. In one embodiment, the signal transmitting and receiving unit 612 transmits a second signal based on the signal previously transmitted by the signal transmitting and receiving unit 610 to the signal transmitting and receiving unit 612. In another embodiment, the signal transmitting and receiving unit 612 transmits a second signal substantially identical to the signal previously transmitted by the signal transmitting and receiving unit 610 to the signal transmitting and receiving unit 610.

The foregoing description is only some examples and embodiments of this disclosure, and various changes to the disclosed embodiments can be made without departing from the scope of the present invention. Accordingly, the above detailed description is not intended to limit the scope of the invention, but to provide a person skilled in the art with a sufficient explanation to practice the invention.

Claims (20)

Board,
A plurality of vias located on the substrate,
A plurality of pin traces having a height and width, each extending from the respective vias toward a side of the substrate and terminating at an end point,
A plurality of end points adjacent to an end point of the pin trace,
A plurality of end traces each having a height and width and each extending from an end point of each pin trace toward a corresponding end point near the pin trace,
And a plurality of traces extending from an end of each end point or end point to an edge of the substrate,
Wherein a pair of adjacent end traces and a pair of adjacent end points are adjacent to each other such that the end points and the end points of each pin trace are adjacent to each other. The test unit of claim 1, wherein each pin trace is spaced from each trace by a first distance. 2. The test unit of claim 1, wherein each end point is spaced from each trace by a second distance. The test unit of claim 1, wherein each end point is connected to an end point of the pin trace that is not adjacent to the end point by an end trace. The test unit of claim 1, wherein adjacent pin traces are spaced a third distance apart. The test unit of claim 1, wherein the substrate includes a ground plane spaced from each trace by a predetermined distance. 2. The test unit of claim 1 wherein the height and width of adjacent traces and the distance separating adjacent traces are adjusted such that adjacent traces are magnetically coupled. 7. The test unit of claim 6 wherein the inductance and capacitance of each trace is adjusted by adjusting a first distance between the ground plane and each trace. 5. The test unit of claim 4, wherein the height and width of the adjacent end traces are adjusted such that the end traces are magnetically coupled. The test unit of claim 1, wherein the substrate is a RO XT8100, Rogers material. 9. The test unit of claim 8 wherein the capacity of each trace is adjusted to be between 0.51 pF and 2 pF. 7. The test unit of claim 6 including a second ground plane positioned between a first ground plane and a surface of the substrate opposite the surface of the substrate having a plurality of traces. 13. The test unit of claim 12 wherein the inductance and capacitance of each trace is adjusted by adjusting the distance between the first ground plane and the second ground plane and the distance between the first ground plane and each trace. The test unit of claim 1, wherein a pin of an RJ45 jack is connected to each via. 2. The test unit of claim 1, wherein the ends of each trace are magnetically coupled to a connecting unit. 16. The test unit of claim 15, wherein the connecting unit is an RJ45 connector. The test unit of claim 1, wherein the height and width of adjacent pin traces and the distance separating adjacent pin traces are adjusted such that adjacent pin traces are magnetically coupled. 2. The test unit of claim 1, wherein the height and width of the adjacent end point and the adjacent end point and the distance separating the adjacent end point and the end point are adjusted such that the adjacent end point and the adjacent end points are magnetically coupled. 7. The test unit of claim 6 wherein the inductance and capacitance of each endpoint and endpoint is adjusted by adjusting the distance between the ground plane and each endpoint or endpoint. 7. The test unit of claim 6, wherein the inductance and capacitance of each pin trace is adjusted along the length of the trace by adjusting the distance between the ground plane and each end trace.

Images