JP2018536974A - Jack for high-speed communication - Google Patents

Abstract

A housing having a port having a plurality of pins each receiving a plug and connected to a corresponding signal line of the plug, a shield case surrounding the housing, and a rigid circuit board in the housing, wherein the substrate and each via are on the housing A plurality of vias extending through the substrate, each trace extending from a corresponding one of the plurality of vias, a plurality of traces on an intermediate layer of the substrate, and a middle of the substrate A first shield layer on a first side of the layer, a second shield layer on a second side of the intermediate layer of the substrate, and a third shield layer adjacent to the second shield layer, A high-speed communication jack comprising a rigid circuit board.
[Selection] Figure 4A

Description

[Cross-reference of related applications]
This disclosure claims priority to US Pat. No. 8,858,266 entitled “HIGH SPEED COMMUNICATION JACK” filed on January 11, 2013, October 1, 2014. “HIGH SPEED COMMUNICATION JACK” filed on December 1, 2015, claiming priority over US Pat. No. 9,337,592, entitled “HIGH SPEED COMMUNICATION JACK” This is a continuation-in-part of US patent application Ser. No. 14 / 955,166, entitled “JACK”. All of these US patents and US patent applications are hereby incorporated by reference in their entirety.

  The present disclosure relates to a network connection jack used to connect a network cable to a device.

  As telecommunication equipment and related applications of telecommunication equipment become more sophisticated and powerful, the ability of telecommunication equipment to collect information and share information with other equipment becomes more important. With the proliferation of these intelligent inter-network devices, it is necessary to increase the data processing capacity on the network to which these devices are connected and to provide the improved data rate necessary to meet this requirement. . As a result, existing communication protocol standards are constantly being improved or new standards are being created. Nearly all of these standards require or benefit significantly from high-quality signal communication over a wired network, either directly or indirectly. The transmission of these high quality signals may have higher bandwidth and correspondingly higher frequency requirements and needs to be supported in a consistent manner. However, even though newer versions of various standards theoretically provide higher data rates or data rates, these high definition signals are still limited by the current design of certain physical components. . Unfortunately, the design of such physical components faces difficulties by not understanding what is necessary to achieve consistent signal quality at multi-gigahertz and higher frequencies.

  For example, a communication jack is used in a communication device and a device that connects or links cables used for transmitting and receiving electrical signals representing data to be communicated. A registered jack (RJ) is a standardized physical interface used to connect telecommunication and data devices. The RJ standardized physical interface has both a jack structure and a wiring pattern. The RJ standardized physical interface commonly used for data devices is the RJ45 physical network interface, also called the RJ45 jack. The RJ45 jack is widely used in local area networks, such as networks that implement the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet protocol. RJ45 jacks are described in various standards, including those promulgated by the American National Standards Institute (ANSI) / American Telecommunications Industry Association (TIA) at ANSI / TIA-1096-A.

  All electrical interface components such as cables and jacks, including RJ45 jacks, not only resist the initial current flow, but also resist any current change. This characteristic is called reactance. Two related types of reactance are inductive reactance and capacitive reactance. Inductive reactance may occur, for example, based on the movement of current through a cable that creates resistance, causing a magnetic field that induces a voltage in the cable. On the other hand, capacitive reactance is generated by charging that appears when electrons from two opposing surfaces approach each other.

  The various components of the communication circuit preferably have matching impedances so as to reduce or avoid any degradation of the transmitted signal. Otherwise, a load with one impedance value reflects or echoes part of the signal carried by cables with different impedance levels, causing a signal failure. For this reason, designers and manufacturers of data communication equipment, such as cable distributors, are responsible for verifying that cable impedance values and resistance and capacitance levels meet certain performance parameters. Design and test the cables. The RJ45 jack is an important component in almost all communication circuits, but the manufacturer of the jack has not paid as much attention to the performance of the jack. Thus, while the problems with existing RJ45 jacks are well documented in testing and the adverse effects of existing RJ45 jacks on high frequency signal lines are understood, the industry is concerned with this important component of the physical layer. It seems not ambitious to deal with. As a result, an improved high speed communication jack is needed.

One embodiment of the present disclosure is:
A housing having a port for receiving a plug and having a plurality of pins each connected to a corresponding signal line of the plug;
A shield case surrounding the housing;
A rigid circuit board in the housing,
A substrate,
A plurality of vias extending through the substrate, each via configured to receive a pin on the housing;
A plurality of traces on an intermediate layer of the substrate, each trace extending from a corresponding one of the plurality of vias;
A first shield layer on a first side of the intermediate layer of the substrate;
A second shield layer on a second side of the intermediate layer of the substrate;
A third shield layer adjacent to the second shield layer;
A rigid circuit board, and
Including a high-speed communication jack.

  In another embodiment, when excited, each trace of the plurality of traces is differentially matched to an adjacent second trace of the plurality of traces.

  In another embodiment, the impedance value of the first trace in the matched pair trace is adjusted to be approximately equal to the impedance value of the second trace in the matched pair trace.

  In another embodiment, a capacitor is formed in each via by a trace layer and a return signal layer embedded in a dielectric layer.

  In another embodiment, the distance between the return signal layer and the trace layer is adjusted so that the capacitor has a value of approximately 0.1 pf to approximately 0.5 pf.

  In another embodiment, the width, height, or length of each trace in the matched set of traces is adjusted so that the impedance of the first trace matches the impedance of the second trace.

  In another embodiment, a second return signal layer is formed in the dielectric layer below the first return signal layer to form a second capacitor.

  In another embodiment, the distance between the first signal layer and the second signal layer is adjusted to adjust the value of the second capacitor to 0.1 pf to 0.5 pf.

  In another embodiment, the impedance of the first trace and the second trace is such that a first signal is transmitted on the first trace and a second signal is transmitted on the second trace. The traces are adjusted to match.

  In another embodiment, the capacitor, the trace, and the return signal layer form a common mode filter for the matched set of traces.

  In another embodiment, the capacitor value is adjusted so that the common mode filter prevents reflection of signals from the matching traces.

  In another embodiment, there is a second shield tab on the opposite side of the substrate from the first shield.

  In another embodiment, the trace is plated with gold.

  In another embodiment, the substrate comprises a dielectric material having a dielectric constant greater than 3.0.

Another embodiment of the present disclosure is a high speed communication jack comprising a standard RJ45 housing having a port that receives a plug and has a plurality of pins connected to corresponding signal lines of the plug, the jack comprising:
A shield case surrounding the housing;
A rigid circuit board in the lower part of the housing,
A substrate,
A plurality of vias extending through the substrate, each via configured to receive a pin on the housing;
A plurality of traces on an intermediate layer of the substrate, each trace extending from a corresponding one of the plurality of vias;
A first shield layer on a first side of the intermediate layer of the substrate;
A second shield layer on a second side of the intermediate layer of the substrate;
A third shield layer adjacent to the second shield layer;
A rigid circuit board, and
Including a high-speed communication jack.

Another embodiment of the present disclosure is:
Forming a first ground layer;
Forming a second layer of dielectric material on one side of the first layer;
Forming a third layer on the opposite side of the second layer from the first layer and having a ground plane made from a conductive material;
Forming a fourth layer of the third layer opposite to the second layer and made of a dielectric material;
Forming a fifth layer on the opposite side of the fourth layer from the third layer and having a ground plane made of a conductive material;
Forming a sixth layer formed on the opposite side of the fifth layer from the fourth layer and made of a dielectric material;
Forming a seventh layer formed on the opposite side of the sixth layer from the fifth layer and having a ground plane made of a conductive material;
Forming vias through the first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth layer, and the seventh layer;
And the third layer includes a method of forming a high-speed communication jack having a plurality of traces extending from each via.

Another embodiment of the present disclosure is:
A housing having a port for receiving a plug and having a plurality of pins each connected to a corresponding signal line of the plug;
A shield case surrounding the housing;
A multilayer rigid circuit board in the housing,
A first ground layer;
A second layer of dielectric material on one side of the first layer;
A third layer on the opposite side of the second layer from the first layer and having a ground plane made from a conductive material;
A fourth layer on the opposite side of the third layer from the second layer and made of a dielectric material;
A fifth layer on the opposite side of the fourth layer from the third layer and having a ground plane made of a conductive material;
A sixth layer formed on the opposite side of the fifth layer from the fourth layer and made of a dielectric material;
A seventh layer having a ground plane formed on the opposite side of the sixth layer from the fifth layer and made of a conductive material;
The first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth, each via configured to receive a pin on the housing A plurality of vias penetrating the layer and the seventh layer;
A multilayer rigid circuit board having:
Including a high-speed communication jack.

  In another embodiment, a capacitor is formed in each via by a combination of one of the plurality of traces on the first layer, the second layer, and the third layer.

  In another embodiment, the depth of the second layer is adjusted so that the capacitor in each via has a value between approximately 0.1 pf and approximately 0.5 pf.

  In another embodiment, a plurality of through the first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth layer and the seventh layer. A ground via is formed.

FIG. 3 illustrates a high speed communication jack comprising an RJ45 jack configured in accordance with one embodiment of various aspects of the present disclosure. It is a figure of the lower surface perspective part of the left side part of the RJ45 jack of FIG. FIG. 4 is a bottom and right side view of a jack shield providing a shield for the RJ45 jack and flexible printed circuit board of FIG. 1. FIG. 2 is a schematic plan view of the front surface of the printed circuit board of FIG. 1. FIG. 3 is a schematic plan view of the front surface of another embodiment of the printed circuit board of FIG. 1. FIG. 5 is a schematic plan view of the rear surface of the printed circuit board of FIG. 4. FIG. 5 is a schematic plan view of the rear surface of another embodiment of the printed circuit board of FIG. 4. FIG. 5 is a cross-sectional view of the printed circuit board substrate of FIG. 4 taken along line BB. FIG. 5 is a cross-sectional view of a via in the printed circuit board of FIG. 4. FIG. 5 is a cross-sectional view of another example of a via in the printed circuit board of FIG. 4. FIG. 5 is a schematic diagram of an RJ45 jack having a transmit cable and receive cable pair that are aligned and balanced with each other. FIG. 3 is a schematic diagram of a pair of signal lines that are differentially balanced. FIG. 5 is a schematic diagram of a process used to differentially balance the two traces in FIG. 4 based on a first signal and a second signal. FIG. 4 is a rear perspective view of the RJ45 jack of FIG. 1 with the shield removed. FIG. 6 is a rear perspective view of another embodiment of the RJ45 jack of FIG. 1 with the shield removed. It is a figure which shows one Embodiment of the jack for high-speed communication provided with a rigid board | substrate. It is the schematic of the layer in the jack for rigid high-speed communication. It is a side view of the jack for high-speed communication. It is a top view of a rigid substrate. It is a figure which shows the uppermost layer of a rigid board | substrate. It is a figure which shows the 3rd layer of a rigid board | substrate. It is a figure which shows the 4th layer of a rigid board | substrate. It is a bottom view of a substrate. It is a top view of a substrate.

  FIG. 1 illustrates a high-speed communication jack configured in accordance with one embodiment of various aspects of the present disclosure. The high-speed communication jack includes an RJ45 jack 110, a flexible printed circuit board (PCB) 120, and a jack shield 130. As described herein, in accordance with various aspects of the present disclosure, the flexible PCB 120 provides a balanced radio frequency tuning circuit that can be soldered directly to each pin of the RJ45 jack 110. On the other hand, the jack shield 130 provides a shield for the RJ45 jack 110 and the flexible PCB 120 and a function as a case ground. When combined, the RJ45 jack 110, flexible PCB 120, and jack shield 130 may provide functions similar to a tuned waveguide and a tube that can be passed through when a communication signal is transmitted. In this case, the energy portion of the communication signal is transmitted through the jack shield 130 outside the tube, and the information portion of the communication signal is transmitted along the non-resistant gold wire in the tube. Thereby, a high data signal speed can be obtained. For example, it is assumed that a data rate of 40 gigabits (Gbs) or higher can be supported.

  The RJ45 communication jack is used in the following, but the communication jack is not limited to the RJ45 communication jack, and may be used in any type of high-speed communication jack. High-speed communication jacks include all classes of modular RJ type connectors, universal serial bus (USB) connectors and jacks, firewire (1394) connectors and jacks, HDMI (high definition multimedia interface) connectors and jacks, D-subminiatures Type connectors and jacks, ribbon type connectors or jacks, or any other connector or jack that receives high speed communication signals.

  In various aspects of the present disclosure, the various pins and traces disclosed herein may be any suitable conductive element and combination of any suitable conductive elements, such as gold, silver, or copper, or alloys. May be configured. For example, the set of pins and plug contacts of the RJ45 jack 110 may include gold plated copper pins or copper wires. On the other hand, a set of traces of flexible PCB 120 may include a copper path that is gold plated. Gold plating is used to attach a corrosion-resistant conductive layer to copper, which is usually a material that is easily oxidized. Alternatively, a suitable barrier metal layer such as nickel may be deposited on the copper substrate before gold plating. The nickel layer may improve the wear resistance of the gold plating by providing a mechanical backing for the gold layer. Also, the nickel layer may reduce the effects of pores that may be present in the gold layer. At higher frequencies, gold plating not only reduces signal loss, but may increase bandwidth due to the skin effect where current density is highest on the outer edge of the conductor. In contrast, the use of nickel alone results in signal degradation at higher frequencies due to the same effect. Therefore, higher speeds may not be achieved with RJ45 jacks that use nickel plating alone. For example, a pin or trace plated only with nickel may reduce its effective signal length by as much as three times when the signal enters the GHz range. Although some benefits of using gold plating on the surface of the copper path are described herein, other conductive elements may be used to plate the copper path. For example, instead of gold, platinum, which is also a non-resisting but good conductor, may be used to plate the copper path.

  Each of the major components of the high speed communication jack, namely the RJ45 jack 110, the flexible printed circuit board (PCB) 120, and the jack shield 130, determine which of these components will achieve high speed communication support. Before providing a discussion of how to work together, it is briefly described herein.

  FIG. 2 shows a bottom perspective view of the front portion of the RJ45 jack 110 of FIG. Here, it can be seen that a plug opening 230 for inserting a plug (not shown) is provided. The plug opening 230 may be configured to receive a plug and couple the contacts on the plug to a set of plug contacts 212 on the RJ45 jack 110. The plug may be an RJ45 8-pole 8-core (8P8C) modular plug. A set of plug contacts 212 is formed into a set of pins 210 configured to be attached to a communication circuit on a circuit board. For example, the RJ45 jack 110 may be attached to the circuit board of the network switch device by using a pair of posts 220. Thereafter, a set of pins 210 may be soldered to respective contact pads on the circuit board of the device. A jack similar to the RJ45 jack 110 as shown in FIG. 2 alone provides basic connectivity between the plug of the RJ45 cable and the circuit board of the device in which the jack is integrated. However, the jack is not designed to handle the communication frequency required for high speed communication. The RJ45 jack 110 configured in accordance with various aspects of the disclosed techniques described herein may be integrated with other components such as the jack shield 130 and the flexible PCB 120, thereby allowing the RJ45 jack 110 to be integrated. It is possible to communicate at a higher speed without interference from the transition signal.

  FIG. 3 shows a bottom and right side view of the jack shield that provides a shield for the RJ45 jack 110 and flexible PCB 120. The jack shield 130 has an upper portion 302, a lower portion 304, a rear portion 306, a front portion 308, a left side portion (not shown, but substantially the same as the right side portion), and a right side portion 310. To provide the desired shielding properties, in one embodiment of the present disclosure, the jack shield 130 may include a conductive material such as, but not limited to, steel, copper, or any other conductive material. On both the right side 310 and the left side (not shown) of the jack shield 130, a pair of tabs 320 near the lower portion 304 are used to ground the jack shield 130 and the circuit board in the device (not shown). It may be fixed to. For example, a pair of tabs 320 on the jack shield 130 may be inserted into a pair of matching mounting holes on the circuit board and soldered to the circuit board.

  FIG. 4A shows a schematic plan view of the front surface of the PCB 120 of the RJ45 jack. The PCB 120 includes a multilayer substrate 402 made of a dielectric material incorporating stripline flex or equivalent technology. The edge of the substrate 402 is surrounded by a protective layer 404. The protective layer 404 is made of a non-conductive material such as, but not limited to, plastic or a flexible solder mask. The front surface of the substrate 402 has a plurality of vias 406, 408, 410, 412, 414, 416, 418, and 420 created through the substrate 402. Each via 406, 408, 410, 412, 414, 416, 418, and 420 is sized to pass through the substrate 402 and accommodate the pin 210. The area surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 is coated with a conductive material such as gold. The coating surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 can be substantially square or substantially rectangular. In another embodiment shown in FIG. 4B, the coating surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 can be substantially circular. The circular coating reduces interference between adjacent vias 406, 408, 410, 412, 414, 416, 418, and 420.

  A plurality of traces 422, 424, 426, 428, 430, 432, 434, and 436 extend from each via 406, 408, 410, 412, 414, 416, 418, and 420 toward the edge of the PCB 120. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 is made of a conductive material including copper or gold. In one embodiment, a nickel layer is formed on the substrate 402 and a gold layer is formed on the nickel layer to form each trace 422, 424, 426, 428, 430, 432, 434, and 436. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 includes traces 422, 424, 426, 428, 430, 432, 434, or 436, and vias 406, 408, 410, 412, 414, It extends toward the rear edge of the PCB 120 until it reaches a shield trace layer 490 near the edge of the PCB 120 opposite 416, 418, and 420. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 has a first portion 454, 456, 458, 460, 462, 464, 466, and 468, where the first portion is Adjacent to second portions 470, 472, 474, 476, 478, 482, and 484. Each second portion 470, 472, 474, 476, 478, 480, 482, and 484 extends to the shield trace layer 490 without contacting the shield trace layer 490. Each first portion 454, 456, 458, 460, 462, 464, 466, and 468 includes a respective via 406 from the respective second portion 470, 472, 474, 476, 478, 480, 482, and 484. , 408, 410, 412, 414, 416, 418, or 420. Each second portion 470, 472, 474, 476, 478, 480, 482, and 484 has a length that varies depending on the traces 422, 424, 426, 428, 430, 432, 434, or 436.

  Two shield tabs 486 and 488 are positioned on opposite edges of PCB 120. Each shield tab 486 and 488 is made of a substrate coated with a conductive material, such as gold or copper. The shield tabs 486 and 488 are electrically connected by a shield trace layer 490 on the substrate 402. The shield trace layer 490 extends between the shield tabs 486 and 488 and includes a second portion 470, 472, 474, 476, 478, a second portion of each trace 422, 424, 426, 428, 430, 432, 434, and 436. 480, 482, and 484 are positioned between the edges of the PCB 120 opposite the vias 406, 408, 410, 412, 414, 416, 418, and 420.

  FIG. 5A shows a schematic plan view of the rear surface of the printed circuit board of FIG. 4A. The rear surface includes vias 406, 408, 410, 412, 414, 416, 418, and 420, shield tabs 486 and 488, and a shield trace layer 502 extending between the rear surface of each shield tab 486 and the rear surface of 488. Have. The shield trace layer 502 covers the portion of the rear surface of the PCB 120 between the shield tabs 486 and 488. Shield tabs 486 and 488 have return vias 504, 506, 508, 510, 512, 514, 516 and 518 that connect shield trace layer 490 and shield trace layer 502 through substrate 402. FIG. 5B shows a plan view of the back side of another embodiment of the printed circuit board of FIG. 4B.

  FIG. 6A shows a cross-sectional view of the multilayer substrate 402 of the PCB 120 along line BB in FIG. The first layer 602 of the multilayer substrate 402 has a solder mask portion made of a material such as a PSR9000 FST flexible solder mask. The second layer 604 is formed below the top layer and has each of the traces 422, 424, 426, 428, 430, 432, 434, and 436. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 has a length (L), height (H), and width (W), and is a distance (S) from the adjacent trace. It is separated. The length (L) of each trace is determined from the edge of each via 406, 408, 410, 412, 414, 416, 418, and 420 of the flexible circuit board 120 along the surface of the flexible circuit board 120. The length extends to the shield trace layer 490.

  Each trace 422, 424, 426, 428, 430, 432, 434, and 436 has a first so that each trace 422, 424, 426, 428, 430, 432, 434, and 436 is not covered by a flexible solder mask. Extending through layer 602 of A shield trace layer 490 is also formed over a portion of the second layer 604, and the shield trace layer 490 extends through the first layer 602. A third dielectric layer 606 is formed below the second layer 604. The third layer 606 is made of a material having a depth (D) of approximately 0.002 mils to approximately 0.005 mils and having a dielectric constant greater than 3.0. This material may be, but is not limited to, Rogerson Material RO XT8100 or any other material capable of isolating high frequency electrical signals.

  A fourth layer 608 is formed below the third layer 606. The fourth layer 608 includes a signal return portion and a shield trace portion 502. Both the signal return portion and the shield trace portion 502 are made of a conductive material, preferably gold or copper. A fifth layer 610 is formed on the fourth layer 608. The fifth layer 610 has a flexible solder mask portion and a shield trace layer 502 portion. The flexible solder mask portion is made of the same material as the flexible solder mask portion of the first layer 602. In an alternative example, the flexible solder mask portion is made from a different material than the flexible solder mask of the first layer 602. In an alternative example, a second signal return layer (not shown) may be positioned on the dielectric material.

  To eliminate crosstalk caused by adjacent traces, each trace 422, 424, 426, 428, 430, 432, 434, and 436 has an adjacent trace 422, 424, 426, 428, 430, 432, 434, And 436 are electrically coupled. As an illustrative example, trace 422 may be coupled to trace 424. In operation, a first signal is transmitted along the first trace, and the same signal having opposite polarity is transmitted along the matching trace, thereby coupling the traces differentially together. Since the traces are differentially coupled together, the impedance of each trace determines how the traces are driven. Accordingly, the impedance of the matched traces in each set should be approximately equal.

  The physical characteristics of each trace 422, 424, 426, 428, 430, 432, 434, and 436 in the matched set of traces are between matching traces due to the transmit and return signals transmitted through each trace. Adjusted to balance impedance. The impedance of each trace 422, 424, 426, 428, 430, 432, 434, and 436 is for each signal transmitted through each trace 422, 424, 426, 428, 430, 432, 434, and 436, It is adjusted by adjusting any one or combination of the length (L), width (W), height (H), and spacing between matching traces (S) of each trace. The height (H) of each trace 422, 424, 426, 428, 430, 432, 434, and 436 may be approximately 2 mils to approximately 6 mils, with adjacent traces 422, 424, 426, 428, 430, The spacing (S) between 432, 434, and 436 may be about 3 mils to about 10 mils.

  Returning to FIG. 4, each trace has a variable width in the first portion 454, 456, 458, 460, 462, 464, 466, and 468 and a second portion 470, 472, 474, 476, 478, 480 and 482 having a substantially constant width. Accordingly, the width of each trace 422, 424, 426, 428, 430, 432, 434, and 436 is the first portion 454, 456, 458, 460, 462, 464, 466, and 468 or the second. Of the first portion 454, 456, 458, 460, 462, 464, 466, and 468 and the second portion 470, 470, 472, 474, 476, 478, 480, and 482. In both 472, 474, 476, 478, 480, and 482, the height (H) of the traces 422, 424, 426, 428, 430, 432, 434, and 436 is adjusted. Thereby, each trace in the matching set has substantially the same impedance when the matching traces are separated by a distance (S).

  Due to manufacturing and material inconsistencies, the signals driven through each set of differentially matched traces 422, 424, 426, 428, 430, 432, 434, and 436 may not be identical. , So that part of the signal is reflected back and causes common mode interference. Each trace 422, 424, 426, 428, 430, 432, 434, or 436 in the matched set of traces is adjusted to eliminate any common mode interference in the matched set so as to eliminate any common mode interference. Has a common mode filter. Each filter includes a via 406, 408, 410, 412, 414, 416, 418, or 420 in each trace 422, 424, 426, 428, 430, 432, 434, or 436 and a fourth layer of the multilayer substrate 402. And 608. Each via 406, 408, 410, 412, 414, 416, 418, and 420 is a second layer 604 of the substrate 402 around the periphery of the via 406, 408, 410, 412, 414, 416, 418, and 420. And a conductive material layer such as gold or copper formed on the fourth layer 608. The conductive material on the first layer 602 can be traces 422, 424, 426, 428, 430, 432, 434, or 436 corresponding to the vias 406, 408, 410, 412, 414, 416, 418, and 420. Connected, the conductive material on the fourth layer 608 is connected to the signal return of the fourth layer 608. The size of each capacitor is determined by the distance between the conductive materials on the second layer 604 and the fourth layer 608. Accordingly, each via 406, 408, 410 is adjusted by adjusting the depth of the third layer 606 with respect to the conductive material on the vias 406, 408, 410, 412, 414, 416, 418, and 420. 412, 414, 416, 418 and 420 can be adjusted. Capacitors created by vias 406, 408, 410, 412, 414, 416, 418, and 420 and the return of fourth layer 608 are approximately 0.1 picofarads (pf) to approximately 0.5 pf in size. It is. The top and bottom surfaces of the substrate 402 may be coated with a plastic insulating layer to further improve circuit operation.

  The combination of the capacitors created in each via 406, 408, 410, 412, 414, 416, 418, and 420, and the characteristic inductance of the signal return layer, each trace 422, 424, 426, 428, 430, 432 A common mode filter for 434 or 436 is created. By adjusting the capacitance value of each capacitor based on the impedance of the traces 422, 424, 426, 428, 430, 432, 434, and 436, the common mode noise is significantly reduced, thereby reducing each trace 422, Signal processing on 424, 426, 428, 430, 432, 434, and 436 is improved.

  FIG. 6B shows a schematic cross-sectional view of the via 406, 408, 410, 412, 414, 416, 418, or 420. Each via 406, 408, 410, 412, 414, 416, 418, and 420 includes a first layer 602, a second layer 604, a third layer 606, a fourth layer 608, and a fifth layer 610. Formed through. The second layer 604 is made of a conductive material such as gold or copper and surrounds the outer periphery of each via 406, 408, 410, 412, 414, 416, 418, and 420. The second layer 604 also includes vias 406, 408, 410, 412, 414, 416, 418, and 420 for respective traces 422, 424, 426, 428, 430, 432, 434 of the second layer 604. Or 436. The third layer 606 functions as a dielectric layer as described in FIG. 6A. The fourth layer 608 is formed in the third layer 606 and functions as a signal return layer. The fifth layer 610 is similarly made of a conductive material such as copper or gold, and similarly surrounds the outer periphery of the via in the same manner as the second layer 602. A seal layer (not shown) may also be formed on the fifth layer 610.

  The fourth layer 608 is separated from the second layer 604 by a distance D1 and from the fifth layer 610 by a second distance D2. The combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 creates a capacitor having a capacitance value of approximately 0.1 pf to 0.5 pf. By adjusting the distance D1 of the fourth layer 608 with respect to the second layer 604, the capacitance value of the via capacitor is adjusted. Because the via connects its associated trace to the fourth return signal layer 608, the combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 provides a common mode filter. It is formed. This common mode filter removes any interference caused by signal reflections resulting from failure of the manufacturing process. By adjusting the capacitance value of the via capacitor, the common mode filter may be adjusted to eliminate substantially all signal noise caused by reflection of the transmitted signal or return signal.

  FIG. 6C shows another example of a cross-sectional view of vias 406, 408, 410, 412, 414, 416, 418 and 420. A second return signal layer 612 is added to the third layer 606 between the first return signal layer 608 and the fifth layer 610. The second return signal layer 612 extends in parallel to the first signal layer 608 and improves the filtering effect of the common mode filter. The first return signal layer 608, the third layer 606, and the second return signal layer 612 are adjusted by adjusting the distance D3 between the first return signal layer 608 and the second return signal layer 612. A second capacitor formed by is created in the via. By adjusting the distance D3, the value of the second via capacitor may be adjusted to improve the operation of the common mode filter. Furthermore, where the present inventors have located, forming a second capacitor in the via allows the traces to be aligned on the spaced ends of the PCB 102. As an illustrative example, trace 422 may be matched to trace 436. Accordingly, a plurality of pairs of signal lines positioned according to the RJ45 standard can be realized by forming a second capacitor.

  FIG. 7 shows a schematic diagram of an RJ45 jack with matching transmit and receive traces. By adjusting the height (H), width (W), and length (L) of each trace 422, 424, 426, 428, 430, 432, 434, or 436, impedance matching is achieved between the transmission line and the reception line. Can be made. The same high frequency signal with opposite polarity is transmitted along each pair to improve jack operation. Since matching traces are coupled through a shield, these pairs function as a common mode filter for each other. Also, even when one signal cannot be transmitted, the corresponding reverse signal line transmits the same signal. The matching traces act as a filter coupled to the shield so that noise caused by high bandwidth transmission is removed from the signal through the filter. Furthermore, since the transmission line is aligned with the reception line, signal filtering is performed with higher accuracy. This is because the reference point of the filter is not the ground connection but the signal itself.

  FIG. 8 shows a schematic diagram of a differentially balanced pair of signal lines. As the figure shows, the characteristics of each trace are adjusted to match the impedance of the first trace to the impedance of the second trace using the method described above. Further, the capacitor formed in each via forms a common mode filter in which the return signal line is embedded in the PCB 120. A well-balanced bi-directional communication circuit is achieved by differentially balancing the two traces during transmission of both the transmit and response signals.

  FIG. 9 shows a schematic diagram of a method for balancing matching traces for transmit and return signals. In step 902, the physical characteristics of each trace in the matched pair of traces are adjusted so that the trace impedances are approximately equal. This physical property may include the height, length, and width of each trace, as well as the distance separating each trace in the matched set of traces. In step 904, a first signal having a first polarity is transmitted along the first trace in the matched set of traces. The first signal may be a high frequency communication signal operating at a frequency higher than 10 gigahertz (“GHz”). In step 906, a second signal that is substantially the same as the first signal and has a polarity opposite to that of the first signal is applied to the second trace of the matched set of traces simultaneously with the first signal. Send to. In step 908, the first signal is measured at the beginning and end of the trace and the two measurements are compared to determine the amount of data lost along the length of the trace. In step 910, at least one physical characteristic of the first trace or the second trace is adjusted based on the measured amount of signal loss. The process may return to step 904 until the amount of signal loss is approximately less than 10 decibels (“db”).

  In step 912, a third signal is transmitted on the second trace of the matched set of traces. In step 914, a fourth signal that is substantially the same as the third signal but has the opposite polarity to the third signal is transmitted on the first trace. In step 916, a third signal is measured at the beginning and end of the trace and these two measurements are compared to determine the amount of data lost along the length of the trace. In step 918, at least one physical characteristic of the first trace or the second trace is adjusted based on the measured amount of signal loss. The process may return to step 912 until the amount of signal loss is approximately less than 10 decibels (“db”). In another example, the process may return to step 904 to ensure that the signal loss of the first signal is not affected by adjustments made in response to the third signal loss.

  FIG. 10 shows the PCB 120 positioned on the jack 110. The substrate 402 of the PCB 120 is made from a flexible material that allows the first portion of the PCB 120 to face the second portion of the PCB 120 at an angle of approximately 90 degrees. Accordingly, PCB 120 has vias 406, 408, 410, 412, 414, 416, 418, and 420 positioned on jack pin 210 and traces 422, 424, 426, 428, 430, 432, 434, and 436 is bent to extend from vias 406, 408, 410, 412, 414, 416, 418, and 420 to the jack contact pads. Shield tabs 486 and 488 are bent to be at an approximately 90 degree angle with respect to PCB 120. The shield tabs 486 and 488 are positioned along the sides of the jack so that the jack shield 130 of the jack engages the shield tabs 486 and 488.

  The flexible PCB 120 may be implemented using any flexible plastic substrate that allows the flexible PCB 120 to be bent. As described herein, the flexible PCB 120 may be flexed or bent to conform to the existing form factor of the RJ45 jack 110 and be shielded by the jack shield 130. For example, the flexible PCB 120 may be disposed between the RJ45 jack 110 and the jack shield 130 and attached to the RJ45 jack 110. The shield tabs 486 and 488 of the flexible PCB 120 may be attached to the jack shield 130 to provide a common connection to the flex circuit on the flexible PCB 120. In that case, the set of pins 210 of the RJ45 jack 110 may be electrically coupled to the circuit board of the device in which the RJ45 jack 110 is used.

  The flexible PCB 120 may be configured to be folded and conform to the shape of the RJ45 jack 110 to better fit into an existing enclosure such as the jack shield 130. For example, in one aspect of the disclosed approach, the flexible PCB 120 bends toward the middle section of the flexible PCB 120 at an angle of approximately 90 degrees and is folded into the jack shield 130. The shield tabs 486 and 488 of the flexible PCB 120 will be folded over and contact the jack shield 130 and may be soldered to secure the flexible PCB 120 to the jack shield 130. Those skilled in the art will recognize that the orientation of the flexible PCB 120 relative to the RJ45 jack 110 within the jack shield 130 may vary according to various aspects of the present disclosure. For example, the flexible PCB 120 may be thin enough to be bent and folded into the other side of the jack shield 130. The flexible PCB 120 may be shaped to generally follow the lower section 304 of the jack shield 130. At this time, it is not necessary to bend or bend into the jack shield 130.

  The foregoing detailed description is merely some examples and embodiments of the disclosure, and numerous modifications to the disclosed embodiments can be made without departing from the spirit and scope of the disclosure herein. Can be done according to. Accordingly, the foregoing description is not intended to limit the scope of the present disclosure, but is intended to provide a disclosure sufficient for one skilled in the art to practice the invention without undue burden. Yes.

  FIG. 11 shows one embodiment of a high-speed communication jack comprising a rigid board. High speed communication jack 1100 includes a jack housing 1102 configured to receive a communication plug (not shown). The substrate 1300 is positioned on the lower surface of the housing, so that when installed, the pins 1306 extend from the substrate 1300 to engage the circuit board to which the jack is attached.

  FIG. 12 is a schematic diagram of layers in a rigid high-speed communication jack. The substrate 1300 includes a top layer 1202 having a plurality of vias (not shown) each sized to receive a pin, a second layer 1204 having a plurality of impedance matching traces as described above, and vias in the first layer 1202. A third layer 1206 and a fourth layer 1208 having vias aligned concentrically. The first layer 1202 is separated from the second layer 1204 by a first intermediate layer 1210 made of a non-conductive material such as, but not limited to, a Rogers material. The second layer 1204 is separated from the third layer 1206 by the second intermediate layer 1212, and the third layer 1206 and the fourth layer 1208 are separated by the third intermediate layer 1214. The uppermost solder mask layer 1216 is formed on the opposite side of the first layer 1202 from the first intermediate layer 1210. In one embodiment, the first layer 1202, the second layer 1204, the third layer 1206, and the fourth layer 1208 are composed of 1/4 oz copper and 1/4 oz finished silver. The In one embodiment, the first intermediate layer 1210, the second intermediate layer 1212, and the third intermediate layer 1214 are made of Rogers R04003 material. In another embodiment, the first layer 1202 is adhered to the first intermediate layer 1210 by an adhesive, and the second layer 1204 and the third layer 1206 are adhered to the second intermediate layer 1212 by an adhesive. The third layer 1206 and the fourth layer 1208 are bonded to the third intermediate layer 1214 with an adhesive.

  FIG. 13A shows a side view of the high-speed communication jack. The jack includes a rigid board 1300, a grounding unit 1302, a socket 1304, and a pin 1306 in the socket 1304. The rigid substrate 1300 has a stacked structure shown in FIG. FIG. 13B shows a top view of the rigid substrate 1300. The rigid substrate 1300 has a plurality of pin vias 1402 each having a size for accommodating the pins 1306 so that the pins 13006 pass through the substrate 1302. The rigid substrate has a plurality of ground vias 1310 that penetrate the substrate 1300.

  FIG. 14A shows the top layer 1202 of the rigid substrate 1300. The top layer 1202 has pin vias 1402 positioned at one end of the rigid substrate 1300. The surface of the first layer 1202 is coated with a conductive material so as to form a ground plane. In one embodiment, the material is 1/4 oz copper and 1/4 oz silver. This coating covers substantially the entire surface of the first layer 1202 except for the area around the periphery of each pin via 1402. FIG. 14B shows the second layer 1404 of the rigid substrate 1300. The second layer 1204 is coated with a conductive material, which covers substantially all of the second layer 1204 except for the region around the pin vias 1402 and the region around the trace 1406 extending from each pin via 1402. Cover the surface. Each trace 1406 has a first portion 1408 and a second portion 1410. The length, width, and depth of the first and second portions 1408 and 1410 of two adjacent traces are adjusted so that the traces are impedance matched using any of the techniques described above. The In one embodiment, the material covering the second layer 1204 is 1/4 oz copper and 1/4 oz silver.

  FIG. 14C shows the third layer 1206 of the rigid substrate 1300. The third layer 1206 is substantially covered with a conductive material except for the region of the pin via 1402. In one embodiment, the material covering the second layer 1204 is 1/4 oz copper and 1/4 oz silver. FIG. 14D shows the fourth layer 1208 of the rigid substrate 1300. The fourth layer 1208 is covered with a conductive material except for the outer periphery of the pin via 1402. In one embodiment, the material covering the second layer 1204 is 1/4 oz copper and 1/4 oz silver.

  FIG. 15 is a bottom view of the substrate 1300. A pin 1306 is inserted into each of the pin vias 1402 such that the pin 1306 penetrates the substrate. Each of the ground vias 1310 is filled with a conductive material so that the bottom surface of the substrate 1300 is connected to the first layer 1202, the second layer 1204, the third layer 1206, and the fourth layer 1208 of the substrate 1300. Is done. Two ground planes 1502 are formed at both ends of the substrate 1300. A ground plane 1502 is formed across at least two ground vias 1306 to connect the ground plane 1502 to the first layer 1202, the second layer 1204, the third layer 1206, and the fourth layer 1208 of the substrate. . When jack housing 1102 is connected to a circuit board (not shown), ground plane 1510 engages a corresponding ground plane on the circuit board to ground the jack to the circuit board.

  FIG. 16 shows a top view of the substrate 1300. A socket 1304 is formed in the pin via 1402. Each socket is sized to engage a conductor (not shown) that engages a conductor in a corresponding plug inserted into jack housing 1100. A ground via 1301 corresponding to the ground via 1310 is on the back side of the substrate 1300.

  In this disclosure, terms that do not specify a quantity should be construed to include both the singular and the plural. Conversely, any reference to a plurality of elements shall include the singular where appropriate.

It should be understood that various changes and modifications to the presently preferred embodiments disclosed herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present disclosure and without diminishing its intended advantages. Accordingly, such changes and modifications are intended to be included within the scope of the appended claims.

Claims (20)

A housing having a port for receiving a plug and having a plurality of pins each connected to a corresponding signal line of the plug;
A shield case surrounding the housing;
A rigid circuit board in the housing,
A substrate,
A plurality of vias extending through the substrate, each via configured to receive a pin on the housing;
A plurality of traces on an intermediate layer of the substrate, each trace extending from a corresponding one of the plurality of vias;
A first shield layer on a first side of the intermediate layer of the substrate;
A second shield layer on a second side of the intermediate layer of the substrate;
A third shield layer adjacent to the second shield layer;
A rigid circuit board, and
A jack for high-speed communication.   The jack of claim 1, wherein when energized, each trace of the plurality of traces is differentially matched to an adjacent second trace of the plurality of traces.   3. The jack of claim 2, wherein the impedance value of the first trace in the matched pair trace is adjusted to be approximately equal to the impedance value of the second trace in the matched pair trace.   The jack of claim 1, wherein a capacitor is formed in each via by a trace layer and a return signal layer embedded in a dielectric layer.   The jack of claim 4, wherein a distance between the return signal layer and the trace layer is adjusted such that the capacitor has a value of approximately 0.1 pf to approximately 0.5 pf.   4. The jack of claim 3, wherein the width, height, or length of each trace in a matched set of traces is adjusted so that the impedance of the first trace matches the impedance of the second trace.   The jack of claim 4, wherein a second return signal layer is formed in the dielectric layer below the first return signal layer to form a second capacitor.   The distance between the first signal layer and the second signal layer is adjusted to adjust the value of the second capacitor to 0.1 pf to 0.5 pf. Jack.   The impedance of the first trace and the second trace is such that when a first signal is transmitted on the first trace and a second signal is transmitted on the second trace, the trace The jack of claim 3, wherein the jack is adjusted to match.   The jack of claim 4, wherein the capacitor, the trace, and the return signal layer form a common mode filter for the matched set of traces.   The jack of claim 10, wherein the capacitor value is adjusted such that the common mode filter prevents reflection of signals from the matching traces.   The jack of claim 11, comprising a second shield tab on the opposite side of the substrate from the first shield.   The jack of claim 1, wherein the trace is plated with gold.   The jack of claim 1, wherein the substrate comprises a dielectric material having a dielectric constant greater than 3.0. A high speed communication jack comprising a standard RJ45 housing having a port having a plurality of pins for receiving a plug and connected to a corresponding signal line of the plug, the jack comprising:
A shield case surrounding the housing;
A rigid circuit board in the lower part of the housing,
A substrate,
A plurality of vias extending through the substrate, each via configured to receive a pin on the housing;
A plurality of traces on an intermediate layer of the substrate, each trace extending from a corresponding one of the plurality of vias;
A first shield layer on a first side of the intermediate layer of the substrate;
A second shield layer on a second side of the intermediate layer of the substrate;
A third shield layer adjacent to the second shield layer;
A rigid circuit board, and
A jack for high-speed communication. Forming a first ground layer;
Forming a second layer of dielectric material on one side of the first layer;
Forming a third layer on the opposite side of the second layer from the first layer and having a ground plane made from a conductive material;
Forming a fourth layer of the third layer opposite to the second layer and made of a dielectric material;
Forming a fifth layer on the opposite side of the fourth layer from the third layer and having a ground plane made of a conductive material;
Forming a sixth layer formed on the opposite side of the fifth layer from the fourth layer and made of a dielectric material;
Forming a seventh layer formed on the opposite side of the sixth layer from the fifth layer and having a ground plane made of a conductive material;
Forming vias through the first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth layer, and the seventh layer;
Wherein the third layer has a plurality of traces extending from each via. A housing having a port for receiving a plug and having a plurality of pins each connected to a corresponding signal line of the plug;
A shield case surrounding the housing;
A multilayer rigid circuit board in the housing,
A first ground layer;
A second layer of dielectric material on one side of the first layer;
A third layer on the opposite side of the second layer from the first layer and having a ground plane made from a conductive material;
A fourth layer on the opposite side of the third layer from the second layer and made of a dielectric material;
A fifth layer on the opposite side of the fourth layer from the third layer and having a ground plane made of a conductive material;
A sixth layer formed on the opposite side of the fifth layer from the fourth layer and made of a dielectric material;
A seventh layer having a ground plane formed on the opposite side of the sixth layer from the fifth layer and made of a conductive material;
The first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth, each via configured to receive a pin on the housing A plurality of vias penetrating the layer and the seventh layer;
A multilayer rigid circuit board having:
And the third layer has a plurality of traces extending from each via.   The jack of claim 17 wherein a capacitor is formed in each via by a combination of one of the plurality of traces on the first layer, the second layer, and the third layer.   19. The jack of claim 18, wherein the depth of the second layer is adjusted so that the capacitor in each via has a value of approximately 0.1 pf to approximately 0.5 pf. A plurality of ground vias formed through the first layer, the second layer, the third layer, the fourth layer, the fifth layer, the sixth layer, and the seventh layer; The jack of claim 17.

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