KR20160131724A - Light emitting device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a light emitting device and a method for fabricating the same, capable of improving the tolerance of electrostatic discharge and reducing luminous efficiency at the same time. The light emitting device of an embodiment comprises: a support substrate; a luminous structure which includes a first semiconductor layer sequentially formed on the support substrate, a pit forming layer having a trigger layer inserted therein, an active layer, and a second semiconductor layer; a first pit group which includes at least one first pit having the bottom disposed between the first semiconductor layer and the trigger layer; and a second pit group which includes at least one second pit having the bottom disposed between the trigger layer and the active layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting device,

Embodiments of the present invention relate to a light emitting device and a method of manufacturing the same.

A light emitting diode (LED) is one of light emitting devices that emits light when current is applied. The light emitting diode is capable of emitting light with high efficiency at a low voltage, thus providing excellent energy saving effect. In recent years, the problem of luminance of a light emitting diode has been greatly improved, and it has been applied to various devices such as a backlight unit of a liquid crystal display device, a display board, a display device, and a home appliance.

The light emitting device includes a light emitting structure including an N-type semiconductor layer, an active layer, and a P-type semiconductor layer provided on a support substrate, and includes an N-type electrode and a P-type electrode connected to the light emitting structure.

However, due to a large lattice mismatch between the light emitting structure and the supporting substrate, lattice defects such as dislocation can be formed in the first semiconductor layer. The potential can extend to the active layer, and when the potential extends to the active layer, a leakage current of the light emitting element is generated. In addition, when static electricity is applied from the outside, the active layer may be broken by the electric potential, so that the reliability of the light emitting device may be deteriorated.

Embodiments of the present invention provide a light emitting device capable of improving electrostatic discharge resistance and compensating for a decrease in luminous efficiency, and a method of manufacturing the same.

The light emitting device of the embodiment includes a support substrate; A light emitting structure including a first semiconductor layer sequentially formed on the support substrate, a pit forming layer having a trigger layer inserted therein, an active layer, and a second semiconductor layer; A first pit including a bottom at least one first pit disposed between the first semiconductor layer and the trigger layer; And at least one second pit whose bottom is disposed between the trigger layer and the active layer.

The light emitting device of the embodiment includes a support substrate; And a light emitting structure including a first semiconductor layer formed in sequence on the support substrate, a pit forming layer having a trigger layer inserted therein, an active layer, and a second semiconductor layer, wherein the indium content of the pit forming layer .

A method of manufacturing a light emitting device according to an embodiment includes forming a first semiconductor layer on a supporting substrate; Forming a fin formation layer on the first semiconductor layer at a second temperature lower than a first temperature for forming the first semiconductor layer; Forming an active layer on the pitch-forming layer; And forming a second semiconductor layer on the active layer, wherein forming the pitch formation layer includes forming at least one trigger layer at a third temperature lower than the second temperature.

The light emitting device of the embodiment of the present invention and its manufacturing method have the following effects.

First, a pit forming layer may be provided on the first semiconductor layer to prevent the dislocation from extending to the active layer.

Second, by inserting a trigger layer in the pit formation layer, the pit formation layer can be divided into the first region and the second region based on the trigger layer. The first pit having a bottom in the first region between the trigger layer and the first semiconductor layer secures electrostatic discharge (ESD) immunity and can prevent deformation of the light emitting structure. The second pit having the bottom in the second region between the trigger layer and the active layer can compensate for the decrease in the internal quantum efficiency (IQE) due to the first pit.

Third, a first pit forming layer in which a pit forming layer is sequentially stacked and a second pit forming layer in which a trigger layer is inserted are formed, and a first pit having a bottom in the first pit forming layer and a second pit having a bottom on the trigger layer It can have a sufficient width difference.

Fourth, by forming a plurality of trigger layers in the pitch formation layer, the width of the pit and the upper surface area of the pit can be easily controlled.

1A is a cross-sectional view of a light emitting device according to an embodiment of the present invention.
1B is an enlarged view of region A of FIG. 1A.
2 is a graph showing characteristics of a light emitting device according to the size of a pit.
FIG. 3 is a cross-sectional view of the first and second fits of FIG. 1a.
4A is a cross-sectional view showing another embodiment of the present invention.
FIG. 4B is an enlarged view of the area B in FIG. 4A. FIG.
FIG. 5 is a cross-sectional view of the first and second fits of FIG. 4A. FIG.
6 is a cross-sectional view showing another structure of the second pinning layer of FIG. 4A.
7 is a cross-sectional view showing still another embodiment of the present invention.
8A to 8F are process sectional views showing a method of manufacturing a light emitting device according to an embodiment of the present invention.
9A is a plan view of the active layer of the embodiment of the present invention.
9B is a photograph of the active layer of the embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the embodiments of the present invention are not intended to be limited to the specific embodiments but include all modifications, equivalents, and alternatives falling within the spirit and scope of the embodiments.

Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, the second component may be referred to as a first component, and similarly, the first component may also be referred to as a second component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the description of the embodiments, in the case where one element is described as being formed "on or under" another element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, wherein like or corresponding elements are denoted by the same reference numerals, and redundant description thereof will be omitted.

Hereinafter, the light emitting device of the embodiment will be described in detail with reference to the accompanying drawings.

1A is a cross-sectional view of a light emitting device according to an embodiment of the present invention, and FIG. 1B is an enlarged view of a region A of FIG. 1A.

1A and 1B, the light emitting device of the embodiment of the present invention includes a support substrate 10, and a light emitting structure disposed on the support substrate. The light emitting structure includes a first semiconductor layer 15 formed in order on a support substrate 10, a pit forming layer 20 having a trigger layer 25 inserted therein, an active layer 30, and a second semiconductor layer 35 ).

The supporting substrate 10 includes a conductive substrate or an insulating substrate. The support substrate 10 may be a material or carrier wafer suitable for semiconductor material growth. The supporting substrate 10 may be formed of a material selected from the group consisting of sapphire (Al 2 O 3), SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

A buffer layer 11 may be further provided between the light emitting structure and the supporting substrate 10. The buffer layer 11 is intended to alleviate the lattice mismatch between the light emitting structure provided on the supporting substrate 10 and the supporting substrate 10. [

The buffer layer 11 may be a combination of Group III and Group V elements or may be formed of one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. The buffer layer 11 may be doped with a dopant, but is not limited thereto.

The buffer layer 11 can be grown as a single crystal on the support substrate 10 and the buffer layer 11 grown with a single crystal can improve the crystallinity of the first semiconductor layer 15 grown on the buffer layer 11.

The light emitting structure provided on the supporting substrate 10 includes a first semiconductor layer 15, a pit forming layer 20 including a trigger layer 25, an active layer and a second semiconductor layer 35. In general, the light emitting structure may be divided into a plurality of parts by cutting the supporting substrate 10.

The first semiconductor layer 15 may be formed of a compound semiconductor such as a III-V group or a II-VI group, and the first semiconductor layer 15 may be doped with a first dopant. The first semiconductor layer 15 is a semiconductor material having a composition formula of Inx1Aly1Ga1-x1-y1N (0? X1? 1, 0? Y1? 1, 0? X1 + y1? 1), for example, GaN, AlGaN, InGaN, InAlGaN and the like. The first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first semiconductor layer 15 doped with the first dopant may be an n-type semiconductor layer.

Generally, a large lattice mismatch between the supporting substrate 10 and the first semiconductor layer 15 may cause lattice defects such as dislocations 10a in the first semiconductor layer 15. [ The dislocation 10a extends to the active layer 30 so that the leakage current increases due to the dislocation 10a and the light emitting element can be vulnerable to external static electricity.

The light emitting device of the embodiment of the present invention may include a pin formation layer 20 formed on the first semiconductor layer 15. The pitch formation layer 20 can form a pit that contacts the dislocation 10a. The pitch formation layer 20 may be formed of Inx2Ga1-x2N (0? X2? 1). Here, x2 > x1 (indium content of the first semiconductor layer). That is, the indium (In) content of the pinhole layer 20 may be greater than the indium content of the first semiconductor layer 15.

Generally, indium (In) has a large lattice size. Therefore, a pit due to lattice mismatching can be easily formed as a gallium nitride (GaN) layer containing a large amount of indium. The pits mitigate the stress of the first semiconductor layer 15 and the active layer 30 and prevent the potential 10a from extending to the active layer 30 and the second semiconductor layer 35, Thereby improving the quality of the device. Furthermore, the pad can prevent leakage current caused by dislocation 10a, thereby improving the electrostatic discharge yield.

In the light emitting device of the embodiment of the present invention, the indium content of the pinning layer 20 is larger than that of the first semiconductor layer 15. Therefore, the first semiconductor layer 15 has a structure in which a part of the pitch formation layer 20 is removed at a potential extended to the top surface of the first semiconductor layer 15 due to the indium content difference between the pinning layer 20 and the first semiconductor layer 15 The occurrence probability of the pit 70 increases. That is, the first pit 70 starts stably at the portion where the potential 10a is formed, so that the bottom of the first pit 70 can be in contact with the potential 10a.

The first pit 70 may have a concave shape and the cross section of the first pit 70 may be circular or polygonal and the shape of the first pit 70 viewed from the plane may be semicircular, A polygon, or the like. In the drawing, the first pit 70 has a V-shape in which the width L becomes wider as the cross-section of the first pit 70 increases.

The light emitting device of the embodiment of the present invention can block the current that the first pit 70 is concentrated through the potential 10a when an external static electricity is applied. Therefore, the first pit 70 can reduce the leakage current due to the potential 10a. Also, the stress of the light emitting structure and the support substrate 10 is relaxed by the first pit 70, so that deformation of the light emitting device can be prevented.

Since the first pit 70 extends to the active layer 30, the larger the width of the first pit 70, the smaller the area of the active layer 30 formed on the pitch formation layer 20 can be. As a result, the internal quantum efficiency (IQE) of the light emitting device is reduced, so that the output power such as the light emitting efficiency can be reduced.

Therefore, the trigger layer 25 can be disposed inside the pitch formation layer 20. [ The trigger layer 25 is for forming a second pit 75 having a narrower width and an upper surface area than the first pit 70.

The trigger layer 25 may be formed of Inx3Ga1-x3N (0? X3? 1). At this time, x2 (x2 is the indium content in the pin formation layer) < x3. That is, the indium (In) content of the trigger layer 25 may be greater than the indium content of the pinhole layer 20.

The probability of occurrence of the second pit 75 of the structure in which the trigger layer 25 is partially removed from the potential extended to the pitch formation layer 20 by the indium content difference between the pitch formation layer 20 and the trigger layer 25 . The second pit 75 can not be removed by the first pit 70 but is formed in a region corresponding to the potential 10a extended to the pitch formation layer 20 so that the bottom of the second pit 75 is connected to the potential 10a ).

Further, a pit can be easily formed in gallium nitride (GaN) containing aluminum. Therefore, the trigger layer 25 is composed of Inx2AlyGa1-x2-yN (0? X2? 1, 0? Y? 1, 0? X2 + y? 1) containing aluminum and having the same indium content as the pitch formation layer 20 Or AlGaN.

 The pitch formation layer 20 between the trigger layer 25 and the first semiconductor layer 15 may be defined as the first region 20a and the trigger layer 25 and the trigger layer 25 may be defined on the basis of the trigger layer 25 as described above. The pitch formation layer 20 between the active layers 30 may be defined as a second region 20b.

The bottom of the first pit 70 is formed in the first region 20a of the pin formation layer 20 so that the bottom of the first pit 70 can be in contact with the potential 10a in the first region 20a. The bottom of the second pit 75 is formed in the second region 20b of the pin formation layer 20 so that the bottom of the second pit 75 can be in contact with the potential 10a in the second region 20b . The potential 10a generated between the support substrate 10 and the active layer 30 is brought into contact with the bottoms of the first pit 70 and the second pit 75 formed in the pitch formation layer 20, Is prevented from extending to the active layer 30.

The width of the pit is wider as the bottom of the pit is closer to the first semiconductor layer 15 than the active layer 30. That is, the width L1 of the first pit 70 having the bottom in the first region 20a is wider than the width L2 of the second pit 75 having the bottom in the second region 20b.

2 is a graph showing characteristics of a light emitting device according to the size of a pit.

As shown in FIG. 2, as the width of the pit becomes wider, the electrostatic discharge yield of the light emitting device is improved, but the area of the active layer is narrowed and the output power of the light emitting device is lowered. That is, the static electricity prevention yield and the output power of the light emitting device according to the width of the pit are in a trade off relationship.

Therefore, the light emitting device of the embodiment of the present invention forms first pits 70 and second pits 75 having different widths. The first pit 70 provided in the first region 20a of the pin formation layer 20 and the second pit 75 provided in the second region 20b of the pin formation layer 20 It is possible to compensate for the decrease in the luminous efficiency and to improve the electrostatic discharge resistance.

Specifically, the first pit 70 having a width larger than the width of the second pit 75 secures electrostatic discharge (ESD) immunity, prevents deformation of the light emitting structure, Can compensate for the decrease in Internal Quantum Efficiency (IQE) by the first pit 70. At this time, the first pit 70 has a width larger than 200 nm to secure the electrostatic discharge yield, and the width L1 of the first pit 70 can be 300 nm to 350 nm. The second pits 75 may have a width narrower than 200 nm to improve IQE and the width L2 of the second pits 75 may be 150 nm to 200 nm.

The depth and width of the first pit 70 can be adjusted according to the thickness of the pitch formation layer 20. Specifically, as the thickness of the fatigue-free layer 20 between the first semiconductor layer 15 and the trigger layer 25 is thicker, the depth of the first pit 70 becomes deeper and wider, The thinner the thickness, the shallower the depth of the first pit 70 and the narrower the width. Therefore, the thickness of the pitch generation layer 20 between the first semiconductor layer 15 and the trigger layer 25 can be 20 nm to 300 nm.

As the thickness of the trigger layer 25 is reduced, the deviation of the width of the at least one second pit 75 can be reduced to form the second pit 75 having a constant width. Therefore, the thickness of the trigger layer 25 may be 1 nm to 5 nm.

3 is a cross-sectional view showing the first and second fits of the embodiment of the present invention.

3, the bottoms of the first pit 70 and the second pit 75 may be variously positioned within the pit formation layer 20. [ That is, the bottom of the first pits 70, which is provided between the first semiconductor layer 15 and the trigger layer 25, is formed in the first region 20a of the pinhole forming layer 20, It is possible to contact the potential 10a.

The bottom of the second pits 75 in which the bottom is provided between the second region 20b of the pinhole forming layer 20, that is, between the trigger layer 25 and the active layer 30, And can be in contact with the potential 10a. In particular, the second region 20b has a lower indium content than the trigger layer 25, and the bottom of most of the second pits 75 can contact the trigger layer 25.

Referring to FIG. 1A again, the first pit 70 and the second pit 75 are extended to the active layer 30 provided on the pitch formation layer 20. That is, the first pit 70 and the second pit 75 have a structure in which the pit formation layer 20, the trigger layer 25, and the active layer 30 are partially removed.

The active layer 30 is a layer where electrons (or holes) injected through the first semiconductor layer 15 and holes (or electrons) injected through the second semiconductor layer 35 meet. As the electrons and holes recombine, the active layer 30 transits to a low energy level, and light having a wavelength corresponding thereto can be generated.

The active layer 30 may have any one of a single well structure, a multiple well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, Is not limited thereto. In the drawing, a single-layer active layer 30 is shown. The active layer 30 may be formed of Inx4Ga1-x4N. At this time, even if x4 > x2 (indium content in the pitch formation layer), the first pit 70 and the second pit 75 are all in contact with the dislocation 10a, so that a new pit is not formed in the active layer 30.

The second semiconductor layer 35 is formed on the active layer 30 and may be formed of a compound semiconductor such as a group III-V or II-VI group. The second semiconductor layer 35 may be doped with a second dopant . The second semiconductor layer 35 may be formed of a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0? X5? 1, 0? Y2? 1, 0? X5 + y2? 1) or AlInN, AlGaAs, GaP, GaAs, GaAsP , AlGaInP, &lt; / RTI &gt; When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second semiconductor layer 35 doped with the second dopant may be a p-type semiconductor layer.

Generally, the second semiconductor layer 35 is formed at a temperature higher than that of the first semiconductor layer 15, the pinning layer 20, the trigger layer 25, and the active layer 30. The second semiconductor layer 35 may be formed to cover the first pit 70 and the second pit 75 without extending the pit to the second semiconductor layer 35. [

The light emitting structure of the present invention includes a first semiconductor layer 15 which is an n-type semiconductor layer and a second semiconductor layer 35 which is a p-type semiconductor layer, or a first semiconductor layer 15 which is a p- And a second semiconductor layer 35 which is an n-type semiconductor layer. In addition, the light emitting structure may have a structure in which an n-type or p-type semiconductor layer is further formed between the first semiconductor layer 15 and the active layer 30. That is, the light emitting structure of the embodiment of the present invention may be formed of at least one of the np, pn, npn, and pnp junction structures, and the light emitting structure of the embodiment of the present invention includes the n- It can be of various structures.

The first semiconductor layer 15 may be electrically connected to the first electrode 40 and the second semiconductor layer 35 may be electrically connected to the second electrode 45. The first electrode 40 and the second electrode 45 may be formed of a transparent conductive oxide (TCO). The transparent conductive oxide film may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide), IZON (IZO Nitride), ZnO, IrOx, RuOx and NiO.

The first electrode 40 and the second electrode 45 may be formed of an opaque metal such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, And may be formed of one or a plurality of layers in which a conductive oxide film and an opaque metal are mixed, but the present invention is not limited thereto. When the second electrode 45 is made of a metal having a high reflectance, light generated in the active layer 30 is reflected by the second electrode 45, passes through the first semiconductor layer 15, Lt; / RTI &gt;

Although not shown, an ohmic layer may be provided between the second semiconductor layer 35 and the second electrode 45. The ohmic layer (not shown) may be formed of at least one material selected from Pt, Ag, and Ti, but is not limited thereto. In addition, when light generated in the active layer 30 is emitted to the outside through the support substrate 10, a reflective layer (not shown) may be further formed between the second semiconductor layer 35 and the second electrode 45 . The reflective layer (not shown) may be formed of a material having a high reflectance such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, , IGZO, IGTO, AZO, ATO, and the like may be mixed and formed, but the present invention is not limited thereto.

The light emitting device of the present invention can prevent the dislocations from extending to the active layer 30 by providing the pitch formation layer 20 on the first semiconductor layer 15. The first pit 70 having a bottom in the first region 20a between the trigger layer 25 inserted into the pin formation layer 20 and the first semiconductor layer 15 is formed by electrostatic discharge ) Resistance, and it is possible to prevent deformation of the light emitting structure. The second pit 75 having a bottom in the second region 20b between the trigger layer 25 and the active layer 30 has an internal quantum efficiency IQE by the first pit 70, Can be compensated for.

4A is a cross-sectional view showing another embodiment of the present invention, and FIG. 4B is an enlarged view of a region B in FIG. 4A. 5 is a sectional view showing the first and second fits of FIG. 4A.

4A and 4B, a light emitting device according to another embodiment of the present invention includes a pin formation layer 120 including a first fin formation layer 120a and a second fin formation layer 120b, and a trigger layer 125 And is inserted into the second pinhole forming layer 120b. At this time, the bottom of the first pit 170 is provided only in the first pitch formation layer 120a.

The first pinning layer 120a is the same as the pinning layer 20 of FIG. That is, the first pinning layer 120a may be formed of Inx2Ga1-x2N (0? X2? 1). Here, x2 > x1 (indium content of the first semiconductor layer). The trigger layer 125 inserted into the second pinning layer 120b is also the same as the trigger layer 25 of FIG. The second pinning layer 120b is formed at a temperature higher than that of the first pinning layer 120a and may be a bulk structure.

5, the bottom of the first pit 170 is provided between the trigger layer 125 and the first semiconductor layer 115, specifically, the first finetization layer 120a. The bottom of the second pit 175 is formed on the trigger layer 125 so that the bottom of most of the second pits 175 can be formed in contact with the trigger layer 125.

Therefore, in the light emitting device according to another embodiment of the present invention, the thickness of the first pinning layer 120a is thin and the thickness of the second pinning layer 120b between the trigger layer 125 and the first pinning layer 120a is The difference between the width L3 of the first pawl 170 and the width L4 of the second pawl 175 can be made clearer.

In particular, the second pinning layer 120b may have a structure in which a plurality of layers are stacked.

6 is a cross-sectional view showing another structure of the second pinning layer of FIG. 4A.

As shown in FIG. 6, the second pinning layer 120b may have a superlattice structure and the second pinning layer 120b may be formed of InAlGaN. At this time, each layer can be replaced with a trigger layer in which the content of indium is different and the content of indium is the highest.

 Meanwhile, the light emitting device of the embodiment of the present invention may include a plurality of trigger layers.

7 is a cross-sectional view showing still another embodiment of the present invention.

As shown in FIG. 7, the pinhole layer 220 of the present invention may include a plurality of trigger layers 225. A plurality of trigger layers 225 are spaced apart from each other within the pitch formation layer 220 and the number of pad groups can be determined according to the number of the trigger layers 225.

The number of pad groups N and the number M of trigger layers 225 satisfy the following equation (1).

[Equation 1]

N = M + 1

As shown in the figure, when three trigger layers 225 are inserted into the fat-forming layer 220, the fat-generating layer 220 is divided into four regions by the trigger layer 225. That is, the fat-forming layer 220 includes a first region 220a between the first trigger layer 225a and the first semiconductor layer 215, a first region 220b between the first trigger layer 225a and the second trigger layer 225b, A third region 220c between the second trigger layer 225b and the third trigger layer 225c and a fourth region 220d between the third trigger layer 225c and the active layer 230. [ .

However, the trigger layer 225 has an indium content higher than that of the fin formation layer 220 and the first semiconductor layer 215, as described above. Thus, when three trigger layers 225 are inserted into the pitch formation layer 220 as shown, the light emitting device includes four groups of pits.

Specifically, the light emitting device is a first pit including a first pit 270, the bottom of which is provided in the first region 220a and is in contact with the potential 210a in the first region 220a, A second pit group including at least one second pit 275 provided in the second region 220b and in contact with the potential 210a in the second region 220b and a bottom provided in the third region 220c A third pit group including at least one third pit 280 in contact with the potential 210a in the third region 220c and a third pit region including the bottom in the fourth region 220d, And at least one fourth pit (285) in contact with the second pit (210a).

That is, the light emitting device of the embodiment of the present invention as described above can easily adjust the width of the pit and the top area of the pit by forming a plurality of trigger layers 225 in the pit forming layer 220.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

8A to 8F are process sectional views showing a method of manufacturing a light emitting device according to an embodiment of the present invention.

8A, the first semiconductor layer 15 is formed on the supporting substrate 10. The first semiconductor layer 15 is formed on the supporting substrate 10 as shown in FIG. Although not shown, the buffer layer 11 may be further formed on the supporting substrate 10 before the first semiconductor layer 15 is formed.

The buffer layer 11 can relax the lattice mismatch between the first semiconductor layer 15 and the supporting substrate 10. [ The buffer layer 11 may be a combination of Group III and Group V elements or may be formed of any one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN, but the dopant may be doped. The buffer layer 11 can be grown as a single crystal on the support substrate 10 and the buffer layer 11 grown with a single crystal can improve the crystallinity of the first semiconductor layer 15 grown on the buffer layer 11.

The first semiconductor layer 15 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, Molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, or the like.

The first semiconductor layer 15 is formed of a semiconductor material having a composition formula of Inx1Aly1Ga1-x1-y1N (0? X1? 1, 0? Y1? 1, 0? X1 + y1? 1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, and the like.

A large lattice mismatch between the supporting substrate 10 and the first semiconductor layer 15 may cause lattice defects such as dislocations 10a in the first semiconductor layer 15. [ The dislocations 10a can extend to the active layer 30 to be described later and the leakage current increases due to the potential 10a extended to the active layer 30 and the light emitting element becomes vulnerable to external static electricity.

In order to prevent this, as shown in FIG. 8B, a fat-forming layer 20 is formed on the first semiconductor layer 15. The pitch formation layer 20 can be formed of Inx2Ga1-x2N (0? X2? 1). Here, x2 > x1 (indium content of the first semiconductor layer). That is, since the indium content of the pinhole layer 20 is larger than the indium content of the first semiconductor layer 15, the pits can easily be formed in the pinhole layer 20. The bottom of the pit can be in contact with the potential 10a.

The formation temperature T2 of the pinhole layer 20 may be lower than the formation temperature T1 of the first semiconductor layer 15. [ The formation temperature T2 of the pinhole layer 20 may be lower than the formation temperature T1 of the first semiconductor layer 15 by 50 ° C to 200 ° C. Generally, as the gallium nitride (GaN) layer is formed at low temperatures, the pits are easily formed.

The step of forming the fat-forming layer 20 includes forming at least one trigger layer 25. Therefore, the trigger layer 25 is inserted into the pitch formation layer 20. The first pit 70 can be easily formed in the pitch formation layer 20 until the trigger layer 25 is formed and the bottom of the first pit 70 can be in contact with the potential 10a.

The trigger layer 25 can be formed of Inx3Ga1-x3N (0? X3? 1), and x2 (indium content in the pinning layer) < x3. That is, the indium (In) content of the trigger layer 25 is larger than the indium content of the pinhole layer 20. The formation temperature T3 of the trigger layer 25 may be lower than the formation temperature T2 of the pitch formation layer 20. [ Therefore, the pits are easily formed when the trigger layer 25 is formed.

The trigger layer 25 is formed of Inx2AlyGa1-x2-yN (0? X2? 1, 0? Y? 1, 0? X2 + y? 1) containing aluminum (Al) Or may be formed of AlGaN. In this case, the temperature T3 at which the trigger layer 25 is formed may be equal to or lower than the formation temperature T2 of the pitch formation layer 20.

After the trigger layer 25 is formed, the indium content is decreased and the formation temperature is raised to further form the fat-forming layer 20 on the trigger layer 25. [ That is, the pit formation layer 20 between the trigger layer 25 and the first semiconductor layer 15 is defined as the first region 20a, and the trigger layer 25 and the active layer 30 ) Can be defined as the second region 20b. The bottom of the second pit 75 abuts the dislocation 10a in the second region 20b and most of the second pit 75 can easily contact the dislocation 10a within the trigger layer 25. [

That is, the potential 10a formed in the first semiconductor layer 15 contacts the bottoms of the first pit 70 and the second pit 75 in the pitch formation layer 20 and the trigger layer 25. Therefore, the embodiment of the present invention can prevent the dislocation 10a from extending to the active layer 30.

4b, when the pinning layer 120 includes the first pinning layer 120a and the second pinning layer 120b, Inx2Ga1-x2N (0? X2? 1, the first fin formation layer 120a is formed so as to satisfy the condition of x2 > x1 (indium content of the first semiconductor layer)) and the first pinning layer 120a is formed on the first pinning layer 120a, And the second pitch formation layer 120b is formed at a high temperature. Therefore, no pits are formed in the second pinning layer 120b. The second pinning layer 120b is formed and at least one trigger layer 125 is formed. At this time, the trigger layer 125 can be formed of Inx3Ga1-x3N (0? X3? 1, x2 (indium content in the pitch formation layer) < x3 as described above.

Next, as shown in FIG. 8C, the active layer 30 is formed on the pinning layer 20. The active layer 30 is a layer in which electrons (or holes) injected through the first semiconductor layer 15 and holes (or electrons) injected through the second semiconductor layer 35 to be described later meet. As the electrons and holes recombine, the active layer 30 transits to a low energy level, and light having a wavelength corresponding thereto can be generated.

The active layer 30 may have any one of a single well structure, a multiple well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, Is not limited thereto. In the drawing, a single-layer active layer 30 is shown. The active layer 30 may be formed of Inx4Ga1-x4N. At this time, even when x4 > x2 (indium content in the pin formation layer), since the bottoms of the first pit 70 and the second pit 75 are all in contact with the potential 10a, a new pit is formed in the active layer 30 Is prevented.

Particularly, since the first pit 70 and the second pit 75 extend to the active layer 30, the area of the active layer 30 is reduced by the first pit 70 and the second pit 75. Therefore, it is preferable that the first pit 70 and the second pit 75 are formed to have a proper width.

2, since the anti-static yield and the output power of the light emitting device depend on the width of the pit, the first pit 70 has a width wider than 200 nm in order to secure the electrostatic discharge yield And the width L1 of the first pit 70 may be 300 nm to 350 nm. The second pits 75 may have a width narrower than 200 nm to improve IQE and the width L2 of the second pits 75 may be 150 nm to 200 nm. The widths of the first and second pits 70 and 75 can be easily adjusted by changing the thicknesses of the first region 20a, the second region 20b, and the active layer 30 of the fat- .

Next, as shown in FIG. 8D, a second semiconductor layer 35 is formed on the active layer 30. The second semiconductor layer 35 may be formed of a compound semiconductor such as a group III-V or II-VI group, and the second semiconductor layer 35 may be doped with a second dopant. The second semiconductor layer 35 may be formed of a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0? X5? 1, 0? Y2? 1, 0? X5 + y2? 1) or AlInN, AlGaAs, GaP, GaAs, GaAsP , AlGaInP, and the like. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second semiconductor layer 35 doped with the second dopant may be a p-type semiconductor layer.

The second semiconductor layer 35 is formed at a temperature higher than that of the first semiconductor layer 15, the pinning layer 20, the trigger layer 25 and the active layer 30 so that the pits extend to the second semiconductor layer 35 Can be prevented. The second semiconductor layer 35 is formed to a thickness sufficient to cover the first pit 70 and the second pit 75.

An isolation etching is performed on the light emitting structure including the first semiconductor layer (1% 5, the pinning layer 20, the active layer 30 and the second semiconductor layer 35) as shown in FIG. 8E. Or a dry etching method such as ICP (Inductively Coupled Plasma). A part of the first semiconductor layer 15 can be opened to the outside of the light emitting structure by the isolation etching.

The first electrode 40 and the second electrode 45 electrically connected to the light emitting structure are formed as shown in FIG. 8F. The first electrode 40 may be electrically connected to the first semiconductor layer 15 and the second electrode 45 may be electrically connected to the second semiconductor layer 35. At this time, the second electrode 45 may be formed only in a part of the upper surface of the second semiconductor layer 35.

The first electrode 40 and the second electrode 45 may be formed of a transparent conductive oxide (TCO). The transparent conductive oxide film may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide), IZON (IZO Nitride), ZnO, IrOx, RuOx and NiO.

The first electrode 40 and the second electrode 45 may be formed of an opaque metal such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, And may be formed of one or a plurality of layers in which a conductive oxide film and an opaque metal are mixed, but the present invention is not limited thereto.

FIG. 9A is a plan view of the active layer of the embodiment of the present invention, showing that the first and second pits are hexagonal in plan view. 9B is a photograph of the active layer of the embodiment of the present invention.

9A and 9B, the first pit 70 and the second pit 75 extend to the active layer 30, so that the first pit 70 and the second pit 75 are formed on the upper surface of the active layer 30, Lt; / RTI &gt; The first pit 70 has a wider width than the second pit 75 and, as shown, the top area of the first pit 70 is wider than the top area of the second pit 75.

As described above, the light emitting device of the embodiment of the present invention includes the pitch formation layer 20 on the first semiconductor layer 15, and dislocations 10a (Dislocation) formed under the active layer 30 extend to the active layer 30 And can be prevented from being extended.

In particular, the fat-forming layer 20 comprises a trigger layer 25 and is formed of a first pit 70 having a bottom in a first region 20a between the trigger layer 25 and the first semiconductor layer 15, Can secure electrostatic discharge (ESD) immunity and can prevent deformation of the light emitting structure. The second pit 75 having a bottom in the second region 20b between the trigger layer 25 and the active layer 30 has an internal quantum efficiency IQE by the first pit 70, Can be compensated for.

More specifically, the fat-forming layer 120 includes a first fin-forming layer 120a and a second fin-forming layer 120b, which are sequentially stacked, The second pit 170 having a bottom on the pit 170 and the trigger layer 125 may have a sufficient width difference. In addition, by forming a plurality of trigger layers 225 in the pitch formation layer 220, the size of the pits can be easily controlled.

The light emitting device of the embodiment further includes optical members such as a light guide plate, a prism sheet, and a diffusion sheet, and can function as a backlight unit. Further, the light emitting element of the embodiment can be further applied to a display device, a lighting device, and a pointing device.

At this time, the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

The reflector is disposed on the bottom cover, and the light emitting module emits light. The light guide plate is disposed in front of the reflection plate to guide light emitted from the light emitting module forward, and the optical sheet includes a prism sheet or the like and is disposed in front of the light guide plate. The display panel is disposed in front of the optical sheet, and the image signal output circuit supplies an image signal to the display panel, and the color filter is disposed in front of the display panel.

The lighting device may include a light source module including a substrate and a light emitting device of the embodiment, a heat dissipation unit that dissipates heat of the light source module, and a power supply unit that processes or converts an electric signal provided from the outside and provides the light source module . Further, the lighting device may include a lamp, a head lamp, or a street lamp or the like.

It will be apparent to those skilled in the art that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

10, 110: support substrate 11, 111: buffer layer
10a, 110a, 210a: potentials 15, 115, 215: first semiconductor layer
20, 120, 220: Pit formation layer 20a, 120a, 220a:
20b, 120b, 220b: second region 25, 125, 225:
30, 130, 230: an active layer 35, 135: a second semiconductor layer
40: first electrode 45: second electrode
70, 170, 270: First Pit 75, 175, 275: Second Pit
220c: third region 220d: fourth region
225a: first trigger layer 225b: second trigger layer
225c: third trigger layer 280: third finger
285: Fourth Fit

Claims (20)

A support substrate;
A light emitting structure including a first semiconductor layer sequentially formed on the support substrate, a pit forming layer having a trigger layer inserted therein, an active layer, and a second semiconductor layer;
A first pit comprising a bottom having at least one first pit disposed between the first semiconductor layer and the trigger layer; And
And at least one second pit whose bottom is disposed between the trigger layer and the active layer. The method according to claim 1,
Wherein the first pit and the second pit have a V-shaped cross section. 3. The method of claim 2,
Wherein a width of the first pit is larger than a width of the second pit, and an area of the upper surface of the first pit is larger than an upper surface of the second pit. The method according to claim 1,
Wherein the trigger layer has a larger content of indium (In) than the pinning layer and the active layer. The method according to claim 1,
Wherein the trigger layer is made of gallium nitride (InAlGaN) containing aluminum and having an indium content equal to the pitch formation layer,
Wherein the trigger layer is made of aluminum gallium nitride (AlGaN). The method according to claim 1,
And the bottom of the second pit contacts the trigger layer. The method according to claim 1,
Wherein a plurality of the trigger layers are provided in the pin formation layer. 8. The method of claim 7,
Wherein the number N of pad groups and the number M of the trigger layers satisfy the following expression (1).
[Equation 1]
N = M + 1 The method according to claim 1,
Wherein a width of the first pit is 300 nm to 350 nm and a width of the second pit is 150 nm to 200 nm. The method according to claim 1,
And the trigger layer is provided in the second pinning layer. The light emitting device according to claim 1, wherein the first pinned layer and the second pinned layer are stacked in this order. 11. The method of claim 10,
Wherein a bottom of the first pit is provided only in the first fit formation layer,
And the bottom of the second pit contacts the trigger layer. A support substrate;
A light emitting structure including a first semiconductor layer sequentially formed on the support substrate, a pit forming layer having a trigger layer inserted therein, an active layer, and a second semiconductor layer;
Wherein the indium content of the pin formation layer is higher than the indium content of the pin formation layer. 13. The method of claim 12,
At least one first pit having a bottom disposed between the first semiconductor layer and the trigger layer; And
And at least one second pit whose bottom is disposed between the trigger layer and the active layer. 14. The method of claim 13,
Wherein a width of the first pit is larger than a width of the second pit, and an area of the upper surface of the first pit is larger than an upper surface of the second pit. Forming a first semiconductor layer on a support substrate;
Forming a fin formation layer on the first semiconductor layer at a second temperature lower than a first temperature for forming the first semiconductor layer;
Forming an active layer on the pitch-forming layer; And
And forming a second semiconductor layer on the active layer,
Wherein forming the pitch formation layer includes forming at least one trigger layer at a third temperature lower than the second temperature. 16. The method of claim 15,
At least one first pit having a bottom between the first semiconductor layer and the trigger layer is formed in the step of forming the pinning layer,
Wherein at least one second pit whose bottom is provided between the trigger layer and the active layer is formed in the step of forming the trigger layer. 16. The method of claim 15,
Wherein the pin formation layer is formed to have an indium (In) content greater than that of the first semiconductor layer. 16. The method of claim 15,
Forming the trigger layer, and further forming the pitch formation layer at the second temperature on the trigger layer. 16. The method of claim 15,
Wherein the trigger layer is formed to have an indium (In) content greater than that of the pin formation layer. 16. The method of claim 15,
The forming of the pin formation layer may include forming a first fin formation layer and forming a second fin formation layer at a temperature higher than a temperature at which the first fin formation layer is formed on the first fin formation layer,
And forming the second fin-shaped layer includes forming at least one trigger layer.

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