KR20160099884A - Semiconductor Device - Google Patents

Semiconductor Device Download PDF

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Publication number
KR20160099884A
KR20160099884A KR1020150022134A KR20150022134A KR20160099884A KR 20160099884 A KR20160099884 A KR 20160099884A KR 1020150022134 A KR1020150022134 A KR 1020150022134A KR 20150022134 A KR20150022134 A KR 20150022134A KR 20160099884 A KR20160099884 A KR 20160099884A
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KR
South Korea
Prior art keywords
subgate
insulating film
region
gate
electrode
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KR1020150022134A
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Korean (ko)
Inventor
장창수
서동수
송인혁
박재훈
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삼성전기주식회사
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Priority to KR1020150022134A priority Critical patent/KR20160099884A/en
Publication of KR20160099884A publication Critical patent/KR20160099884A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/732Vertical transistors
    • H01L29/7322Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a semiconductor device including an emitter section into which a carrier flows, a drift section through which a carrier flowing in from the emitter section moves, a plurality of gates that form a channel to move a carrier introduced from the emitter to a drift section, And a collector portion through which a carrier moving through the drift portion is discharged, wherein the subgate includes a emitter electrode and a subgate insulating film surrounding the emitter electrode, and the subgate insulating film The thickness of the portion arranged in the direction toward the collector portion is larger than the thickness of the portion facing the other direction.

Description

[0001]

The present invention relates to a semiconductor device.

Generally, a power semiconductor device is widely used as a control device of a motor or various kinds of switching devices such as an inverter. Specifically, a power semiconductor device means a semiconductor device used in a power device, and is a core of a power device optimized for power conversion and control.

Typical types of power semiconductor devices include metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

Power semiconductor devices (MOSFETs or IGBTs) must have high breakdown voltages and low on-resistance values in DC characteristics and fast switching speeds in AC characteristics.

Further, in the power semiconductor device, the flow of current should be cut off in the switch-off operation, and the channel should be made small in order to effectively cut off the current. At this time, the gate contributing to the channel formation is only a part of the total number of gates, and the gate not contributing to the channel formation can form a parasitic capacitance. This parasitic capacitance increases the delay time of the switching operation, increases the conduction loss, and causes an oscillation of the gate signal in the short-circuit evaluation, thereby causing current oscillation and faulty power semiconductor devices .

Korean Patent Publication No. 10-2013-0035399

An object of the present invention is to provide a semiconductor device capable of reducing parasitic capacitance and switching loss.

A semiconductor device according to an embodiment of the present invention includes: an emitter section through which a carrier flows; a drift section through which a carrier introduced from the emitter section moves; a plurality of gates that form a channel for moving a carrier introduced from the emitter to a drift section A subgate formed between the gate and the collector, and a collector for transferring the carrier to and from the drift portion, wherein the subgate includes a emitter electrode and a subgate insulating film surrounding the emitter electrode, The thickness of the portion disposed in the direction toward the collector portion is thicker than the thickness of the portion disposed in the portion facing the other direction.

A semiconductor device according to an embodiment of the present invention includes a first region of a first conductivity type, a second region of a second conductivity type disposed over the first region, a gate electrode disposed in each of the second region, A first gate and a second gate arranged to penetrate from the second region to a portion of the first region and including a gate insulating film, and a portion of the first region from the second region to the first region between the first gate and the second gate Wherein the subgate includes a subgate electrode disposed inside and a subgate insulating film surrounding the subgate electrode, wherein the subgate insulating film is in contact with a lower surface of the subgate electrode The thickness of the portion is thicker than the thickness of the other portions of the subgate insulating film.

A semiconductor device according to another embodiment of the present invention includes a first region of a first conductivity type, a second region of a second conductivity type disposed over the first region, a gate electrode disposed in each of the second region, A first gate and a second gate arranged to penetrate from the second region to a portion of the first region and a second gate and a second gate disposed between the first region and the second gate, And the subgate includes a subgate electrode disposed therein, a subgate dielectric film surrounding the subgate electrode, and a dummy dielectric film extending in a downward direction of the subgate dielectric film do.

The semiconductor device according to the embodiment of the present invention can reduce the parasitic capacitance and the switching loss.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention in which an emitter electrode is omitted.
FIG. 2 is a cross-sectional view of FIG. 1 cut along AA 'and additionally showing an emitter electrode. FIG.
3 is a plan view showing a semiconductor device according to another embodiment of the present invention, in which the emitter electrode is omitted.
FIG. 4 is a cross-sectional view of FIG. 3 cut along BB 'and additionally showing an emitter electrode. FIG.

The embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

The various embodiments disclosed herein are not limited to a particular type of semiconductor device, but may be applied to other types of semiconductor devices including, for example, MOSFETs, power IGBTs, and various types of thyristors.

Also, the first conductivity type may be an N-type impurity doped with an N-type impurity, and in this case, the second conductivity type may be a P-type doped with a P-type impurity. Conversely, the first conductivity type may be P-type and the second conductivity type may be N-type. The N-type and P-type impurities are generally used in semiconductors. The N-type impurities include phosphorus (P), arsenic (As), and the P-type impurities may include boron (B) and the like.

FIG. 1 is a plan view showing a semiconductor device 100 according to an embodiment of the present invention, in which the emitter electrode 140 is omitted. FIG. 2 is a plan view of the semiconductor device 100 taken along line AA ' Fig.

1 and 2, a semiconductor device 100 according to an embodiment of the present invention includes an emitter portion into which a carrier flows, a drift portion through which a carrier introduced from the emitter portion moves, a carrier introduced from the emitter, A sub gate 130 formed between the gates 120 and a collector part for transferring a carrier to and from the drift part, and the sub gate 130, And a subgate insulating film 133 surrounding the emitter electrode 140 and the emitter electrode 140. The thickness of the portion of the subgate insulating film 133 facing the collector is different Is greater than the thickness of the portion disposed at the portion facing the light emitting layer.

The emitter part is connected to an external power source and serves to supply a carrier to the drift part. The carrier may be electron or hole. The drift portion is a region where carriers supplied from the emitter portion move. The drift unit may be divided into a plurality of regions of a first conductivity type or a second conductivity type. The carrier moved through the drift unit may be discharged to the outside of the drift unit through the collector unit. Further, the carrier can be moved to the drift portion through the collector portion. In FIG. 2, the emitter portion may correspond to the emitter electrode 140.

The gate 120 may serve to form a channel in the drift region and to eliminate the channel. The gate 120 includes a gate electrode 121 and a voltage is applied to the gate electrode 121 to form a channel in a part of the drift portion so that carriers introduced through the emitter portion are injected through the drift portion To the collector unit.

A channel is formed in a part of the drift region and the carrier can move through the channel in an ON state in which a voltage higher than a specific value is applied to the gate 120. [ In addition, in the off state in which no voltage is applied to the gate 120, the channel may be extinguished, and movement of carriers may be restricted.

In FIG. 2, the collector unit may correspond to the collector electrode 150. In the semiconductor according to the embodiment of the present invention, the drift may further include a region that is in contact with the collector portion and is in a second conductivity type. The region doped with the second conductivity type may be a portion corresponding to the sixth region 116 of FIG. In this case, when a voltage higher than the built-in potential is applied to the region of the second conductivity type, holes are injected from the collector into the drift region to cause conduction modulation phenomenon, and electrons and holes may be conducted through the conduction.

The subgate 130 may form a channel in the drift portion and may extinguish the same as the gate 120. The subgate 130 may include a fifth region 115 of a second conductivity type below the subgate 130. The fifth region can assist in realizing a high breakdown voltage and can help the holes to disappear when switching off.

In general, the power semiconductor device is required to cut off the current flow during the switch-off operation and to reduce the channel for effective current shutdown. At this time, a parasitic capacitance can be formed between the gate and the collector electrode. Such parasitic capacitance and hole accumulation increase the delay time of the switching operation, increase the conduction loss, cause oscillation of the gate signal in the short-circuit evaluation, and cause occurrence of current oscillation, It can cause defects.

The semiconductor device 100 according to the embodiment of the present invention has a structure in which the portion of the subgate insulating film 133 disposed in the direction toward the collector portion is thicker than the thickness of the other portion, The parasitic capacitors that can be generated can be reduced, and the switching loss can be reduced.

The semiconductor device 100 according to an embodiment of the present invention includes a portion of the subgate insulating film 133 that is in contact with the subgate electrode 131 and a portion of the connection electrode 132 And a fifth region 115, which is a second conductive type, disposed in a portion surrounded by a portion that is in contact with the first region 115. The fifth region 115 can improve conduction loss and switching loss of the semiconductor device 100.

The subgate 130 includes two or more connection electrodes 132 disposed between the gates 120 and connecting the subgate electrodes 131 included in the two or more subgates 130 . The sub-gate insulating layer 133 may be disposed to surround the sub-gate electrode 131 and the connection electrode 132. The portion of the portion of the subgate insulating layer 133 facing the subgate electrode 131 may be thicker than the portion of the portion of the subgate insulating layer 133 facing the connection electrode 132 .

Thus, the parasitic capacitance generated between the sub-gate 130 and the collector portion can be reduced by arranging the portion where the sub-gate insulating film 133 is in contact with the sub-gate electrode 131 to be thick.

The portion of the subgate insulating film 133 that is in contact with the connecting electrode 132 is arranged to be thinner than the portion of the subgate insulating film 133 that is in contact with the subgate electrode 131, The fifth region 115 of the second conductivity type can be disposed. That is, the fifth region 115 is formed in a portion of the drift portion that is adjacent to the sub-gate electrode 131 in the portion of the sub-gate insulating film 133 that faces the collector portion, Or the like.

The fifth region 115 can improve conduction loss and switching loss of the semiconductor device 100. Specifically, the fifth region can help to realize a high breakdown voltage and can help the holes to disappear when switching off.

Referring to FIG. 2, the gate 120 and the sub-gate 130 may be disposed in the drift region, and the sub-gate electrode 131 may be disposed in the drift region.

1 and 2, a semiconductor device 100 according to an embodiment of the present invention will be described in more detail.

A semiconductor device 100 according to an embodiment of the present invention includes a first region 111 of a first conductivity type and a second region 112 of a second conductivity type disposed above the first region 111 . Each of the gate electrodes 121 includes a gate electrode 121 and gate insulating films 122a and 122b surrounding the gate electrode 121. A portion of the first region 111 from the second region 112 (120a) and a second gate (120b) disposed between the first region (120a) and the second region (120b) and between the first region And subgates 130, 130a, and 130b arranged to penetrate up to a portion of the subgates 111, 130a, and 130b. The subgates 130, 130a and 130b include subgate electrodes 131a and 131b and a subgate insulating layer 133 surrounding the subgate electrodes 131a and 131b. The thickness of the portion of the gate electrode 133 contacting the lower surface of the subgate electrodes 131a and 131b is thicker than the thickness of the other portions of the subgate insulating film 133. [

The semiconductor device 100 according to an embodiment of the present invention may further include a sixth region 116 of a second conductivity type between the first region 111 and the collector electrode 150. [ In this case, when a voltage higher than the built-in potential is applied to the sixth region 116, holes may be injected from the sixth region 116 to the first region 111 to cause a conduction modulation phenomenon, The holes may be conducted.

As described above, generally, in the power semiconductor device, the flow of current should be cut off in the switch-off operation, and the channel should be made small in order to effectively cut off the current. At this time, a parasitic capacitance can be formed between the gate and the collector electrode. Such parasitic capacitance and hole accumulation increase the delay time of the switching operation, increase the conduction loss, cause oscillation of the gate signal in the short-circuit evaluation, and cause occurrence of current oscillation, It can cause defects.

The semiconductor device 100 according to the embodiment of the present invention is formed such that the thickness of the part of the subgate insulating film 133 which is disposed in the direction toward the collector electrode 150 is thicker than the thickness of the other part of the subgate insulating film 133, , 130b and the collector electrode 150 can be reduced and the switching loss can be reduced.

The semiconductor device 100 according to the embodiment of the present invention is characterized in that the portion of the subgate insulating film 133 disposed in the direction toward the collector electrode 150 is in contact with the subgate electrodes 131a and 131b And a fifth region 115, which is a second conductive type, disposed at a portion surrounded by the connection electrode 132. The fifth region 115 may assist in realizing a high breakdown voltage, and may also assist in eliminating holes at the time of switching off.

The first region 111 may be formed by implanting a first conductive impurity into one surface of a semiconductor substrate through an implant process or a diffusion process. Also, the first region 111 may be formed by an epitaxial process. The thickness, shape, and concentration of the first region 111 may be determined to be appropriate values to obtain the breakdown voltage and on-resistance required in the semiconductor device 100, The present invention is not limited thereto.

The semiconductor substrate on which the first region 111 is disposed may be a silicon substrate, a silicon carbide substrate, or a sapphire substrate, but is not limited thereto.

The second region 112 may be arranged so as to penetrate into the first region 111 at a predetermined depth. Since the second region 112 may be formed by implanting impurities of the second conductivity type into the substrate on which the first region 111 is formed, a portion of the first region 111 may be penetrated Shape.

The gates 120, 120a, and 120b are arranged to penetrate from the second region 112 to a portion of the first region 111. The gates 120, 120a, and 120b may be disposed within the trenches disposed at regular intervals above the first region 111 and the second region 112. Gate electrodes 121a and 121b having a conductive material such as polysilicon are disposed inside the gates 120, 120a and 120b. The gate electrodes 121a and 121b are surrounded by gate insulating films 122a and 122b. The gate insulating layers 122a and 122b serve to isolate the gate electrodes 121a and 121b from the first and second regions 111 and 112 and may include an insulating material such as a silicon oxide layer.

The subgates 130, 130a and 130b are arranged to penetrate from the second region 112 to a portion of the first region 111 between the gates 120, 120a and 120b. The subgates 130, 130a and 130b may be disposed inside the trenches arranged at regular intervals above the first region 111 and the second region 112 like the gates 120, 120a and 120b. A subgate electrode 131 having a conductive material such as polysilicon is disposed in the subgates 130, 130a, and 130b. The subgate electrodes 131, 131a and 131b may be surrounded by a subgate insulating layer 133. The subgate insulating layer 133 serves to isolate the subgate electrodes 131, 131a and 131b from the first and second regions 111 and 112 and may include an insulating material such as a silicon oxide layer. have.

The gates 120, 120a, 120b and the subgates 130, 130a, 130b may be simultaneously formed by the same etching process. Therefore, the depths of the subgates 130, 130a, and 130b and the depths of the gates 120, 120a, and 120b may be the same. By making the depths of the subgates 130, 130a and 130b and the depths of the gates 120, 120a and 120b equal to each other, the depletion region can be uniformly formed in the OFF operation of the semiconductor device 100 The pressure resistance can be improved.

Referring to FIG. 2, when a plurality of gates 120 are formed, two or more sub-gates 130 (between the first gate 120a and the second gate 120b, which are the gates 120, 120a, , 130a, and 130b. In this case, the connection electrode 132 may further include a connection electrode 132 connecting the side surfaces of the sub gate electrodes 131a and 131b. In this case, the two or more sub-gates 130, 130a, and 130b are electrically connected to each other by the connection electrode 132. The subgate electrodes 131, 131a and 131b and the connection electrodes 132 included in the two or more subgates 130, 130a and 130b may be surrounded by the subgate insulating layer 133. The thickness of a portion of the subgate insulating layer 133 that is in contact with the lower portion of the subgate electrodes 131, 131a and 131b may be greater than a thickness of a portion of the subgate insulating layer 133 that is in contact with the lower portion of the connection electrode 132. [ By arranging in this manner, the parasitic capacitance generated between the sub-gates 130, 130a, and 130b and the collector electrode 150 can be reduced.

The semiconductor device 100 according to an embodiment of the present invention may further include a fifth region 115 of the second conductivity type. When the thickness of the portion of the subgate insulating film 133 that is in contact with the lower portion of the subgate electrodes 131, 131a and 131b is greater than the thickness of the portion of the subgate insulating film 133 that is in contact with the lower portion of the connecting electrode 132 And the fifth region 115 may be disposed under the sub-gate insulating layer 133 in contact with the lower surface of the connection electrode 132.

The fifth region 115 may be formed by implanting a second conductive impurity into a portion of the first region 111. The fifth region 115 may be formed in the process of forming the second region 112. The impurity concentration and height of the second region 112 and the fifth region 115 may be equal to each other have.

The fifth region 115 serves to induce the conduction modulation effect, thereby improving the conduction loss and the switching loss of the semiconductor device 100.

The semiconductor device 100 according to an embodiment of the present invention may further include a third region 113 of the first conductivity type. A third region 113 may be disposed above the second region 112 and be disposed in contact with the gate 120 and the subgate 130. In this case, the third region 113 may be formed between the second region 112 and the gate insulating layer 122, or between the second region 112 and the sub-gate insulating layer 133. Referring to FIG. 2, since the third region 113 can be formed by implanting impurities of the first conductivity type into a portion of the second region 112, And can be arranged in a shape in which a part of the surface is digged in. The remaining portion of the third region 113 other than the gate insulating layer 122 or the subgate insulating layer 133 may be surrounded by the second region 112.

The semiconductor device 100 according to an embodiment of the present invention may further include a fourth region 114 of a second conductivity type. A fourth region 114 may be disposed above the second region 112 and be disposed in contact with the third region 113. Referring to FIG. 2, the fourth region 114 may be formed in a portion of the second region 112 by implanting an impurity of the second conductivity type so that the impurity concentration is higher than that of the second region 112 Therefore, it is possible to arrange the second region 112 in a shape of digging a part of the second region 112 from one side of the substrate.

The emitter electrode 140 may be disposed on the upper portion of the second region 112 to the fourth region 114 and may be disposed to contact the third region 113 and the fourth region 114. The emitter electrode 140 may include a conductive material such as aluminum (Al), and is not particularly limited. The carrier may move to the third region 113 through the emitter electrode 140.

The collector electrode 150 may be disposed under the first region 111. Referring to FIGS. 2 and 3, it may be disposed on the lower surface of the substrate. The collector electrode 150 may include a conductive material such as aluminum (Al) and is not particularly limited. The carrier moved through the first region 111 may be discharged through the collector electrode 150.

3 is a plan view of the semiconductor device 200 according to another embodiment of the present invention, in which the emitter electrode 240 is omitted. FIG. 4 is a plan view of the semiconductor device 200 taken along line BB ' Fig.

3 and 4, a semiconductor device 200 according to another embodiment of the present invention includes a first region 211 that is a first conductive type, a second region 211 that is disposed over the first region 211, Type second region 212. The second region 212 includes a first region 212, Each of the gate electrodes 221, 221a and 221b and the gate insulating films 222 and 222a and 222b surrounding the gate electrodes 221 and 221a and 221b are disposed in the second region 212, And a first gate 220a and a second gate 220b which are arranged to penetrate the first region 211 to a portion thereof. Also included are subgates 230, 230a, 230b disposed between the first and second gates 220a, 220b from the second region 212 to a portion of the first region 211 do. The subgates 230, 230a and 230b are formed in the lower part of the subgate insulating film 233 surrounding the subgate electrode 231, the subgate insulating film 233 surrounding the subgate electrode 231, And extended dummy insulating films 234a and 234b.

Since the semiconductor device 200 according to the embodiment of the present invention includes the dummy insulating films 234a and 234b under the sub-gate insulating film 233, the semiconductor device 200 is formed between the sub-gates 230, 230a and 230b and the collector electrode 250 Space is reduced. Accordingly, parasitic capacitors that may occur between the sub-gates 230, 230a, and 230b and the collector electrode 250 can be reduced, and the switching loss can be reduced.

The dummy insulating films 234a and 234b may include a first dummy insulating film 234a and a second dummy insulating film 234b and the first dummy insulating film 234a and the second dummy insulating film 234b may be spaced apart from each other . At this time, a fifth region 215, which is disposed between the first dummy insulating film 234a and the second dummy insulating film 234b and is of the second conductivity type, may be further included.

The dummy insulating films 234a and 234b are formed to be in contact with the side surfaces of the subgate insulating film 233 facing one side of the first gate 220a and downward from the lower surface of the subgate insulating film 233 The first dummy insulating film 234a and the second gate insulating film 233 are formed on the lower surface of the subgate insulating film 233 in contact with the side surfaces of the subgate insulating film 233 facing the one side of the second gate 220b, And a second dummy insulating film 234b which is extended and disposed. The first dummy insulating film 234a and the second dummy insulating film 234b may be spaced apart from each other. At this time, a fifth region 215, which is disposed between the first dummy insulating film 234a and the second dummy insulating film 234b and is of the second conductivity type, may be further included.

The semiconductor device 200 according to the embodiment of the present invention is formed such that the portion of the subgate insulating film 233 which is disposed in the direction toward the collector electrode 250 in contact with the subgate electrode 231, And a fifth region 215, which is a second conductive type, disposed at a portion surrounded by the connection electrode.

The semiconductor device 200 according to an exemplary embodiment of the present invention may further include a sixth region 216 of a second conductivity type disposed between the first region 211 and the collector electrode 250.

Since the gates 220, 220a and 220b and the subgates 230 and 230a and 230b can be simultaneously formed by the same etching process, the depth of the subgates 230, 230a and 230b, 220a, 220b may be the same.

The semiconductor device 200 may further include a third region 213 and a fourth region 214, as in the semiconductor device 200 described above with reference to FIGS. The substrate 200 includes first to sixth regions 211, 212, 213, 214, 215 and 216, a collector electrode 250, an emitter electrode 240, gates 220, 220a and 220b, subgates 230 and 230a , And 230b are the same as those of the above-described embodiment, and therefore, description thereof will not be repeated.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 200: semiconductor element
111, 211: first region
112, < / RTI > 212:
113, 213: the third region
114, 214: fourth region
115, 215: fifth region
116, 216: sixth region
120, 120a, 120b, 220, 220a, 220b:
121, 121a, 121b, 221, 221a, 221b:
122, 122a, 122b, 222, 222a, and 222b:
130, 130a, 130b, 230, 230a, 230b:
131, 131a, 131b, 231, 231a, 231b:
132: connecting electrode
133 and 233: Sub-
234a, 234b: a dummy insulating film
140, 240: Emitter electrode
150, 250: collector electrode
160, 260: gate bus

Claims (16)

An emitter portion into which the carrier flows;
A drift portion through which the carrier introduced from the emitter portion moves;
A plurality of gates forming a channel such that the carrier introduced from the emitter moves to the drift portion;
A subgate formed between the gates; And
And a collector unit for transferring the carrier to and from the drift unit,
Wherein the subgate includes a emitter electrode and a subgate insulating film surrounding the emitter electrode, wherein a thickness of a portion of the subgate insulating film that is disposed in a direction toward the collector portion is thicker than a thickness of a portion of the subgate insulating film that faces the other direction Semiconductor device.
The method according to claim 1,
Wherein the subgate further comprises a connection electrode connecting two or more subgate electrodes included in the two or more subgates between the gates.
3. The method of claim 2,
Wherein the subgate insulating film surrounds the subgate electrode and the connecting electrode, and a portion of the subgate insulating film facing the subgate electrode is thicker than a thickness of a portion of the subgate insulating film facing the collector electrode, Semiconductor device.
The method of claim 3,
And a fifth region, which is a second conductivity type, disposed in a portion surrounded by a portion in contact with the sub gate electrode and a portion in contact with the connection electrode among the portions arranged in the direction toward the collector portion of the sub gate insulating film in the drift portion Semiconductor device.
3. The method of claim 2,
Wherein the gate and the sub gate are disposed intruding into the drift portion, and the sub gate electrode is disposed to penetrate the drift portion.
A first region of a first conductivity type;
A second region disposed over the first region and being a second conductive type;
A first gate and a second gate including a gate electrode disposed in each of the first region and the gate electrode and a gate insulating film surrounding the gate electrode, the first gate and the second gate penetrating from the second region to a portion of the first region; And
And a subgate disposed between the first gate and the second gate so as to penetrate from the second region to a portion of the first region,
Wherein the subgate includes a subgate electrode disposed inside and a subgate insulating film surrounding the subgate electrode, wherein a thickness of a portion of the subgate insulating film that is in contact with a lower surface of the subgate electrode is different from that of the subgate insulating film The thickness of the semiconductor element being greater than the thickness of the portion.
The method according to claim 6,
Wherein the subgate disposed between the first and second gates is at least two, and further comprises a connecting electrode connecting the side surfaces of the respective subgate electrodes.
8. The method of claim 7,
Wherein the subgate insulating film surrounds the subgate electrode and the connecting electrode and the thickness of the subgate insulating film contacting the bottom surface of the subgate electrode is thicker than the thickness of the subgate insulating film contacting the bottom surface of the connecting electrode.
9. The method of claim 8,
And a fifth region disposed under the emitter gate insulating film in contact with the lower surface of the connection electrode and being a second conductive type.
The method according to claim 6,
The depth penetrated by the subgate and the depth penetrating the gate are the same.
A first region of a first conductivity type;
A second region disposed over the first region and being a second conductive type;
A first gate and a second gate including a gate electrode disposed in each of the first region and the gate electrode and a gate insulating film surrounding the gate electrode, the first gate and the second gate penetrating from the second region to a portion of the first region; And
And a subgate disposed between the first gate and the second gate so as to penetrate from the second region to a portion of the first region,
Wherein the subgate includes a subgate electrode disposed inside, a subgate insulating film surrounding the subgate electrode, and a dummy insulating film extending in a downward direction of the subgate insulating film.
12. The method of claim 11,
The depth penetrated by the subgate and the depth penetrating the gate are the same.
12. The method of claim 11,
Wherein the dummy insulating film includes a first dummy insulating film and a second dummy insulating film spaced apart from each other.
14. The method of claim 13,
And a fifth region which is disposed between the first dummy insulating film and the second dummy insulating film and is of the second conductivity type.

12. The method of claim 11,
Wherein the dummy insulating film includes a first dummy insulating film extending in a downward direction from a lower surface of the subgate insulating film in contact with a side surface of the subgate insulating film facing one side of the first gate, And a second dummy insulating film extending downward from a lower surface of the subgate insulating film in contact with a side surface of the subgate insulating film opposite to the first dummy insulating film, wherein the first dummy insulating film and the second dummy insulating film are spaced apart from each other device.
16. The method of claim 15,
And a fifth region which is disposed between the first dummy insulating film and the second dummy insulating film and is of the second conductivity type.



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