KR20160090461A - Source driver circuit device and display device comprising thereof - Google Patents

Abstract

Embodiments of the present invention relate to a source driver circuit device and a display device including the same. The source driver circuit device comprising a resister, a digital-analog conversion unit, and an output buffer includes a power detection unit which compares a logic voltage with a reference voltage to switch the output buffer. In the embodiments of the present invention, provided is the display device including the same. The source driver circuit device can protect the display panel by not applying a data signal to a data line when the abnormality of logic voltage occurs.

Description

TECHNICAL FIELD [0001] The present invention relates to a source driver circuit device and a display device including the source driver circuit device.

The present embodiments relate to a source driver circuit device and a display device including the same.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. Recently, a liquid crystal display device, a plasma display device, an organic light emitting display device Organic Light Emitting Display Device) are being utilized.

Such a display device includes a display panel in which data lines and gate lines are arranged, subpixels are arranged in a matrix type at each intersection of data lines and gate lines, a data driver for supplying data signals to data lines, A gate driver for supplying a scan signal to the gate lines, and a timing controller for controlling the data driver and the gate driver.

The timing controller performs a process of receiving and recognizing corresponding data from one or a plurality of source driver integrated circuits included in a data driver to perform a specific process (e.g., a compensation process, etc.).

On the other hand, the source driver integrated circuits included in the data driver reflect the result of logic circuit operation in order to apply data to the data line, and it is necessary to prevent the voltage from being applied to the data line when an error occurs in such logic circuit operation . However, there is a problem that a separate logic circuit is required to determine the error of the logic circuit from outside the logic circuit.

Also, when a data voltage is applied to the data line of the display panel without controlling the error of the logic circuit, there is a high possibility that errors in operation of the display panel occur. Therefore, a technique for controlling the application of the data voltage to the display panel when an error occurs in the logic circuit is required.

It is an object of these embodiments to confirm whether or not a problem arises in a logic voltage applied to a logic circuit constituting a source driver circuit device so that an error of a logic voltage occurs in the logic circuit of the source driver circuit device We want to prevent it from being propagated as error.

An object of these embodiments is to compare a logic voltage applied to a source driver circuit device with a reference voltage so that a data signal is applied to a data line only when a logic voltage is applied within a normal range, do.

One embodiment includes a power sensing section for comparing a logic voltage and a reference voltage to switch the output buffer, wherein the source driver circuit device comprising a resistor, a digital-to-analog converter section and an output buffer, In the example, a display device including this is provided.

In another embodiment, the power sensing unit further includes a gamma buffer that provides a power supply voltage with N gamma voltages, wherein the reference voltage includes any one of N gamma voltages.

In another embodiment, the display device includes a gate driver, a data driver, and a display panel. The data driver includes a resistor, a digital-analog converter, an output buffer, and a power switch And at least one source driver circuit device including a sensing portion.

In yet another embodiment, the present disclosure provides a display device comprising a source printed circuit board or a control printed circuit board including a power sensing section for comparing the logic voltage and the reference voltage to switch the output buffer.

According to the embodiments described above, when a logic voltage such as VCC is compared with a specific reference voltage to prevent a logic voltage from being applied, a data signal is not applied to the data line to protect the display panel .

According to the present embodiment, when a malfunction occurs in either the top or the bottom in a display panel using a dual source driver circuit device, the output buffer of the source driver circuit device in which a malfunction occurs is floated so that a voltage So that only the data voltage generated by the normal source driver circuit device is output on the screen, and no burst occurs.

1 is an exemplary diagram of a schematic system configuration of a display device 100 according to the present embodiments.
2 is a diagram showing the configuration of the logic voltage VCC and the drive circuit power supply voltage SVDD.
3 is a diagram illustrating a configuration of a source driver integrated circuit including a configuration for detecting an error of VCC and controlling an output of SVDD according to an embodiment of the present invention.
4 is a diagram illustrating a detailed configuration for checking an abnormal operation of a logic voltage according to an embodiment of the present invention.
FIG. 5 is a block diagram illustrating an abnormal operation of a logic voltage according to another embodiment of the present invention. Referring to FIG.
6 is a view illustrating an operation of a single source printed circuit board according to an exemplary embodiment of the present invention.
7 is a view illustrating an operation of a dual source printed circuit board according to another embodiment of the present invention.
8 is a view showing a configuration of a source driver circuit device according to an embodiment of the present invention.
9 is a diagram showing the configuration of a source driver circuit device according to another embodiment of the present invention.
10 is a view showing an embodiment where a power sensing unit is located on a source printed circuit board according to another embodiment of the present invention.
11 is a view showing a configuration in which a power sensing unit is disposed on a control printed circuit board according to another embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is an exemplary diagram of a schematic system configuration of a display device 100 according to the present embodiments.

Referring to FIG. 1, a display device 100 according to the present embodiment includes a display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like.

In the display panel 110, a plurality of data lines (DL) are arranged in a first direction, a plurality of gate lines (GL) are arranged in a second direction crossing the first direction, (SP: Sub Pixel) are arranged in a matrix type. The data driver 120 supplies the data voltages to the data lines to drive the data lines. The gate driver 130 sequentially supplies the scan signals to the gate lines to sequentially drive the gate lines. The timing controller 140 supplies control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The timing controller 140 starts scanning in accordance with the timing to be implemented in each frame and outputs the image data input from the outside (for example, a host system (not shown) or the like) to a data signal format used by the data driver 120 And the converted image data is outputted, and the data driving is controlled at a proper time according to the scan.

The gate driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the gate lines sequentially according to the control of the timing controller 140 to sequentially drive the gate lines.

1, the gate driver 130 may be located only on one side of the display panel 110, or may be located on both sides, depending on the case.

In addition, the gate driver 130 may include a plurality of gate driver ICs.

The gate driver IC included in the gate driver 130 is illustrated as being five (GDIC # 1, ..., GDIC # 5) in FIG. 1, , One, or two or more. However, for convenience of explanation, it is assumed that five gate driver ICs (GDIC # 1, ..., GDIC # 5) are included in the display device 100 in the following description.

The gate driver integrated circuits GDIC # 1, ..., GDIC # 5 included in the gate driver 130 are formed by a tape automated bonding (TAB) method or a chip on glass (COG) (Gate In Panel) type and may be directly disposed on the display panel 110. In some cases, the display panel 110 may be integrated with the Bonding Pad of the display panel 110, .

Each of the gate driver integrated circuits GDIC # 1, ..., GDIC # 5 may include a shift register, a level shifter, and the like.

When the specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies the data voltage to the data lines to drive the data lines.

The data driver 120 may include one or a plurality of source driver ICs (also referred to as data driver ICs).

1, the source driver IC included in the data driver 120 is illustrated as being 10 (SDIC # 1, ..., SDIC # 10) 200 in FIG. 1, Only one, or two or more. However, for convenience of explanation, it is assumed that the display device 100 includes ten source driver integrated circuits (SDIC # 1, ..., SDIC # 10).

The source driver integrated circuits SDIC # 1, ..., SDIC # 10 included in the data driver 120 are controlled by a Tape Automated Bonding (TAB) or a Chip On Glass (COG) And may be connected to a bonding pad of the panel 110 or may be disposed directly on the display panel 110 and may be integrated on the display panel 110 as the case may be.

Each of the source driver integrated circuits (SDIC # 1, ..., SDIC # 10) includes a shift register, a latch, a digital analog converter (DAC), an output buffer, And an analog digital converter (ADC) that senses an analog voltage value for compensation and converts the digital voltage value to a digital value and generates and outputs sensing data.

Also, each of the source driver integrated circuits (SDIC # 1, ..., SDIC # 10) may be implemented by a chip on film (COF) method. In each of the source driver integrated circuits (SDIC # 1, ..., SDIC # 10), one end is bonded to at least one source printed circuit board and the other end is connected to the display panel 110 Bonding.

The above-mentioned source printed circuit board may be one, and may be two (150a, 150b) or three or more as in Fig. Hereinafter, for convenience of explanation, it is assumed that the display device 100 includes two source printed circuit boards 150a and 150b. Also, the source printed circuit board may be formed on only one side of the display panel 110 and on both sides thereof. A configuration formed on only one side will be referred to as a single source PCB, and a configuration formed on both sides will be referred to as a dual source PCB.

On the other hand, the source driver integrated circuits (SDIC # 1, ..., SDIC # 10) included in the data driver 120 may be included in the same group or may be divided into several groups.

1, five source driver integrated circuits (SDIC # 1, ..., SDIC # 5) are included in the first group G1 from the left, and five source driver ICs # 6, ..., SDIC # 10) are included in the second group G2.

The source driver integrated circuits included in each group transmit and receive signals and data to and from the timing controller 140 through one wiring structure.

Accordingly, the display device 100 according to the present embodiment is capable of outputting a signal between the source driver integrated circuits (SDIC # 1, ..., SDIC # 5) included in the first group G1 and the timing controller 140 / Data transmission / reception between the source driver ICs (SDIC # 6, ..., SDIC # 10) and the timing controller 140 included in the second group G2 and the first group wiring structure for data transmission / And a second group wiring structure for the second group wiring structure.

In this regard, the first group wiring structure is constituted by the first group source printed circuit board 150a (SDIC # 1) to which the source driver integrated circuits (SDIC # 1, ..., SDIC # 5) included in the first group G1 are bonded And a first group connection medium 160a for connecting the first group source printed circuit board 150a and the control printed circuit board 170 on which the timing controller 140 is disposed.

The second group wiring structure includes a second group source printed circuit board 150b to which the source driver integrated circuits (SDIC # 6, ..., SDIC # 10) included in the second group G2 are bonded A second group connection medium 160b for connecting the second group source printed circuit board 150b and the control printed circuit board 170 on which the timing controller 140 is disposed, and the like.

The first group connection medium 160a and the second group connection medium 160b may be, for example, a flexible flat cable (FFC) or a flexible printed circuit (FPC).

The timing controller 140 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and an input data enable (DE) together with video data of an input video from an external host system (not shown) Signal, a clock signal (CLK), and the like.

The timing controller 140 may switch the image data input from the host system to the data signal format used by the data driver 120 and output the converted image data. The data driver 120 and the gate driver 130 A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal to generate various control signals and supplies the generated control signals to the data driver 120 and the gate driver 130 .

For example, in order to control the gate driver 130, the timing controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like. The gate start pulse GSP controls the operation start timing of the gate driver integrated circuits GDIC # 1, ..., GDIC # 5 constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuits GDIC # 1, ..., GDIC # 5, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies timing information of the gate driver integrated circuits GDIC # 1, ..., GDIC # 5.

The timing controller 140 controls the data driver 120 such that a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, (DCS: Data Control Signal) including a data signal The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits SDIC # 1, ..., SDIC # 10 constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source driver integrated circuits (SDIC # 1, ..., SDIC # 10). The source output enable signal SOE controls the output timing of the data driver 120. The polarity control signal POL may be further included in the data control signal DCS in order to control the polarity of the data voltage of the data driver 120. [

1, a control circuit board 170 is connected to a power source for controlling various voltages or currents to supply or supply various voltages or currents to the display panel 110, the data driver 120, the gate driver 130, A controller (not shown) may be further disposed. These power controllers are also referred to as power management ICs (PMICs).

The display device 100 shown in FIG. 1 briefly includes, for example, a liquid crystal display (PDP), a plasma display device, an organic light emitting display device Lt; / RTI >

In each subpixel SP formed on the display panel 110, circuit elements such as transistors and capacitors are formed. For example, when the display panel 110 is an organic light emitting display panel, each sub-pixel includes a circuit composed of an organic light emitting diode (OLED), two or more transistors and one or more capacitors, Respectively.

As described above, the configuration in which the source printed circuit board is formed on only one side of the display panel 110 and the configuration formed on both sides of the single source printed circuit board is shown in the configuration of the dual source printed circuit board through the source printed circuit board, A logic voltage VCC and a drive circuit power supply voltage SVDD of a high voltage are applied to the integrated circuits SDIC # 1 to SDIC # The drive circuit power supply voltage SVDD, which is a high voltage, supplies power to the gamma circuit and the output buffer by the control of the circuit, that is, the digital control block.

2 is a diagram showing the configuration of the logic voltage VCC and the drive circuit power supply voltage SVDD. FIG. 2 shows an example in which power is applied from the source driver integrated circuits (SDIC # 1,..., SDIC # 10) 200 shown in FIG. The logic voltage VCC is applied to a digital control block 210, which in one embodiment may have a value of 1.8V and is a low voltage. The digital control block 210 applies a channel control signal to the latch control unit 220 and the VCC controls the switch 250 of the output buffer 240 through the digital control block 210. The drive circuit power supply voltage SVDD supplies power to the gamma circuit 250 and supplies power to the output buffer 240.

On the other hand, the logic voltage VCC and the driving circuit power supply voltage SVDD are separately controlled. In this case, when only SVDD is applied in a state in which the VCC is not normally applied, the IC and the panel malfunction. Therefore, a configuration for preventing the SVDD from being applied when a malfunction of the VCC occurs occurs in the source driver integrated circuits to ensure the stability of the display panel. In particular, even when the VCC and VDD are individually driven when the Top / Bottom Dual S-PCB is used, one VCC may be abnormal, thereby eliminating operational errors through the safety device of the source driver integrated circuit according to the present invention.

3 is a diagram illustrating a configuration of a source driver integrated circuit including a configuration for detecting an error of VCC and controlling an output of SVDD according to an embodiment of the present invention. As shown in FIG. 2, the logic voltage VCC is applied to the power sensing unit 310 through the digital control block 210. The power sensing unit 310 senses whether the logic voltage VCC is abnormal or normal and controls the output buffer 240.

In one embodiment of the reference voltage for detecting whether the power sensing unit 310 is abnormal or normal, the logic voltage VCC is applied to the comparator so that VCC and a low level of gamma voltage are applied to the comparator, The switch 250 of the final output buffer 240 for applying the source data to the panel is switched to apply the black data or the black data It is possible to control to perform a floating operation. In one embodiment, the power sensing unit 310 controls the switch 250 of the output buffer 240 to apply black data in the configuration of a single source printed circuit board and to be floating in a dual source printed circuit board. A detailed configuration of the power sensing unit 310 for controlling the switch 250 of the output buffer 240 will be described with reference to FIG.

4 is a diagram illustrating a detailed configuration for checking an abnormal operation of a logic voltage according to an embodiment of the present invention. The logic voltage VCC is connected to the input of the comparator 312 of the power sensing unit 310. A reference voltage for checking whether the VCC is normal or abnormal is input to another input terminal of the comparator 312. In one embodiment, the reference voltage may be a low level gamma voltage VH1. The comparator 312 compares the voltage of VCC with a low level of gamma voltage using a comparator. As a result, when the VCC is determined to be abnormal, the final output buffers 240a to 240n, which apply the source data to the panel, Or to control the switch control block 315 for controlling the switches 250a to 250n to apply black data or to perform a floating operation.

4, VCC may be compared to a specific magnitude of gamma voltage created by SVDD when the VCC is lower than the logic voltage or on an abnormal operation, based on the source driver IC (Source D-IC). For example, when the gamma voltage of any one of VH10 (15.8V) to VH1 (0.7V) is selected and compared with VCC, SVSS (0V) is output to the switch control block 315 if it is different. The output switch control block 315 is a block for controlling the switches 250a to 250n of the final output stage buffers 240a to 240n for applying the data voltage to the display panel 310. [ When the VCC and the SVDD voltages of the source driver integrated circuit are normally operated, the output switch control block 315 controls the output switch control block 315 such that, for example, when the logic voltage VCC input to the comparator 312 of FIG. 4 is lower than the gamma voltage VH1 The output switch control block 315 controls the final output stage buffers 240a to 240n. In the case of a single source printed circuit board, VSS may be applied to allow the black data to be applied. Also, in case of a dual source printed circuit board, the final output stage buffers 240a to 240n are made to be opened by floating the switches 250a to 250n so that the signals output from the opposite source printed circuit board are applied to the data lines.

FIG. 5 is a block diagram illustrating an abnormal operation of a logic voltage according to another embodiment of the present invention. Referring to FIG. In the source driver integrated circuit, the area using low voltage such as VCC and the area using high voltage such as SVDD are shown, and the output buffer is controlled by monitoring the error of low voltage VCC in the area using high voltage. 5, the low voltage region 501 of the source driver integrated circuit 500 includes a control unit 510, a shift register 520, a latch 530, and a converter 540. The latch 530 may comprise a first latch and a second latch. The high voltage region includes an analog output buffer 560, a power sensing unit 570, and a gamma buffer 580. A digital analog converter (DAC) 550 is located between the low voltage region 501 and the high voltage region 502.

The control unit 510 of the low voltage region 501 is supplied with the logic voltage VCC for control. The control unit 510 controls the shift register 520. When the video data are input to the converter 540 as serial data, they are stored in the latch 530 and output to the analog output buffer 560 through the DAC 550 . More specifically, the converter 540 receives video data (digital data) from a timing controller (not shown). The first latch of the latch 530 receives video data in parallel from the converter 540 under the control of the control unit 510 and the shift register 520. [

At this time, all of the video data corresponding to one gate line GLj selected as the start signal of the horizontal synchronizing signal Hsync is output to the horizontal clock signal CLK by the control of the shift register 520 and the control signal CONTROL_TM applied from the timing controller Signal (Hclock), sequentially sampled and input to the first latch and stored.

The video data corresponding to one selected gate line GLj stored in the first latch is simultaneously transmitted to the second latch and stored by the load control signal. The video data stored in the second latch is converted into an analog voltage (data voltage) in the DAC 550.

At this time, the DAC 550 supplies the video data to the analog voltage (Vdd) based on the reference gamma voltage of the gamma buffer 580 provided from the externally applied reference gamma voltage (SVDD) . The gamma buffer 580 divides the driving circuit power supply voltage SVDD to generate R (Red), G (Green), B (Blue) and W (White) gamma reference voltages and supplies the RGBW gamma reference voltages Rref, Gref, Bref, Wref) to the DAC 550, and the DAC 550 can adjust the gamma reference voltages of the respective RGBW according to the selected gamma data under the control of the timing controller.

The analog output buffer 560 outputs the analog voltage converted by the DAC 550 as an output signal (i.e., a data voltage) so as to have sufficient current driving capability to drive the corresponding data line DLi. At this time, when the analog output buffer 560 outputs the output signal, the power sensing unit 570 is controlled, and the value of the applied VCC and the reference voltage (for example, (VCC) is determined to be a value outside the normal range, the data voltage output of the analog output buffer 560 becomes black data, or the circuit of the analog output buffer 560 is opened so that the floating state To protect the display panel.

3 to 5, an example in which the power sensing unit is configured in the source driver integrated circuit has been described. However, the present invention is not limited thereto, and the power sensing unit may be coupled to the source printed circuit board, and in another embodiment, it may be formed on the control printed circuit board.

In addition, when an error occurs in the application of the VCC in the power sensing unit, the timing controller is notified to the timing controller to instruct the timing controller to restart the data driver again or to restart the corresponding source driver integrated circuit, VCC is normally applied. The data driver, the source driver integrated circuit, the source printed circuit board, and the like are reset and redriven, so that the application error of the VCC can be resolved.

6 is a view illustrating an operation of a single source printed circuit board according to an exemplary embodiment of the present invention. 6 shows a configuration in which a power sensing unit is formed in a source driver integrated circuit according to an embodiment. Five source driver integrated circuits (SDIC # 1 to SDIC # 5) are connected to the source printed circuit board 150, and externally applied VCC and SVDD are applied to each source driver integrated circuit. Since each source driver integrated circuit includes a power sensing unit, it corresponds to an abnormal operation of VCC for each source driver integrated circuit. That is, when the VCC of the SDIC # 4 is not finely applied, as shown in 601a and 601b, the RGBW colors reflecting the normal gamma voltage are output from the SDIC # 1, the SDIC # 2, the SDIC # However, in the case of the SDIC # 4, the black data can be outputted as indicated by 602. When the black data is outputted, the display panel can be turned off or on.

In another embodiment of the present invention, several source driver ICs may be grouped in FIG. 6 to control one power sensing unit. For example, when one power sensing unit is controlled by grouping SDIC # 1 and SDIC # 2, if an error occurs in one of the SDIC # 1 or SDIC # 2, the SDIC # 1 and the SDIC # Black data can be applied to all the data lines.

7 is a view illustrating an operation of a dual source printed circuit board according to another embodiment of the present invention. 5, five source driver ICs (SDIC # 1 to SDIC # 5) are connected to the first source printed circuit board 150a and five source driver ICs SDIC # 6 to SDIC # 10) are connected. 7, each source driver integrated circuit includes a power sensing unit, and thus corresponds to an abnormal operation of VCC for each source driver integrated circuit. That is, when the VCC of the SDIC # 4 is not finely applied, the RGBW colors are output from the SDIC # 1 to the SDIC # 3, and the SDIC # 5 to the SDIC # 10, as shown in 701a and 701b. However, in SDIC # 4, the output buffer is floated and the data voltage of SDIC # 9 is applied to the data line, such as 702. In this case, the data line to which the SDIC # 4 and the SDIC # 9 are connected may be applied with the data voltage only at the Han side, unlike the 701a and 701b to which the data voltage is applied at both sides.

6 and 7, it is possible to prevent malfunction of the IC and the display panel when only VDD is applied in a state in which the VCC is not normally applied. For example, when VDD is applied in a state in which VCC is not normally applied, a screen may flicker and then the power may be turned off or a screen error may occur due to gargage data. In the case of applying the present invention , The black data is output in the case of a single source print circuit configuration, and the data voltage is applied only on one side in the case of a dual source print circuit configuration.

Particularly, in the configuration of the top / bottom dual S-PCB as shown in FIG. 7, in the process of supplying power to the data line (source line), even if VCC of a source driver integrated circuit is abnormal, There is a risk that an operation error may occur due to the absence of a power safety device. In the case of applying a present invention, in the case of a source driver integrated circuit in which VCC is not properly applied, a data voltage is applied only to one of the source driver integrated circuits The problematic source driver integrated circuit becomes a floating state and can prevent the above-described problems.

8 is a view showing a configuration of a source driver circuit device according to an embodiment of the present invention.

The configuration includes a register 810, a digital-analog converter 820, an output buffer 830, and a sensing unit 840. The register 810 receives a logic voltage such as VCC, and stores and outputs video data (Vdata) to be applied to a plurality of data lines. Also, the digital control unit 805 can control the register 810 described above.

The digital-analog converter 820 receives a power supply voltage such as SVDD, and converts the video data output from the register into an analog voltage.

The output buffer 830 applies the analog voltage output from the digital-analog converter 820 to the data line. The power sensing unit 840 switches the output buffer 830 by comparing the logic voltage with the reference voltage Vcheck. The reference voltage, Vcheck, can be applied to any voltage that can be used to determine the presence or absence of a logic voltage as compared to a logic voltage.

9 is a diagram showing the configuration of a source driver circuit device according to another embodiment of the present invention. In addition to the components of FIG. 8 above, it further includes a gamma buffer 850 that provides a reference voltage. More specifically, the power supply voltage applied from the outside can be supplied to the digital-analog converter 820 with N gamma voltages. Alternatively, a power supply voltage applied from the outside may be applied to the gamma buffer 850 with N gamma voltages, and the gamma buffer 850 may provide it to the digital-analog converter 820 again. Meanwhile, the gamma buffer 850 can supply one of the N gamma voltages as a reference voltage to the output buffer 840. The gamma voltage of the lowest gamma voltage or the gamma voltage of the specific level, As shown in FIG. As a result, it is possible to check whether the logic voltage is normal without providing a separate reference voltage, thereby improving the efficiency of the circuit and the power supply configuration.

8 and 9, the power sensing unit 840 can transmit an error signal to the timing controller when it is determined that a problem has occurred in the logic voltage. If the timing controller is found to have a problem with the logic voltage, it can reset the source drive circuitry and correct errors in the logic voltage as a result.

10 is a view showing an embodiment where a power sensing unit is located on a source printed circuit board according to another embodiment of the present invention. A plurality of source driver integrated circuits (SDIC # 1 to SDIC # 5) are arranged on the source printed circuit board 150. [ The power sensing unit 1010 is supplied with a logic voltage VCC and a power supply voltage SVDD. The power supply voltage SVDD may be applied as shown in 1015. Also, a separate reference voltage may be applied to the power sensing unit 1010 outside the power sensing unit 1010, or a specific gamma voltage of the SVDD may be used as a reference voltage. The power sensing unit 1010 compares the applied logic voltage VCC with a reference voltage to control an output buffer constituting each source driver IC (SDIC # 1 to SDIC # 5) when the logic voltage is out of the normal range . For example, black data may be output in the output buffer, or the output buffer may be in a floating state.

The power sensing unit 1010 of FIG. 10 may monitor the logic voltages applied to all the source driver integrated circuits (SDIC # 1 to SDIC # 5) coupled to one source printed circuit board 150. Therefore, there is an effect of controlling a plurality of source driver integrated circuits using only one power sensing unit 1010. [

Similarly, when the logic voltage is compared with the reference voltage on the control printed circuit board 170 on which the timing controller is located, if the logic voltage falls within the abnormal range, the black data is applied to the data line in the display panel, It can be floated.

11 is a view showing a configuration in which a power sensing unit is disposed on a control printed circuit board according to another embodiment of the present invention. The control printed circuit board can control the output of VCC and SVDD by comparing the reference voltage with VCC, which is the logic voltage. The control of the output of VCC and SVDD is performed by comparing the logic voltage and the reference voltage as previously described with reference to FIG. 10, and when the logic voltage is in the abnormal range, the black data is applied to the data line in the display panel, .

In the case of applying the present invention, the power detection circuit, which is an embodiment of the power sensing unit, may be embedded in a source driver driving circuit, for example, a source driver integrated circuit, and may be connected to a source printed circuit board or a control printed circuit board And can be disposed inside.

Any one of the gamma voltages, such as the VCC voltage, which is a logic voltage, may be input as a reference voltage through the comparator in the power sensing unit. The gamma voltage of a specific level may be input to the comparator as a reference voltage in consideration of the characteristics and conditions of the panel among various gamma voltages.

An output switching block composed of switches (250a to 250n in FIG. 4) constituting the power sensing unit controls the output buffer stage and controls the output buffer to operate normally according to the relationship between the logic voltage VCC and the power supply voltage SVDD, or The output buffer can be controlled to apply black data, or the output buffer can be controlled to be floated.

In one embodiment of applying the black data in the output switch block, all the output data of the output buffer stage can be controlled such that the ground voltage SVSS or the lowest gamma voltage is applied directly to the data line. This can be applied to the configuration shown in FIG.

Also, in one embodiment for controlling the output buffer to be floated in the output switch block, one end of the data line is opened to float. The present invention can be applied to the configuration shown in FIG.

When an embodiment of the present invention is applied, a logic voltage such as VCC is compared with a specific reference voltage to prevent a data signal from being applied to a data line when an abnormality occurs in a logic voltage, thereby protecting the display panel have. In particular, in order to apply a reference voltage, a low-level gamma voltage generated by a high voltage (SVDD), which is a power supply voltage, is compared to limit the output of video data in case of an abnormal operation due to an abnormal range of VCC, It is possible to prevent the garbage data from being displayed on the display panel.

For example, in the case of a single source printed circuit board, the source driver circuit device according to the present invention or the source printed circuit board or the control printed circuit board according to the present invention may be configured to apply black data to the display panel on the data line controlled by the problematic logic voltage. (Control PCB) or the like. As a result, it is possible to control so as not to cause a pixel bunch due to a wrong logic circuit result.

On the other hand, in the case of a dual source printed circuit board, the output buffer can be opened to control the floating operation. When the normal operation is performed, the conventional VCC is normally applied, and the channel latch voltage can be applied to the latch constituting the register 810 through the digital controller 805. As a result, in a dual source printed circuit board, even if an error occurs in any of the source drive circuit devices on both sides of the source printed circuit board, the opposite source drive circuit device can apply the video data to the data line, Output.

Therefore, when the present invention is applied, the power sensing unit is configured so that a data signal is applied to the display panel only when a logic voltage (for example, 1.8V) such as VCC and a voltage of SVDD (for example, 16V) The display panel can be controlled.

The VCC voltage and the SVDD voltage, which are conventionally supplied to the source driver integrated circuit, are individually applied. In such a conventional configuration, if a voltage malfunctions due to an external / internal environment during driving, garbage data may be displayed on the screen or a burnt due to an IC malfunction may occur. However, when the present invention is applied, It is possible to check whether the VCC is abnormal by comparing the VCC and the SVDD positive voltages so that the stability of the display panel can be improved by eliminating the possibility of outputting or bursting of the garbage data.

In particular, in a display panel using a dual source driver circuit device, when a malfunction occurs in either the top or the bottom, the output buffer of the source driver circuit device in which a malfunction occurs is floated so that a different voltage is not applied to one data line , It is possible to prevent a burst from occurring while allowing only a data voltage generated by a normal source driver circuit device to be outputted on the screen.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: Timing controller
150: source printed circuit board
200, 500: Source driver integrated circuit
310, 570, 1010 and 1110:

Claims (10)

A register which receives a logic voltage and stores and outputs video data to be applied to a plurality of data lines;
A digital-analog converter for receiving the power supply voltage and converting the video data output from the register into an analog voltage;
An output buffer for applying an analog voltage output from the digital-analog converter to a data line; And
And a power sensing unit for comparing the logic voltage with a reference voltage to switch the output buffer.
The method according to claim 1,
And a gamma buffer for providing the power supply voltage with N gamma voltages,
Wherein the reference voltage is any one of the N gamma voltages.
The method according to claim 1,
Wherein the power sensing unit controls the output buffer so that the output buffer outputs black data when it determines that the logic voltage is not a normal state as a result of comparing the logic voltage with the reference voltage.
The method according to claim 1,
Wherein the power sensing unit controls the output buffer to be in a floating state when it is determined that the logic voltage is not a normal state as a result of comparing the logic voltage with the reference voltage.
A plurality of gate lines and a plurality of data lines intersect to form a pixel region, a gate driver for applying a gate signal to the gate line, and a timing controller for controlling a data driver for applying a data signal to the data line In addition,
The data driver
A register which receives a logic voltage and stores and outputs video data to be applied to a plurality of data lines;
A digital-analog converter for receiving the power supply voltage and converting the video data output from the register into an analog voltage;
An output buffer for applying an analog voltage output from the digital-analog converter to a data line; And
And a power sensing unit for comparing the logic voltage with a reference voltage to switch the output buffer.
6. The method of claim 5,
And a gamma buffer for providing the power supply voltage with N gamma voltages,
Wherein the reference voltage is any one of the N gamma voltages.
6. The method of claim 5,
The power sensing unit controls the output buffer to output black data or controls the output buffer to be in a floating state when it is determined that the logic voltage is not a normal state as a result of comparing the logic voltage with the reference voltage Display device.
A plurality of gate lines and a plurality of data lines intersect to form a pixel region, a gate driver for applying a gate signal to the gate line, and a timing controller for controlling a data driver for applying a data signal to the data line In addition,
The data driver
A digital-to-analog converter converting the video data output from the register into an analog voltage, the digital-to-analog converter converting the video data output from the register into an analog voltage, And at least one source driver circuit device including an output buffer for applying the analog voltage output from the digital-analog converter to the data line,
A source printed circuit board for applying a signal between the data driver and the timing controller or a control printed circuit board on which the timing controller is located comprises a power sensing unit for comparing the logic voltage with a reference voltage to switch the output buffer, Device.
9. The method of claim 8,
And a gamma buffer for providing the power supply voltage with N gamma voltages,
Wherein the reference voltage is any one of the N gamma voltages.
9. The method of claim 8,
The power sensing unit controls the output buffer to output black data or controls the output buffer to be in a floating state when it is determined that the logic voltage is not a normal state as a result of comparing the logic voltage with the reference voltage Display device.

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