KR20160087009A - Nitride-based Semiconductor Device with Nanowire Structure and Method Thereof - Google Patents

Abstract

The present invention relates to a method to manufacture a nitride semiconductor device with a nanowire structure, capable of minimizing leak current by implementing a normally-off characteristic. The method comprises the following steps: forming a vertical nanowire on a nitride semiconductor substrate; depositing a first spacer on the nanowire and the substrate, and forming a first photoresist (PR) coating film on the first spacer; etching the first PR coating film to expose a nanowire part; etching the first spacer remaining in a lower part from which the first PR coating film is etched; forming a gate terminal layer on the nanowire and the first spacer; depositing a second spacer on the gate terminal layer and forming a second PR coating film on the second spacer; etching the second PR coating film to expose the nanowire part; sequentially etching the second spacer and the gate terminal layer remaining in a lower part from which the second PR coating film is etched, so as to expose a part of the nanowire on the upper part; forming a source electrode on one side of the upper part of the substrate and forming a drain electrode on one side of the upper part of the nanowire; and forming a gate terminal on one side of the gate terminal layer.

Description

Technical Field [0001] The present invention relates to a nitride semiconductor device having a nanowire structure,

[0001] The present invention relates to a nitride semiconductor device having a nanowire structure and a method of manufacturing the same, and more particularly, to a nitride semiconductor device having a nanowire structure in which vertical nanowires are formed to realize a normally- To a nitride semiconductor device having a nanowire structure capable of minimizing a current and a manufacturing method thereof.

Recently, as the information and communication industry has rapidly developed, demand for personal mobile communication devices, satellite communication devices, broadcasting communication devices, communication relay devices, and military radar devices related to wireless communication technology is gradually expanding. Therefore, there is a demand for a high-speed, high-power electronic device required for a microwave (탆) or millimeter wave (mm) band high-speed information communication system. Further, research and development are required to reduce energy loss of high-power power devices and power devices.

A GaN semiconductor material has a wide energy gap, and has excellent physical properties such as high thermal / chemical stability and high electron saturation rate (~ 3 x 107 cm / sec). Therefore, an optical device, a high frequency or high output electronic device Lt; / RTI > In addition, electronic devices using gallium nitride (GaN) based semiconductor materials have advantages such as high breakdown field (~ 3 x 10 6 V / cm), high current density, stable operation at high temperature, and high thermal conductivity.

Heterostructure field effect transistor (HFET) using hetero-junction structure of aluminum gallium nitride (AlGaN) / gallium nitride (GaN) causes band discontinuity at the bonding interface, . Thus, an HFET can have a high electron mobility. This allows the HFET to be used as a high power device.

Generally, a power device requires a large current density. However, since the HFET has a high electron mobility, current flows even when the threshold voltage is below 0 V and the signal is unfavorable, which consumes power. Such a normally-on type semiconductor device has a disadvantage in that power flow is large due to the current flow, the normal switching operation can not be performed, and the circuit itself becomes complicated.

In order to compensate for this, various techniques have been developed, such as a recess gate structure in which a part of the aluminum gallium nitride (AlGaN) layer corresponding to the gate region is removed, and a technique in which F ions are implanted in the gate region. However, conventional techniques have difficulties in controlling the plasma power uniformly, so that it is difficult to control the threshold voltage of the FET or the plasma performance of the device deteriorates due to plasma damage.

Korean Registered Patent No. 1200274 (Registered on November 6, 2012)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a vertical nanowire that can realize a normally off characteristic, A nitride semiconductor device having a nanowire structure that can be minimized, and a manufacturing method thereof.

A nitride semiconductor device having a nanowire structure capable of realizing a volume inversion phenomenon through a nanowire and capable of realizing a further improved output characteristic even at a lower operating voltage than a conventional nitride semiconductor device, and a method for manufacturing the same.

It is another object of the present invention to provide a nitride semiconductor device having a nanowire structure that can be finer and more compact than a conventional lithography process by finely adjusting nanowire patterns, gates and channel lengths of semiconductor devices using a solution capable of directional etching And a method for manufacturing the same.

According to a preferred embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a nanowire in a vertical direction on a nitride semiconductor substrate; Depositing a first spacer on the nanowire and the substrate, and forming a first PR coating on the first spacer; Etching the first PR coating to expose the nanowire portion; Etching the first spacer remaining on the bottom of the first PR coating layer; Forming a gate terminal layer on the nanowire and the first spacer; Depositing a second spacer on the gate terminal layer and then forming a second PR coating on the second spacer; Etching the second PR coating to expose the nanowire portion; Etching the second spacer and the gate terminal layer remaining in the lower portion by etching the second PR coating to sequentially expose a portion of the nanowire on the upper portion; Forming a source electrode on one side of the substrate and forming a drain electrode on one side of the nanowire; And forming a gate electrode on one side of the gate terminal layer. The present invention also provides a method for manufacturing a nitride semiconductor device having a nanowire structure.

Here, the nitride semiconductor material may be GaN.

The step of forming the nanowires in the vertical direction on the nitride semiconductor substrate may include depositing an insulating film on the substrate and etching both sides except for the center to expose a portion of the nitride semiconductor material from the lower side to the outside Forming a base wire; Etching the base wire to reduce its width; And removing the insulating film.

At this time, the step of reducing the width by etching the base wire may include wet etching the base wire in the horizontal direction, and the wet etching may be performed by directional etching using TMAH (TetraMethyl Ammonium Hydroxide) or KOH solution It is possible.

In addition, the insulating film is a material having etch characteristics different from those of the nitride semiconductor material. For example, any one of SiO ₂ , SiN, and HfO may be used.

The step of forming a gate terminal layer on the nanowire and the first spacer may include depositing a gate dielectric layer on the nanowire and the first spacer; And depositing a gate metal layer on the gate dielectric layer.

Forming a gate terminal layer on the nanowire and the first spacer and forming a source electrode on one side of the substrate and forming a drain electrode on an upper side of the nanowire, It is preferable that the step of removing all the PR coating film precedes each.

According to another aspect of the present invention, there is provided a nitride semiconductor light emitting device comprising: a substrate made of a nitride semiconductor material and having a nanowire in a vertical direction on an upper side; A gate terminal layer formed on one side of the substrate to surround the nanowire; Spacers formed on upper and lower sides of the gate terminal layer to surround the nanowires, respectively; A source electrode formed on an upper side of the substrate; And a drain electrode formed on an upper side of the nanowire.

Here, the gate terminal layer may include a gate dielectric layer formed to surround the nanowire, and a gate metal layer formed to surround the gate dielectric layer. Preferably, the plurality of nanowires are spaced apart from each other on the substrate Do. At this time, the gate metal layer may be formed to surround all the nanowires formed with the gate dielectric layer.

The nitride semiconductor device having a nanowire structure according to the present invention has excellent device characteristics and can realize a normally off characteristic in a nitride semiconductor, so that it can be applied to a high-frequency device and a high-output power device.

It can reduce the power consumption by minimizing the leakage current by inducing positive threshold voltage and minimizing the leakage current. It is also possible to fabricate a pattern of less than 100nm, which is difficult to be realized by E-beam lithography equipment, It is possible to greatly reduce the processing cost, and it is possible to obtain a higher integration density than the horizontal element in comparison with the same area.

1 is a structural view illustrating a nitride semiconductor device having a nanowire structure according to an embodiment of the present invention.
2 is a plan view as seen from above in Fig.
3A to 3M sequentially illustrate a method of manufacturing a nitride semiconductor device of a nanowire structure according to an embodiment of the present invention.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas. Also, the purpose or effect of the present invention should not be construed as limiting the scope of the present invention, since it does not mean that a specific embodiment should include all or only such effect.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used predefined terms should be interpreted to be consistent with the meanings in the context of the related art and can not be interpreted as having ideal or overly formal meaning unless explicitly defined in the present invention.

FIG. 1 is a structural view showing a nitride semiconductor device having a nanowire structure according to an embodiment of the present invention, and FIG. 2 is a plan view as seen from above in FIG.

1 and 2, a nitride semiconductor device having a nanowire structure according to an embodiment of the present invention includes a substrate having a nitride semiconductor material and a nanowire W formed in a vertical direction on one side of the substrate, A gate terminal layer 20 formed to surround the nanowire W at one side of the upper side of the substrate 10 and a gate terminal layer 20 surrounding the nanowire W at upper and lower sides of the gate terminal layer 20, Spacers 11 and 13, a source electrode S formed on one side of the substrate 10 and a drain electrode D formed on one side of the nanowire W.

The nitride semiconductor material constituting the substrate 10 may be gallium nitride (GaN). As described above, since the gallium nitride (GaN) semiconductor material has a wide energy gap, high thermal / chemical stability, and high electron saturation rate (~ 3 x 107 cm / sec) Can be applied to high-frequency or high-output electronic devices, and has advantages such as high breakdown field (~ 3 x 10 6 V / cm), high current density, stable operation at high temperature, high thermal conductivity.

The nanowire W is a cylindrical structure extending from the substrate 10 in the vertical direction by the nitride semiconductor material, and it is preferable that the nanowire W is formed in a very fine size with a diameter of about 50 to 100 nm. A plurality of such nanowires W may be spaced apart from each other on the substrate 10. A source electrode S is formed on one side of the substrate 10 on which the nanowires W are not formed.

The gate terminal layer 20 may include a gate dielectric layer 21 formed to surround the nanowire W and a gate metal layer 22 formed to surround the gate dielectric layer 21. [ When a plurality of nanowires W are formed, it is preferable that the gate metal layer 22 is formed so as to surround all the nanowires W formed with the gate dielectric layer 21. In this structure, one end of the gate metal layer 22 is connected to the gate electrode G. [

The material constituting the spacers 11 and 13 may be SiO ₂ and is formed so as to surround each nanowire W on the upper or lower side of the gate terminal layer 20. At this time, a drain electrode D is formed on one side of the upper portion of the spacer 13 located on the gate terminal layer 20 and connected to one side of the upper part of the nanowire W. It is preferable that the drain electrode D is formed in a bar shape along the arrangement direction of the nanowires W so that a plurality of nanowires W can be connected.

In the nitride semiconductor according to the present invention, since the gate metal layer 22 is formed so as to surround the nanowire W operating as an electron channel, unlike a general nitride semiconductor device in which the channel has a two-dimensional plane, The number of electrons available for operation of the device is relatively increased. On the other hand, the electron channel is isolated from the bottom of the substrate 10 through the spacers 11 and 13, thereby greatly reducing the leakage current.

In addition, since each nanowire W is formed in a nano-size and the cross-section of the fin becomes smaller, when the input voltage is not present, the nanowire W is always kept in the depletion state, Off characteristics can be realized and a plurality of nanowires W can be formed in parallel to offset a decrease in channel width due to a small cross section. In addition, by inducing a volume inversion phenomenon due to the structural characteristics of the nanowire (W), improved output characteristics can be realized even at a lower operating voltage than the conventional nitride semiconductor device.

3A to 3M sequentially illustrate a method of manufacturing a nitride semiconductor device of a nanowire structure according to an embodiment of the present invention.

Referring to FIG. 3, a method of fabricating a nitride semiconductor device having a nanowire structure according to an embodiment of the present invention includes forming a nanowire W in a vertical direction on a nitride semiconductor substrate 10, A step S2 of forming a first PR coating film 12 on the first spacer 11 after depositing the first spacer 11 on the substrate W and the wire W, (S4) of etching the first spacer 11 remaining in the lower portion of the first PR coating film 12 by etching the first PR coating layer 12 to expose the nanowire W Forming a gate terminal layer 20 on the second spacer 13 and the first spacer 11 and depositing a second spacer 13 on the gate terminal layer 20, A step S6 of forming a second PR coating film 14, a step S7 of etching the second PR coating film 14 to expose the nanowire W, a step of etching the second PR coating film 14 Remain on Etching the second spacer 13 and the gate terminal layer 20 in order to expose a portion of the nanowire W in the upper portion S8; forming a source electrode S on one side of the substrate 10 A step S9 of forming a drain electrode D on one side of the nanowire W and a step S10 forming a gate electrode G on one side of the gate terminal layer 20.

First, at step S1, a nanowire W in a vertical direction is formed on the nitride semiconductor substrate 10 as shown in FIGS. 3A to 3C.

3A, the insulating film M is deposited on the substrate 10, and then both sides except for the central portion are etched to expose a portion of the nitride semiconductor material, A step S1-2 for reducing the width by etching the base wire W0 as shown in FIG. 3B and a step S1 for removing the insulating film M as shown in FIG. 3C, -3). Here, the nitride semiconductor material constituting the substrate 10 may be gallium nitride (GaN), and its advantages are as described above.

3A, the insulating film M is deposited on the substrate 10, and both sides except for the center are etched to form a base wire, in which a part of the nitride semiconductor material is exposed from the lower side to the outside, (W0).

As the insulating film M, a material having etching properties different from those of the nitride semiconductor material may be used. For example, a dielectric material such as SiO ₂ , SiN, and HfO may be used. That is, these dielectric materials do not react with gases or solutions used for etching nitride semiconductors. On the contrary, nitride semiconductors have a structure that does not react with gases or solutions used for etching dielectric materials such as SiO ₂ , The nitride semiconductor device of the present invention can be easily manufactured.

When the insulating film M is deposited on the substrate 10 and both sides except for the center are etched, the insulating film M is first dry-etched and then the underlying nitride semiconductor material is dry-etched. Here, when dry etching of the insulating film (M), the CF ₄ gas to the gas of the F series to be used, including, and, when the nitride semiconductor material of the substrate 10 is dry etched, the gas of the Cl series, including BCl ₃ / Cl ₂ mixture Can be used.

After the base wire W0 is formed, the base wire W0 is etched to reduce its width as shown in FIG. 3B. The vertical side of the base wire W0 is wet-etched in the horizontal direction to reduce its width. A TMAH (TetraMethyl Ammonium Hydroxide) solution can be used for such wet etching. The TMAH solution has a property of etching direction of the nitride semiconductor material when etched. That is, the TMAH solution is etched well in the direction orthogonal to the forming direction of the base wire W0, but is not substantially etched in the direction parallel to the forming direction of the base wire W0.

Therefore, when the base wire W0 is etched for about 10 minutes with the TMAH solution of about 5%, the portion of the lower substrate 10 is not etched and only the vertical side of the base wire W0 is etched, As desired. Another etching solution such as a KOH solution may be used in addition to the TMAH solution. In this step, the substrate 10 on which the nanowire W is formed can be prepared as shown in FIG. 3C.

After the nanowires W are formed on the substrate 10 in step S1, the first spacers 11 are deposited on the nanowires W and the substrate 10 as shown in FIG. 3D in step S2, A first PR (Photoresist) coating film is formed on the first spacer 11 as shown in FIG. Here, the material constituting the spacer may be SiO ₂ , and the PR coating layer is preferably PR coated using a polymethyl-methacrylate (PMMA) solution, which is a methacrylic resin. When PR coating is performed on the first spacer 11 with PMMA, a property of spin coating relatively thinly on the upper side of the nanowire W than the upper side of the substrate 10 can be used.

After the first PR coating layer 12 is formed in step S2, the first PR coating layer 12 is etched so that the nanowire W is exposed as shown in FIG. 3F in step S3, The first spacers 11 remaining on the bottom of the coating film 12 are etched. Since the thickness of the PMMA coated on the upper side of the nanowire W is relatively thinner than the side of the upper side of the substrate 10, when PMMA is etched using acetone or the like, The PR coating film 12 is removed.

After the first PR coating layer 12 of the nanowire W is removed and the first spacer 11 remaining in the lower layer is dry etched, only the nanowire W is exposed to the outside You can.

It is preferable to remove all of the remaining first PR coating layer 12 after etching the first spacer 11. In step S5, the nanowire W is deposited on the first spacer 11 A gate terminal layer 20 is formed, and in step S6, a second spacer 13 is deposited on the gate terminal layer 20. Then,

The step S5 of forming the gate terminal layer 20 on the nanowire W and the first spacer 11 more particularly comprises the step of forming the gate dielectric layer 20 on the nanowire W and the first spacer 11, (S5-1) of depositing a gate metal layer 21 and depositing a gate metal layer 22 on the gate dielectric layer 21 (S5-2). The gate dielectric layer 21 may be formed of various materials such as SiO ₂ , Al ₂ O ₃ , TiO ₂ and HfO ₂ and the gate metal layer 22 may be formed of a Ti / Al-based metal compound such as TiN or Al ₃ Ti .

Al ₃ Ti inhibits the oxidation of Ti by blocking the reaction of oxygen with Ti in the air, and TiN consumes nitrogen of GaN and generates a large amount of nitrogen vacancies on the junction of semiconductor and metal. Due to the nitrogen vacancy, a high doping region is formed on the surface, and electrons tunnel to the high concentration surface to form an ohmic contact. The advantage of the Ti / Al-based ohmic metal is that it exhibits excellent electrical characteristics and is excellent in thermal stability, so that the contact resistance does not greatly increase up to 800 ° C.

Here, the material constituting the second spacer 13 may be SiO ₂ similarly to the first spacer 11.

In step S6, a second spacer 13 is deposited on the gate terminal layer 20, and then a second PR coating film 14 is formed on the second spacer 13 as shown in FIG. 3I. In step S7, The second PR coating layer 14 is etched to expose the nanowires W as shown in FIG. 3J. In step S8, the second spacer layer 14 is etched to expose the second spacer layer 14 13 and the gate terminal layer 20 are sequentially etched to expose a part of the nanowire W as shown in FIG. 3L.

Since the method and principle of the steps are the same as those in steps S2 to S4, detailed description will be omitted. However, when the second spacer 13 and the gate terminal layer 20 are sequentially etched, an appropriate etching method should be selected according to the etching characteristics of the respective constituent materials. It is preferable to remove all of the remaining second PR coating film 14 after the etching. If a part of the nanowire W is exposed at the top, it may be stopped in this step. Alternatively, a third spacer may be deposited It is also possible to form the layer by repeating the same method.

3M, a source electrode S is formed on one side of the substrate 10 and a drain electrode D is formed on an upper side of the nanowire W. In step S10, A gate electrode G is formed on one side of the layer 20. If the resistance of the source and the drain is large, the high-frequency characteristics of the device deteriorate and a lot of heat is generated during high-output operation. Thus, the ohmic metal process and the annealing process are performed so as to reduce the contact resistance. Finally, The gate electrode G is formed so as to be connected to the layer 20.

By repeating the above-described method, a plurality of nanowires W can be spaced apart from each other, and a nitride semiconductor device having a nanowire structure in which a spacer, a gate dielectric layer 21, a gate metal layer 22, Can be manufactured. The completed form of the nitride semiconductor device is the same as that described above in FIGS. 1 and 2.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

10: substrate
11: first spacer 12: first PR coating film
13: second spacer 14: second PR coating film
20: gate terminal layer
21: gate dielectric layer 22: gate metal layer
W: nanowire W0: foundation wire
M: insulating film S: source electrode
D: drain electrode G: gate electrode

Claims (13)

Forming a nanowire in a vertical direction on the nitride semiconductor substrate;
Depositing a first spacer on the nanowire and the substrate, and forming a first PR coating on the first spacer;
Etching the first PR coating to expose the nanowire portion;
Etching the first spacer remaining on the bottom of the first PR coating layer;
Forming a gate terminal layer on the nanowire and the first spacer;
Depositing a second spacer on the gate terminal layer and then forming a second PR coating on the second spacer;
Etching the second PR coating to expose the nanowire portion;
Etching the second spacer and the gate terminal layer remaining in the lower portion by etching the second PR coating to sequentially expose a portion of the nanowire on the upper portion;
Forming a source electrode on one side of the substrate and forming a drain electrode on one side of the nanowire; And
And forming a gate electrode on one side of the gate terminal layer.
The method according to claim 1,
Wherein the nitride semiconductor material is GaN.
The method according to claim 1,
The step of forming nanowires in the vertical direction on the nitride semiconductor substrate includes:
Depositing an insulating film on the substrate and etching both sides except for the central part to form a base wire, wherein a part of the nitride semiconductor material is exposed to the outside from the side of the side surface;
Etching the base wire to reduce its width; And
And removing the insulating film. The method of manufacturing a nitride semiconductor device of a nanowire structure according to claim 1,
The method of claim 3,
Wherein the step of reducing the width by etching the base wire comprises wet-etching the base wire in the horizontal direction.
5. The method of claim 4,
Wherein the wet etching is a directional etching using TMAH (TetraMethyl Ammunium Hydroxide) or a KOH solution.
The method of claim 3,
Wherein the insulating film is made of a material having an etching property different from that of the nitride semiconductor material.
The method of claim 3,
Wherein the insulating film is formed of any one of SiO ₂ , SiN, and HfO.
The method according to claim 1,
Wherein forming the gate terminal layer on the nanowire and the first spacer comprises:
Depositing a gate dielectric layer on the nanowire and the first spacer; And
And depositing a gate metal layer on the gate dielectric layer.
The method according to claim 1,
Before forming the gate terminal layer on the nanowire and the first spacer,
Forming a source electrode on one side of the substrate and forming a drain electrode on an upper side of the nanowire,
And removing all of the remaining PR coating film.
A substrate made of a nitride semiconductor material and having nanowires formed in a vertical direction on an upper side thereof;
A gate terminal layer formed on one side of the substrate to surround the nanowire;
Spacers formed on upper and lower sides of the gate terminal layer to surround the nanowires, respectively;
A source electrode formed on an upper side of the substrate; And
And a drain electrode formed on one side of the upper portion of the nanowire.
11. The method of claim 10,
Wherein the gate terminal layer comprises a gate dielectric layer formed to surround the nanowire, and a gate metal layer formed to surround the gate dielectric layer.
11. The method of claim 10,
Wherein the substrate has a plurality of nanowires spaced apart from each other.
12. The method of claim 11,
Wherein the gate metal layer is formed so as to surround all the nanowires formed with the gate dielectric layer.

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