KR20160084033A - Light emitting device - Google Patents

Abstract

The present invention provides a light emitting device and a light emitting device package, capable of reducing an energy gap between a conduction band and a valence band in at least one of well layers of an active layer. According to an embodiment, the light emitting device comprises: a first conductive semiconductor layer and a second conductive semiconductor layer; and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer. The active layer comprises a plurality of well layers and a plurality of barrier layers. At least one of the well layers comprises: a first region which is closer to the first conductive semiconductor layer than the second conductive semiconductor layer; a second region adjacent to the first region; and a third region which is closer to the second conductive semiconductor layer than the first region. The second region includes a fourth region which has an indium composition that gradually increases from an indium composition of the first region, and a fifth region which has an indium composition that gradually decreases from the indium composition of the fourth region to an indium composition of the third region. The second region has a thickness thicker than a thickness of the first region or the third region.

Description

[0001] LIGHT EMITTING DEVICE [0002]

An embodiment relates to a light emitting element.

In general, a nitride semiconductor material including a Group V source such as nitrogen (N) and a Group III source such as gallium (Ga), aluminum (Al), or indium (In) has excellent thermal stability, Has a band structure and is widely used as a nitride semiconductor device, for example, a nitride semiconductor light emitting device in an ultraviolet region and a material for a solar cell.

The nitride-based material has a wide energy band gap of 0.7 eV to 6.2 eV, and is thus widely used as a material for a solar cell device due to its characteristics matching the solar spectrum region. In particular, ultraviolet light emitting devices have been utilized in various industrial fields such as a curing apparatus, a medical analyzer, a therapeutic apparatus, and a sterilizing, water purification, and purification system.

The embodiment provides a light emitting device having a well structure of a new active layer.

Embodiments provide a light emitting device capable of reducing an energy gap between a conduction band and a valence band in at least one well layer among well layers of an active layer.

Embodiments provide a light emitting device, a light emitting device package, and an illumination system having an active layer with improved internal light emitting efficiency.

A light emitting device according to an embodiment includes a first conductive semiconductor layer and a second conductive semiconductor layer; And an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the active layer includes a plurality of well layers and a plurality of barrier layers,

At least one of the plurality of well layers includes a first region closer to the first conductivity type semiconductor layer than the second conductivity type semiconductor layer; A second region adjacent to the first region; And a third region closer to the second conductivity type semiconductor layer than the first region, the second region comprising a fourth region having an indium composition gradually increasing from the indium composition of the first region, And a fifth region that gradually decreases from the indium composition to the indium composition of the third region, and the second region includes a thickness greater than the thickness of the first or third region.

A light emitting device according to an embodiment includes a first conductive semiconductor layer and a second conductive semiconductor layer; And an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the active layer includes a plurality of well layers and a plurality of barrier layers, A first region closer to the first conductivity type semiconductor layer than a second conductivity type semiconductor layer; A third region closer to the second conductivity type semiconductor layer than the first region; And a second region disposed between the first region and the second region, wherein the second region has a narrower bandgap than the bandgap of the first and third regions, and the indium composition of the second region is The second region gradually increases from the indium composition of the first and third regions, and the second region includes a thickness greater than the thickness of the first or third region.

According to the light emitting device, the light emitting device package, and the illumination system according to the embodiment, the radiative recombination rate can be improved to increase the internal light emitting efficiency.

The embodiment can improve the bending phenomenon of the band gap in the active layer.

Embodiments can improve the piezoelectric field in the active layer.

1 is a cross-sectional view of a light emitting device according to an embodiment.
2 is an example of energy bands of the active layer in the light emitting device of FIG.
FIG. 3 is a view for explaining a well layer of the active layer of FIG. 2. FIG.
FIG. 4 is a view for explaining a wave function according to a band gap in the well layer of the active layer of FIG. 2. FIG.
5 is another example of the active layer of Fig.
6 is an example in which electrodes are arranged in the light emitting device of Fig.
7 is another example in which electrodes are arranged in the light emitting element of Fig.
8 is a graph showing the internal quantum efficiency according to the indium composition of the second region of the well layer of the active layer of FIG.
FIG. 9 is a diagram showing the internal quantum efficiency according to the thicknesses of the first and third regions in the well layer of the active layer of FIG. 4; FIG.
10 is a view showing the internal quantum efficiency according to the thickness of the second region in the well layer of the active layer of FIG.
FIG. 11 is a diagram comparing light intensities in a light emitting device according to Comparative Examples and Examples.
12 is a graph showing voltage characteristics of a light emitting device according to Comparative Examples and Examples.
13 is a graph comparing light intensities according to wavelengths according to Comparative Examples and Examples.
FIG. 14 is a diagram showing a histogram of luminous intensity data and density according to Comparative Examples and Examples.
15 is a cross-sectional view of a light emitting device package having a light emitting device according to an embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

In the description of the embodiments, each layer (film), region, pattern or structure is referred to as being "on" or "under" the substrate, each layer (film) Quot; on "and" under "are intended to include both" directly "or" indirectly " do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

(Example)

FIG. 1 is a cross-sectional view of a light emitting device according to an embodiment, FIG. 2 is an example of an energy band of an active layer in the light emitting device of FIG. 1, FIG. 3 is a view for explaining a well layer of the active layer of FIG. Is a diagram for explaining a wave function according to a band gap in a well layer of the active layer of FIG.

1 to 4, the light emitting device according to the embodiment includes a first conductive semiconductor layer 41, a well layer 62 and a barrier layer (not shown) disposed on the first conductive semiconductor layer 41, An electron blocking layer 71 disposed on the active layer 51 and a second conductivity type semiconductor layer 75 disposed on the electron blocking layer 71 have.

The light emitting device may include at least one or both of a low conduction layer 33, a buffer layer 31, and a substrate 21 under the first conductive type semiconductor layer 41.

The light emitting device includes a first clad layer 43 between the first conductive semiconductor layer 41 and the active layer 51 and a second clad layer 43 between the active layer 51 and the second conductive semiconductor layer 75. [ (73). ≪ / RTI >

The substrate 21 may be, for example, a translucent, conductive substrate or an insulating substrate. For example, the substrate 21 may include at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ . A plurality of protrusions (not shown) may be formed on the upper surface and / or the lower surface of the substrate 21, and each of the plurality of protrusions may include at least one of a hemispherical shape, a polygonal shape, and an elliptical shape, Or in the form of a matrix. The protrusions can improve the light extraction efficiency.

A plurality of compound semiconductor layers may be disposed on the substrate 21. The plurality of compound semiconductor layers may be grown using an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD) A dual-type thermal evaporator, sputtering, metal organic chemical vapor deposition (MOCVD), or the like. However, the present invention is not limited thereto.

A buffer layer 31 may be formed between the substrate 21 and the first conductivity type semiconductor layer 41. The buffer layer 31 may be formed of at least one layer using Group II to VI compound semiconductors. The buffer layer 31 includes a semiconductor layer using a Group III-V compound semiconductor, for example, In _x Al _y Ga _1-xy N (0 = x = 1, 0 = y = 1, 0 = x + y = 1). ≪ / RTI > The buffer layer 31 includes at least one of materials such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and ZnO.

The buffer layer 31 may include a superlattice structure in which different semiconductor layers are alternately arranged. The buffer layer 31 may be formed to reduce the difference in lattice constant between the substrate 21 and the nitride-based semiconductor layer, and may be defined as a defect control layer. The lattice constant of the buffer layer 31 may have a value between lattice constants between the substrate 21 and the nitride-based semiconductor layer. The buffer layer 31 may not be formed, but the present invention is not limited thereto.

The low conductivity layer 33 may be disposed between the buffer layer 31 and the first conductive semiconductor layer 41. The low conductivity layer 33 is an undoped semiconductor layer and has lower electrical conductivity than the first conductivity type semiconductor layer 41.

The low conduction layer 33 may be formed of a Group II-VI compound semiconductor, for example, a Group III-V compound semiconductor. Even if the undoped semiconductor layer is intentionally doped with a conductive dopant, . The undoped semiconductor layer may not be formed, but the present invention is not limited thereto. The low conduction layer 33 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The low conductivity layer 33 may not be formed, but the present invention is not limited thereto.

The first conductive semiconductor layer 41 may be disposed between the active layer 51 and at least one of the substrate 21, the buffer layer 31, and the conductive layer 33. The first conductive semiconductor layer 41 may be formed of at least one of Group III-V and Group II-VI compound semiconductors doped with a first conductivity type dopant.

The first conductivity type semiconductor layer 41 is a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0 = x = 1, 0 = y = 1, 0 = x + y = 1) . The first conductive semiconductor layer 41 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The first conductive semiconductor layer 41 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se, or Te.

The first conductivity type semiconductor layer 41 may be a single layer or a multilayer structure. The first conductive semiconductor layer 41 may have a superlattice structure in which at least two different layers are alternately arranged. The first conductive semiconductor layer 41 may be an electrode contact layer.

The first clad layer 43 may be disposed between the first conductive semiconductor layer 41 and the active layer 51. The first clad layer 43 may be in contact with the first conductive semiconductor layer 41 and the active layer 51. The first cladding layer 43 may include an AlGaN-based semiconductor. The first cladding layer 43 may be an n-type semiconductor layer having a dopant of the first conductivity type, for example, an n-type dopant. The first cladding layer 43 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, May be an n-type semiconductor layer doped with an n-type dopant. The first clad layer 43 may not be formed.

The active layer 51 may be formed of at least one of a single well, a single quantum well, a multi-well, a multi quantum well (MQW), a quantum-wire structure, or a quantum dot structure .

The active layer 51 may be formed by combining electrons (or holes) injected through the first conductive type semiconductor layer 41 and holes (or electrons) injected through the second conductive type semiconductor layer 75, And is a layer that emits light due to a band gap difference of an energy band according to a material of the active layer 51. [

The active layer 51 may be formed of a compound semiconductor. The active layer 51 may be formed of at least one of Group II-VI and Group III-V compound semiconductors.

When the active layer 51 is implemented as a multi-well structure, the active layer 51 includes a plurality of well layers 62 and a plurality of barrier layers 52. In the active layer 51, a well layer 62 and a barrier layer 52 are alternately arranged. The pair of the well layer 62 and the barrier layer 52 may be formed in 2 to 30 cycles.

InGaN / AlGaN, InGaN / AlGaN, InGaN / InGaN, AlGaAs / GaAs, InGaAs / GaAs, InGaP / GaN , AlInGaP / InGaP, or a pair of InP / GaAs.

A layer closest to the first conductivity type semiconductor layer 41 among the well layer 62 and the barrier layer 52 of the active layer 51 may be a well layer 62, The layer closest to the barrier layer 75 may be the barrier layer 52. The well layers 62 may be disposed between adjacent barrier layers 52 in the active layer 51, respectively.

The well layer 62 of the active layer 51 according to the embodiment may be implemented by an InGaN semiconductor, for example, an InGaN or InAlGaN semiconductor. The barrier layer 52 may be formed of GaN-based semiconductor, for example, InGaN, AlGaN, or InAlGaN semiconductor. The active layer 51 may emit blue or ultraviolet light. The indium composition of the well layer 62 may be higher than the indium composition of the barrier layer 52. The barrier layer 52 has a higher aluminum composition than the aluminum layer of the well layer 62.

The well layer 62 may be arranged in a semiconductor material having a composition formula of, for example, In _x Al _y Ga _1-xy N (0 <x? 1, 0? Y? 1, 0? _X + y < . The barrier layer 52 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? _X? 1, 0? Y? 1, 0? _X + y < .

The indium composition of the well layer 62 may range from 4% to 20%, for example from 6% to 17%. The barrier layer 52 may have an indium content of 1% or less, for example, 0.5% or less. The barrier layer 52 may not have an indium composition.

As shown in FIG. 2, at least one, more than two, or all of the plurality of well layers 62 may include a plurality of regions 63, 64, 65. At least one well layer 62 having the plurality of regions 63, 64 and 65 may be disposed adjacent to the electron blocking layer 71, for example, a barrier layer adjacent to the electron blocking layer 71 52, respectively. At least one well layer 62 having the plurality of regions 63, 64 and 65 may be disposed adjacent to or in direct contact with the first conductive semiconductor layer 41 or the first cladding layer 43 .

The plurality of regions 63, 64, 65 of the well layer 62 include at least three regions, for example, first through third regions 63, 64, 65. Each of the first to third regions 63, 64, 65 may be one layer or a plurality of layers, and may be, for example, at least one layer structure of each of the first and third regions 63, 65, The region 64 may be at least one or more than two layer structures.

In the well layer 62, the first region 63 may be disposed closer to the first conductivity type semiconductor layer 41 than the third region 65 or the second conductivity type semiconductor layer 75, The third region 65 may be disposed closer to the second conductivity type semiconductor layer 75 than the first region 63 or the first conductivity type semiconductor layer 41. The second region 64 is adjacent to the first region 63 and the third region 65 and may be disposed between the first and third regions 63 and 65.

The first region 63 has a composition of indium (In) larger than the indium composition of the barrier layer 52 and smaller than the indium composition of the second region 64. The second region 64 has an indium composition greater than the indium composition of the first and third regions 63 and 65. The third region 65 has a composition that is greater than the indium composition of the barrier layer 52 and less than the indium composition of the second region 64.

The indium composition of the first and third regions 63 and 65 has a composition between the indium composition of the barrier layer 52 and the indium composition of the second region 64. The indium compositions of the first and third regions 63 and 65 may be the same or different. The indium composition of the first and third regions 63 and 65 ranges from 4% to 10%, such as from 5% to 8%, for example, from 6% to 6.5%. In the first and third regions 63 and 65, if the indium composition is out of the above range, the problem of increasing the diffraction of the wave function of carriers such as electrons and holes have. The indium composition of the first and third regions 63 and 65 can be controlled to reduce the separation of the carrier wave function.

The indium composition of the second region 64 gradually increases from the indium composition of the first and third regions 63 and 65. For example, the indium composition of the indium composition of the first and third regions 63 and 65 Can be increased to a composition of more than 2 times. The maximum indium composition of the second region 64 may range from 13% to 20%, e.g., from 15% to 17%. By making the indium composition of the second region 64 at least twice the indium composition of the first and third regions 63 and 65, the well trap efficiency of the implanted carrier can be increased, The brightness can be improved. If the indium composition of the second region 64 is out of the above-mentioned range, the carrier may overflow.

In an embodiment, the well layer 62 includes a first region 63 having an indium composition a, a third region 65 having the indium composition c, a second region 63 having an indium composition c, ) And the indium composition is changed from a to b (where a > b) to the fourth region (4) and the indium composition changes from b to c And a second region 64 having a second region 64 (see FIG. The amount of the indium composition changing from a to b or b to c may be continuously increased or decreased, increased or decreased in a tilted structure, or increased or decreased in a stepped structure. The difference in indium composition between the second region 64 and the first or third regions 63 and 65 may be different from the indium composition difference between the first or third regions 63 and 65 and the barrier layer 52, .

The fourth region 4 may include a first conductivity type semiconductor layer 41 or a first region 63 or a third conductivity type semiconductor layer . The fifth region 5 may be disposed closer to the second conductivity type semiconductor layer 75 or the third region 65 than the first conductivity type semiconductor layer 41 or the first region 62.

As another example, the structure of the well layer 62 is changed to the indium composition, but the composition of aluminum can be changed. For example, when the composition of aluminum in the second region 64 is minimized and the composition of aluminum in the first and third regions 63 and 65 gradually decreases as the composition of the aluminum is further away from the first region 63, 65), it can be increased gradually.

The bandgaps G2, G3 and G4 of the well layer 62 may be narrower than the band gap G1 of the barrier layer 52. [ The band gap G2 of the first region 63 of the well layer 62 is narrower than the band gap G1 of the barrier layer 52 and wider than the band gap G4 of the second region 64 have. The band gap G4 of the second region 64 of the well layer 62 is greater than the band gap G3 and G4 of the first and third regions 63 and 65 and the band gap G3 of the barrier layer 52 (G1). The band gap G3 of the third region 65 of the well layer 62 is wider than the band gap G4 of the second region 64 and narrower than the band gap G1 of the barrier layer 52, May be wider than the band gap (G4) of the second region (64). The band gaps G2 and G3 of the first and third regions 63 and 65 may be a gap between the band gap G1 of the barrier layer 52 and the band gap G4 of the second region 64 . The band gaps G2 and G4 of the first and third regions 63 and 65 may be the same or different from each other, but the present invention is not limited thereto. The difference T1 between the band gaps G2 and G3 of the first region 63 or the third region 65 and the band gap G1 between the barrier layer 52 is greater than the band gap G1 of the first region 63 G2 of the second region 64 or the band gap G3 of the third region 65 and the band gap G4 of the second region 64. [

The band gap energy of the second region 64 of the well layer 62 may be varied with a curvature or a curvature between the first and third regions 63 and 65. The band gap energy of the second region 64 of the well layer 62 can be changed into a nonlinear curve shape. The second region 64 of the well layer 62 has a fourth region 4 in which the indium composition gradually increases from the indium composition of the first region 63 to the maximum value and the indium composition gradually decreases from the maximum value And a fifth area (5). The second region 64 may be implemented as a hemispherical shape such as a two dimensional curvilinear function and the fourth region 4 has a positive value in a two dimensional curve function and the fifth region 5 ) Can have a negative value in a two-dimensional curve function. Since the second region 64 of the well layer 62 is implemented as a two-dimensional curve function, the phenomenon of bending the band gap can be reduced.

The embodiment may approach a distance (e.g., G4) between the minimum energy of the conduction band and the maximum energy of the valence band in the second region 64 of the well layer 62. Accordingly, the wave functions of electrons and holes can be superimposed, thereby improving internal quantum efficiency at high current densities. The structure of the well layer 62 may reduce the piezoelectric field between the well layer 62 and the barrier layer 52.

As shown in FIG. 3, the thickness of each well layer 62 may be thinner than the thickness of each barrier layer 52. The first region 63 of the well layer 62 may have a thickness D1 that is less than the thickness D2 of the second region 64. The third region 65 may have a thickness D3 that is less than the thickness D2 of the second region 64. The thickness D2 of the second region 64 of the well layer 62 may be greater than the thicknesses D1 and D3 of the first or third regions 63 and 65, For example, in the range of 1 nm to 2 nm. The thickness D2 of the second region 64 of the well layer 62 may be greater than or equal to 1.5 times the thickness D1 or D3 of the first or third region 63 or 65, have.

The thicknesses D1 and D3 of the first and third regions 63 and 65 may be in the range of 0.3 nm to 1.5 nm, for example, in the range of 0.5 nm to 1 nm. Current drive or a low current drive according to the thicknesses D1 and D3 of the first and third regions 63 and 65. For example, the first and third regions 63 and 65 may be formed to have a thickness of 0.5 nm for the high current mode, And can be formed close to a thickness of 1 nm for the current mode. The thicknesses D1 and D3 of the first and third regions 65 may be equal to or different from each other.

The second region 64 of the well layer 62 has a thickness D4 of the fourth region 4 closer to the first conductivity type semiconductor layer 41 than the second conductivity type semiconductor layer 75 May be thicker than the thickness (D5) of the fifth region (5) adjacent to the second conductivity type semiconductor layer (75). The boundary between the fourth region 4 and the fifth region 5 can be changed by the difference in lattice constant between the well layer / barrier layer 52/62 during growth of the active layer 51. [ A boundary point between the fourth region 4 and the fifth region 5 may be located at the center between the first and third regions 63 and 65, 63, or closer to the third region 65 than the first region 63. As shown in FIG. The difference between the boundary of the fourth region 4 and the fifth region 5 may be a band offset between the well layer 62 and the barrier layer 52.

Since the thickness D2 of the second region 64 of the well layer 62 is thicker than the thicknesses D1 and D3 of the first or third regions 63 and 65, The volume that can hold the carrier within the well structure of the two regions 64 can increase. Also, since the second region 64 of the well layer 62 has a two-dimensional curved function, it is possible to prevent the capacity of the carrier contributing to radiative recombination from becoming small. The second region 64 of the well layer 62 may be implemented with a delta sine symmetric quantum well structure or a delta sine asymmetric well structure, Can be improved. Accordingly, the internal quantum efficiency of the active layer 51 can be improved.

As shown in FIG. 4, the second region 64 of the well layer 62 is arranged such that the center portion or the boundary portion between the fourth and fifth regions 5 is located below the electron Fermi level F1, And is disposed above the Fermi level (F2). This may approach the distance between the minimum energy of the conduction band and the maximum energy of the valence band (e.g., G4) in the well layer 62. Thus, the overflow of carriers in the well layer 62 can be prevented and the trapping efficiency of the carrier can be increased.

The overlap ratio of the electron wave functions R1 and the hole wave functions R2 in the region A1 of the well layer 62 is increased so that the radiative recombination ratio recombination rate, the internal quantum efficiency at high current density can be improved. This reduces the piezoelectric field between the well layer 62 and the barrier layer 52 and reduces the phenomenon that the wave functions R1 and R2 of the electrons and electrons are separated in opposite directions to prevent the internal quantum efficiency from decreasing can do.

As shown in FIG. 1, the second cladding layer 73 is disposed on the electron blocking layer 71. The second clad layer 73 is disposed between the electron blocking layer 71 and the second conductive semiconductor layer 75.

The second cladding layer 73 may include an AlGaN-based semiconductor. The second cladding layer 73 may be a p-type semiconductor layer having a second conductivity type dopant, for example, a p-type dopant. The second cladding layer 73 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, Type dopant such as Ba.

The second conductive semiconductor layer 75 may be disposed on the second clad layer 73. The second conductivity type semiconductor layer 75 is a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + . The second conductive semiconductor layer 75 may include at least one of, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, May be a doped p-type semiconductor layer.

The second conductivity type semiconductor layer 75 may be a single layer or a multilayer. The second conductive semiconductor layer 75 may have a superlattice structure in which at least two different layers are alternately arranged. The second conductive semiconductor layer 75 may be an electrode contact layer. The second conductivity type semiconductor layer 75 and the second clad layer 73 may be disposed of an AlGaN-based semiconductor to prevent absorption of ultraviolet wavelengths.

The light emitting structure may include the first conductivity type semiconductor layer 41 to the second conductivity type semiconductor layer 75. As another example, in the light emitting structure, the first conductivity type semiconductor layer 41 and the first cladding layer 43 are a p-type semiconductor layer, the second cladding layer 73 and the second conductivity type semiconductor layer 75 are n Type semiconductor layer. Such a light emitting structure can be implemented by any one of an np junction structure, a pn junction structure, an npn junction structure, and a pnp junction structure.

5 is another example of the well layer 62 of the active layer according to the embodiment. In describing the active layer in Fig. 5, the same structure will be described with reference to the description of the active layer described above.

Referring to FIG. 5, the well layer 62 of the active layer includes first to third regions 63, 64, 65. The second region 64 may be disposed between the first and third regions 63 and 65. The second region 64 includes a form of a two-dimensional function curve. The second region 64 may have a fourth region 4 and a second region 64. The second region 64 may have a stepped structure ranging from the indium composition of the first region 63 to the maximum of the indium composition of the second region 64, 64) from the maximum value of the indium composition to the indium composition of the third region (65). The step structure of the fourth and fifth regions 5 may be reduced or increased to a step structure without continuously decreasing or increasing the indium composition.

6 shows an example in which electrodes are arranged in the light emitting element of Fig. In describing FIG. 6, the same parts as those described above will be described with reference to the description of the embodiments disclosed above.

Referring to FIG. 6, the light emitting device 101 includes a first electrode 91 and a second electrode 95. The first electrode 91 may be electrically connected to the first conductive semiconductor layer 41 and the second electrode 95 may be electrically connected to the second conductive semiconductor layer 75. The first electrode 91 may be disposed on the first conductive semiconductor layer 41 and the second electrode 95 may be disposed on the second conductive semiconductor layer 75.

The first electrode 91 and the second electrode 95 may have a current diffusion pattern having an arm structure or a finger structure. The first electrode 91 and the second electrode 95 may be made of a metal having properties of an ohmic contact, an adhesive layer, and a bonding layer, and may not be transparent. The first electrode 93 and the second electrode 95 are formed of a material selected from the group consisting of Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Alloys.

An electrode layer 93 may be disposed between the second electrode 95 and the second conductive semiconductor layer 75. The electrode layer 93 may be a light transmissive material that transmits light of 70% And may be formed of a metal or a metal oxide, for example. The electrode layer 93 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide ), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), ZnO, IrOx, RuOx, NiO, Al, Ag, Pd, Rh, Pt and Ir.

An insulating layer 81 may be disposed on the electrode layer 93. The insulating layer 81 may be disposed on the upper surface of the electrode layer 93 and the side surface of the semiconductor layer and may be selectively in contact with the first and second electrodes 91 and 95. The insulating layer 81 includes an insulating material or an insulating resin formed of at least one of oxides, nitrides, fluorides, and sulfides having at least one of Al, Cr, Si, Ti, Zn and Zr. The insulating layer 81 may be selectively formed of, for example, SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , or TiO ₂ . The insulating layer 81 may be formed as a single layer or a multilayer, but is not limited thereto.

Embodiments of the present invention provide a light emitting device capable of reducing the diffraction of the wave function of electrons and holes in the active layer 51 to improve the trapping efficiency of the carrier to thereby increase the internal luminous efficiency. According to the embodiment, it is possible to increase the overlap ratio between the wave function of electrons and the wave function of electrons in the well layer of the active layer, thereby improving the radiative recombination rate and increasing the internal luminous efficiency .

7 is a view showing an example of a vertical light emitting device using the light emitting device of FIG. In describing Fig. 7, the same portions as those described above will be described with reference to the description of the embodiments disclosed above.

8, the light emitting device 102 includes a first electrode 91 and a plurality of conductive layers 96, 97, and 98 under the second conductive type semiconductor layer 75 on the first conductive type semiconductor layer 41. Referring to FIG. , 99).

The second electrode is disposed under the second conductive semiconductor layer 75 and includes a contact layer 96, a reflective layer 97, a bonding layer 98, and a support member 99. The contact layer 96 is in contact with the semiconductor layer, for example, the second conductivity type semiconductor layer 75. The contact layer 96 may be made of a low conductive material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, or Ni or Ag. A reflective layer 97 is disposed under the contact layer 96 and the reflective layer 97 is formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, And at least one layer made of a material selected from the group. The reflective layer 97 may be in contact with the second conductive semiconductor layer 75, but the present invention is not limited thereto.

A bonding layer 98 is disposed under the reflective layer 97 and the bonding layer 98 may be used as a barrier metal or a bonding metal. The material may be, for example, Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, and Ta and an optional alloy.

A channel layer 83 and a current blocking layer 85 are disposed between the second conductive type semiconductor layer 75 and the second electrode.

The channel layer 83 is formed along the bottom edge of the second conductive semiconductor layer 75, and may be formed in a ring shape, a loop shape, or a frame shape. The channel layer 83 comprises a transparent conductive material or an insulating material, such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, SiO _2, SiO _x, SiO _x N _y, Si ₃ N _4, Al ₂ O ₃ , and TiO ₂ . The inner side of the channel layer 163 is disposed below the second conductivity type semiconductor layer 75 and the outer side of the channel layer 163 is located further outward than the side surface of the light emitting structure.

The current blocking layer 85 may be disposed between the second conductive semiconductor layer 75 and the contact layer 96 or the reflective layer 97. The current blocking layer 85 may include at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ and TiO ₂ . As another example, the current blocking layer 85 may also be formed of a metal for Schottky contact.

The current blocking layer 161 is disposed to correspond to the first electrode 181 disposed on the light emitting structure 150A and the thickness direction of the light emitting structure 150A. The current blocking layer 161 may cut off current supplied from the second electrode 170 and diffuse the current blocking layer 161 to another path. The current blocking layer 85 may be disposed in one or a plurality of regions, and at least a part of the current blocking layer 85 may overlap the first electrode 91 in the vertical direction.

A support member 99 is formed under the bonding layer 98 and the support member 99 may be formed of a conductive material such as copper-copper, gold-gold, nickel (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), and carrier wafers (e.g., Si, Ge, GaAs, ZnO, SiC and the like). As another example, the support member 99 may be embodied as a conductive sheet.

Here, the substrate of FIG. 1 can be removed. The substrate may be removed by a physical method such as laser lift off or chemical method such as wet etching to expose the first conductivity type semiconductor layer 41. The first electrode 91 is formed on the first conductive type semiconductor layer 41 by performing the isolation etching through the direction in which the substrate is removed.

The upper surface of the first conductive semiconductor layer 41 may be formed with a light extraction structure (not shown) such as a roughness. An insulating layer (not shown) may be further disposed on the surface of the semiconductor layer, but the present invention is not limited thereto. Accordingly, the light emitting device 102 having a vertical electrode structure having the first electrode 91 and the supporting member 99 under the light emitting structure can be manufactured.

Embodiments of the present invention provide a light emitting device capable of reducing the diffraction of the wave function of electrons and holes in the active layer 51 to improve the trapping efficiency of the carrier to thereby increase the internal luminous efficiency. According to the embodiment, it is possible to increase the overlap ratio between the wave function of electrons and the wave function of electrons in the well layer of the active layer, thereby improving the radiative recombination rate and increasing the internal luminous efficiency .

8 is a graph showing the internal quantum efficiency according to the indium composition of the second region of the well layer of the active layer of FIG. 4 according to the embodiment.

Referring to FIG. 8, the internal quantum efficiency IQE may be varied depending on the indium composition of the second region 64 of the well layer 62 and the current Id. The first internal quantum efficiency IQE 1 is the maximum indium composition of the second region 64 and the second internal quantum efficiency IQE 2 is the maximum indium composition of the second region 64 15%, and the third internal quantum efficiency IQE 3 is the case where the maximum indium composition of the second region 64 is 17%. Such a light emitting device can be selected by adjusting the maximum indium composition of the second region 64 in accordance with the supply current of the application. For example, when the indium composition is 13% to 15%, it can be applied to a device for low current. It can be applied to a device for high current. Also, if the indium composition of the second region is set, the indium composition of the first and third regions 63 and 65 may be changed to a value less than two times.

FIG. 9 is a graph showing current Id and internal quantum efficiency according to the thicknesses of the first and third regions in the well layer of the active layer of FIG. 4; FIG.

Fig. 9 is a graph comparing the comparative example and the example. In the comparative example, the well layer has a constant indium composition. It can be seen that the internal quantum efficiency (IQE 4, 5, 6) according to the embodiment is higher than the internal quantum efficiency (IQE) of the comparative example regardless of the current (Id) characteristic. The fourth internal quantum efficiency IQE4 is a case where the thickness of the first and third regions 63 and 65 is 0.75 nm, 3 region 63 and 65 is 1 nm, and the sixth internal quantum efficiency IQE6 is a case where the thickness of the first and third regions 63 and 65 is 0.5 nm. An active layer having a well layer adjacent to the first and third regions (63, 65) with a thickness of 0.5 nm can be provided as a light emitting device for high current, and the thickness of the first and fourth regions Layer can be provided as a light emitting device for low current.

10 is a view showing the internal quantum efficiency according to the thickness of the second region in the well layer of the active layer of FIG.

Fig. 9 is a graph comparing the comparative example and the example. In the comparative example, the well layer has a constant indium composition. It can be seen that the internal quantum efficiency (IQE 7, 8) according to the embodiment is higher than the internal quantum efficiency (IQE) of the comparative example. The seventh internal quantum efficiency IQE7 of the embodiment is the case where the thickness of the second region 64 is 2 nm and the eighth internal quantum efficiency IQE8 is the thickness of the second region 64 of 1 nm . When the thickness of the second region 64 is less than 1 nm, the capacity of the carrier is abruptly decreased. Therefore, the thickness of the second region 64 may be 1 nm or more. If the thickness of the second region 64 is increased to 2 nm or more, the thickness of the first and third regions 63 and 65 may be reduced from 1 nm to 0.5 nm.

FIG. 11 is a view showing a box plot comparing the luminosity (let) of the light emitting device according to the comparative example and the embodiment, and FIG. 12 is a box plot showing the voltage characteristics of the light emitting device according to the comparative example and the example. Here, the comparative example is a structure in which the well layer of the active layer has a constant indium composition.

As shown in FIG. 11, the luminous intensity of the embodiment (let: light emitting intensity) is higher than that of the comparative example.

As shown in FIG. 12, the forward voltage (Vf) characteristic of the embodiment is higher than the forward voltage characteristic of the comparative example.

13 is a graph comparing light intensities according to wavelengths according to Comparative Examples and Examples. Here, the comparative example is a structure in which the well layer of the active layer has a constant indium composition.

Referring to FIG. 13, it can be seen that the embodiment has a higher luminous eff (let) in the whole luminous area, for example, in the wavelength range of 444 nm to 458 nm as compared with the comparative example.

FIG. 14 is a diagram showing a histogram of luminous intensity data and density according to Comparative Examples and Examples. Here, the comparative example is a structure in which the well layer of the active layer has a constant indium composition. The histogram of FIG. 14 is obtained by converting the density for the luminous intensity of the comparative example and the example into the normal distribution.

In the histogram shown in FIG. 14, the density for the luminous intensity of the comparative example is about 53, and the density for the luminous intensity according to the embodiment is about 64, which is higher than 10.

&Lt; Light emitting device package &

15 is a view showing a light emitting device package having the light emitting element of FIG.

15, the light emitting device package 200 includes a body 221, a first lead electrode 211 and a second lead electrode 213 at least partially disposed on the body 221, And the light emitting element 101 is electrically connected to the first lead electrode 211 and the second lead electrode 213 on the first and second lead electrodes 221 and 221.

The body 221 may be formed of a silicon material, a synthetic resin material, or a metal material. The body 221 may be formed as a cavity 225 in the top view and an inclined surface with respect to the bottom of the cavity around the cavity 225 as viewed from above.

The first lead electrode 211 and the second lead electrode 213 may be electrically separated from each other and penetrate the body 221. That is, the first lead electrode 211 and the second lead electrode 213 may be partially disposed inside the cavity 225 and the other portion may be disposed outside the body 221.

The first lead electrode 211 and the second lead electrode 213 may supply power to the light emitting device 101 and increase the light efficiency by reflecting the light generated from the light emitting device 101, And may also function to discharge heat generated in the light emitting device 101 to the outside. The first and second lead electrodes 211 and 213 may be formed of a metal material and are separated by a gap portion 223.

The light emitting device 101 may be mounted on the body 221 or on the first lead electrode 211 and / or the second lead electrode 213.

The light emitting device 101 may be connected to the first lead electrode 211 by a first wire 242 and may be connected to a second lead electrode 213 by a second wire 243.

A molding member 231 or a transparent window may be disposed on the cavity 225. The molding member 231 may include a resin material such as silicone or epoxy, and may include a fluorescent material therein. The phosphor may convert the wavelength of some light emitted from the light emitting element 101. The transparent window may include a glass material and may be spaced apart from the light emitting device 101.

An optical lens may be further disposed on the cavity 225, but the present invention is not limited thereto.

A light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, and the like, which are optical members, are disposed on a path of light emitted from the light emitting device or the light emitting device package . The light emitting device or the light emitting device package, the substrate, and the optical member may function as a backlight unit or function as a lighting unit. For example, the lighting system may include a backlight unit, a lighting unit, a pointing device, a lamp, .

According to the light emitting device, the light emitting device package, and the illumination system according to the embodiment, the radiative recombination rate can be improved to increase the internal light emitting efficiency.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

21: substrate 31: buffer layer
33: Low conduction layer 41: First conduction type semiconductor layer
43: first cladding layer 51: active layer
52: barrier layer 62: well layer
63: first area 64: second area
65: third region 71: electron blocking structure layer
73: second cladding layer 75: second conductivity type semiconductor layer

Claims (14)

A first conductivity type semiconductor layer and a second conductivity type semiconductor layer; And
And an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer,
Wherein the active layer comprises a plurality of well layers and a plurality of barrier layers,
Wherein at least one of the plurality of well layers comprises:
A first region closer to the first conductivity type semiconductor layer than the second conductivity type semiconductor layer;
A second region adjacent to the first region; And
And a third region closer to the second conductivity type semiconductor layer than the first region,
Wherein the second region includes a fourth region having an indium composition that gradually increases from an indium composition of the first region and a fifth region that gradually decreases from an indium composition of the fourth region to an indium composition of the third region,
Wherein the second region includes a thickness greater than a thickness of the first or third region. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer; And
And an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer,
Wherein the active layer comprises a plurality of well layers and a plurality of barrier layers,
Wherein at least one of the plurality of well layers comprises:
A first region closer to the first conductivity type semiconductor layer than the second conductivity type semiconductor layer;
A third region closer to the second conductivity type semiconductor layer than the first region; And
And a second region disposed between the first region and the second region,
The second region has a narrower bandgap than the bandgap of the first and third regions,
The indium composition of the second region gradually increases from the indium composition of the first and third regions,
Wherein the second region includes a thickness greater than a thickness of the first or third region. 3. The method according to claim 1 or 2,
Wherein each of the plurality of well layers has the first to third regions. 3. The method according to claim 1 or 2,
Wherein at least one well layer having the first to third regions is disposed adjacent to the second conductivity type semiconductor layer than the first conductivity type semiconductor layer. 3. The method according to claim 1 or 2,
Wherein at least one well layer having the first to third regions is disposed adjacent to the first conductivity type semiconductor layer than the second conductivity type semiconductor layer. 3. The method according to claim 1 or 2,
And the indium composition of the second region is at least twice the indium composition of the first or third region. The method according to claim 6,
Wherein the first and third regions have the same indium composition. 3. The method according to claim 1 or 2,
Wherein the thickness of the second region is at least twice the thickness of the first or third region. 9. The method of claim 8,
Wherein the first and third regions have a thickness smaller than the thickness of the second region and the same thickness. 3. The method according to claim 1 or 2,
Wherein the band gap energy of the second region changes into a nonlinear curve shape. The method according to claim 1,
Wherein a thickness of the fourth region is thicker than a thickness of the fifth region. 3. The method according to claim 1 or 2,
Wherein a difference in indium composition between the second region and the first or third region is greater than a difference in indium composition between the first or third region and the barrier layer. 3. The method according to claim 1 or 2,
And the second region gradually changes in indium composition from the first and third regions to a step structure. 3. The method according to claim 1 or 2,
Wherein the first conductive semiconductor layer includes an n-type semiconductor layer,
And the second conductive semiconductor layer includes a p-type semiconductor layer.

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