KR20160080924A - Low voltage differential signaling system and display device with lvds - Google Patents

Abstract

The present invention relates to a low voltage differential signaling system and a display device using the same. According to an embodiment of the present invention, when a receiver of the low voltage differential signaling system is in a normal state, the state data of a device connected to the receiver is provided through a locked signal line. Thereby, the locked state and the state of the device can be checked at the same time. Configuration can be simplified and cost can be reduced because a separate data line is not formed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low voltage differential signaling system and a display device employing the low voltage differential signaling system.

The present invention relates to a low voltage differential signaling system and a display device employing the same.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. In addition, a liquid crystal display device (LCD), a plasma display device (Plasma Display Device) OLED (Organic Light Emitting Display Device), and the like.

As shown in FIG. 5, the display device 100 includes m data lines DL1 through DLm, m natural numbers, and n gate lines GL1 through GLn, A data driver 120 for driving the m data lines DL1 to DLm and a plurality of gate lines GL1 to GLn sequentially driven A timing controller 140 for controlling the data driver 120 and the gate driver 130, and the like.

In this case, the timing controller 140 starts scanning according to the timing implemented in each frame, switches the image data input from the interface to the data signal format used by the data driver 120, and outputs the converted video data (Video Data ), And controls the data driving at a proper time according to the scan.

The data driver 120 stores the input image data in a memory (not shown) under the control of the timing controller 140 and, when a specific gate line is opened, converts the image data Data into an analog data voltage Vdata) and supplies the m data lines DL1, ..., DLm to the m data lines DL1, ..., DLm to drive the m data lines DL1, ..., DLm.

The data driver 120 may include a plurality of data driver ICs (DIC: source driver ICs), and each data driver IC is connected to each data line, The status of the data line can be detected.

When the timing controller 140 supplies the image data to the data driver 120, in each data driver IC of the data driver 120, the data driver IC can supply the image data to the data lines in a normal state . If it is determined that the data driving ICs are in a normal state, the data driving integrated circuit transmits a Locked signal, which is a High signal, to the timing controller 140 through a locked signal line. On the other hand, if it is not a normal state, it transmits a Low signal, Unlocked signal, to the timing controller 140.

When the data driving integrated circuit is in a normal state, image data is provided to each data line. When the image data is provided, the data driving IC controls the driving state of the pixels connected to the respective data lines, State information of the display panel 110 can be transmitted to the timing controller 140 via a separate data line.

Such a conventional display device uses a separate signal line and a data line to transmit the locked information of the data driving integrated circuit and the status information of the display panel 110 to the timing controller 140. Therefore, the use of a plurality of signal lines complicates the configuration of the display device, and increases the cost. Accordingly, it is necessary to search for a method capable of reducing the number of signal lines.

It is an object of the present embodiments to provide a low-voltage differential signaling system in which a configuration is simplified and a cost is reduced by allowing additional data to be transmitted through a locked signal line in a locked state.

The purpose of these embodiments is to provide a low voltage differential signaling system that allows the transmitter to simultaneously determine whether the receiver is in a steady state and the state of the device by transmitting data indicative of the state of the device connected to the receiver to the transmitter, .

It is an object of the embodiments of the present invention to provide data indicating the state of the display panel to the timing controller when the display panel becomes a normal state in which image data can be transmitted to the panel, thereby simplifying the structure and reducing the cost, And a display device capable of grasping the state of the display device.

One embodiment includes a transmitter that synchronizes and transmits data to a reference clock signal; And a receiver for synchronizing the status information on the device to be processed with the recovery clock signal generated based on the reference clock signal to the transmitter through a signal line for transmitting the steady- Voltage differential signal system including a low voltage differential signal system.

Another embodiment includes a timing controller for providing image data displayed on a display panel; And a control unit for receiving response data generated by synchronizing the state information of the display panel with a clock signal to the normal state when the state information of the display panel is received and it is determined that the data can be transmitted and received between the timing controller and the display panel. And a data driver for transmitting the information to the timing controller through a signal line that transmits information on the timing controller.

According to an embodiment of the present invention, when the receiver is in the locked state, information on the state of the device is transmitted to the transmitter through the locked signal line, so that the transmitter can simultaneously determine whether the receiver is in the locked state and the state of the device, And reduce costs.

According to another embodiment of the present invention, a display device employing the present low-voltage differential signaling system transmits state information of a display panel to a timing controller using a locked signal line when the data driving integrated circuit is in a locked state, Can be easily grasped, and the configuration of the display device can be simplified and the cost can be reduced.

1 is a block diagram of a low-voltage differential signaling system according to an embodiment of the present invention.
FIGS. 2 (a) to 2 (h) are diagrams for explaining a signal modulation process of response data generated in the receiver of FIG.
3 is a block diagram of a low-voltage differential signaling system according to another embodiment of the present invention.
4A to 4D are diagrams for explaining the signal modulation process of the response data generated in the receiver of FIG.
5 is a schematic configuration diagram of a display device employing a low-voltage differential signaling system according to the present invention.
6 is a diagram showing a data transmission / reception relationship between the timing controller and the data driver in Fig.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."

1 is a block diagram of a low-voltage differential signaling system according to an embodiment of the present invention.

The low voltage differential signal according to the present invention includes a transmitter 10 for serializing and transmitting data and a receiver 30 for receiving and parallelizing data from the transmitter 10, So that it is not necessary to provide a separate data line for transmitting data from the receiver 30 to the transmitter 10 by allowing the receiver 30 to transmit data from the receiver 30 to the transmitter 10. [

In the low-voltage differential signaling system according to the present embodiment, the signal indicating the locked state or the unlocked state of the receiver 30 and the data indicating the state of the device connected to the receiver 30 are converted into a single signal by PWM (Pulse Width Modulation) Response data, and transmits the response data to the transmitter 10 using the locked signal line.

Generally, a low-voltage differential signaling system is an electrical signaling system in which two different voltages are transmitted by a transmitter (LVDS) in a transmitter (10), and two voltage signals are compared in a receiver (30) to recover data. That is, a low-voltage differential signaling system uses the voltage difference between two wires for information encoding.

Since the transmitter 10 of such a low voltage differential signaling system transmits data of a low voltage differential signal (LVDS) structure through a low voltage differential signal cable (LVDS cable), the amplitude of the signal LVDS is small, It is possible to achieve high-speed data transmission with small electromagnetic noise and power consumption accordingly.

The transmitter 10 according to the present embodiment may include a serial conversion unit 11, a clock generation unit 13, a data transmission unit 15, and a signal analysis unit 17.

The serializer 11 can generate serial data by serializing the parallel data input from a plurality of channels using a high-speed signal. That is, the serializer 11 converts the parallel data formed by 16 bits, 32 bits, etc. into serial data of 1 bit string. The serial converter 11 may be implemented as an FPGA (Field Programmable Gate Array).

The clock generating unit 13 can generate a reference clock signal which is transmitted together when the serial data is transmitted and used for synchronizing the serial data.

The data transmitting unit 15 transmits the serial data converted by the serial converting unit 11 and the reference clock from the clock generating unit 13 to the receiver 30. At this time, the data transmitting unit 15 transmits the serial data converted by the receiver 30 The serial data and the reference clock may be separately transmitted to the receiver 30 in accordance with the type of the clock recovery unit 33. Alternatively, the reference clock signal may be inserted into the serial data, and the receiver 30 ).

One of a PLL (Phase Locked Loop) circuit and a CDR (Clock Data Recovery) circuit may be used as the clock recovery unit 33 on the receiver 30 side. When the PLL circuit is used, a data line for transmitting the serial data and a clock line for transmitting the reference clock signal are separately provided. The data transmitting unit 15 transmits the serial data through the data line, Line. ≪ / RTI > When the CDR circuit is used, an embedded clock line for transmitting the serial data and the reference clock signal at a time is provided, and the data transmitting unit 15 inserts the reference clock signal into the serial data to transmit the serial data and the reference clock signal to the receiver 30 through the embedded clock line. .

The signal analyzer 17 analyzes the data transmitted from the receiver 30 using a predetermined analysis method. Here, the data transmitted from the receiver 30 is response data in which a clock signal is inserted into a status signal indicating the status of a device connected to the receiver 30. [

The receiver 30 generates response data when the receiver 30 is in the locked state and transmits the response data to the transmitter 10. When the receiver 30 is in the unlocked state, the receiver 30 transmits a signal indicating the unlocked state to the transmitter 10 .

Generally, a locked signal includes one of a locked state and an unlocked state, and the locked state indicates a normal state, which means that the receiver 30 is ready to receive data. On the other hand, the Unlocked state indicates an abnormal state and means that the receiver 30 is not ready to receive data. The Locked signal can be marked with a Locked state as a High signal, or 1, and the Unlocked state can be marked with a Low signal, or 0.

The state signal is a signal indicating the state of the device connected to the receiver 30 or the receiver 30. When the receiver 30 is in the locked state, a state signal in which the clock signal is embedded is provided to the transmitter 10. [ The state signal is embedded in the clock signal using the PWM method. Accordingly, the signal analyzer 17 can grasp the state of the device connected to the receiver 30 according to the pulse width of the state signal. A detailed description of the status signal will be given later.

When the receiver 30 is ready to receive data and is in the locked state, the receiver 30 transmits response data in which the clock signal is inserted into the status signal by the transmitter 10. Accordingly, when the response data is received from the receiver 30, the signal analyzer 17 can not only determine that the receiver 30 is in the locked state, but also determine the state of the device connected to the receiver 30 .

The receiver 30 may include a parallel conversion unit 31, a clock recovery unit 33, and a signal generation unit 35.

The parallel conversion unit 31 can convert the serial data converted by the serial conversion unit of the transmitter 10 into parallel data using the reference clock signal. That is, the parallel conversion unit 31 restores 1-bit serial data into 16-bit or 32-bit parallel data.

The clock recovery unit 33 may recover the reference clock signal transmitted from the transmitter 10 and generate a recovery clock signal using the reference clock signal.

The clock recovery unit 33 may be a PLL circuit or a CDR circuit. When the clock recovery unit 33 is configured as a PLL circuit, the serial data and the reference clock signal are received through separate data lines and clock lines, so that the clock recovery unit 33 restores only the reference clock signal.

Generally, the PLL circuit may be composed of a phase detector, a voltage controlled oscillator (VCO), and a loop filter.

The phase detector can use an analog multiplier, an exclusive-OR gate, a flip-flop, etc., and can generate a voltage proportional to the phase difference between the input signal and the output signal. The VCO outputs a signal voltage having a frequency proportional to a voltage value input from the loop filter to the VCO, and the loop filter uses a low-pass filter or an integrator.

The clock recovery unit 33 receives the reference clock signal transmitted through the clock line as an input signal, and restores the reference clock signal to output a recovery clock signal.

When the clock recovery unit 33 is constituted by a CDR circuit, the serial data in which the reference clock signal is inserted is received from the transmitter 10. The clock recovery unit 33 separates the data and the reference clock signal, . Then, the clock recovery unit 33 samples the received data using the extracted reference clock signal, thereby reconstructing the data correctly. Here, the recovered reference clock signal is used to generate a recovered clock signal used when data is transmitted from the receiver 30 to the transmitter 10.

The signal generator 35 may receive information on the status of the device from a device connected to the receiver 30 and may generate data to be transmitted to the transmitter 10 by inserting a recovery clock signal into the information.

When the receiver 30 is ready to receive data from the transmitter 10, that is, in a locked state, the signal generating unit 35 generates a data by inserting a recovery clock signal into the status signal of the apparatus, If the transmitter 30 is not ready to receive data from the transmitter 10, that is, in the unlocked state, data can be generated by inserting a recovery clock signal into the Unlocked state signal indicating the Unlocked state.

The signal generating unit 35 can generate a state signal indicating the state of the apparatus by using the PWM method and insert the generated state signal into the clock signal. That is, the state of the apparatus can be expressed in various ways, and the signal generating unit 35 has information on state signals having different pulse widths depending on the state of the apparatus. At this time, the pulse width of the status signal is set based on the recovery clock signal, and the widest pulse width of the status signal may be set to be smaller than or equal to the width of the recovery clock signal.

2 is a diagram for explaining a signal modulation process of response data generated in the receiver of FIG.

The state signal is generated when it is in the locked state, as shown in Fig. 2 (a), and can be generated by modulating the width of the recovery clock signal shown in Fig. 2 (b). As shown in FIGS. 2 (c) to 2 (g), when five states of the apparatus are shown and each state is represented by states 1 to 5, the pulse widths of the state signals depend on the state of the apparatus, .

In the state 1, the pulse width of the state signal is set to have a width of 1/5 of the width of the recovery clock signal, and in the state 2, the pulse width of the state signal is 2/5 of the width of the recovery clock signal. In the state 3, the pulse width of the state signal is set to have a width of 3/5 of the recovery clock signal. In the state 4, the pulse width of the state signal is set to be 4/5 of the width of the recovery clock signal. And in the state 5, the pulse width of the status signal may be set to have the same width as the recovery clock signal.

The number of such state signals can be adjusted according to the type of the state of the apparatus. That is, if the state of the apparatus is 10, the state and the state signal of the apparatus can be matched by adjusting the pulse width of the state signal to 10 levels.

On the other hand, the signal generating unit 35 can generate an unlocked state signal when the apparatus is in the unlocked state. The unlocked state signal is set to be different from the pulse width of the state signal generated when the apparatus is in the locked state. For example, as shown in FIG. 2 (h), the signal generating unit 35 can generate a state signal corresponding to a width of 1/10 of the width of the recovery clock signal in the unlocked state . The generation of the unlocked status signal indicating the unlocked status is intended to determine whether the signal line between the transmitter 10 and the receiver 30 is cut off or whether the receiver 30 or the transmitter 10 fails to transmit the signal.

Generally, since the signal is transmitted from the receiver 30 to the transmitter 10 only in the locked state, if the status signal is not received from the receiver 30, the transmitter 10 determines that the receiver 30 is in the unlocked state. That is, even if the signal line between the transmitter 10 and the receiver 30 is cut off or the signal transmission between the receiver 30 and the transmitter 10 fails, the receiver 30 can not transmit a signal to the transmitter 10, The controller 10 determines that the receiver 30 is in an unlocked state. However, in the receiver 30 of the present embodiment, the transmitter 10 transmits the unlocked state signal to the transmitter 10 in the unlocked state. Therefore, if the transmitter 10 does not receive the state signal or the unlocked state signal, ) Or the signal transmission between the receiver (30) and the transmitter (10) fails.

3 is a block diagram of a low-voltage differential signaling system according to another embodiment of the present invention.

The low voltage differential signaling system according to another embodiment of the present invention includes a transmitter 10 and a receiver 30 and receives a response clock signal into a status signal using a Manchester code in a locked state of the receiver 30 So that data can be transmitted to the transmitter 10 via the Locked signal line.

The transmitter 10 according to the present embodiment includes a serial conversion unit 11, a clock generation unit 13, a data transmission unit 15 and a signal analysis unit 27. The receiver 30 includes a parallel conversion unit 31, a clock recovery unit 33, and a signal generation unit 45, as shown in FIG. 1 and FIG. However, the present embodiment differs from the above-described embodiment in the specific process for performing the role of the signal analyzer 27 and the signal generator 45.

Thus, the serial conversion unit 11, the clock generation unit 13, the data transmission unit 15, the parallel conversion unit 31 of the receiver 30, and the clock recovery unit 33 of the transmitter 10, 1 and FIG. 2, a description thereof will be omitted, and only the signal analysis unit 27 and the signal generation unit 45 will be described.

The signal analyzer 27 of the transmitter 10 uses the Manchester decoder and the signal generator 45 of the receiver 30 uses the Manchester encoder. First, the signal generating unit 45 will be described as follows.

The signal generator 45 receives information on the status of the device from a device connected to the receiver 30 and inserts a recovery clock signal into the information to generate data to be transmitted to the transmitter 10. At this time, when the receiver 30 is ready to receive data from the transmitter 10, that is, in a locked state, the signal generating unit 45 inserts a recovery clock signal into the state signal of the apparatus to generate response data can do.

The signal generating unit 45 may insert a state signal indicating the state of the apparatus into the clock signal using the Manchester encoding scheme. That is, the signal generator 45 can generate a binary status code according to the type of the status of the apparatus. The signal generator 45 performs logical operation using the exclusive OR (XOR) gate of the clock signal and the status code, As shown in FIG.

For example, when the status of the apparatus is five, the signal generator 45 can convert the status information into the next binary status code when the status information is input from the apparatus. That is, the signal generator 45 sets the state code to 00000001 in state 1, the state code to 00000010 in state 2, the state code to 00000011 in state 3, the state code to 00000100 in state 4, state You can convert the code to 00000101.

Then, the signal generating unit 45 can generate response data by performing an XOR operation on the clock signal and the status code. By XORing each state code of the state 1 to state 5 with the recovery clock signal, the following response data can be generated.

State 1

Status code 00000001

Recovery Clock Signal 10101010

Response data 10101011

State 2

Status code 00000010

Recovery Clock Signal 10101010

Response data 10101000

State 3

Status code 00000011

Recovery Clock Signal 10101010

Response data 10101001

State 4

Status code 00000100

Recovery Clock Signal 10101010

Response data 10101110

State 5

Status code 00000101

Recovery Clock Signal 10101010

Response data 10101111

Such a status code, a recovery clock signal, and response data are shown in a graph as shown in FIG.

 As shown in Fig. 4 (a), in the locked state, the recovery clock signal as shown in Fig. 4 (b) is XORed with the state code shown in Fig. 4 (c) Data is generated.

When the state of the apparatus is indicated using the Manchester coding scheme, since 0 to 255 codes can be generated by an 8-bit signal, it is possible to represent 256 device states.

The signal analyzer 27 of the transmitter 10, when receiving the response data from the receiver 30, can separate the response data into the status code and the recovery clock signal using the Manchester decoding method. At this time, the signal analyzer 27 uses the reference clock signal having the same pattern as the recovery clock signal, and XORs the reference clock signal and the response data to extract the status code.

For example, when the response data is 10101110, an XOR operation with the reference clock signal 10101010 results in a state code of 00000100, and the signal analyzer 27 can determine that the state of the apparatus is state 4. The signal analyzer 27 of the transmitter 10 has state code information for each state, and if the state code is extracted, the state code can be used to determine the state of the apparatus.

5 is a schematic configuration diagram of a display device employing a low-voltage differential signaling system according to the present invention.

The display device 100 may be one of a liquid crystal display device (LCD), a plasma display device, and an organic light emitting display device (OLED).

The display device 100 employing the low voltage differential signaling system according to the present invention includes m data lines DL1 to DLm, m being a natural number and n gate lines GL1, ..., GLn, n A data driver 120 for driving the m data lines DL1 to DLm and n gate lines GL1 to GLn sequentially A timing controller 140 for controlling the data driver 120 and the gate driver 130, and the like.

In the display panel 110, one sub-pixel (P) is formed at a point where one data line and one or two or more gate lines cross each other. The red subpixels are divided into three subpixels (red subpixel R, green subpixel G and blue subpixel B) or four subpixels (red subpixel R, white subpixel W, Pixel G, and blue sub-pixel B constitute one pixel.

The timing controller 140 starts scanning according to the timing implemented in each frame, switches the video data input from the interface according to the data signal format used by the data driver 120, and outputs the converted video data (Video Data) And controls the data driving at a proper time according to the scan.

The timing controller 140 controls various control signals such as a data control signal (DCS) and a gate control signal (GCS) to control the data driver 120 and the gate driver 130 Can be output.

Among the low-voltage differential signal systems described above, the transmitter 10 may be provided in the timing controller 140, serializes the image data provided from the timing controller 140 to the data driver 120, The response data can be analyzed.

The gate driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the n gate lines GL1 through to GLn under the control of the timing controller 140 sequentially drives the n gate lines GL1, ..., and GLn.

The data driver 120 stores the inputted image data Data in a memory (not shown) under the control of the timing controller 140 and stores the image data Data in an analog form And DLm to the m data lines DL1 through to DLm to drive the m data lines DL1 through to DLm.

The data driver 120 may include a plurality of data driver ICs (DICs), as shown in FIG. 6, and the above-described low voltage differential circuits The receiver 30 of the signal system can be applied. Here, the N data drive ICs DIC # 1, ..., DIC # K, ..., DIC # M, Respectively. Each data driving integrated circuit 150 receives image data from a timing controller 140 through a data line and receives data from the timing controller 140 through a normal It is possible to transmit the response data that replaces the Locked signal or the Unlocked signal to the timing controller 140. [

The N data driving ICs 150 (DIC # 1, ..., DIC #N) are provided with status signals or status codes for the display panel 110 using the information provided from the pixels, . The status signal or status code indicates status information of the display panel 110 that can be sensed by the data driving integrated circuit 150. The status signal or the status code includes an image defect phenomenon such as image blanking, can do.

When the status signal is used, each of the data driving ICs 150 synchronizes the status signal having a predetermined pulse width with the recovery clock signal, and transmits the generated response data to the adjacent data driving integrated circuit 150 along the locked signal line do. In the case of using the status code, each data driving IC 150 generates response data obtained by XORing the status code and the recovery clock signal, and outputs the generated response data to the adjacent data driving integrated circuit 150 along the locked signal line . Accordingly, the last data driving IC 150 can sequentially transmit the response data transferred from each data driving IC 150 to the timing controller 140 using the locked signal line.

In this locked state, the state information of the display panel provided from the pixels is transferred to the timing controller 14 via the locked signal line, so that there is no need to construct a separate data line for transmission of the status information of the display panel.

On the other hand, when the data driving integrated circuit 150 is in an unlocked state, an unlocked state signal can be generated. The unlocked state signal is set to be different from the pulse width of the state signal generated when the apparatus is in the locked state. For example, the data driving integrated circuit 150 can generate a narrow-width signal with respect to the width of the recovery clock signal in the unlocked state. The generation of the unlocked state signal indicating the unlocked state is intended to determine whether the signal line is disconnected or the communication error occurs between the data driving integrated circuit 150 and the timing controller 140.

As described above, in the low-voltage differential signaling system according to the present invention, when the transmitter 30 transmits serial data together with the reference clock signal, if the receiver 30 is in the locked state, the receiver 30 transmits a recovery clock signal to the receiver 30 To the transmitter 10 via the locked signal line. Accordingly, in the present invention, when the receiver 30 is in the locked state without transmitting another Locked signal from the receiver 30, information on the state of the apparatus is transmitted to the transmitter 10 via the locked signal line, It is possible to determine whether or not the receiver 30 is in the locked state and also to grasp the state of the device connected to the receiver 30 at the same time. In the low-voltage differential signaling system of the present invention, it is not necessary to construct a separate data line by simultaneously transmitting the locked information of the receiver 30 and the status information of the device connected to the receiver 30 using the locked signal line, It is possible to simplify the configuration of a device employing a low-voltage differential signaling system and reduce the cost.

When the data driving integrated circuit 150 of the data driving part 120 is in the locked state, the display device using the low voltage differential signaling system detects the state information of the display panel 110 sensed by the data driving integrated circuit 150 Is transferred to the timing controller 140 by using the locked signal line, the state of the display panel 110 can be easily grasped, and the configuration of the display device can be simplified and the cost can be reduced.

The standard content or standard documents referred to in the above-mentioned embodiments constitute a part of this specification, for the sake of simplicity of description of the specification. Therefore, it is to be understood that the content of the above standard content and portions of the standard documents are added to or contained in the scope of the present invention.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as falling within the scope of the present invention.

10: Transmitter 11: Serial conversion section
13: clock generator 15: data transmitter
17, 27: Signal analysis section 30: Receiver
31: parallel conversion unit 33: clock recovery unit
35, 45: signal generating unit

Claims (10)

A transmitter for synchronizing and transmitting data to a reference clock signal; And
A receiver for synchronizing the status information of the device on which the data is processed with a recovery clock signal generated based on a reference clock signal and transmitting the status information to the transmitter through a signal line for transmitting the normal status; Voltage differential signal system. The method according to claim 1,
The receiver comprising:
A clock recovery unit for recovering the reference clock signal to generate a recovery clock signal,
Generating a plurality of status signals having pulse widths different from each other in accordance with a plurality of status information indicating a status of the apparatus and generating a response data to be provided to the transmitter by synchronizing the plurality of status signals with the recovery clock signal, Voltage differential signal system comprising a generator. 3. The method of claim 2,
Wherein the signal generator comprises:
And generates and provides an unlocked state signal having a pulse width different from the plurality of state signals to the transmitter if the state of the receiver is not a normal state. 3. The method of claim 2,
The transmitter comprising:
And a signal analyzer having the plurality of state information and information on the plurality of state signals and determining the state of the apparatus in accordance with the pulse width of the response data. The method according to claim 1,
The receiver comprising:
A clock recovery unit for recovering the reference clock signal to generate a recovery clock signal,
And a signal generator for generating a plurality of status codes in accordance with a plurality of status information of the apparatus and logically computing the status codes with the recovery clock signal to generate response data provided to the transmitter. 6. The method of claim 5,
The transmitter comprising:
And a signal analyzer having information on the plurality of status information and the plurality of status codes and for separating the status code from the recovery clock signal to determine the status of the apparatus, Differential signaling system. A timing controller for providing image data displayed on the display panel; And
Wherein the controller receives the status information of the display panel and transmits response data generated by synchronizing the status information of the display panel with the clock signal to the normal state when it is determined that the data can be transmitted and received between the timing controller and the display panel, And a data driver for transmitting the information to the timing controller through a signal line for transmitting information. 8. The method of claim 7,
Wherein the data driver generates a state signal having a variable pulse width according to a state of the display panel and transmits the state signal to the timing controller when the state is determined to be the normal state. 9. The method of claim 8,
Wherein the data driver generates an unlocked status signal having a pulse width different from the pulse width of the status signal and transmits the unlocked status signal to the timing controller if the data driver is not in a normal state. 8. The method of claim 7,
Wherein the data driver generates a plurality of status codes that match a plurality of status information of the display panel and logically computes the status codes with the recovery clock signal and transmits the status codes to the timing controller.

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