KR20160053177A - Display device - Google Patents

Abstract

According to the present invention, a display device comprises a display panel, a data driving unit, and a gate driving unit. The display panel comprises a data line and a gate line. The data driving unit provides a data voltage to the data line. The gate driving unit provides a gate pulse to the gate line. The gate line comprises: a vertical gate line which receives the gate pulse from the gate driving unit and vertically crosses a pixel region while the vertical gate line is separated from the data line; and a horizontal gate line which receives the gate pulse from the vertical gate line and provides the gate pulse to pixels arranged along a horizontal line. Therefore, the display device can reduce a bezel width.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : EPD). Among them, the liquid crystal display device displays an image by controlling the electric field applied to the liquid crystal molecules in accordance with the data voltage. The active matrix type liquid crystal display device has been widely used because it is applied to almost all display devices from small mobile devices to large-sized televisions due to its low price and high performance due to development of process technology and driving technology.

Manufacturers of liquid crystal display devices have made various attempts to implement a narrow bezel.

The present invention provides a display device capable of reducing a bezel width.

A display device of the present invention includes a display panel, a data driver, and a gate driver. The display panel includes a data line and a gate line. The data driver provides the data voltage to the data line. The gate driver supplies a gate pulse to the gate line. The gate line is supplied with gate pulses from the gate driver and is supplied with gate pulses from the vertical gate lines and vertical gate lines vertically crossing the pixel region while being spaced apart from the data lines. Lt; / RTI >

Since the display device of the present invention uses a vertical gate line not passing through the bezel area, the size of the bezel can be reduced.

Further, since the vertical gate line of the present invention passes through the pixel region in a state of being separated from the data line, the area of the black matrix covering the vertical gate line can be reduced. Therefore, the present invention can improve the reduction of brightness because the size of the black matrix is reduced.

1 to 3 are views showing a display device of the present invention.
4 is a view showing a pixel array structure of a display panel;
5 is a plan view showing an embodiment of a pixel array;
6A to 6F are a plan view and a sectional view showing a process of forming a pixel array substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1, a display device of the present invention includes a display panel (PNL), a drive IC (Integrated Circuit: DIC) 10, a timing controller (TCON) 12, and the like.

The host system 10 may be implemented in any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, have. The host system 10 converts the digital video data RGB of the input image into a format suitable for the display panel PNL. The host system 10 transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 12 together with the digital video data of the input video.

The timing controller 12 transmits the digital video data of the input image received from the host system 10 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock CLK from the host system 10. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 generates a timing control signal for controlling the operation timing of the source drive ICs SIC using the timing signals Vsync, Hsync, DE, and CLK and a timing control signal for controlling the operation timings of the gate drive ICs (GIC) Lt; RTI ID = 0.0 > timing control < / RTI >

The gate timing control signal generated by the timing controller 12 includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The data timing control signal generated by the timing controller 12 includes a source start pulse SSP, a source sampling clock SSC and a source output enable signal SOE . The source start pulse (SSP) indicates the starting pixel on the line where data is to be displayed. The source sampling clock SSC indicates the latch operation of data in the data driver SIC based on the rising or falling edge.

The driving unit 14 includes a data driver SIC and a gate driver GIC. The data driver SIC latches the digital video data of the input image under the control of the timing controller 12 and converts the digital video data into data of a parallel data structure. The data driver SIC generates a data voltage by converting the digital video data into an analog gamma compensation voltage using a digital-to-analog converter (ADC) under the control of the timing controller 12, To the data lines DL. The gate driver GIC sequentially supplies gate pulses (or scan pulses) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12. [

FIG. 2 and FIG. 3 are views showing an embodiment of a driving unit (DIC), respectively.

As shown in FIG. 2, the data driver SIC may be mounted on a flexible circuit board such as a COF (Chip on Film) or directly bonded on a lower substrate by a COG (Chip on Glass) process. The gate driver (GIC) can be formed directly on the lower side of the lower substrate simultaneously with the TFT array by a GIP (Gate In Panel) process.

Alternatively, as shown in FIG. 3, the data driver SIC and the gate driver GIC may be mounted together on the COF. An input terminal of the COF is connected to a PCB (Printed Circuit Board), and an output terminal of the COF is connected to an upper end of the lower substrate of the display panel (PNL).

The display panel (PNL) includes a plurality of pixels (P), and displays an image based on the gradation displayed by each of the pixels (P). The pixels P are formed in the region where the data line DL and the gate line GL intersect. Each pixel P includes a pixel circuit PC that operates in response to a supplied data signal DATA corresponding to a scan signal supplied through a switch element SW connected to a gate line GL and a data line DL, . The pixel circuit PC and the switch element SW may be implemented in different forms according to the type of the display panel, and for example, a transistor which is turned on in response to a gate pulse may be used.

FIG. 4 is a view showing a pixel array of a display panel according to the present invention, and FIG. 5 is a view showing an embodiment of a first unit pixel shown in FIG.

Referring to FIGS. 4 and 5, a unit pixel GP for displaying an arbitrary color includes first to third pixels R, G and B. The first through third pixels R, G, and B may be pixels displaying red, green, and blue, respectively. The first to third pixels R, G, and B are arranged in parallel with the data lines DL.

The data line DL and the vertical gate line VGL are formed along the vertical direction (y-axis direction in Fig. 1) of the display panel PNL.

The first data line DL1 sequentially outputs the data voltages to the first to third pixels R, G, and B during one horizontal period 1H. That is, since one data line DL provides the data voltages to the first to third pixels R, G, and B included in the unit pixel GP, the first to third pixels R, G, , B) can be reduced to 1/3 of the number of data lines in the structure in which the horizontal line direction is formed.

The vertical gate line VGL is formed in parallel with the data line DL. The vertical gate lines VGL are formed in a number corresponding to the number of the horizontal lines HL, and each vertical gate line is supplied with a gate pulse from the gate driver GIC. Also, the vertical gate line VGL is not disposed at the boundary surface of the pixels but vertically penetrates the regions of the first to third pixels R, G and B. Therefore, it is not necessary to form a black matrix for distinguishing the boundaries of the pixels on the vertical gate line (VGL).

If the vertical gate line VGL is formed adjacent to the data line DL at the boundary of the pixels, the width of the black matrix becomes large because a black matrix must be formed to cover both the data line DL and the vertical gate line VGL . However, when the width of the black matrix is increased, the transmissivity is lowered and the luminance is lowered. However, since the black matrix is not required in the upper region of the vertical gate line (VGL), the luminance can be reduced.

The horizontal gate line HGL is arranged in the horizontal line HL direction and is formed in a metal layer different from the vertical gate line VGL. The horizontal gate line HGL is connected to the i-th vertical gate line VGL through the i-th contact hole CONTi passing through the insulating layer. For example, the first horizontal gate line HGL is connected to the first vertical gate line VGL through the first contact hole CONT1, the second horizontal gate line HGL2 is connected to the second vertical gate line VGL, And is connected through the second contact hole CONT2. The ith horizontal gate line HGL provides the ith gate pulse to the pixels arranged in the ith horizontal line HLi.

Although not shown in FIG. 4, a common voltage line for supplying a common voltage in the horizontal line direction may be formed.

6A to 6F are views illustrating a pixel array substrate forming process of the present invention. 6A to 6F are cross-sectional views taken along the line I-I ', II-II' and III-III 'shown in FIG.

Referring to FIG. 6A, a first metal pattern including first and second horizontal gate lines HGL and a common line VCL is formed on a substrate SUB. The first metal pattern is formed using a metal material selected from a single metal of any one of copper (Cu), aluminum (Al), aluminum neodymium (AlNd) and molybdenum (Mo) or a double metal layer of Cu / MoTi.

Referring to FIG. 6B, a gate insulating film GI is formed on the substrate SUBS to cover the first metal patterns. The gate insulating film GI may be formed of an inorganic insulating material such as silicon nitride (SiNx). The source / drain electrodes S and D and the first vertical gate line VGL are formed on the gate insulating layer GI.

A second metal pattern including the first and second data lines DL and the first vertical gate line VGL is formed on the gate insulating film GI. The drain electrode D of the TFT is formed to be branched from the first vertical gate line VGL and the source electrode S is formed adjacent to the drain electrode D. [ The second metal pattern may be selected from any one of molybdenum (Mo), aluminum neodymium (AlNd), chromium (Cr), and copper (Cu).

Referring to FIG. 6C, the second metal patterns are covered with an organic insulating film (PAC). The first through third contact holes CONT1 through CONT3 are formed to penetrate the organic insulating film PAC. The first contact hole CONT1 is formed to expose a part of the first horizontal gate line HGL and the first vertical gate line VGL. And the second contact hole CONT2 is formed so as to expose a part of the source electrode S. [ And the third contact hole CONT3 is formed to expose the common voltage line Vcoml.

Referring to FIG. 6D, a third metal pattern is formed over the entire surface of the pixel array substrate while exposing the TFT region and the first contact hole CONT1 region. The third metal pattern uses a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). And the third metal pattern formed on the entire surface of the pixel array substrate becomes the common electrode Vcom. The third metal pattern covering the first contact hole CONT1 connects the first horizontal gate line HGL and the first vertical gate line VGL. The third metal pattern covering the third contact hole CONT3 connects the common voltage line VCL and the common electrode Vcom.

Referring to FIG. 6E, the third metal pattern is covered with a passivation (PAS). The protective film PAS may be formed of an inorganic insulating material such as silicon nitride (SiNx).

Referring to FIG. 6F, the pixel electrode 120 and the common electrode Vcom are formed on the passivation layer PAS. The pixel electrode 120 and the common electrode Vcom may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Since the common electrode Vcom is formed across the pixel region, even if the vertical gate line VGL is formed to cross the pixel region, it is possible to shield the magnetic field caused by the gate pulse applied to the vertical gate line VGL have. That is, the liquid crystal layer (not shown) oriented at the upper portion of the common electrode Vcom is not influenced by the magnetic field induced by the gate pulse supplied to the vertical gate line VGL.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

PNL: Display panel 10: Drive IC
14: Timing controller 12: Host system
DL: Data line VGL: Vertical gate line
HGL: horizontal gate line

Claims (5)

A display panel including a data line and a gate line;
A data driver for providing a data voltage to the data line; And
And a gate driver for supplying a gate pulse to the gate line,
The gate line
A vertical gate line vertically crossing the pixel region in a state in which the gate pulse is received from the gate driver and is spaced apart from the data line; And
And a horizontal gate line that receives the gate pulse from the vertical gate line and provides the gate pulse to pixels arranged along a horizontal line.
The method according to claim 1,
Wherein the vertical gate line includes first to m-th (m is a natural number corresponding to the number of horizontal lines) vertical gate lines,
The horizontal gate line includes first through m-th horizontal gate lines,
Wherein the i-th vertical gate line (i is a natural number of m or less) is connected to the i-th horizontal gate line.
The method according to claim 1,
Wherein the horizontal gate line and the vertical gate line are disposed in different metal layers,
Wherein the horizontal gate line and the vertical gate line are connected through a contact hole.
The method of claim 3,
The horizontal gate line is disposed in the first metal layer,
The vertical gate line is disposed in a second metal layer,
And a common electrode disposed over the second metal layer over the entire pixel region with a protective film interposed therebetween.
The method according to claim 1,
The display panel
And first to third pixels arranged side by side along the vertical gate line and the data line direction,
Wherein the data lines sequentially provide the data of the first through third pixels in a time division manner.

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