KR20160036794A - An interrupt-driven i/o arbiter for a microcomputer system - Google Patents

Abstract

According to an I/O bus arbiter of the presenting invention, a CPU (processor) is used with the I/O bus arbiter to perform burst-mode data transmission in every I/O access. In addition, a DMA signal, a bus-request/bus-grant signal, and a bridge are not required, and it is unnecessary to connect a bus system with a peripheral device like a PCI. The I/O arbiter is made of port engines with an interrupt controller having a circular buffer, FIFO, and a compatibility CPU interrupt signal, the port engines configured to directly connect a device to an appropriate interface buffer, and is able to transmit synchronization data through one arbiter. The purpose of the present invention is to provide a better model and eliminate some features to simplify a system.

Description

[0001] The present invention relates to an interrupt-driven I / O arbiter for a microcomputer system,

The present invention relates to I / O bus arbitration in microcomputer systems.

Conventional I / O bus arbiter and related technology development

Conventional input / output (I / O) bus arbiters are necessary for complex multi-bus systems, as well as for buses as well as simplicity of the system-on-chip (SOC) architecture. For example, a new communications processor, such as the Intel IXP435, has three bus arbiters, four buses, and two bridges on a single chip, where the SOC is a single-CPU based ARM architecture, or two hardware-assisted accelerators or coprocessors Even so. The Intel Pentium series of computer systems and other microcomputer-based SOC systems also operate in the same system.

Most arbiters require at least two signals, a REQ-Request-Grant (REQ-GNT) pair for the bus request signal from the device, and a corresponding bus grant signal from the arbiter. The same is true for CPU (processor), direct memory access (DMA), interrupt (INT) and bus requet-bus grant (BUSREQ-BUSGNT). That is, a complete understanding and familiarity with a particular system is required to implement a simple arbiter. DMA is often the most complex device in PC systems.

Conventional arbiters have no knowledge of the I / O device condition at all, and have no knowledge of the I / O device conditions, and are able to predict and simplify complex hardware schemes such as prioritizing algorithms or timestamps for aging, It is necessary for other systems that can do this. These schemes need to be modified in terms of current processing modules, such as the packets needed for broadband devices.

An example of a method of implementing an I / O arbiter is in a method using a popular arbiter chip in a conventional system. The Intel 8289 is one of the experimental stopping chips designed to work with the Intel 8288 bus controller and the Intel 8086 CPU, which are the founders of all Intel-based Pentium computers. It is part of a group of MCS-86-enabled chips that were introduced after the introduction of the Intel 8086 CPU in 1978. With the 8289, multi-moderation chips can be more confusing when devices require bus arbitration as well as when the arbiter requires intervention.

The development of complex intervention systems is already underway. The arbitration system introduced in Samsung Electronics' US patent 7096293B2 registered on August 22, 2006 largely depends on the INT (interrupt) signal, which is the main CPU signal. However, even in this case, the existing REQ-GNT signal pair is still required for arbitration, and this patent requires the PCU bus.

The block MOVE introduced in Motorola's US Patent 5,185,694, issued Feb. 9, 1993, allows the programmer to control the burst-transfer of data using the CPU. This invention adopts burst-transfer between memories, but this idea can be applied to I / O.

Burst transfer or synchronous data transfer is required for all patented systems since 1993 and we have seen burst-transfer as the basic operation of the PCI bus specification made by Intel in 1994. The same concept can be applied to general SDRAM used in microcomputer from this time, and it is the same in DDR of 2002 and DDR2 of 2009.

For the burst-transfer of data, a FIFO is needed to match the speed difference between both the transmit and receive ports. In accordance with this trend, the inventive I / O arbitration technique has been developed.

I / O arbiter

Current microcomputer systems view buses, arbiters, interrupts, DMAs, and bridges as separate entities that must be handled separately. The current model treats the Unix logical device driver model as a character device and a block device. I / O buses must be different for each device. When there is more than one I / O bus, there must be a bridge to isolate these buses and leap from bus to bus. In this case, there should be an intermediary for the devices bound to each bus, as well as for the arbitration between each arbiter. In order to manage these independent data transfers, DMA signals, which are interrupt signals, must be connected. One example of this complicated scheme is the Intel IXP435 communications processor and the Intel Pentium series processors, both of which are for PCs.

The present invention aims at providing a better model while eliminating some features in order to simplify the system while incorporating all of these functional purposes.

The new I / O arbiter incorporates all proven data transfer technologies after many years of use in many modern systems, including hardware that is operated by burst-transfer or synchronous data transfer, FIFO, and Field-Programmable-Gate-Array (FPGA) I / O arbiter, which is able to integrate the engines, understand and adopt at least the same performance, if not better, as well as simpler. The main feature is that it is consistent in handling devices for bus access without the need for arbiters other than the present invention.

From the cleanest designs best supported by clean CPU designs, conventional interface signals used for I / O arbiters, including the PCI bus, are unnecessary and require only three CPU-controlled sets of synchronous clock signals and CPU interrupt signals It can be completely removed.

The reason is that all processing in the computer system is controlled by an interrupt. Thus, other control signals that weaken the interrupt signals may be dispensed with in creating an interrupt-driven processor that allows the system designer to think in terms of an interrupt. By observing all I / O operations, we let the internal operations flow like a single uniform interrupt event and put the sources into the interrupt controller.

This paradigm is to view heterogeneous devices such as characters, blocks, boot ROM devices, and network devices as a homogeneous device with FIFOs and buffers. Devices of the same class provide the same interface to the I / O arbitration engine and CPU, resulting in different sizes of buffers and FIFOs. In this case, the CPU can not directly access the control register in the device, but can read / write only the complete 32-bit word block, thereby eliminating the physical device driver code at the software level.

These models can be connected directly to the device, with or without complexity, and do not require any bus, such as PCI, with bus bridges and electrical signal limits, other than a single I / O arbiter.

SUMMARY OF THE INVENTION

1 is a schematic diagram of an I / O arbiter of the present invention, showing three main elements within a CPU 100, a device interface signal 106, an arbiter interrupt controller 105, a FIFO 104 and a port engine 103, Lt; / RTI > Regardless of whether the character is character or block data transfer, the device is connected to the port engine, and the port engine is responsible for 32-bit word translation from the engine or FSM (Finite-State-Machine) for device format and device signal control .

The main function of this I / O arbiter 101 is to connect one of the seven FIFO buses to the CPU 101 bus, one at a time during burst transfer. The device activates a dedicated INT signal to request attention by the associated FIFO, which then queues the request to the circular buffer 216 on a first-in, first-out basis.

The I / O arbitration process begins at port engine 103, which translates all data formats from device 102 into complete 32-bit words. The device transmits a 32-bit data packet, and the I / O arbiter must buffer this data in the associated FIFO 104. [ As a result, the CPU 100 must place this data in a buffer in main memory, like all other processes. When the FIFO 104 is charged, the FIFO controller of the FIFO block 104 generates a unique interrupt. The I / O arbiter interrupt controller knows that the native interrupt comes from a specific port and queues the port ID into the pending interrupt circular buffer.

When the port ID operates this queue, the I / O arbiter activates the CPU INT 107 and waits for the CPU INTA (Interrupt-Acknowledgment) signal 108, and the I / O arbiter assigns the interrupt vector, . The CPU 100 reads this ID and jumps to the interrupt service routine for this vector, and if this port has a block of data in the FIFO 104 and leads all of it to a port dedicated main memory buffer I know.

The data block write process of the CPU 100 is reversed. The CPU 100 writes a data block at any time, or writes it in response to an interrupt via the I / O arbiter 101 whenever possible. In addition to the 32-bit word and port address that the CpU requires, you also need to know that it uses the synchronous clock signal on the control line to read or write to the port only in burst mode.

The I / O arbiter basically operates based on the interrupt start of the I / O port request service. All pending interrupts are queued in the circular buffer and sent to the CPU's single interrupt pin along with the associated vector when the INTA is received from the CPU. Each port has its own INT & INTA pins to queue the I / O arbiter and sends INT to the CPU.

1 is a schematic diagram of an I / O arbiter of the present invention;
Figure 2 is an internal view of the I / O arbiter with all necessary interface signals.

Will be described in detail with reference to FIG. The I / O arbiter includes an arbitration interface 200, an interrupt controller 201, a plurality of FIFO modules 204 including FIFO-0, and a plurality of port engines including a port-0 engine. A number of devices 202, shown as a dashed box and not comprising an arbiter and containing device-0, are shown. Here, device-0 202, which is one of the device data paths, is connected to the I / O arbiter on behalf of other devices.

Controlling all synchronous burst transfers between the CPU 100 and the FIFOs to the CPU 100 is a key point, so the CLK 209 signal is unidirectional. Under these conditions, all independent DMA transfers by the device are not possible. Whether reading or writing a series of data in response to an interrupt request, the initial connection of the FIFO device begins with a write instruction for the desired FIFO. This command is written to the FIFO by activating the WR 210 signal with each address line (A ₁₂ -A ₀ ) 206 forming a CS (Chip-Select) signal to select the FIFO device. When interrupting an instruction, the FIFO device is an open-drain connection and responds with an active STP2 (207) signal bound to all STP2 (207) signals. The CPU 100 then activates the CLK 209, STP1 208, RD 211 and WR 210 signals to start burst mode data transmission.

A burst transfer protocol for simple full transfer for a data block of a predetermined length in main memory or FIFO

A read from the device-0 202 is initiated by the CPU 10 so that the WR 210 signal together with each address (A ₁₂ -A ₀ ) 206 lines forms a CS_10 205, -0 204 Write a command to form a device. The FIFO-0 204 notifies that the CLK 208 signal is stopped and recognizes that the write operation does not start the burst data transfer but the instruction phase.

When this command decodes by the FIFO-0 204 to mean that the CPU 100 desires to read a set of data, the FIFO-0 204 immediately receives the STP2 207 signal indicating that this command is ready At which time the CPU 100 activates the CLK 209 signal synchronously with the 32-bit data block in the FIFO-0 204 to begin the burst-read sequence. After the predetermined block length is transmitted, the FIFO-0 204 activates the STP2 207 signal to inform the CPU that the end of the burst transmission has reached the end of the FIFO buffer.

Similarly, when writing to the FIFO-0 204, the FIFO-0 204 decodes this instruction into a write instruction after the instruction phase, and then the FIFO-0 204 issues STP2 The CPU 100 immediately activates the signal 207, at which time the CPU 100 activates the CLK (209) signal synchronously with the 32-bit data word block in the main memory to initiate the burst write sequence. After the predetermined block length is transmitted, the CPU 100 operates the STP1 208 signal to inform the FIFO-0 204 that the burst transmission is completed.

A burst transfer protocol for incomplete transmission of unknown data blocks in the FIFO

Data transfer from the CPU 100 to the FIFO is always known under the control of software. The software can always know the number of data blocks for the device and the data length for optimum data transfer. The only unavoidable variable is the data transfer from the device, that is, the burst read by the CPU 100, because there is no way of knowing in advance the number of data blocks and the data length from the device. For example, packets from a LAN device continue to flow until the FIFO buffer overflows, in which case an interrupt occurs.

At this time, the interrupt controller starts to operate; There may be many devices that require the CPU 100 to read and empty the FIFO.

FIFO-0 (204), which takes device-0 (204) as a data path, generates a unique interrupt when it is completely filled. At the I / O arbiter, the interrupt controller 201 knows that the interrupt is coming from FIFO-0 204 and queues the port ID of the interrupt circular buffer 216 being pending.

When the ID is queued, the I / O arbiter 101 activates the CPU INT 212 and waits for a CPU INTA 213 (interrupt-aware) signal, at which time the I / The interrupt vector is loaded on this signal. CPU 100 reads this ID and jumps to an interrupt service routine (ISR) for this vector, and notices that this port has a block of data in FIFO-0 (204). The interrupt controller 201 determines that the next device to be serviced at the end of the FSM cycle comes from the FIFO-0 204 and sends an INTA 217 signal to the FIFO-0 204. The FIFO-0 204 activates the STP2 207 signal to recognize that it is ready to transfer, allowing the CPU 100 to know that the burst-read sequence has begun. Subsequently, the CPU 100 reads all of these into the main memory buffer reserved for the port-0 (204). When the FIFO-0 204 is emptied, the FIFO-0 204 activates the STP2 207 signal informing the CPU 100 that the block transfer is finished, and then waits for the next interrupt coming from the device- Should be.

When the CPU 100 makes a burst write transmission, the FIFO-0 204 activates the STP2 207 signal to notify the CPU 100 when the FIFO buffer is filled, in which case the CPU 100 may perform a burst- End it.

The interrupt controller 201 receives two signal pairs INT 212 - 212 from the CPU 100 for the FSM to calculate pointers for the buffer head 215 and the buffer tail 214 in managing all pending interrupts in the system. Only the INTA 212 is needed to reproduce its own INT-INTA 217 cycle for all connected devices.

The above description is intended for any device, such as a character or block device, an integrated circuit such as a ROM, a hard disk drive, a LAN, another CPU, and any other device that can be imagined without DMA mechanisms, bridges, Provides the foundation of the system.

Claims (10)

1) an I / O bus including a peripheral-connect-interface (PCI), 2) a bus control signal that is a Bus-Request-Bus-Grant (BUSGNT) pair, 3) ) Bus bridge to isolate various peripheral devices of different speeds, and 5) one or more arbiters for PCI, I / O and memory, and low speed peripheral devices including boot ROM, It is characterized by the elimination of many data transfer methods running on computer boards including SOC (system-on-chip) devices, the implementation of a new processor module embedded in the processor or implemented on a separate chip, I / O arbiter block 2. The method of claim 1, wherein the I / O arbiter implements a plurality of FIFOs and port-engines for every device, and wherein the I / O arbiter has a common processor interrupt signal pair (INT -INTA) and three synchronization signals (CLK, STP1, STP2), and all I / O devices are regarded as block devices. The system of claim 1, wherein the FIFO and the port-engines cooperate with a common processor interrupt signal pair (INT-INTA) and three synchronization signals (CLK, STP1, STP2) to remove all bus bridges from the SOC or microcomputer Gt; I / O < / RTI > 2. The method of claim 1, wherein the CPU performs burst-transfer for all I / O devices using only the interrupt signal pair (INT-INTA) and the three associated synchronization signals (CLK, STP1, STP2) Data strobe, and STP1 and STP2 each indicate the end of a burst period of input / output to / from the FIFO controller. The method according to claim 1, further comprising the steps of: controlling the address channel to the CPU address bus for the direct address of the CPU main memory and making the DMA interface signals of the CPU for shutting down the CPU unnecessary; To perform DMA transfer under the control of the CPU using the I / O arbiter. 3. The I / O arbiter block of claim 1, wherein a conventional BUSREQ-BUSGNT signal pair that controls bus mastering of the CPU that disables the CPU address and data buses is dispensed with. 3. The method of claim 2, further comprising: using an internal interrupt controller to arbitrate device access of a single pair of INT-INTA signals to the processor interface signal, And queues an individual interrupt into its own internal circular FIFO buffer. ≪ RTI ID = 0.0 > I / O < / RTI > 3. The method of claim 2, further comprising: using a plurality of device port engines to access external peripherals of various data transfer modes and speeds, wherein the character or block device presents a block of data of a certain view to perform burst- Characterized by an I / O arbiter block. 3. The method of claim 2, wherein a plurality of FIFOs are used to transmit and receive data from the device, and data and device types are converted using different interface signals for the same data block entering the FIFO for each port engine of each device I / O arbiter blocks. 3. The I / O arbiter block of claim 2, wherein the arbitration scheme and the buffer size that can cause the priority are changed to rely on the knowledge of the CPU software of the device to adopt a scheme suitable for the burst-transfer of the device.

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