KR20160031818A - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell. The solar cell according to an embodiment of the present invention comprises: a semiconductor substrate containing impurities having a first conductive type; a plurality of emitter units located on a back side of the semiconductor substrate, having a second conductive type opposite to the first conductive type, and made up of a poly-crystal silicon material; plural backside electric field units formed on the back side of the semiconductor substrate as separated from the emitter units, containing high concentration impurities having the first conductive type and made up of a poly-crystal silicon material; a first passivation layer located between the emitter units and the back side electric field units on the back side of the semiconductor substrate; a plurality of first electrodes connected to the emitter units respectively; and plural second electrodes connected to the backside electric field units respectively. At least one of the emitter units includes a plurality of emitter unit poles which are separated from one another and are made up of silicon material, and at least one of the backside electric field units includes plural backside electric field unit poles which are separated from one another and are made up of a poly-crystal silicon material.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, respectively, so that electrons move toward the n- And moves toward the semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

The object of the present invention is to provide a solar cell.

A solar cell according to an example of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; A plurality of emitter regions located on a rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, the emitter portions being formed of a polycrystalline silicon material; A plurality of rear electric parts located on the rear surface of the semiconductor substrate and spaced apart from the plurality of emitter portions and formed of a polycrystalline silicon material and containing impurities of the first conductive type at a high concentration than the semiconductor substrate; A first passivation layer positioned between a plurality of emitter portions and a plurality of rear electrical portions on the rear surface of the semiconductor substrate; A plurality of first electrodes connected to each of the plurality of emitter portions; And a plurality of second electrodes connected to each of the plurality of rear electric fields, wherein at least one of the plurality of emitter portions is spaced apart from each other and includes a plurality of emitter column portions formed of a polycrystalline silicon material, At least one of the plurality of rear electric fields is spaced apart from each other and includes a plurality of rear electric tower pillars formed of a polycrystalline silicon material.

Here, the plurality of emitter pillars provided on any emitter portion of the plurality of emitter portions are commonly connected to any one of the plurality of first electrodes, and one of the plurality of rear electric portions, The plurality of rear electric field pillars formed on the first electrode may be commonly connected to any one of the plurality of second electrodes.

Here, the plurality of emitter pillars formed on one of the emitter portions and the plurality of rear wall pillars formed on the one of the backside electrical portions may be elongated in the direction of each of the first and second electrodes from the semiconductor substrate have.

At this time, the length of each of the plurality of emitter-side pillars formed on one of the emitter portions and the plurality of rear-side conductive pillars formed on one of the rear-side electric portions may be longer than the width. For example, each of the plurality of emitter-side pillars formed on one emitter portion and the plurality of rear-side pillars provided on the one rear-side electric portion may have a width of 1: 1/3 to 2/3 .

More specifically, the length of each of the plurality of emitter-side pillars formed on one emitter portion and the plurality of rear-side bank portions formed on one of the rear-side electric portions is between 150 nm and 750 nm, and a plurality of The width of each of the plurality of rear electric-field pillars formed in each of the emitter-side pillars and the one rear-side electric portion may be between 50 nm and 500 nm.

In addition, the spacing between the plurality of emitter pillars formed in any one emitter portion and the plurality of back wall pillars formed in any one back electrified portion may be between 50 nm and 500 nm.

Further, a tunnel layer may be further formed between each of the plurality of rear electric field pillars formed on each of the plurality of emitter pillars formed in one of the emitter portions and the semiconductor substrate, and between the plurality of rear electric field pillars formed on one of the rear electric field portions, and the semiconductor substrate. At this time, the material of the tunnel layer may be SiOx or SiCx.

The tunnel layer is disposed on each of a plurality of emitter pillars formed on one of the emitter portions and a plurality of rear wall pillars formed on the one of the rear wall portions of the rear surface of the semiconductor substrate, May not be located at portions where each of the plurality of emitter pillars and the plurality of rear wall pillars do not overlap with each other.

Thus, the width of the tunnel layer may be the same as the width of the emitter and column backing pillars.

In addition, a first passivation layer may be further provided between the plurality of emitter-side pillars formed on any one emitter portion and the plurality of rear-side electrum pillars formed on any one of the backside electrified portions.

Such a first passivation layer may comprise a dielectric material, and the thickness of the first passivation layer may be equal to the length of the emitter pillar and the back conductor pillar.

In addition, the second passivation layer may further include a second passivation layer on the rear surface of the first passivation layer. In the second passivation layer, an opening portion may be formed at a portion overlapping the plurality of emitter portions and the plurality of rear electric field portions, and a plurality of emitter portions formed in any one emitter portion through each opening portion formed in the second passivation layer. The column may be commonly connected to any one of the first electrodes, and a plurality of rear electric column portions formed on one of the rear electric fields may be commonly connected to any one of the second electrodes.

The solar cell according to the present invention has a plurality of emitter pillars spaced apart from each other and a plurality of rear wall pillars spaced from each other in each emitter portion and each rear electric field portion to prevent junction leakage, , It is possible to naturally form the first passivation layer between the emitter portion and the rear electric field portion in the manufacturing process, so that the manufacturing process can be further simplified.

1 is a partial perspective view of a solar cell according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view taken along the line II-II in Fig. 1. Fig.
3A and 3B illustrate a solar cell according to another embodiment of the present invention.
FIGS. 4A to 4G are views for explaining an example of a method of manufacturing a structure of a rear surface of a semiconductor substrate in the solar cell shown in FIGS. 1 and 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, the front surface may be one surface of a semiconductor substrate to which the direct light is incident, and the rear surface may be the opposite surface of the semiconductor substrate in which direct light is not incident, or reflected light other than direct light may be incident.

1 is a perspective view of a solar cell according to a first embodiment of the present invention, and Fig. 2 is a cross-sectional view taken along the line II-II in Fig. 1 And FIGS. 3A and 3B are views for explaining another embodiment of the present invention.

1 and 2, the solar cell according to the first embodiment of the present invention includes an antireflection film 130, a semiconductor substrate 110, an emitter section 121, a rear electric section 172, A passivation layer 191, a second passivation layer 192, a first electrode 141, and a second electrode 142. [

In the solar cell, the anti-reflection film 130 and the second passivation layer 192 are illustrated in FIGS. 1 and 2 as an example, but may be omitted. However, as shown in FIGS. 1 and 2, the efficiency of the solar cell, if provided, can be further improved.

The semiconductor substrate 110 may be formed of a single crystal silicon material doped with an impurity of a first conductivity type, for example, an n-type conductivity type. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) may be doped into the semiconductor substrate 110 when the semiconductor substrate 110 has an n-type conductivity type.

Alternatively, the semiconductor substrate 110 may be a p-type conductive type. In this case, the semiconductor substrate 110 may be formed of an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In) Can be doped to the semiconductor substrate 110.

The incident surface of the semiconductor substrate 110 is textured to have an irregular surface. In FIG. 1, only the edge portion of the semiconductor substrate 110 is shown as an uneven surface. However, substantially the entire front surface of the semiconductor substrate 110 may have an uneven surface.

The antireflection film 130 may be formed entirely on the front surface of the semiconductor substrate 110 and may include a dielectric material such as SiOx, SiNx, SiOxNy, or AlOx.

Each of the plurality of emitter sections 121 may be formed of a polycrystalline silicon material having a second conductivity type opposite to the first conductivity type and arranged in a first direction x on the rear surface of the semiconductor substrate 110, , The emitter section 121 may form a pn junction with the semiconductor substrate 110.

Therefore, the pn junction formed between the semiconductor substrate 110 and the plurality of emitter sections 121 separates the electron-hole pairs, which are charges generated by the light incident on the semiconductor substrate 110, into electrons and holes, the electrons move toward the n-type and the holes move toward the p-type.

Therefore, when the semiconductor substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes move toward the respective emitter portions 121 and the separated electrons are higher in impurity concentration than the semiconductor substrate 110 And can move toward the plurality of rear electric sections 172.

When the semiconductor substrate 110 has a p-type conductivity type, the emitter section 121 is formed to have an n-type conductivity, that is, Type. In this case, the separated electrons move toward the plurality of emitter portions 121 and the separated holes can move toward the plurality of rear electric fields 172.

When the plurality of emitter sections 121 have a p-type conductivity type, the emitter section 121 can be doped with an impurity of a trivalent element. Conversely, when the plurality of emitter sections 121 have an n-type conductivity type , The emitter portion 121 may be doped with an impurity of a pentavalent element.

The emitter layer 121 is formed by forming an intrinsic semiconductor layer 150 made of polycrystalline material on the back surface of the semiconductor substrate 110 and then implanting impurities of the second conductivity type into the intrinsic semiconductor layer 150 made of polycrystalline material .

Each of the plurality of rear electric sections 172 may be spaced apart from the plurality of emitter sections 121 on the rear surface of the semiconductor substrate 110 in a first direction x. The rear electric field portion 172 may be formed of a polycrystalline silicon material doped with impurities of the first conductivity type at a higher concentration than the semiconductor substrate 110. Thus, for example, when the substrate is doped with an n-type impurity, the plurality of backside electrical paths 172 may be n + impurity regions.

The rear electric field 172 disturbs the hole movement toward the rear electric field 172, which is the movement direction of the electrons, due to the potential barrier due to the difference in impurity concentration between the semiconductor substrate 110 and the rear electric field 172, (E. G., Electrons) to the backside electrical < / RTI > Thus, by reducing the amount of charge lost due to recombination of electrons and holes in the rear electric field 172 and in the vicinity thereof or at the first and second electrodes 142, 141 and 142 and accelerating electron movement, 172 can be increased.

The rear electric section 172 and the emitter section 121 may be spaced apart from each other, as shown in FIGS. 1 and 2.

The first passivation layer 191 may be positioned between the emitter portion 121 and the backside electrical portion 172 in the rear surface of the semiconductor substrate 110.

More specifically, the first passivation layer 191 is positioned between the emitter portion 121 and the backside electrical portion 172, wherein the first passivation layer 191 is positioned between each emitter portion 121 and each backside electrical portion 172 The semiconductor substrate 110 can be directly contacted to the rear surface of the semiconductor substrate 110. [

The thickness T of the first passivation layer 191 may be equal to the thickness T of the emitter section 121 and the thickness T of the rear electric section 172.

The first passivation layer 191 may perform a passivation function to remove defects on the rear surface of the semiconductor substrate 110 and prevent the carriers generated in the semiconductor substrate 110 from being recombined and being destroyed have.

For this purpose, the first passivation layer 191 includes a dielectric material, and may be formed by containing hydrogen in at least one of SiNx, SiOx, SiOxNy, and AlOx, for example.

The second passivation layer 192 is located on the first passivation layer 191 and the second passivation layer 192 is formed on the portion overlapping the plurality of emitter portions 121 and the plurality of the backside electrical portions 172 A plurality of emitter sections 121 and a plurality of first electrodes 141 are connected through respective openings and a plurality of rear electric sections 172 are connected to a plurality of second electrodes 142 .

The second passivation layer 192 may include a dielectric material. For example, hydrogen may be contained in at least one of SiNx, SiOx, SiOxNy, and AlOx.

In addition, the material of the second passivation layer 192 may be the same as that of the first passivation layer 191.

Each of the plurality of first electrodes 141 is located on the plurality of emitter sections 121 and extends along the plurality of emitter sections 121 and may be electrically and physically connected to the plurality of emitter sections 121. Accordingly, each first electrode 141 can collect charges (for example, holes) that have migrated toward the corresponding emitter section 121.

Each of the plurality of second electrodes 142 is located on the plurality of rear electric sections 172 and extends long along the plurality of rear electric sections 172 and is electrically and physically connected to the plurality of rear electric sections 172 . Thus, each second electrode 142 may collect an electrical charge, e. G., Electrons, moving toward the corresponding rear electric field 172.

 The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, a metal such as nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti) , Or alternatively may be formed of a transparent conductive metal, for example, a TCO.

The operation of the solar cell according to this embodiment having such a structure is as follows.

When light is irradiated to a solar cell and is incident on the semiconductor substrate 110, electron-hole pairs are generated in the semiconductor substrate 110 due to light energy. These electron-hole pairs are separated from each other by the pn junction of the semiconductor substrate 110 and the emitter section 121, and the holes move toward the emitter section 121 having the p-type conductivity type, and electrons move to the n- To the first electrode 141 and the second electrode 142, and are collected by the first and second electrodes 141 and 142, respectively. When the first electrode 141 and the second electrode 142 are connected to each other by a conductor, a current flows and can be used as an external power.

In the solar cell according to the present invention, at least one of the plurality of emitter sections 121 includes a plurality of emitter section pillars 121C, and at least one of each of the plurality of rear electric section sections 172 Includes a plurality of rear electric tower pillars (172C).

1 and 2, the solar cell according to the present invention is characterized in that at least one of the plurality of emitter sections 121 has a plurality of emitter pillars 121 formed of a polycrystalline silicon material, And the plurality of emitter pillars 121C included in one emitter section 121 may be spaced apart from each other.

At least one of the plurality of rear electric sections 172 includes at least one rear electric section 172 including a plurality of rear electric conductive pillars 172C formed of a polycrystalline silicon material and one rear electric conductive section 172, The plurality of rear electric-field pillars 172C included in the rear-side conductive pillars 172C may be spaced apart from each other.

1 and 2 illustrate a case where each of the plurality of emitter sections 121 includes a plurality of emitter column pillars 121C and each of the plurality of rear electric power sections 172 includes a plurality of rear wall pillars 172C One emitter section 121 of the plurality of emitter sections 121 includes a plurality of emitter section columns 121C and one of the plurality of rear electric sections 172 May include a plurality of rear electrical tower pillars (172C).

Each of the plurality of emitter pillars 121C formed on one of the emitter layers 121 is formed to be elongated in the direction of each of the first electrodes 141 from the semiconductor substrate 110, Each of the plurality of rear electric field pillars 172C formed on the step portion 172 may be elongated in the direction of each of the second electrodes 142 from the semiconductor substrate 110. [

For example, as shown in FIGS. 1 and 2, a plurality of emitter pillars 121C and a plurality of rear wall pillars 172C may be in direct contact with the semiconductor substrate 110, The plurality of emitter pillars 121C included in the tab 121 may be commonly connected to any one of the first electrodes 141. The plurality of emitter pillars 121C, The column 172C may be connected to any one of the second electrodes 142 in common.

As shown in FIG. 2, the solar cell is divided into a plurality of emitter-side pillars 121C and a plurality of rear-side bank pillars 172C, The length T may be longer than the widths W1 and W2.

2, the width W1 of the emitter column 121C and the width W2 of the rear electric column 172C are the same as the width W2 of the emitter- The width of the photovoltaic cell cut in two directions y means the width in the second direction y and the longitudinal direction of the emitter pillar 121C and the back surface pillar 172C is the width of the first, Refers to a third direction (z) intersecting the two directions (x, y), i.e., the thickness direction of the solar cell.

More specifically, in the present invention, the widths W1 and W2 of the lengths T of the plurality of emitter column pillars 121C and the plurality of rear wall column pillars 172C are in a range of 1: 1/3 to 2/3 Lt; / RTI >

For example, when the widths W121 and W172 of one emitter section 121 and one rear electric section 172 are formed to be between 100 μm and 1 mm, as shown in FIG. 1, The length T of each of the plurality of rear electric tower pillars 172C formed on each of the emitter pillars 121C and one rear electric section 172 may be between 150 nm and 750 nm and the widths W1 and W2 may be between 150 nm and 750 nm, Lt; RTI ID = 0.0 > (T). ≪ / RTI >

At this time, the distance between the plurality of emitter pillars 121C formed on any one emitter section 121 and the plurality of the rear wall pillars 172C formed on one of the rear electric sections 172 D1, D2) may be between 50 nm and 500 nm.

1 and 2, a plurality of rear electric tower pillars 121 are formed between a plurality of emitter pillars 121C formed on any one emitter section 121 and between a plurality of rear electric tower pillars 121 formed on one of the rear electric sections 172. [ And a first passivation layer 191 may be further provided between the first passivation layer 172C and the second passivation layer 172C.

The first passivation layer 191 formed between each emitter section 121 and each of the rear electric sections 172 and the first passivation layer 191 or the rear electric section 191 provided between the emitter pillars 121C The thickness T of the first passivation layer 191 provided between the first and second passivation layers 172 and 172 may be the same as the length T of each of the emitter pillars 121C and the respective rear wall pillars 172C.

1 and 2, the second passivation layer 192 formed on the rear surface of the first passivation layer 191 may have a plurality of emitter pillars (not shown) formed in one emitter section 121 through the respective openings, A plurality of rear electric field pillars 172C formed on one rear electric unit 172 are commonly connected to one first electrode 141 and one rear electrode pre- .

When the emitter section 121 and the rear electric section 172 are formed of a plurality of emitter pillars 121C and a plurality of silicon pillars, It is possible to prevent junction leakage that the generated carriers are recombined between the emitter section 121 and the rear electric section 172 and also to prevent junction leakage between the emitter section 121 and the rear electric section 172 The first passivation layer 191 made of a dielectric material having insulating properties can be formed naturally, and the manufacturing process can be further simplified.

The first passivation layer 191 formed between each emitter section 121 and the rear electric section 172 is formed in direct contact with the rear surface of the semiconductor substrate 110 without a separate intrinsic semiconductor layer The fill factor FF and the open-circuit voltage Voc can be improved.

Although a plurality of emitter pillars 121C and a plurality of rear wall pillars 172C are directly in contact with the semiconductor substrate 110, as described above, as shown in FIGS. 3A and 3B, The solar cell according to the present invention includes a plurality of emitter regions 121C formed on one emitter portion 121 and a plurality of rear electric field portions 122 formed between the semiconductor substrate 110 and one of the rear electric field portions 172, A tunnel layer 180 may be further formed between each of the pillars 172C and the semiconductor substrate 110. [

The material of the tunnel layer 180 may be SiOx or SiCx. Alternatively, the tunnel layer 180 may be formed of silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenerated SiON.

When the tunnel layer 180 is formed between the plurality of emitter column pillars 121C and the semiconductor substrate 110 and between the plurality of the rear column pillars 172C and the semiconductor substrate 110, Voc) can be further improved.

3A, the tunnel layer 180 may include a plurality of emitters (not shown) formed on one of the emitter portions 121 of the back surface of the semiconductor substrate 110, A plurality of emitter pillars 121C are formed on the rear surface of the semiconductor substrate 110. The plurality of emitter pillars 121C are disposed on portions of the base pillars 121C and the plurality of back wall pillars 172C formed on each of the back wall pillars 172, And the plurality of rear electric tower pillars 172C, respectively.

The reason why the tunnel layer 180 is located at a portion of the back surface of the semiconductor substrate 110 where the tunnel layer 180 is overlapped with the emitter column 121C and the plurality of rear wall columns 172C is that, (Voc).

The reason why the tunnel layer 180 is not located at a portion of the back surface of the semiconductor substrate 110 that does not overlap with the emitter pillar 121C and the plurality of the rear electrical tower pillars 172C is that, This is because the region in which the tunnel layer 180 is formed is relatively small regardless of the improvement in the open-circuit voltage (Voc), thereby further reducing the process time and cost and facilitating the manufacturing process.

Here, the width of the tunnel layer 180 may be the same as the width W2 of the emitter pillar 121C and the rear electric tower pillar 172C, and the thickness of the tunnel layer 180 may be between 1 nm and 1.5 nm. have.

The reason for limiting the thickness of the tunnel layer 180 as described above is that the tunneling effect can be most effectively exerted in the above-described numerical range. The width of the tunnel layer 180 is set such that the emitter- This is because the manufacturing process of such a structure is easier if the width W2 of the step column 172C is equal to the width W2 of the step column 172C.

In another example of forming the tunnel layer 180, the tunnel layer 180 may be formed entirely on the rear surface of the semiconductor substrate 110, unlike FIG. 3A.

3B, the tunnel layer 180 may be formed entirely on the rear surface of the semiconductor substrate 110 and may be formed between the semiconductor substrate 110 and the plurality of emitter pillars 121C and between the semiconductor substrate 110 and the semiconductor substrate 110. [ But also between the semiconductor substrate 110 and the first passivation layer 191 as well as between the plurality of rear electric column portions 172C.

The first passivation layer 191 does not directly contact the rear surface of the semiconductor substrate 110 and the tunnel layer 180 is formed entirely on the rear surface of the semiconductor substrate 110, The first conductive layer 172C and the first passivation layer 191 may be formed in direct contact with the tunnel layer 180. [

Although the structure of a solar cell according to an example of the present invention has been described so far, an example of a method of manufacturing such a solar cell will be briefly described below.

FIGS. 4A to 4G are views for explaining an example of a method of manufacturing the structure of the rear surface of the semiconductor substrate 110 in the solar cell shown in FIGS. 1 and 2. FIG.

As shown in FIG. 4A, a dielectric layer 191L made of a dielectric material may be deposited on the entire rear surface of the semiconductor substrate 110. FIG. The dielectric layer 191L may be deposited using a PECVD method, but is not limited thereto.

4B, a semiconductor substrate (not shown) is formed in the emitter forming region S1 and the rear electric conductor forming region S2 in which the emitter section 121 and the rear electric section 172 are to be formed in the dielectric layer 191L The first passivation layer 191 may be formed by forming a plurality of first and second grooves H1 and H2 spaced apart from each other such that a rear surface of the first passivation layer 110 is exposed.

As described above, the method of forming the plurality of grooves H1 and H2 includes the steps of forming the plurality of first and second grooves H1 and H2 in the emitter forming region S1 and the rear electric conductor forming region S2, (Not shown) is formed on the remaining portions except for the portion where the etching-resistant mask (not shown) is formed by using the etching solution, A plurality of grooves H1 and H2 spaced apart from each other can be formed. Alternatively, it is also possible to form a plurality of grooves H1 and H2 by irradiating laser beams differently.

4C, the semiconductor substrate 110 exposed through the first passivation layer 191 and the first passivation layer 191 and the first and second recesses H1 and H2 formed on the first passivation layer 191, The polysilicon layer PS may be formed on the rear surface of the polysilicon layer PS.

Such a polycrystalline silicon material layer (PS) can use an LPCVD method for depositing polycrystalline silicon by a CVD method at 600 ° C or higher. However, it is also possible to use a solid-phase crystallization method in which an amorphous silicon (a-Si) layer is formed and then heat-treated at a temperature of 550 DEG C or higher to polycrystallize the semiconductor, or a laser Annealing methods may also be used.

A plurality of first silicon pillars PCS1 formed of a polycrystalline silicon material are formed in the plurality of first grooves H1 provided in the emitter forming region S1, A plurality of second silicon pillars PCS2 formed of a polycrystalline silicon material may be formed on the plurality of second grooves H2 provided on the substrate.

4D, impurities of the second conductivity type are implanted into the plurality of first silicon pillars PCS1 provided in the emitter forming region S1 to form a plurality of emitter pillars 121C, Impurities of the first conductivity type may be implanted into the plurality of second silicon pillars PCS2 provided in the step forming region S2 to form a plurality of rear electric field pillars 172C.

When the impurity of the second conductivity type is implanted into the emitter forming region S1, the impurity of the second conductivity type may be implanted into the first passivation layer 191 provided in the emitter forming region S1 The impurity of the first conductivity type may be injected into the first passivation layer 191 provided in the rear electric field forming region S2 when the impurity of the first conductivity type is injected into the rear electric field forming region S2 have.

As described above, in the method of implanting impurities of the first and second conductivity types into the first and second regions S1 and S2, the impurity of the first and second conductivity types is included in the first and second regions S1 and S2 A method may be used in which first and second dopant layers (not shown) are respectively formed and then heat-treated and diffused.

Thereafter, the polycrystalline silicon material layer PS located on the rear surface of the first passivation layer 191 located in the emitter forming region S1, the rear conductor forming region S2, and the region between the emitter forming region S1 and the rear conductor forming region S2 is entirely etched, One emitter section 121 having a plurality of emitter section pillars 121C spaced apart from each other and one rear electric section 172 having a plurality of rear electrical part pillars 172C spaced apart from each other, ) Can be formed.

4F, a second passivation layer 192 may be formed on the first passivation layer 191 located between the emitter section 121 and the backside electrical section 172. In this case, Accordingly, the second passivation layer 192 may include a plurality of openings through which a portion overlapping one emitter portion 121 and one backside electrical portion 172 is exposed.

The ends of the plurality of emitter pillars 121C provided in one emitter section 121 are exposed through the respective openings of the second passivation layer 192, The ends of the plurality of rear electric tower pillars 172C may be exposed.

As shown in FIG. 4G, a metal electrode layer is formed on the openings of the second passivation layer 192, and a first electrode (not shown) commonly connected to the plurality of emitter pillars 121C exposed through the openings And the second electrode 142 connected to the plurality of rear electric field pillars 172C exposed through the openings may be formed.

4A to 4G illustrate the method of manufacturing the solar cell according to the first embodiment of the present invention. However, when manufacturing the solar cell according to the second embodiment of the present invention, as shown in FIG. 4B Similarly, the first passivation layer 191 having the first and second grooves H1 and H2 is formed, and the plurality of first and second grooves H1 and H2 are formed by the Oxidation method and the PECVD method, A tunnel layer 180 formed of SiOx can be formed.

Thereafter, the solar cell shown in FIG. 3 can be manufactured by performing the same method as described in FIGS. 4C to 4G.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (18)

A semiconductor substrate containing an impurity of a first conductivity type;
A plurality of emitter regions located on a rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type and formed of a polycrystalline silicon material;
A plurality of rear electrical parts located on the rear surface of the semiconductor substrate, the rear electrical parts being spaced apart from the plurality of emitter parts and containing impurities of the first conductive type at a high concentration than the semiconductor substrate;
A first passivation layer disposed between the plurality of emitter portions and the plurality of rear electric fields in the rear surface of the semiconductor substrate;
A plurality of first electrodes connected to each of the plurality of emitter portions; And
And a plurality of second electrodes connected to each of the plurality of rear electric fields,
At least one of the plurality of emitter portions being spaced apart from each other and including a plurality of emitter pillars formed of the polycrystalline silicon material,
Wherein at least one of the plurality of rear electric fields is spaced apart from each other and includes a plurality of rear electric field columns formed of the polycrystalline silicon material. The method according to claim 1,
A plurality of emitter pillars formed on any one of the plurality of emitter portions are commonly connected to any one of the plurality of first electrodes,
And a plurality of rear electric field pillars formed on one of the plurality of rear electric fields are commonly connected to any one of the plurality of second electrodes. 3. The method of claim 2,
Wherein each of the plurality of emitter pillars provided on the emitter portion and the plurality of rear wall pillars formed on the one of the plurality of backside electrical portions are formed to be elongated in the direction of one of the first and second electrodes from the semiconductor substrate, Solar cells. The method according to claim 1,
Wherein each of the plurality of emitter pillars formed on one of the emitter portions and the plurality of rear electric power pillars formed on the one of the rear electric portions is longer than the width of each of the emitter pillars. 5. The method of claim 4,
Wherein each of the plurality of emitter pillars formed on one of the emitter portions and each of the plurality of rear electric field pillars formed on the one of the rear electric portions is between 1: 1/3 and 2/3. 6. The method of claim 5,
Wherein a length of each of the plurality of emitter pillars provided on any one of the emitter portions and a plurality of the rear wall pillars formed on the one of the plurality of rear electrical portions is between 150 nm and 750 nm. 6. The method of claim 5,
Wherein a width of each of the plurality of emitter pillars provided on any one of the emitter portions and a plurality of the rear wall pillars formed on the one of the rear electric portions is between 50 nm and 500 nm. 6. The method of claim 5,
Wherein the spacing between the plurality of emitter pillars provided on any one of the emitter portions and between the plurality of rear wall pillars formed on the one of the rear wall portions is between 50 nm and 500 nm. The method according to claim 1,
Wherein a tunnel layer is further formed between each of the plurality of emitter post columns formed in any one of the emitter sections and a plurality of rear electric field columns formed between the semiconductor substrate and either one of the rear surface electric sections and the semiconductor substrate, . 10. The method of claim 9,
Wherein the material of the tunnel layer is SiOx or SiCx. 10. The method of claim 9,
Wherein the tunnel layer is formed on each of a plurality of emitter pillars formed on one of the emitter portions of the semiconductor substrate and a plurality of rear wall pillars formed on the one of the rear electrical portions,
Wherein the plurality of emitter pillars and the plurality of rear wall pillars are not overlapped with each other in the rear surface of the semiconductor substrate. 10. The method of claim 9,
Wherein the width of the tunnel layer is equal to the width of the emitter pillar and the rear electric tower pillar. The method according to claim 1,
Wherein the first passivation layer is further provided between a plurality of emitter pillars provided on any one of the emitter portions and between a plurality of rear wall pillars formed on any one of the backside electrified portions. 14. The method of claim 13,
Wherein the first passivation layer comprises a dielectric material. 14. The method of claim 13,
Wherein the thickness of the first passivation layer is equal to the length of the emitter pillar and the back surface pillar. The method according to claim 1,
And a second passivation layer on the rear surface of the first passivation layer. 17. The method of claim 16,
And an opening is formed in a portion of the second passivation layer overlapping the plurality of emitter portions and the plurality of rear electric fields. 18. The method of claim 17,
A plurality of emitter pillars formed on one of the emitter portions are commonly connected to one of the first electrodes through respective openings formed in the second passivation layer, And a stepped column is commonly connected to any one of the second electrodes.

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