KR101531468B1 - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell. The solar cell according to an embodiment of the present invention comprises a semiconductor substrate; an emitter part; a back electroluminescent part; an intrinsic semiconductor layer; a first electrode electrically connected to the emitter part; and a second electrode electrically connected to the back electroluminescent part, wherein the emitter part arranged long in the first direction are partially separated, and a first bypass part is further arranged in a space between the partially separated emitter part, and a back electroluminescent arranged long in the first direction is partially separated, and a second bypass part is further arranged in a space between the partially separated back electroluminescent part.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, respectively, so that electrons move toward the n- And moves toward the semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

An object of the present invention is to provide a solar cell that provides a bypass path.

A solar cell according to an example of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter section containing an impurity of a second conductivity type opposite to the first conductivity type and being arranged in a long direction in a first direction on the rear surface of the semiconductor substrate; A rear electric field portion containing impurities of the first conductivity type at a high concentration than the semiconductor substrate and spaced apart from the emitter portion on the rear surface of the semiconductor substrate and being arranged long in the first direction; An intrinsic semiconductor layer disposed on a rear surface of the semiconductor substrate in a spaced-apart space between the emitter portion and the rear electric portion; A first electrode electrically connected to the emitter portion; And a second electrode electrically connected to the back electroluminescent portion, wherein the emitter portion arranged long in the first direction is partially spaced apart, and the space between the partially spaced emitter portions is electrically connected to the first electrode And a first bypass portion connected to the emitter portion and containing an impurity of the first conductivity type opposite to the emitter portion; a rear electric field portion disposed in a long direction in the first direction is partially spaced, And a second bypass portion electrically connected to the second electrode and containing an impurity of the second conductivity type opposite to the rear electric portion.

Here, in the case where the emitter portions are disposed apart from each other along the longitudinal direction of the first electrode, and the first bypass portion is further included in the spaced space between the emitter portions, the intrinsic semiconductor layer is formed in a space between the partially- And may be positioned between the semiconductor substrate and the first bypass portion.

The width of the first bypass portion may be smaller than the width of the emitter portion, and may be larger than 1/2 of the width of the emitter portion.

In addition, the first bypass portion is spaced apart from the emitter portion, and when the semiconductor substrate is viewed from the rear, the first bypass portion can be surrounded by the intrinsic semiconductor layer.

In addition, the first bypass portion may have a thickness smaller than that of the emitter portion. For example, the thickness of the first bypass portion may be between 1/3 and 2/3 of the emitter portion thickness.

 Further, when the rear electric field portion is disposed to be spaced apart along the longitudinal direction of the first electrode, and the second bypass portion is further included in the spaced-apart space between the rear electric fields, the intrinsic semiconductor layer is formed between the partially- And may be positioned between the semiconductor substrate and the second bypass portion.

At this time, the width of the second bypass portion may be smaller than the width of the rear electric field portion, and may be larger than half of the width of the rear electric field portion.

In addition, the second bypass portion is spaced apart from the rear electric field portion, and when the semiconductor substrate is viewed from the rear, the second bypass portion can be surrounded by the intrinsic semiconductor layer.

In addition, the second bypass portion may have a thickness smaller than that of the rear electrical portion. For example, the thickness of the second bypass portion may be between 1/3 and 2/3 of the thickness of the rear electrical portion.

In addition, a tunnel layer of a dielectric material may be further disposed between the front surface of each of the emitter layer, the intrinsic semiconductor layer, and the back surface electric field portion and the rear surface of the semiconductor substrate to allow carriers generated in the semiconductor substrate to pass therethrough.

At this time, the dielectric material of the tunnel layer may be SiCx or SiOx.

In addition, the emitter portion, the intrinsic semiconductor layer, and the rear surface electric portion may be polycrystalline silicon materials.

The photovoltaic cell according to the present invention includes a bypass part between the emitter part and the backside electric part so that the bypass current can flow through the solar cell when the solar cell does not operate normally due to the shadow.

1 to 3 are views for explaining a first embodiment of a solar cell according to the present invention.
4 to 6 are views for explaining the operation of the solar cell according to the first embodiment of the present invention.
7 to 8 are views for explaining a second embodiment of the solar cell according to the present invention.
9 to 11 are views for explaining the operation of the solar cell according to the second embodiment of the present invention.
12 and 13 are diagrams for explaining the difference between the first and second bypass units BP1 and BP2 provided in the solar cell according to the present invention and the bypass diode provided in the junction box JB in general .
14 shows an example in which first and second bypass units are provided together in one solar cell.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, the front surface may be one surface of a semiconductor substrate to which the direct light is incident, and the rear surface may be the opposite surface of the semiconductor substrate in which direct light is not incident, or reflected light other than direct light may be incident.

1 to 3 are views for explaining a first embodiment of a solar cell according to the present invention.

2 is a cross-sectional view of the solar cell shown in FIG. 1, in which the emitter section 121, the rear electric section 172, and the rear surface of the first bypass section BP1 3 illustrates a rear surface of the solar cell shown in Fig. 2, in which passivation layer 190 and first and second electrodes 141 and 142 are omitted, FIG. 2 is a cross-sectional view taken along the line CC-Cla when the layer 190 and the first and second electrodes 141 and 142 are provided.

1, a solar cell according to a first embodiment of the present invention includes an antireflection film 130, a semiconductor substrate 110, a tunnel layer 180, an emitter section 121, a rear electric section 172, An intrinsic semiconductor layer 150, a passivation layer 190, a first electrode 141, and a second electrode 142. [0031]

The antireflection film 130 on the front surface of the semiconductor substrate 110, the tunnel layer 180 on the rear surface of the semiconductor substrate 110, and the passivation layer 190 may be omitted in the solar cell, In this case, since the efficiency can be further improved, the case where it is provided will be described as an example.

The antireflection film 130 is formed on the front surface of the semiconductor substrate 110 to minimize the reflection of light incident from the outside to the front surface of the semiconductor substrate 110. The antireflection film 130 is formed of an aluminum oxide film (AlOx), a silicon nitride film (SiNx) An oxide film (SiOx), and a silicon oxynitride film (SiOxNy), and may be formed of a single film as shown in FIGS. 1 and 2, but may also be formed of a plurality of films .

The semiconductor substrate 110 may be formed of a single crystal silicon material doped with an impurity of a first conductivity type, for example, an n-type conductivity type. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) may be doped into the semiconductor substrate 110 when the semiconductor substrate 110 has an n-type conductivity type.

Alternatively, the semiconductor substrate 110 may be a p-type conductive type. In this case, the semiconductor substrate 110 may be formed of an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In) Can be doped to the semiconductor substrate 110.

The incident surface of the semiconductor substrate 110 is textured to have an irregular surface. In FIG. 1, only the edge portion of the semiconductor substrate 110 is shown as an uneven surface. However, substantially the entire front surface of the semiconductor substrate 110 may have an uneven surface.

Next, the tunnel layer 180 is disposed on the entire rear surface of the semiconductor substrate 110, and may include a dielectric material.

1, the tunnel layer 180 is formed on the back surface and the rear surface electric field portion 172, the intrinsic semiconductor layer 150, and the emitter portion 121 of the semiconductor substrate 110 formed of a single crystal silicon material May be formed between the front surface of the layer of the polycrystalline silicon material to be formed.

The tunnel layer 180 may pass carriers generated in the semiconductor substrate 110 and passivate the back surface of the semiconductor substrate 110.

In addition, the tunnel layer 180 may be formed of a dielectric material formed of SiCx or SiOx having high durability even at a high temperature process of 600 DEG C or more. However, silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenerated SiON can be formed. The thickness of the tunnel layer 180 may be 0.5 nm to 2.5 nm .

The emitter section 121 may be formed of a polycrystalline silicon material having a second conductivity type opposite to the first conductivity type and disposed in a part of the rear surface of the tunnel layer 180 in a first direction x, , The emitter section 121 can form a pn junction with the semiconductor substrate 110 with the tunnel layer 180 therebetween.

When the semiconductor substrate 110 has a p-type conductivity type, the emitter section 121 is formed to have an n-type conductivity, that is, Type. In this case, the separated electrons move toward the plurality of emitter portions 121 and the separated holes can move toward the plurality of rear electric fields 172.

When the plurality of emitter sections 121 have a p-type conductivity type, the emitter section 121 can be doped with an impurity of a trivalent element. Conversely, when the plurality of emitter sections 121 have an n-type conductivity type , The emitter portion 121 may be doped with an impurity of a pentavalent element.

The emitter layer 121 is formed by forming an intrinsic semiconductor layer 150 made of polycrystalline material on the back surface of the semiconductor substrate 110 and then implanting impurities of the second conductivity type into the intrinsic semiconductor layer 150 made of polycrystalline material .

A plurality of the rear electric field lines 172 are arranged in a part of the rear surface of the tunnel layer 180 where the plurality of emitter layers 121 are not formed in a long direction in the same first direction x as the emitter layer 121 . The rear electric field portion 172 may be formed of a polycrystalline silicon material doped with impurities of the first conductivity type at a higher concentration than the semiconductor substrate 110. Thus, for example, when the substrate is doped with an n-type impurity, the plurality of backside electrical paths 172 may be n + impurity regions.

The rear electric field 172 disturbs the hole movement toward the rear electric field 172, which is the movement direction of the electrons, due to the potential barrier due to the difference in impurity concentration between the semiconductor substrate 110 and the rear electric field 172, (E. G., Electrons) to the backside electrical < / RTI > Thus, by reducing the amount of charge lost due to recombination of electrons and holes in the rear electric field 172 and in the vicinity thereof or at the first and second electrodes 142, 141 and 142 and accelerating electron movement, 172 can be increased.

The rear electric section 172 and the emitter section 121 may be spaced apart from each other, as shown in FIGS. 1 and 2.

Here, the thickness of the emitter section 121 and the rear electric section 172 may be between 100 nm and 300 nm.

The intrinsic semiconductor layer 150 may be formed in a spaced space between the emitter section 121 and the rear electric section 172 in the rear surface of the tunnel layer 180. The intrinsic semiconductor layer 150 may be formed in the emitter section 121 and the rear electric section 172. The p-type or n-type impurity is not doped in the polycrystalline silicon material.

The intrinsic semiconductor layer 150 may be formed in a spaced space between the emitter section 121 and the rear electric section 172.

The passivation layer 190 is formed by removing a defect caused by a dangling bond formed on the rear surface of the polycrystalline silicon layer formed on the rear electric field portion 172, the intrinsic semiconductor layer 150, and the emitter portion 121 , And to prevent the carriers generated from the semiconductor substrate 110 from being recombined by a dangling bond and disappearing.

The passivation layer 190 completely covers the rear surface of the intrinsic semiconductor layer 150 and covers the remaining portion of the rear surface of the emitter layer 121 excluding the portion to which the first electrode 141 is connected, 172 except the portion to which the second electrode 142 is connected.

The passivation layer 190 may be formed of a dielectric layer. For example, the passivation layer 190 may be formed of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and aluminum oxide (AlOx) .

A plurality of first electrodes 141 may be provided and extend in a first direction x along a plurality of emitter portions 121 on a plurality of emitter portions 121 and may include a plurality of emitter portions 121, May be electrically and physically connected. Accordingly, each first electrode 141 can collect charges (for example, holes) that have migrated toward the corresponding emitter section 121.

A plurality of second electrodes 142 may also be present and extend over the plurality of rear electrical components 172 in a first direction x along a plurality of rear electrical components 172, And may be electrically and physically connected to the step 172. Thus, each second electrode 142 may collect an electrical charge, e. G., Electrons, moving toward the corresponding rear electric field 172.

 The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, a metal such as nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti) , Or alternatively may be formed of a transparent conductive metal, for example, a TCO.

1 to 3, the solar cell according to the first embodiment of the present invention may further include a first bypass unit BP1.

Hereinafter, the first bypass unit BP1 will be described in more detail with reference to FIGS. 2 and 3. FIG.

In FIG. 2, CT141 shows a region to which the first electrode 141 is connected, and CT142 shows a region to which the second electrode 142 is connected.

2, when the semiconductor substrate 110 is viewed from the rear, the emitter portions 121 are formed in a long distance in the first direction x but partially separated from each other, and the first bypass portion BP1 is partially And may be disposed in a space between the emitter portions 121 separated from each other.

1 and 3, the first bypass unit BP1 may include an impurity of the first conductivity type, which is electrically connected to the first electrode 141 and is opposite to the emitter unit 121 .

In the first bypass unit BP1, when light is incident on the front surface of the solar cell, the solar cell is not operated when the solar cell normally operates, but when a shadow is formed on the front surface of the solar cell, A turn-on operation may be performed to provide a bypass path in the solar cell so that the first electrode 141 and the second electrode 142 are electrically connected to each other. As a result, the bypass current can flow through the shadowed solar cell.

The first bypass unit BP1 will be described later in more detail with reference to Figs. 4 to 6, after a detailed description of the structure will be given later.

2, the back surface pattern of the solar cell according to the first embodiment of the present invention in which the first bypass portion BP1 is formed is formed by the emitter portion 121). ≪ / RTI >

3, the intrinsic semiconductor layer 150 further disposed in the space between the spaced apart emitter portions 121 overlaps the semiconductor substrate 110 and the first bypass portion BP1, can do.

Since the intrinsic semiconductor layer 150 is positioned between the semiconductor substrate 110 and the first bypass unit BP1 as described above, when the solar cell normally operates, carriers such as positive (+) and electron It is possible to minimize recombination near the first bypass unit BP1.

The width of the first bypass portion BP1 in the second direction y is smaller than the width of the emitter portion 121 in the second direction y and the width of the emitter portion 121 is 1 / 2 < / RTI > However, the width of the first bypass unit BP1 is not essential and can be changed.

The side surface of the first bypass portion BP1 may be spaced apart from the side surface of the emitter portion 121, as shown in FIGS.

2 and 3, the length LBP1 of the first bypass part BP1 in the first direction x is smaller than the length D1 of the spacing space of the emitter part 121 The side surface of the first bypass section BP1 can be located apart from the side surface of the emitter section 121. [ However, as shown in the drawing, the side surface of the first bypass portion BP1 and the side surface of the emitter portion 121 may be in contact with each other.

When the side surface of the first bypass section BP1 is spaced apart from the side surface of the emitter section 121 as described above, the intrinsic semiconductor layer (the first bypass section BP1) and the emitter section 121 are separated from each other, The first bypass unit BP1 may be surrounded by the intrinsic semiconductor layer 150 when the semiconductor substrate 110 is viewed from the rear side.

3, since the intrinsic semiconductor layer 150 is located between the semiconductor substrate 110 and the first bypass unit BP1 when the cross section of the semiconductor substrate 110 is viewed, The pass section BP1 may have a thickness smaller than that of the emitter section 121. [

For example, the thickness TBP1 of the first bypass section BP1 may be between 1/3 and 2/3 of the emitter section thickness T121.

The thickness TBP1 of the first bypass section BP1 is set to be larger than 1/3 of the thickness of the emitter section T121 by minimizing the thickness TBP1 of the first bypass section BP1, The function of minimizing the function of allowing the bypass current to flow through the first bypass unit BP1 when the solar cell is not normally operated due to the shadow formed on the entire surface of the solar cell.

The reason why the thickness TBP1 of the first bypass section BP1 is made smaller than 2/3 of the thickness of the emitter section T121 is that the solar cell normally operates while ensuring the function of the first bypass section BP1 The amount of carriers recombined by the first bypass unit BP1 is minimized.

The operation of the solar cell according to the first embodiment of the present invention having such a structure will now be described with reference to FIGS. 4 to 6. FIG.

FIG. 4 is a cross-sectional view taken along the line Clb-Clb in FIG. 2. FIG. 5 is a view illustrating a carrier path when the solar cell operates normally. FIG. Is bypassed through the first bypass unit BP1 when the first bypass unit BP1 does not normally operate.

In order to explain the operation of the solar cell according to the first embodiment of the present invention, the case where the impurity of the first conductivity type is n-type and the impurity of the second conductivity type is the p-type is shown as an example in FIG. 4, .

Type semiconductor, the emitter section 121 is of p-type, the rear electric section 172 is of n-type, the emitter section 121 of p-type, and the rear electric section 172 of n + type, and the impurity of the first conductivity type is n- -type, and the first bypass unit BP1 located in the spaced-apart space between the emitter units 121 may be n-type.

A plurality of solar cells having the above-described structure are connected in series to form a module. In each of the first and second electrodes 141 and 142 of the solar cell, interconnectors IC1 and IC2 are connected to electrodes having different polarities of the adjacent solar cells, Lt; / RTI >

For example, the first interconnection IC1 connected to the second electrode 142 of another adjacent solar cell may be connected to the first electrode 141 of the solar cell as shown in Fig. 4, A second interconnector IC2 connected to the first electrode 141 of another adjacent solar cell may be connected to the electrode 142 as shown in Fig.

Thus, in the state where the solar cell is connected in series, the solar cell can be operated.

5, when a solar cell is irradiated with light and is incident on the semiconductor substrate 110, electrons (-) and holes (+) are generated in the semiconductor substrate 110 by light energy Lt; / RTI >

The positive holes (+) move toward the emitter section 121 having the p-type conductivity type and the electrons (-) move toward the rear electric section 172 having the n-type conductivity type, 141 and the second electrode 142 and may be collected by the first and second electrodes 141, 142.

Therefore, positive (+) is collected in the first electrode 141, electrons are collected in the second electrode 142, and a forward bias voltage Vfb is applied between the first and second electrodes 141 and 142. Therefore, You can take this.

The positive electrode (+) moved to the first electrode 141 is coupled to the negative electrode (-) moved through the first inter connecter IC1 and the negative electrode The current path can be formed by being coupled with the positive (+) electrode that has been moved through the second interconnection IC2.

As a result, a current flows to a plurality of solar cells connected in series to each other, and this can be used as electric power from the outside.

Thus, when the solar cell normally operates, the first bypass unit BP1 is in a non-operating state. However, a leakage current in which a small number of electrons (-) are recombined with the positive (+) collected in the first electrode 141 through the first bypass unit BP1 may occur, The width and thickness of the bypass section BP1 and the concentration of the flameproof can be minimized or almost eliminated.

The concentration of impurities of the first conductivity type included in the first bypass section BP1 is higher than the concentration of impurities of the first conductivity type contained in the semiconductor substrate 110 and is lower than the concentration of impurities of the first conductivity type contained in the rear electric section 172, May be equal to or lower than the concentration of the impurity of the first conductivity type contained in the first conductive type.

In addition, when the solar cell is not normally operated due to the shadow formed on the entire surface of the solar cell, electrons and holes (+) are not generated in the semiconductor substrate 110 as shown in FIG.

Accordingly, the electrons (-) generated by the other solar cells adjacent to the first electrode 141 can be collected and transferred to the first electrode 141, and the holes (+ Can be moved and collected.

Therefore, a reverse bias voltage Vrb is applied between the first and second electrodes 141 and 142 of the solar cell, and the p-type emitter portion 121, the n-type semiconductor substrate 110, and the n + A current path can not be formed in the path leading to the rear electric section 172. [

However, when the reverse bias voltage Vrb applied between the first and second electrodes 141 and 142 of the solar cell increases by a certain level or more, the first bypass unit BP1 is turned on, Type semiconductor substrate 150, an n-type semiconductor substrate 110, and an n + -type backside electrical portion (not shown). The first bypass portion BP1, the i-type intrinsic semiconductor layer 150, And the electrons (-) thus moved are combined with the positive holes (+) collected in the second electrode 142 to form a bypass path, As a result, current can flow into the solar cell.

As described above, in the solar cell according to the first embodiment of the present invention, when a shadow is generated in the solar cell, and the solar cell does not operate normally, the bypass path BP1 causes the bypass path The efficiency of the solar cell module can be further increased.

In addition, when the reverse bias voltage Vrb is applied between the first and second electrodes 141 and 142 of the solar cell, the temperature of the portion where the corresponding solar cell exists in the solar cell module rises due to the reverse bias voltage Vrb Hot spots may occur. If the first bypass unit BP1 is provided in the solar cell as described above, such hot spots can be prevented.

Although only the case where the emitter section 121 is provided with the first bypass section BP1 has been described as an example in order to provide the bypass path to the solar cell up to now, (BP2) may be provided to provide a bypass path to the solar cell.

7 to 8 are views for explaining a second embodiment of the solar cell according to the present invention.

7 is a cross-sectional view of a passivation layer 190 for explaining a rear planar pattern of the emitter portion 121, the rear electric portion 172 and the second bypass portion BP2 in the solar cell according to the second embodiment of the present invention. And FIG. 8 is a cross-sectional view of a back surface of the solar cell shown in FIG. 7, showing a passivation layer 190 and first and second electrodes 141 and 142. FIG. And 142 are provided, the cross-sectional view taken along line C2a-C2a in FIG.

7 to 8, description of the same contents as those of the first embodiment of the present invention will be omitted, and other contents will be mainly described.

As shown in FIG. 7, the solar cell according to the second embodiment of the present invention may be partially spaced apart from the rear electric section 172, which is arranged long in the first direction (x).

In addition, a space between the partially spaced rear electric sections 172 may include a second bypass portion 182 electrically connected to the second electrode 142 and containing an impurity of the second conductive type opposite to the rear electric portion 172, (BP2) can be further disposed.

7 and 8, the intrinsic semiconductor layer 150 is further disposed in a space between the partially spaced rear electric sections 172, and the semiconductor substrate 110 and the second bypass section BP2. ≪ / RTI >

The width of the second bypass portion BP2 in the second direction y is smaller than the width of the rear electric portion 172 in the second direction y and is smaller than the width of the rear electric portion 172 by 1 / 2 < / RTI > However, such a width of the second bypass section BP2 is not essential and can be changed.

 7 and 8, the side surface of the second bypass portion BP2 may be spaced apart from the side surface of the backside electrical portion 172. As shown in FIG.

7 and 8, the length LBP2 of the second bypass portion BP2 in the first direction x is longer than the length D2 of the spacing space of the rear electric portion 172. In other words, So that the side surface of the second bypass portion BP2 can be spaced apart from the side surface of the rear electric portion 172. [ However, as shown in the drawing, the side surfaces of the second bypass portion BP2 and the rear surface electric portion 172 may be in contact with each other.

When the side surface of the second bypass section BP2 is spaced apart from the side surface of the rear electric section 172 as described above, The second bypass portion BP2 may be surrounded by the intrinsic semiconductor layer 150 when the semiconductor substrate 110 is viewed from the rear side.

8, since the intrinsic semiconductor layer 150 is located between the semiconductor substrate 110 and the second bypass portion BP2 when the cross section of the semiconductor substrate 110 is viewed, The pass section BP2 may have a thickness smaller than that of the rear electric section 172. [

For example, the thickness TBP2 of the second bypass portion BP2 may be between 1/3 and 2/3 of the rear electrical conductor thickness T172.

The thickness TBP2 of the second bypass portion BP2 is set to be larger than 1/3 of the thickness T172 of the rear electrical conductor portion by minimizing the thickness of the impurity of the second conductivity type opposite to the rear electrical portion 172 Thereby ensuring at least the function of allowing the bypass current to flow through the second bypass unit BP2 when the solar cell is not normally operated due to the shadow formed on the entire surface of the solar cell.

The reason why the thickness TBP2 of the second bypass section BP2 is made smaller than 2/3 of the thickness T172 of the rear electric section is that the solar cell normally operates while ensuring the function of the second bypass section BP2 The amount of carriers recombined by the second bypass unit BP2 is minimized.

Here, the impurity concentration of the second conductivity type contained in the second bypass section BP2 may be equal to or lower than the impurity concentration of the second conductivity type contained in the emitter section 121, But is not limited to.

The operation of the solar cell according to the second embodiment of the present invention having such a structure will now be described with reference to FIGS. 9 to 11. FIG.

FIG. 9 is a cross-sectional view taken along the line C2b-C2b in FIG. 7, FIG. 10 is a view showing a carrier path when the solar cell operates normally, Is bypassed through the second bypass unit BP2 when the second bypass unit BP2 does not normally operate.

In order to explain the operation of the solar cell according to the second embodiment of the present invention, the case where the impurity of the first conductivity type is n-type and the impurity of the second conductivity type is the p-type is shown as an example in FIG. 9, .

Type semiconductor, the emitter section 121 is of p-type, the rear electric section 172 is of n-type, the emitter section 121 of p-type, and the rear electric section 172 of n + type, and the impurity of the first conductivity type is n- -type and the second bypass portion BP2 located in the spaced-apart space between the rear electric lines 172 may be p-type.

9, a first inter connecter IC1 connected to a second electrode 142 of another adjacent solar cell may be connected to the first electrode 141 of the solar cell having such a structure, The second interconnection IC2 connected to the first electrode 141 of another adjacent solar cell may be connected to the second electrode 142 as shown in Fig.

Thus, in the state where the solar cell is connected in series, the solar cell can be operated.

When the solar cell is normally operated, as shown in FIG. 10, the positive (+) light generated by irradiation with the solar cell moves toward the emitter part 121 having the p-type conductivity type, And the electrons may be collected on the second electrode 142 by moving to the backside electrical portion 172 having the n-type conductivity type.

Therefore, positive (+) is collected in the first electrode 141, electrons are collected in the second electrode 142, and a forward bias voltage Vfb is applied between the first and second electrodes 141 and 142. Therefore, You can take this.

The positive electrode (+) moved to the first electrode 141 is coupled to the negative electrode (-) moved through the first inter connecter IC1 and the negative electrode The current path can be formed by being coupled with the positive (+) electrode that has been moved through the second interconnection IC2.

Thus, when the solar cell normally operates, the second bypass unit BP2 is in a non-operating state.

In addition, when a shadow is formed on the entire surface of the solar cell and the solar cell does not normally operate, as shown in FIG. 11, electrons (-) and holes (+ do.

Accordingly, the electrons (-) generated by the other solar cells adjacent to the first electrode 141 can be collected and transferred to the first electrode 141, and the holes (+ Can be moved and collected.

Therefore, a reverse bias voltage Vrb is applied between the first and second electrodes 141 and 142 of the solar cell, and the p-type emitter portion 121, the n-type semiconductor substrate 110, and the n + A current path can not be formed in the path leading to the rear electric section 172. [

However, when the reverse bias voltage Vrb applied between the first and second electrodes 141 and 142 of the solar cell increases by a certain level or more, the second bypass unit BP2 is turned on, A forward bias is applied to the path leading to the bypass unit BP1, the i-type intrinsic semiconductor layer 150, and the n-type semiconductor substrate 110. [

Accordingly, the positive (+) ions collected by the second electrode 142 pass through the p-type first bypass unit BP1, the i-type intrinsic semiconductor layer 150, the n-type semiconductor substrate 110, n + -type rear electric field 172, and the thus-moved electrons are coupled to the electrons (-) collected in the second electrode 142, A path is formed, and thus a current can flow into the solar cell.

Accordingly, when the solar cell according to the second embodiment of the present invention generates shadows and the solar cell does not operate normally, the bypass path BP2 allows the bypass path to pass through the solar cell The efficiency of the solar cell module can be further increased, and hot spots can be prevented.

As described above, the solar cell according to the first and second embodiments of the present invention includes the first bypass unit BP1 and the second bypass unit BP2, so that when the solar cell does not normally operate due to the shadow, By providing a bypass path, the efficiency of the solar cell module can be further improved and hot spots can be prevented.

In the present invention, only the case where the first bypass unit BP1 and the second bypass unit BP2 are separately formed is described as an example. However, as shown in FIG. 14, And bypass portions BP1 and BP2 may be provided together.

The method of manufacturing the first and second bypass portions BP1 and BP2 may be formed as follows, for example.

The tunneling layer 180 and the intrinsic semiconductor layer 150 are formed on the rear surface of the semiconductor substrate 110 and then the intrinsic semiconductor layer 150 is partially removed to form the emitter layer 121, (x) of a second conductivity type dopant, and applying a first conductive dopant containing an impurity of the first conductivity type to the region between the partially isolated second conductive dopant The first and second conductive dopants are diffused into the intrinsic semiconductor layer 150 and activated so that the emitter section 121 and the first bypass section BP1 can be formed together.

The second bypass unit BP2 may include a first conductive type impurity in a first direction x so as to be partially separated to form a rear electric field portion 172 on another portion of the intrinsic semiconductor layer 150 And a second conductive dopant containing an impurity of the second conductivity type is applied to a region between the partially separated first conductive dopants and is then thermally treated to form the rear electric field 172 and the second electric conductive dopant, Two bypass portions BP2 can be formed together.

As described above, the method of manufacturing the first and second bypass portions BP1 and BP2 is only one example, and any other method can be used.

As described above, the first and second bypass units BP1 and BP2 provided in the solar cell can be distinguished from the bypass diode provided in the junction box for collecting power in the solar cell module.

12 and 13 are diagrams for explaining the difference between the first and second bypass units BP1 and BP2 provided in the solar cell according to the present invention and the bypass diode provided in the junction box JB in general .

12 is a view for explaining bypass diodes BD1 to BD3 provided in a junction box JB of a solar cell module. FIG. 13 is a view for explaining bypass diodes BD1 to BD3 of FIG. 12, FIG. 4 is a view for explaining a difference in efficiency of generated voltages with the first and second bypass units BP1 and BP2 provided in the solar cell.

As shown in FIG. 12, one solar cell module may include first, second, and third strings ST1, ST2, and ST3 connected in series with a plurality of solar cells. Such a solar cell module may be provided with a junction box JB for collecting electric power generated from the first, second and third strings ST1, ST2 and ST3.

In the junction box JB, first, second and third bypass diodes BD1 to BD3 may be provided between the first, second and third strings ST1, ST2 and ST3, respectively.

In this case, for example, when the first solar cell C1 can not be driven due to the shadow, the first bypass diode BD1 is turned on and the junction box JB is turned on in the second and third strings ST2 and ST3 The generated power can be collected.

However, in such a case, power is not supplied from the entire first string ST1 to which the first solar cell C1 belongs as well as the first solar cell C1. Thus, as shown in Fig. 13, A considerable voltage drop of VD1 corresponding to almost 1/3 of the voltage may occur.

However, when the solar cell according to the present invention is applied to the solar cell module shown in Fig. 12, only power generated from the corresponding solar cell can not be supplied, and power can be supplied from the remaining solar cells of the string to which the solar cell belongs Therefore, the voltage drop of the solar cell module can generate a relatively small voltage drop as much as VD2 corresponding to the open-circuit voltage of the first solar cell C1, thereby greatly increasing the efficiency of the solar cell module.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (16)

A semiconductor substrate containing an impurity of a first conductivity type;
An emitter portion containing an impurity of a second conductivity type opposite to the first conductivity type and being disposed in a long direction in a first direction on a rear surface of the semiconductor substrate;
A rear electric field portion that contains impurities of the first conductive type at a high concentration from the semiconductor substrate and is spaced apart from the emitter portion on the rear surface of the semiconductor substrate and is arranged long in the first direction;
An intrinsic semiconductor layer disposed on a rear surface of the semiconductor substrate in a spaced-apart space between the emitter section and the rear electric section;
A first electrode electrically connected to the emitter; And
And a second electrode electrically connected to the rear electric field portion,
Wherein the emitter portion disposed in the first direction is partially spaced apart and a space between the partially spaced emitter portions is electrically connected to the first electrode and includes an impurity of a first conductivity type opposite to the emitter portion, Or a first bypass portion,
Wherein a portion of the rear surface electric field disposed in the first direction is partially spaced apart and a space between the partially spaced rear electric conductive portions is electrically connected to the second electrode and includes a second conductive type impurity And a second bypass portion including a first bypass portion and a second bypass portion. The method according to claim 1,
When the emitter portion is disposed along the longitudinal direction of the first electrode and the first bypass portion is further included in the spaced space between the emitter portions,
Wherein the intrinsic semiconductor layer is further disposed in a space between the partially-spaced emitter portions, and is positioned between the semiconductor substrate and the first bypass portion. 3. The method of claim 2,
Wherein the width of the first bypass portion is smaller than the width of the emitter portion and is larger than 1/2 of the width of the emitter portion. 3. The method of claim 2,
Wherein the first bypass portion is spaced apart from the emitter portion. 3. The method of claim 2,
Wherein the first bypass portion is surrounded by the intrinsic semiconductor layer when viewed from the rear surface of the semiconductor substrate. 3. The method of claim 2,
Wherein the first bypass portion has a thickness smaller than that of the emitter portion. The method according to claim 6,
Wherein the thickness of the first bypass portion is between 1/3 and 2/3 of the thickness of the emitter portion. The method according to claim 1,
When the rear electric field portion is disposed to be spaced apart along the longitudinal direction of the first electrode and the second bypass portion is further included in the spaced space between the rear electric field portions,
Wherein the intrinsic semiconductor layer is further disposed in a space between the partially spaced rear electric fields, and is positioned between the semiconductor substrate and the second bypass portion. 9. The method of claim 8,
Wherein a width of the second bypass portion is smaller than a width of the rear electric field portion and is larger than a half of a width of the rear electric field portion. 9. The method of claim 8,
And the second bypass portion is spaced apart from the rear electric portion. 9. The method of claim 8,
And the second bypass portion is surrounded by the intrinsic semiconductor layer when viewed from the rear surface of the semiconductor substrate. 9. The method of claim 8,
And the second bypass portion has a thickness smaller than that of the rear electric field portion. 13. The method of claim 12,
Wherein the thickness of the second bypass portion is between 1/3 and 2/3 of the thickness of the rear electrical portion. The method according to claim 1,
And a tunnel layer of a dielectric material for passing a carrier generated in the semiconductor substrate between the front surface of each of the emitter portion, the intrinsic semiconductor layer, and the rear electric portion, and the rear surface of the semiconductor substrate. 15. The method of claim 14,
And the dielectric material of the tunnel layer is SiCx or SiOx. The method according to claim 1,
Wherein the emitter portion, the intrinsic semiconductor layer, and the rear electric field portion are polycrystalline silicon materials.

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