KR102244604B1 - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell.
A solar cell according to an example of the present invention includes a semiconductor substrate containing impurities of a first conductivity type; An emitter unit disposed on the rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A rear electric field portion disposed on the rear surface of the semiconductor substrate to be spaced apart from the emitter portion and containing an impurity of a first conductivity type at a higher concentration than that of the semiconductor substrate; An intrinsic semiconductor layer disposed in a space spaced apart between the emitter part and the back electric field part of the back surface of the semiconductor substrate; A first passivation layer disposed on a first bonding surface on which side surfaces of the intrinsic semiconductor layer and the emitter portion are bonded to each other; A first electrode connected to the emitter unit; And a second electrode connected to the rear electric field, wherein the first passivation layer has a fixed charge (Qf) having the same polarity as the first conductivity.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as the depletion of existing energy resources such as oil and coal is predicted, interest in alternative energy to replace them is increasing, and accordingly, solar cells that produce electric energy from solar energy are attracting attention.

A typical solar cell includes a semiconductor portion forming a p-n junction by different conductivity types, such as a p-type and an n-type, and electrodes connected to the semiconductor portions of different conductivity types, respectively.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, which are electric charges, so that the electrons move toward the n-type semiconductor part and the holes are p-type. It moves toward the semiconductor part. The transferred electrons and holes are collected by different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and power is obtained by connecting these electrodes with wires.

An object of the present invention is to provide a solar cell with improved efficiency.

A solar cell according to an example of the present invention includes a semiconductor substrate containing impurities of a first conductivity type; An emitter unit disposed on the rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A rear electric field portion disposed on the rear surface of the semiconductor substrate to be spaced apart from the emitter portion and containing an impurity of a first conductivity type at a higher concentration than the semiconductor substrate; An intrinsic semiconductor layer disposed in a space spaced apart between the emitter portion and the rear electric field portion of the rear surface of the semiconductor substrate; A first passivation layer disposed on a first bonding surface on which side surfaces of the intrinsic semiconductor layer and the emitter portion are bonded to each other; A first electrode connected to the emitter unit; And a second electrode connected to the rear electric field, wherein the first passivation layer has a fixed charge (Qf) having the same polarity as the first conductivity.

Here, the first passivation layer may not overlap with the rear electric field portion, and the first passivation layer may overlap a portion of the intrinsic semiconductor layer including the first junction surface and a portion of the emitter portion.

For example, the first passivation layer may be located up to a point 1/5 to 4/5 of the distance from the first junction surface to the rear electric field in the rear region of the intrinsic semiconductor layer.

In this case, the thickness of the first passivation layer may be between 150 nm and 250 nm.

More specifically, when the first conductivity type is n-type, the first passivation layer may be a dielectric layer having a (-) fixed charge, and for example, the first passivation layer may be formed of aluminum oxide (AlOx).

And, the first conductivity type is p-type, the first passivation layer may be a dielectric layer having a (+) fixed charge, for example, the first passivation layer is formed of silicon nitride (SiNx) or silicon oxide (SiOx) Can be.

In addition, a second passivation layer having a fixed charge having a polarity opposite to that of the first passivation layer may be further disposed on the intrinsic semiconductor layer and the first passivation layer.

More specifically, the second passivation layer may be disposed to cover all of the first passivation layer and the remaining regions of the intrinsic semiconductor layer in which the first passivation layer is not disposed.

In addition, the thickness of the emitter portion and the rear electric field portion may be between 100 nm and 300 nm.

In addition, a tunnel layer including a dielectric material and passing carriers generated in the semiconductor substrate between the semiconductor substrate and the layer in which the rear electric field part, the intrinsic semiconductor layer, and the emitter part are formed; may be further disposed, and such a tunnel layer It may be a dielectric layer formed of SiC or SiO. However, it is not necessarily limited thereto, and the tunnel layer may be formed of silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenerated SiON.

In this case, the tunnel layer may have a thickness of 0.5 nm to 2.5 nm.

In the solar cell according to the present invention, by disposing a first passivation layer having a fixed charge having the same polarity as the conductivity of the semiconductor substrate on the first bonding surface in which the side surfaces of the intrinsic semiconductor layer and the emitter part are bonded to each other, the intrinsic semiconductor layer and the emitter part are Junction leakage in which some carriers are recombined between taboos can be improved.

1 to 3 are diagrams for explaining a first embodiment of a solar cell according to the present invention.
4A to 4B are diagrams for explaining a comparative example without the first passivation layer 191 unlike the solar cell structure of the present invention.
FIG. 5 is a diagram for explaining the effect of the case where the first passivation layer described in FIGS. 1 to 3 is formed with a (-) fixed charge.
FIG. 6 is a diagram for explaining the effect of the case where the first passivation layer described in FIGS. 1 to 3 is formed of positive fixed charge.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and similar reference numerals are attached to similar parts throughout the specification.

In the drawings, the thicknesses are enlarged in order to clearly express various layers and regions. Like reference numerals are attached to similar parts throughout the specification. When a part such as a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where the other part is "directly above", but also the case where there is another part in between. Conversely, when one part is "directly above" another part, it means that there is no other part in the middle. In addition, when a part is "overall" formed on another part, it means that it is formed not only on the entire surface (or the entire surface) of the other part, but also not formed on a part of the edge.

In addition, hereinafter, the front surface may be a surface of the semiconductor substrate to which direct sunlight is incident, and the rear surface may be a surface opposite to the semiconductor substrate to which direct sunlight is not incident or reflected light other than direct sunlight may be incident.

1 to 3 are diagrams for explaining a first embodiment of a solar cell according to the present invention.

Specifically, FIG. 1 is a partial perspective view of a solar cell according to the present invention, FIG. 2 (a) is a cross-sectional view of the solar cell shown in FIG. 1 taken along line II-II, and FIG. 3 is A diagram for explaining a planar pattern of the first passivation layer 191 in a solar cell.

1 and 2, the solar cell according to the first embodiment of the present invention includes a semiconductor substrate 110, a tunnel layer 120, an emitter part 121, a rear electric field part 172, and an intrinsic semiconductor. A layer 150, a first passivation layer 191, a second passivation layer 192, a first electrode 141 and a second electrode 142 may be included.

In such a solar cell, although not shown on the front surface of the semiconductor substrate 110, an antireflection film (not shown) and a front electric field unit (not shown) may be further formed.

In addition, in FIGS. 1 and 2, a case in which the tunnel layer 120 and the second passivation layer 192 are provided is illustrated as an example, but these may be omitted. However, as shown in FIGS. 1 and 2, since it is possible to further improve the efficiency of the solar cell when provided, the provided case will be described as an example.

The semiconductor substrate 110 may be formed of a single crystal silicon material doped with impurities of a first conductivity type, for example, an n-type conductivity type. When the semiconductor substrate 110 has an n-type conductivity type, impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) may be doped into the semiconductor substrate 110.

However, unlike this, the semiconductor substrate 110 may be a p-type conductivity type, and in this case, the semiconductor substrate 110 is an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In), etc. The semiconductor substrate 110 may be doped.

The semiconductor substrate 110 has an uneven surface by texturing the incident surface. For convenience, in FIG. 1, only the edge portion of the semiconductor substrate 110 is illustrated as an uneven surface, but substantially the entire front surface of the semiconductor substrate 110 may have an uneven surface.

Next, the tunnel layer 120 is disposed on the entire rear surface of the semiconductor substrate 110 and may include a dielectric material.

That is, the tunnel layer 120 is a semiconductor substrate 110 formed of a single crystal silicon material, a rear electric field part 172, an intrinsic semiconductor layer 150, and an emitter part 121, as shown in FIGS. 1 and 2 It may be formed between layers of a polycrystalline silicon material in which is formed.

More specifically, the tunnel layer 120 may be formed on the entire rear surface of the semiconductor substrate 110, passes the carriers generated in the semiconductor substrate 110, and performs a passivation function for the rear surface of the semiconductor substrate 110. can do.

As such, the tunnel layer 120 may be formed of a dielectric material made of SiCx or SiOx, which is durable even in a high temperature process of 600°C or higher. However, it can also be formed with silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON) or hydrogenerated SiON.

If a material containing amorphous silicon (a-Si) is used as the tunnel layer 120 differently, it may be difficult to expect a desired tunneling effect because amorphous silicon (a-Si) is vulnerable to a high temperature process of 600°C or higher. .

More specifically, when the tunnel layer 120 is formed of SiOx, the difference in the band offset voltage between the semiconductor substrate 110 and the tunnel layer 120 is large, and the thickness T120 of the tunnel layer 120 is It may be formed between 0.8nm ~ 1.2nm, when the tunnel layer 120 is formed of SiCx, the band offset voltage difference between the semiconductor substrate 110 and the tunnel layer 120 is relatively the tunnel layer ( The thickness T120 of 120) may be formed from 0.5 nm to 2.5 nm.

A plurality of emitter units 121 are disposed on a part of the rear surface of the tunnel layer 120 in a predetermined direction, and may be formed of a polycrystalline silicon material having a second conductivity type opposite to the first conductivity type. 121 may form a pn junction with the semiconductor substrate 110 with the tunnel layer 120 interposed therebetween.

Therefore, by the pn junction formed between the semiconductor substrate 110 and the plurality of emitter units 121, the electron-hole pair, which is the charge generated by the light incident on the semiconductor substrate 110, is separated into electrons and holes, so that the electrons are It moves toward the n-type and the hole moves toward the p-type. Therefore, when the semiconductor substrate 110 is n-type and the plurality of emitter parts 121 are p-type, separated holes move toward each emitter part 121 and the separated electrons have a higher impurity concentration than the semiconductor substrate 110. It can move toward a plurality of rear electric field units 172.

Since each emitter part 121 forms a pn junction with the semiconductor substrate 110, unlike the present embodiment, when the semiconductor substrate 110 has a p-type conductivity type, the emitter part 121 has n-type conductivity. It has a type. In this case, the separated electrons may move toward the plurality of emitter units 121 and the separated holes may move toward the plurality of rear electric field units 172.

When the plurality of emitter parts 121 have a p-type conductivity type, the emitter part 121 may be doped with an impurity of a trivalent element. Conversely, when the plurality of emitter parts 121 have an n-type conductivity type. , The emitter part 121 may be doped with an impurity of a pentavalent element.

The emitter part 121 is formed by forming an intrinsic semiconductor layer 150 made of a polycrystalline material on the rear surface of the semiconductor substrate 110 and then implanting a second conductive type impurity into the intrinsic semiconductor layer 150 made of a polycrystalline material. Can be.

A plurality of rear electric field units 172 may be formed by being longly disposed in the same direction as the emitter unit 121 in a portion of the rear surface of the tunnel layer 120 in which the plurality of emitter units 121 are not formed. The rear electric field 172 may be formed of a polycrystalline silicon material in which impurities of the first conductivity type are doped at a higher concentration than the semiconductor substrate 110. Thus, for example, when the substrate is doped with an n-type impurity, the plurality of rear electric field portions 172 may be n+ impurity regions.

The rear electric field part 172 prevents the movement of holes toward the rear electric field part 172, which is the direction of movement of electrons, due to a potential barrier due to the difference in impurity concentration between the semiconductor substrate 110 and the rear electric field part 172, It facilitates the movement of electric charges (eg, electrons) toward the rear electric field part 172. Accordingly, the amount of charge lost due to the recombination of electrons and holes in the rear electric field unit 172 and its vicinity or the first and second electrodes 141 and 142 is reduced, and electron transfer is accelerated to the rear electric field unit 172. The amount of electron movement can be increased.

The rear electric field unit 172 and the emitter unit 121 may be spaced apart from each other, as shown in FIGS. 1 and 2.

Here, the thickness of the emitter part 121 and the rear electric field part 172 may be formed between 100 nm and 300 nm.

In addition, in FIGS. 1 and 2, the emitter portion 121 and the rear electric field portion 172 have the same thickness, but the emitter portion 121 and the rear electric field portion 172 may have different thicknesses. The 121 and the rear electric field 172 may have resistance values between 50 Ω and 300 Ω per unit area.

The intrinsic semiconductor layer 150 may be formed in a space spaced apart between the emitter unit 121 and the rear electric field unit 172 among the rear surface of the tunnel layer 120, and such an intrinsic semiconductor layer 150 is an emitter unit ( 121) and the rear electric field portion 172 may be formed of a polycrystalline silicon material that is not doped with p-type or n-type impurities.

Since the intrinsic semiconductor layer 150 is formed in a space spaced apart between the emitter part 121 and the rear electric field part 172, the intrinsic semiconductor layer 150 has one side of the intrinsic semiconductor layer 150 The first bonding surface JIE bonded to the side surface of 121) and the other side surface may include a second bonding surface JIB bonded to the side surface of the rear electric field part 172.

The first passivation layer 191 may be disposed on the first bonding surface JIE where side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121 are bonded to each other. The first passivation layer 191 will be described after the first electrode 141 and the second electrode 142 are described.

The second passivation layer 192 may be disposed on the intrinsic semiconductor layer 150 and the first passivation layer 191. The second passivation layer 192 will be described in detail after the first passivation layer 191 is described in detail.

The first electrode 141 may be plural, positioned on the plurality of emitter units 121 and extending along the plurality of emitter units 121, and may be electrically and physically connected to the plurality of emitter units 121 . Accordingly, each of the first electrodes 141 may collect charges, for example, holes, which have moved toward the emitter unit 121.

The second electrode 142 may also be plural, located on the plurality of rear electric field units 172 and extending along the plurality of rear electric field units 172, and the plurality of rear electric field units 172 and electrical and Can be physically connected. Accordingly, each second electrode 142 may collect electric charges, for example, electrons moving toward the corresponding rear electric field unit 172.

The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), gold (Au) and these It may be made of at least one conductive material selected from the group consisting of a combination of, or alternatively, may be formed of a transparent conductive metal, for example, TCO.

The operation of the solar cell according to the present embodiment having such a structure is as follows.

When light is irradiated to the solar cell and incident on the semiconductor substrate 110, electron-hole pairs are generated in the semiconductor substrate 110 by light energy. These electron-hole pairs are separated from each other by the pn junction of the semiconductor substrate 110 and the emitter part 121, so that the holes move toward the emitter part 121 having a p-type conductivity type, and the electrons are of the n-type conductivity type. It moves toward the rear electric field part 172 having a, is transferred to the first electrode 141 and the second electrode 142, respectively, and is collected by the first and second electrodes 141 and 142. When the first electrode 141 and the second electrode 142 are connected with a conductive line, a current flows, which can be used as electric power from the outside.

Meanwhile, as described above, in the solar cell according to the present invention, as shown in FIGS. 1 to 3, the first passivation layer 191 is bonded to the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121. It may be disposed on the first bonding surface JIE.

In addition, the first passivation layer 191 is not disposed on the second bonding surface JIB where the side surfaces of the intrinsic semiconductor layer 150 and the rear electric field part 172 are bonded to each other, but as viewed from the rear surface of the semiconductor substrate 110. At this time, the first passivation layer 191 and the rear electric field part 172 may not overlap each other and may be spaced apart.

Specifically, the solar cell according to the present invention will be described with reference to FIG. 3 viewed from the rear side of the semiconductor substrate 110. 3 is a partial view of the rear surface of the semiconductor substrate 110 in which the second passivation layer 192 is omitted from the first electrode 141 and the second electrode 142 among the constituent elements of the solar cell described above.

2 and 3, when viewed from the rear surface of the semiconductor substrate 110, the first passivation layer 191 is a part of the intrinsic semiconductor layer 150 and the emitter of the first bonding surface JIE. It may overlap with a part of the tab 121.

More specifically, as shown in FIGS. 2 and 3, the first passivation layer 191 overlapping with a part of the intrinsic semiconductor layer 150 is in the direction of the rear electric field part 172 of the first passivation layer 191. 1/ of the distance (DBE) from the first junction surface (JIE) to the rear electric field part 172 (or the second junction surface (JIB)) in the rear area of the intrinsic semiconductor layer 150 at the end 191EB of the intrinsic semiconductor layer 150 It can be formed to be located up to the point of 5 to 4/5.

Here, the first passivation layer 191 is longer than 1/5 of the distance DBE from the first bonding surface JIE to the rear electric field part 172 (or the second bonding surface JIB). By being formed, it is possible to prevent junction leakage in which current is lost due to recombination at the first junction surface JIE.

In addition, the first passivation layer 191 is formed longer than 4/5 of the distance (DBE) from the first bonding surface (JIE) to the rear electric field part 172 (or the second bonding surface (JIB)). Thus, when the rear electric field portion 172 is formed, the carrier collected by the emitter portion 121 is moved to the rear electric field portion 172 along the surface of the first passivation layer 191 to cause junction leakage. The first passivation layer 191 is 4/5 of the distance (DBE) from the first junction surface (JIE) to the rear electric field part 172 (or the second junction surface (JIB)). By forming shorter than the point, it is possible to prevent such junction leakage, and also, while preventing such junction leakage, it is possible to reduce the manufacturing cost of the first passivation layer 191.

Also, the first passivation layer 191 may overlap a part of the emitter part 121.

Here, the width of the first passivation layer 191 overlapping the emitter unit 121 is not particularly limited, or the entire area other than the portion connected to the first electrode 141 in the emitter unit 121 is not overlapped. They can also be overlapped.

For example, as shown in FIG. 3, when viewed from the rear side of the semiconductor substrate 110, the first passivation layer 191 exposes a part of the emitter unit 121, so that the first electrode 141 is an emitter unit. A plurality of openings OP191 may be formed to be connected to the 121. The openings OP191 of the first passivation layer 191 may be arranged to be spaced apart from each other in a line along the length direction of the emitter part 121. That is, the opening OP191 of the first passivation layer 191 may be formed in an island shape.

However, unlike FIG. 3, the openings OP191 of the first passivation layer 191 are not formed in plural, but may be formed as one, but may be formed to extend along the length direction of the emitter part 121.

In this way, the first electrode 141 may be directly connected to and connected to the emitter unit 121 as described in FIGS. 1 and 2 through the opening OP191 of the first passivation layer 191.

Here, the thickness T191 of the first passivation layer 191 may be formed between 150 nm and 250 nm. Here, the thickness (T191) of the first passivation layer 191 is made larger than 150 nm in order to at least secure the function of preventing junction leakage of the first passivation layer 191, and the thickness of the first passivation layer 191 ( T191) is made smaller than 250 nm in order to minimize the manufacturing cost for the first passivation layer 191.

As such, the first passivation layer 191 may have a fixed charge (Qf) having the same polarity as the first conductivity.

As an example, when the first conductivity type of the semiconductor substrate 110 and the rear electric field part 172 is n-type, the first passivation layer 191 may be a dielectric layer having a (-) fixed charge. The passivation layer 191 may be formed of aluminum oxide (AlOx). In this case, the concentration of the fixed charge included in the first passivation layer 191 may be -5*10 ¹¹ /cm2 to -1*10 ¹³ /cm2.

In addition, when the first conductivity type of the semiconductor substrate 110 and the rear electric field part 172 is p-type, the first passivation layer 191 may be a dielectric layer having a (+) fixed charge. For example, the first passivation The layer 191 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

As described above, in the solar cell according to the present invention, the first passivation layer 191 having a fixed charge (Qf) having the same polarity as the first conductivity is formed on the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121. The carriers (eg, electrons) generated in the semiconductor substrate 110 are formed on the first bonding surface JIE bonded to each other, and the carriers (eg holes) collected by the emitter unit 121 and the first bonding surface ( In JIE), it is possible to prevent junction leakage in which current is lost due to recombination.

In addition, the first passivation layer 191 may perform a passivation function for a part of the intrinsic semiconductor layer 150 and the surface of the emitter unit 121.

In this way, the solar cell according to the present invention minimizes the loss of current recombined at the first junction surface JIE to prevent reduction of the open-circuit voltage (Voc) and fill factor (FF), and as a result, It can prevent the efficiency from being lowered. This will be described in more detail below in FIG. 4A.

In addition, in FIGS. 1 and 2, the second passivation layer 192 disposed on the intrinsic semiconductor layer 150 and the first passivation layer 191 is specifically, the first passivation layer 191 in the intrinsic semiconductor layer 150. It may be disposed so as to cover all of the remaining areas that are not disposed and the first passivation layer 191.

Specifically, the second passivation layer 192 may be disposed to overlap the entire region of the intrinsic semiconductor layer 150 when viewed from the rear surface of the semiconductor substrate 110 and may be disposed on the second bonding surface JIB, A part of the second passivation layer 192 may overlap the rear electric field part 172.

In addition, the second passivation layer 192 may overlap the intrinsic semiconductor layer 150 and the first passivation layer 191 formed on a part of the emitter part 121 when viewed from the rear surface of the semiconductor substrate 110. Accordingly, the second passivation layer 192 may be positioned on the first passivation layer 191 to overlap the first passivation layer 191 disposed on the first junction surface JIE of the intrinsic semiconductor layer 150.

The second passivation layer 192 may have a fixed charge having a polarity opposite to that of the first passivation layer 191.

Specifically, when the first passivation layer 191 is formed of a dielectric layer having a (-) fixed charge, for example aluminum oxide (AlOx), the second passivation layer 192 is a dielectric layer having a (+) fixed charge, for example , It may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

In addition, on the contrary, when the first passivation layer 191 is formed of a dielectric layer having a (+) fixed charge, for example, silicon nitride (SiNx) or silicon oxide (SiOx), the second passivation layer 192 is ( -) A dielectric layer having a fixed charge, for example, may be formed of aluminum oxide (AlOx).

The thickness of the second passivation layer 192 may be equal to or smaller than the thickness T191 of the first passivation layer 191.

Such a second passivation layer 192 may facilitate the movement of a carrier moving in the direction of the rear electric field part 172 from the semiconductor substrate 110, and the intrinsic semiconductor layer 150 and the rear electric field part 172 ) Can perform a passivation function on the surface.

Until now, the structure of the solar cell according to the exemplary embodiment of the present invention has been described, but hereinafter, the function of the first passivation layer 191 in the solar cell structure will be described in more detail.

4A to 4B are diagrams for explaining a comparative example without a first passivation layer 191 unlike the solar cell structure of the present invention, and FIG. 5 is a diagram illustrating the first passivation layer 191 described in FIGS. 1 to 3. A diagram for explaining the effect when formed with (-) fixed charge, and FIG. 6 is a diagram for explaining the effect when the first passivation layer 191 described in FIGS. 1 to 3 is formed with (+) fixed charge to be.

Here, FIG. 4A shows a polarity of the same polarity as that of the first conductivity on the first bonding surface JIE where the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121 are bonded to each other, unlike the present invention shown in FIGS. It is a comparative example showing a structure without the first passivation layer 191 having a fixed charge, and FIG. 4B is a diagram showing changes in current and voltage according to the amount of current Jo2 lost due to junction leakage. It is a graph, and FIG. 4C is a graph showing the relationship between the open-circuit voltage (Voc), the fill factor (FF), and the efficiency according to the amount of the current (Jo2) lost due to junction leakage.

First, different from the present invention, as shown in FIG. 4A, a fixed charge having the same polarity as the first conductivity is on the first bonding surface JIE where the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121 are bonded to each other. In the absence of the first passivation layer 191 having, electrons generated in the semiconductor substrate 110 move to the rear electric field 172 through the tunnel layer 120, or the tunnel layer 120 and the intrinsic semiconductor layer ( 150 may move to the rear electric field part 172, and holes generated in the semiconductor substrate 110 may move to the emitter part 121 through the tunnel layer 120.

Here, as shown in FIG. 4A, some of the electrons moving to the rear electric field part 172 through the tunnel layer 120 and the intrinsic semiconductor layer 150 and some of the holes moving to the emitter part 121 are intrinsic. The side surfaces of the semiconductor layer 150 and the emitter unit 121 may be recombined to each other at the first bonding surface JIE to be bonded to each other and disappear.

In this way, when electrons and holes are recombined to each other in the first junction surface JIE, carriers are eliminated, which is referred to as junction leakage.

Here, as shown in FIG. 4B, it can be seen that as the amount of leakage current Jo2 extinguished by recombination of carriers increases, the voltage generated in the solar cell decreases, and accordingly, the fill factor FF is also It can be seen that it decreases.

In addition, as the amount of the leakage current Jo2 increases, as shown in FIG. 4C, it can be seen that the reduction ratio of the open-circuit voltage (Voc), the fill factor (FF), and the efficiency (efficiency) increases exponentially. have.

That is, the reduction ratio of open-circuit voltage (Voc), fill factor (FF), and efficiency (efficiency) does not increase in proportion to the amount of leakage current (Jo2), but as the amount of leakage current (Jo2) increases, the open-circuit voltage (Voc) ), it can be seen that the rate of decrease in the fill factor (FF) and efficiency increases in the form of exponential (e).

As described above, it can be seen that the amount of leakage current Jo2 due to junction leakage has a very large influence on the open circuit voltage (Voc), the fill factor (F.F), and the efficiency.

However, as in the present invention, the first passivation layer 191 having a fixed charge of the same polarity as the first conductivity on the first bonding surface JIE where the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121 are bonded to each other. ), it is possible to prevent junction leakage as described above.

For example, as shown in FIG. 5, the first conductivity type of the semiconductor substrate 110 and the rear electric field part 172 is n-type, the second conductivity type of the emitter part 121 is p-type, and the intrinsic semiconductor layer When the first passivation layer 191 having a fixed charge of the same (-) polarity as that of the n-type is provided on the first bonding surface JIE where the side surfaces of the emitter unit 121 are bonded to each other, the tunnel layer Electrons moving to the rear electric field part 172 through 120 and the intrinsic semiconductor layer 150 cannot move toward the emitter part 121 due to the negative polarity of the first passivation layer 191.

Accordingly, the solar cell according to the present invention may prevent junction leakage as described above in FIGS. 4A to 4C, thereby improving efficiency.

In addition, when a second passivation layer 192 having a fixed charge of (+) polarity opposite to the fixed charge of (-) polarity of the first passivation layer 191 is further formed, as shown in FIG. Electrons moving to the rear electric field unit 172 through the layer 120 and the intrinsic semiconductor layer 150 may more efficiently move to the rear electric field unit 172.

In addition, as shown in FIG. 6, the first conductivity type of the semiconductor substrate 110 and the rear electric field part 172 is p-type, and the second conductivity type of the emitter part 121 is n-type, and the first bonding surface When the first passivation layer 191 having a fixed charge of the same (+) polarity as that of the p-type is provided on the (JIE), it is transferred to the rear electric field part 172 through the tunnel layer 120 and the intrinsic semiconductor layer 150. The moving holes cannot move toward the emitter part 121 due to the (+) polarity of the first passivation layer 191.

In addition, when a second passivation layer 192 having a fixed charge of negative (-) polarity opposite to the fixed charge of the first passivation layer 191 is further formed, as shown in FIG. 5, the tunnel layer 120 and the Holes moving to the rear electric field unit 172 through the intrinsic semiconductor layer 150 may more efficiently move to the rear electric field unit 172.

As described above, in the solar cell according to the present invention, a fixed charge having the same polarity as the conductivity of the semiconductor substrate 110 is applied on the first bonding surface JIE where the side surfaces of the intrinsic semiconductor layer 150 and the emitter unit 121 are bonded to each other. By arranging the having the first passivation layer 191, the junction leakage in which some carriers are recombined between the intrinsic semiconductor layer 150 and the emitter unit 121 is improved, and thus the efficiency of the solar cell is further improved. Can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also present. It belongs to the scope of rights of

Claims (15)

A semiconductor substrate containing impurities of a first conductivity type;
An emitter unit disposed on a rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
A rear electric field unit disposed on a rear surface of the semiconductor substrate to be spaced apart from the emitter unit and containing an impurity of the first conductivity type in a higher concentration than the semiconductor substrate;
An intrinsic semiconductor layer disposed in a space between the emitter portion and the rear electric field portion of the rear surface of the semiconductor substrate;
A first bonding surface comprising a first portion overlapping a portion of the rear surface of the emitter portion and a second portion overlapping a portion of the rear surface of the intrinsic semiconductor layer, wherein a side surface of the intrinsic semiconductor layer and a side surface of the emitter portion are bonded to each other A first passivation layer disposed thereon;
A first electrode connected to the emitter and collecting second electric charges of the second conductivity type; And
A second electrode connected to the rear electric field and collecting a first charge of the first conductivity type; and
The first passivation layer has a fixed charge (Qf) having the same polarity as that of the first conductivity type, and prevents the first charge from flowing toward the first junction surface through the intrinsic semiconductor layer. A solar cell that prevents recombination of the first charge and the second charge on a first junction surface. The method of claim 1,
The first passivation layer does not overlap with the rear electric field part. delete The method of claim 2,
The second portion of the first passivation layer is located to a point 1/5 to 4/5 of the distance from the first junction surface to the rear electric field in the rear area of the intrinsic semiconductor layer. The method of claim 1,
The thickness of the first passivation layer is between 150nm ~ 250nm solar cell. The method of claim 1,
The first conductivity type is n-type,
The first passivation layer is a dielectric layer having a (-) fixed charge. The method of claim 6,
The first passivation layer is a solar cell formed of aluminum oxide (AlOx). The method of claim 1,
The first conductivity type is p-type,
The first passivation layer is a dielectric layer having a (+) fixed charge. The method of claim 8,
The first passivation layer is a solar cell formed of silicon nitride (SiNx) or silicon oxide (SiOx). The method of claim 1,
A solar cell further comprising: a second passivation layer having a fixed charge having a polarity opposite to that of the first passivation layer on a rear surface of the intrinsic semiconductor layer and a rear surface of the first passivation layer. The method of claim 10,
The second passivation layer is disposed so as to cover all of the first passivation layer and the rest area of the intrinsic semiconductor layer in which the first passivation layer is not disposed. The method of claim 1,
The thickness of the emitter part and the rear electric field part is between 100 nm and 300 nm. The method of claim 1,
A tunnel layer comprising a dielectric material between the semiconductor substrate and the layer in which the rear electric field part, the intrinsic semiconductor layer, and the emitter part are formed, and passing carriers generated in the semiconductor substrate; a solar cell further disposed. The method of claim 13,
The tunnel layer is a dielectric layer formed of SiCx or SiOx solar cell. The method of claim 13,
The tunnel layer is a solar cell having a thickness between 0.5nm ~ 2.5nm.

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