KR20160028242A - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

Info

Publication number
KR20160028242A
KR20160028242A KR1020140117063A KR20140117063A KR20160028242A KR 20160028242 A KR20160028242 A KR 20160028242A KR 1020140117063 A KR1020140117063 A KR 1020140117063A KR 20140117063 A KR20140117063 A KR 20140117063A KR 20160028242 A KR20160028242 A KR 20160028242A
Authority
KR
South Korea
Prior art keywords
portion
upper surface
active pattern
substrate
formed
Prior art date
Application number
KR1020140117063A
Other languages
Korean (ko)
Inventor
정수연
이동구
이태종
임재포
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020140117063A priority Critical patent/KR20160028242A/en
Publication of KR20160028242A publication Critical patent/KR20160028242A/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1116Peripheral circuit region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An objective of the present invention is to provide a semiconductor device and a manufacturing method thereof which reduce a height of a pin playing a role of a seed of an epitaxial film used as a source/drain to reduce a size of the source/drain and improve reliability. The semiconductor device comprises: a first pin-shaped active pattern which is formed on a substrate, is extended in a first direction, and comprises a first to a third portion sequentially arranged in the first direction, and wherein a height from an upper surface of the substrate to an upper surface of the first portion is higher than a height from the upper surface of the substrate to an upper surface of the second portion, and the height from the upper surface of the substrate to the upper surface of the second portion is higher than a height from the upper surface of the substrate to an upper surface of the third portion; a gate electrode extended in a second direction different from the first direction, and formed on the first portion; and a first source/drain formed on the third portion.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

The present invention relates to a semiconductor device and a method of manufacturing the same.

As one of scaling techniques for increasing the density of semiconductor devices, there is a multi-gate technique for forming a fin-shaped silicon body on a substrate and forming a gate on the surface of the silicon body. Transistors have been proposed.

Since such a multi-gate transistor uses a three-dimensional channel, scaling is easy. Further, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

A problem to be solved by the present invention is to provide a semiconductor device capable of reducing the size of a source / drain and improving reliability by reducing the height of a pin serving as a seed of an epitaxial film used as a source / drain.

Another object of the present invention is to provide a semiconductor device manufacturing method capable of reducing the size of a source / drain and improving reliability by reducing the height of a pin serving as a seed of an epitaxial film used as a source / drain will be.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

An aspect of the semiconductor device of the present invention for solving the above problems is a first pinned active pattern formed on a substrate and extending in a first direction and including first through third portions, Wherein a height from an upper surface of the substrate to an upper surface of the first portion is higher than a height from an upper surface of the substrate to an upper surface of the second portion, The height from the upper surface of the first portion to the upper surface of the second portion is higher than the height from the upper surface of the substrate to the upper surface of the third portion, the second pinned active pattern extending in the second direction different from the first direction, And a first source / drain formed on the third portion.

In some embodiments of the present invention, a field insulating film formed on the substrate and in contact with a part of the sidewalls of the first pinned active pattern, the sidewalls of the third portion being entirely in contact with the field insulating film.

In some embodiments of the present invention, at a first height from an upper surface of the field insulating film, the width of the first portion is larger than the width of the second portion.

In some embodiments of the present invention, the top surface of the second portion and the top surface profile of the first portion are discontinuous, and both side walls of the second portion facing in the second direction, The profiles of both side walls of the first portion are discontinuous.

In some embodiments of the present invention, the first portion includes a connecting sidewall, the connecting sidewall connects an upper surface of the first portion and an upper surface of the second portion, Connect the two side walls.

In some embodiments of the invention, the device further comprises a gate spacer formed on the second portion and extending in the second direction, the gate spacer overlapping the connecting sidewall.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; a first transistor formed in the first region, wherein the first transistor is formed on the substrate A first pinned active pattern extending in a first direction and including first through third portions, the first through third portions being sequentially arranged in the first direction; and a second pinned active pattern extending in a second direction different from the first direction A first transistor including a first gate electrode formed on the first portion and a first source / drain formed on the third portion, and a second transistor formed in the second region, 2 transistor is formed on the substrate and extends in a third direction and includes fourth to sixth portions, and the fourth to sixth portions are formed in a second pinned active A second gate electrode extending in a fourth direction different from the third direction and formed on the fourth portion, and a second transistor including a second source / drain formed on the sixth portion The height from the upper surface of the substrate to the upper surface of the first portion is higher than the height from the upper surface of the substrate to the upper surface of the second portion, Wherein a height from an upper surface of the substrate to an upper surface of the third portion and a height from an upper surface of the substrate to an upper surface of the fourth portion and a height from an upper surface of the substrate to an upper surface of the fifth portion, 6 < / RTI >

In some embodiments of the present invention, the height from the upper surface of the substrate to the upper surface of the fourth portion is equal to the height from the upper surface of the substrate to the upper surface of the fifth portion.

In some embodiments of the present invention, the first transistor further comprises a first gate spacer formed on the second portion, and the second transistor further comprises a second gate spacer formed on the fifth portion do.

In some embodiments of the present invention, a field insulating film formed on the substrate and in contact with a part of the sidewalls of the first pinned active pattern, the sidewalls of the third portion being entirely in contact with the field insulating film.

In some embodiments of the present invention, the first area is an SRAM area, and the second area is a logic area.

In some embodiments of the present invention, the first region is a PMOS forming region of the SRAM, and the second region is an NMOS forming region of the SRAM.

In some embodiments of the present invention, the width of the second source / drain in the fourth direction is larger than the width of the first source / drain in the second direction.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; a first transistor formed in the first region; A first pinned active pattern extending in a first direction and including a first portion and a second portion and the second portion disposed on both sides in the first direction about the first portion, A first transistor including a first gate electrode extended in another second direction and formed on the first portion, and a first source / drain formed on the second portion, and a second transistor formed on the second region, 2 transistor, wherein the second transistor is formed on the substrate and extends in a third direction and includes a third portion and a fourth portion, and the fourth portion is formed on the substrate in the third direction A second gate electrode formed on the first portion and a second source / drain formed on the fourth portion; a second gate electrode formed on the first portion, And a width of the second source / drain in the fourth direction is larger than a width of the first source / drain in the second direction.

In some embodiments of the present invention, the height from the top surface of the substrate to the top surface of the first portion is higher than the height from the top surface of the substrate to the top surface of the second portion, Is higher than the height from the upper surface of the substrate to the upper surface of the fourth portion.

In some embodiments of the present invention, the first fin-shaped active pattern includes a fifth portion disposed between the first portion and the second portion, wherein a height from an upper surface of the substrate to an upper surface of the fifth portion is greater than a height Is lower than the height from the upper surface of the substrate to the upper surface of the first portion and higher than the height from the upper surface of the substrate to the upper surface of the second portion.

In some embodiments of the present invention, the height from the upper surface of the substrate to the upper surface of the third portion is higher than the height from the upper surface of the substrate to the upper surface of the first portion.

In some embodiments of the present invention, the height of the second source / drain is higher than the height of the first source / drain.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; a first transistor formed in the first region; A first pinned active pattern extending in a first direction and including a first portion and a second portion and the second portion disposed on both sides in the first direction about the first portion, A first transistor including a first gate electrode extended in another second direction and formed on the first portion, and a first source / drain formed on the second portion, and a second transistor formed on the second region, 2 transistor, wherein the second transistor is formed on the substrate and extends in a third direction and includes a third portion and a fourth portion, and the fourth portion is formed on the substrate in the third direction A second gate electrode formed on the first portion and a second source / drain formed on the fourth portion; a second gate electrode formed on the first portion, Wherein a height from an upper surface of the substrate to an upper surface of the first portion is higher than a height from an upper surface of the substrate to an upper surface of the second portion, The height from the upper surface of the substrate to the upper surface of the fourth portion is higher than the height from the upper surface of the substrate to the upper surface of the third portion, Respectively.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including first to third portions defined by a field insulating film and extending in a first direction and sequentially arranged in the first direction, Forming a dummy gate electrode extending in a second direction different from the first direction on the first portion and intersecting with the pinned active pattern, The second portion and the third portion protruding above the upper surface of the field insulating film are trimmed using the dummy gate electrode as a mask, and after the trimming, gate spacers are formed on the sidewalls of the second portion and the dummy gate electrode Forming a recess in the third portion using the dummy gate electrode as a mask, and forming, on the third portion, Filling the recess includes forming a source / drain.

Other specific details of the invention are included in the detailed description and drawings.

1 is a perspective view illustrating a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a view showing only the pinned active pattern and the field insulating film in Fig. 1. Fig.
3 and 4 are sectional views taken along line A - A, B - B, C - C and D - D, respectively, of the semiconductor device of FIG.
5 and 6 are views for explaining a semiconductor device according to a second embodiment of the present invention.
7 to 9 are views for explaining a semiconductor device according to a third embodiment of the present invention.
10 is a perspective view illustrating a semiconductor device according to a fourth embodiment of the present invention.
11 is a cross-sectional view taken along line A-A and E-E in Fig.
12 is a cross-sectional view taken along line C-C and F-F in Fig.
13 is a cross-sectional view taken along line D-D and G-G in Fig.
14 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention.
15 to 17 are views for explaining a semiconductor device according to a sixth embodiment of the present invention.
18 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment of the present invention.
19 to 21 are views for explaining a semiconductor device according to an eighth embodiment of the present invention.
22 and 23 are a circuit diagram and a layout diagram for explaining a semiconductor device according to a ninth embodiment of the present invention.
24 is a conceptual diagram for explaining a semiconductor device according to a tenth embodiment of the present invention.
FIGS. 25 to 32 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
33 and 34 are intermediate diagrams for explaining a semiconductor device manufacturing method according to another embodiment of the present invention.
35 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the present invention.
36 and 37 are exemplary semiconductor systems to which a semiconductor device according to some embodiments of the present invention may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

1 is a perspective view illustrating a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a view showing only the pinned active pattern and the field insulating film in Fig. 1. Fig. 3 and 4 are sectional views taken along line A - A, B - B, C - C and D - D, respectively, of the semiconductor device of FIG. For convenience of explanation, the interlayer insulating film 150 is not shown in Fig.

1 to 4, a semiconductor device 1 according to a first embodiment of the present invention includes a substrate 100, a field insulating film 105, a first finned active pattern 110, a first gate electrode 120 A first gate spacer 140, a first source / drain 130, and the like.

The substrate 100 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide . Alternatively, the substrate 100 may have an epilayer formed on the base substrate.

The first pinned active pattern 110 may protrude from the substrate 100 and be formed on the substrate 100. The first pinned active pattern 110 protrudes above the field insulating film 105 formed on the substrate 100 because the field insulating film 105 covers a part of the side wall of the first pinned active pattern 110. [ The field insulating film 105 is in contact with a part of the side wall of the first pinned active pattern 110. The first pinned active pattern 110 is defined by a field insulating film 105.

The first fin-shaped active pattern 110 may be elongated along the first direction X1. The first pinned active pattern 110 includes a first portion 111, a second portion 112, and a third portion 113. The first portion 111, the second portion 112 and the third portion 113 of the first pinned active pattern 110 may be sequentially arranged in the first direction X1.

In other words, the second portion 112 of the first pinned active pattern is disposed on both sides in the first direction X1 about the first portion 111 of the first pinned active pattern. Also, the third portion 113 of the first pinned active pattern is disposed on both sides in the first direction X1 about the first portion 111 of the first pinned active pattern.

2, the upper surface 111u of the first portion 111 of the first fin-shaped active pattern and the upper surface 112u of the second portion 112 of the first fin-shaped active pattern are formed on the upper surface 105u of the field insulating film ). The top surface 113u of the third portion 113 of the first pinned active pattern may not protrude above the top surface 105u of the field insulating film, but is not limited thereto.

The first portion 111 of the first pinned active pattern and the second portion 112 of the first pinned active pattern may protrude above the field insulating layer 105 and the third portion 113 of the first pinned active pattern And may not protrude above the field insulating film 105. The side wall 113s of the third portion 113 of the first pinned active pattern can be entirely in contact with the field insulating film 105. [

The height from the upper surface of the substrate 100 to the upper surface 111u of the first portion 111 of the first pinned active pattern is the first height h1 and the height from the upper surface of the substrate 100 to the second The height from the top surface of the substrate 100 to the top surface 113u of the third portion 113 of the first pinned active pattern is a height (h3).

The second portion 112 of the first pinned active pattern is recessed relative to the first portion 111 of the first pinned active pattern and the third portion 113 of the first pinned active pattern is recessed And is recessed from the second portion 112.

In other words, the height h1 from the upper surface of the substrate 100 to the upper surface 111u of the first portion 111 of the first pinned active pattern is greater than the height h1 from the upper surface of the substrate 100 to the second portion of the first pinned active pattern Is higher than the height h2 to the upper surface 112u of the base plate 112. [ The height h2 from the upper surface of the substrate 100 to the upper surface 112u of the second portion 112 of the first pinned active pattern is greater than the height h2 from the upper surface of the substrate 100 to the third portion of the first pinned active pattern 113) to the upper surface (113u).

The height h1 from the top surface of the substrate 100 to the top surface 111u of the first portion 111 of the first pinned active pattern is greater than the height h1 from the top surface of the substrate 100 to the second portion 112 of the first pinned active pattern, The upper surface 111u of the first portion 111 of the first pinned active pattern and the upper surface 112u of the second portion 112 of the first pinned active pattern are higher than the height h2 of the second pinned active pattern 112a ) May not be continuous.

That is, between the top surface 111u of the first portion 111 of the first pinned active pattern and the second portion 112 of the first pinned active pattern, for example, there may be a step like a step.

The first portion 111 of the first pinned active pattern may include a side wall 111s facing in the second direction Y1 and a connecting side wall 111c facing in the first direction X1. The second portion 112 of the first pinned active pattern may include sidewalls 112s facing in a second direction Y1 and connecting sidewalls 112c facing in a first direction X1.

As shown in Fig. 2, a first pinned active pattern 111a facing the side wall 111s of the first portion 111 of the first pinned active pattern facing in the second direction Y1 in the second direction Y1, The profile of the sidewalls 112s of the second portion 112 of the first portion 112 may not be continuous but is not limited thereto.

That is, the side wall 111s of the first part 111 of the first pinned active pattern facing in the second direction Y1 and the second part 112 of the first pinned active pattern facing in the second direction Y1 May be continuous and only the second portion 112 of the first pinned active pattern may be recessed than the first portion 111 of the first pinned active pattern.

However, for convenience of explanation, in the semiconductor device according to the embodiments of the present invention, the upper surface 111u and the sidewall 111s of the first portion 111 of the first pinned active pattern are respectively connected to the second The upper surface 112u of the portion 112 and the side wall 112s.

The connecting sidewall 111c of the first portion 111 of the first pinned active pattern is connected to the top surface 111u of the first portion 111 of the first pinned active pattern and the second portion 112 of the first pinned active pattern And connects the upper surface 112u. The connecting sidewall 111c of the first portion 111 of the first pinned active pattern is also connected to the side wall 111s of the first portion 111 of the first pinned active pattern and the second portion 112 of the first pinned active pattern To the side walls 112s of the first and second plates.

At a boundary between the first pinned active pattern 110 and the top surface 105u of the field insulating film, a first width w1 of the first portion 111 of the first pinned active pattern and a second width w1 of the second pinned active pattern The second width w2 of the portion 112 and the third width w3 of the third portion 113 of the first pinned active pattern are equal to each other.

However, at a point apart from the top surface 105u of the field insulating film by the first distance L onto the field insulating film 105, the width w11 of the first portion 111 of the first pinned active pattern, The width w21 of the second portion 112 of the pinned active pattern may be different from each other. For example, the width w11 of the first portion 111 of the first pinned active pattern may be greater than the width w21 of the second portion 112 of the first pinned active pattern.

For convenience of explanation, the top surface 105u of the field insulating film is shown as being flat, but it is not limited thereto. In the semiconductor device according to the embodiments of the present invention, the first distance L from the upper surface 105u of the field insulating film 105 to the field insulating film 105 is the distance between the first finned active pattern 110 and the upper surface 105u of the field insulating film, The measurement is based on the point of contact.

The width of the first pinned active pattern 110 at the portion contacting the field insulating film 105 and the width of the first pinned active pattern 110 at the boundary between the second portion 112 of the first pinned active pattern and the top surface 105u of the field insulating film, The width of the first pinned active pattern 110 of the protruding portion may be equal to the second width w2, but is not limited thereto.

The first pinned active pattern 110 may be part of the substrate 100 and may include an epitaxial layer grown from the substrate 100. The first pinned active pattern 110 may comprise, for example, silicon or germanium, which is an elemental semiconductor material. In addition, the first fin-shaped active pattern 110 may include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor. Specifically, as an example of the IV-IV group compound semiconductor, the first pinned active pattern 110 is a binary type active layer including at least two of carbon (C), silicon (Si), germanium (Ge), and tin A binary compound, a ternary compound, or a compound doped with a Group IV element thereon. The first pinned active pattern 110 is a group III element and includes at least one of aluminum (Al), gallium (Ga), indium (In) and indium (In) A ternary compound, a ternary compound or a siliceous compound in which one of arsenic (As) and antimony (Sb) is combined and formed.

In the semiconductor device according to the embodiments of the present invention, the first pinned active pattern 110 is described as including silicon.

The first gate electrode 120 may extend in the second direction Y1 and intersect the first pinned active pattern 110. [ The first gate electrode 120 may be formed on the first finned active pattern 110 and the field insulating film 105. More specifically, the first gate electrode 120 is formed on the first portion 111 of the first pinned active pattern.

The first gate electrode 120 may include metal layers MG1 and MG2. The first gate electrode 120 may be formed by stacking two or more metal layers MG1 and MG2, as shown in FIG. The first metal layer MG1 functions to control the work function and the second metal layer MG2 functions to fill a space formed by the first metal layer MG2. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, and TaC. Further, the second metal layer MG2 may include, for example, W or Al. Alternatively, the first gate electrode 120 may be made of Si, SiGe or the like instead of a metal. The first gate electrode 120 may be formed through, for example, a replacement process, but is not limited thereto.

The first gate spacer 140 may be formed on the sidewall of the first gate electrode 120 extending in the second direction Y1.

A first gate spacer 140 may be formed on the second portion 112 of the first pinned active pattern. More specifically, the first gate spacer 140 may be formed on the upper surface 112u and the sidewalls 112s of the second portion 112 of the first fin-shaped active pattern protruding above the field insulating film 105. [

The height h1 from the top surface of the substrate 100 to the top surface 111u of the first portion 111 of the first pinned active pattern is greater than the height h1 from the top surface of the substrate 100 to the second portion 112 of the first pinned active pattern, A portion of the first gate spacer 140 may overlap with the connecting sidewall 111c of the first portion 111 of the first pinned active pattern because it is higher than the height h2 to the top surface 112u of the first pinned active pattern. For example, a portion of the first gate spacer 140 may contact the connecting sidewall 111c of the first portion 111 of the first pinned active pattern.

A first gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon shot nitride (SiOCN) and at least one of a combination of . Although the first gate spacer 140 is shown as a single film, it is understood that it is not limited thereto and may have a multi-film structure.

The first gate insulating layer 125 may be formed between the first finned active pattern 110 and the first gate electrode 120. Also, a first gate insulating film 125 may be formed between the first gate spacer 140 and the first gate electrode 120.

The first gate insulating layer 125 may be formed on the upper surface 111u and the sidewall 111s of the first portion 111 of the first fin-shaped active pattern. The first gate insulating layer 110 may be disposed between the first gate electrode 120 and the field insulating layer 105. Also, the first gate insulating layer 125 may be formed along the sidewalls of the first gate spacer 140.

A first gate insulating layer 125 is formed on the first portion 111 of the first pinned active pattern and a first gate spacer 140 is formed on the second portion 112 of the first pinned active pattern. The height of the first gate insulating layer 125 formed along the sidewall of the first gate spacer 140 on the top surface 111u of the first portion 111 of the first pinned active pattern is greater than the height of the second portion of the first pinned active pattern, Is lower than the height of the first gate spacer (140) on the upper surface (112u) of the first gate spacer (112).

The first gate insulating film 125 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. For example, the first gate insulating layer 125 may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, Zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, and may include one or more of oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. It is not.

A first source / drain 130 is formed on the first pinned active pattern 110, on both sides of the first gate electrode 120 and the first gate spacer 140. A first source / drain 130 is formed on the third portion 113 of the first pinned active pattern.

More specifically, the first source / drain 130 is connected to the upper surface 113u of the third portion 113 of the first pinned active pattern and the connecting side 112c of the second portion 112 of the first pinned active pattern, As shown in FIG.

The outer circumferential surface of the first source / drain 130 may have various shapes. For example, the outer circumferential surface of the first source / drain 130 may be at least one of a diamond shape, a circular shape, and a rectangular shape. Figures 1 and 4 illustrate diamond shapes (or pentagonal or hexagonal shapes).

When the semiconductor device 1 according to the first embodiment of the present invention is a PMOS transistor, the first source / drain 130 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The compressive stress material may exert a compressive stress on the first pinned active pattern 110 (e.g., the first portion 111 of the first pinned active pattern) to improve the mobility of carriers in the channel region .

Alternatively, when the semiconductor device 1 is an NMOS transistor, the first source / drain 130 may be the same material as the first pinned active pattern 110, or a tensile stressed material. For example, when the first pinned active pattern 110 is Si, the first source / drain 130 may be Si or a material with a smaller lattice constant than Si (e.g., SiC or silicon containing silicon : C).

In addition, although not shown in FIGS. 1 to 4, a seed layer may be formed between the first source / drain 130 and the first pinned active pattern. At this time, the seed layer may be a layer included in the first source / drain 130.

In addition, in the semiconductor device according to the embodiments of the present invention, although not shown in FIGS. 1, 3, and 4, the first source / drain 130 includes a metal silicide Layer. ≪ / RTI >

5 and 6 are views for explaining a semiconductor device according to a second embodiment of the present invention. For convenience of explanation, the differences from those described with reference to Figs. 1 to 4 will be mainly described.

5 and 6, the semiconductor device 2 according to the second embodiment of the present invention further includes a first pin spacer 135. [

In the semiconductor device according to the second embodiment of the present invention, the upper surface 113u of the third portion 113 of the first fin-shaped active pattern may protrude above the upper surface 105u of the field insulating film. That is, the third portion 113 of the first fin-shaped active pattern protrudes above the field insulating film 105.

The width of the third portion 113 of the first pinned active pattern at the boundary between the third portion 113 of the first pinned active pattern and the top surface 105u of the field insulating film is greater than the width of the third portion 113 of the first pinned active pattern 113, but the present invention is not limited thereto.

The first pin spacer 135 is formed on the side wall 113s of the third portion 113 of the first pinned active pattern protruding above the upper surface 105u of the field insulating film.

The height from the top surface 105u of the field insulating film to the top of the first pin spacer 135 is shown to be equal to the height of the third portion 113 of the first pinned active pattern protruding above the top surface 105u of the field insulating film , But is not limited thereto.

The first pin spacer 135 is formed on the side wall 113s of the third portion 113 of the protruding first pinned active pattern so that the first pin spacer 135 can extend in the first direction X1 have.

The first fin spacers 135 are physically connected to the first gate spacers 140 formed on the sidewalls of the first gate electrodes 120. The first pin spacer 135 and the first gate spacer 140 are connected to each other because the first pin spacer 135 and the first gate spacer 140 are formed at the same level. Here, "the same level" means that it is formed by the same manufacturing process.

First pin spacer 135 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon shot nitride (SiOCN) and at least one of a combination of . Although the first pin spacer 135 is shown as a single film, it is of course not limited thereto and may have a multi-film structure.

The first source / drain 130 is formed on the upper surface 113u of the third portion 113 of the first pinned active pattern protruding above the upper surface 105u of the field insulating film.

7 to 9 are views for explaining a semiconductor device according to a third embodiment of the present invention. For convenience of explanation, the differences from those described with reference to Figs. 1 to 4 will be mainly described.

7 to 9, in the semiconductor device 3 according to the third embodiment of the present invention, the first pinned active pattern 110 and the fourth finned active pattern 410 are formed on the substrate 100 Can be elongated along one direction (X1). The first pinned active pattern 110 and the fourth pinned active pattern 410 are formed adjacent to each other with the field insulating film 105 therebetween.

The fourth pinned active pattern 410 protrudes above the field insulating film 105 formed on the substrate 100. The fourth pinned active pattern 410 is defined by the field insulating film 105 like the first pinned active pattern 110. [

The fourth pinned active pattern 410 includes a first portion 411, a second portion 412, and a third portion 413. The first portion 411, the second portion 412 and the third portion 413 of the fourth pinned active pattern 410 may be sequentially arranged in the first direction X1.

In other words, the second portion 412 of the fourth pinned active pattern is disposed on both sides in the first direction X1 about the first portion 411 of the fourth pinned active pattern. In addition, the third portion 413 of the fourth pinned active pattern is disposed on both sides in the first direction X1 about the first portion 411 of the fourth pinned active pattern.

7 and 9, the upper surface of the first portion 411 of the fourth fin-shaped active pattern and the upper surface of the second portion 412 of the fourth fin-shaped active pattern are located above the upper surface 105u of the field insulating film Respectively. The upper surface of the third portion 413 of the fourth pinned active pattern may not project above the upper surface 105u of the field insulating film, but is not limited thereto.

The second portion 412 of the fourth pinned active pattern is recessed relative to the first portion 411 of the fourth pinned active pattern and the third portion 413 of the fourth pinned active pattern is recessed And is recessed from the second portion 412.

In other words, the height h41 from the upper surface of the substrate 100 to the upper surface of the first portion 411 of the fourth pinned active pattern is greater than the height h41 of the second portion 412 of the fourth pinned active pattern from the upper surface of the substrate 100, Is higher than the height (h42) The height h42 from the upper surface of the substrate 100 to the upper surface of the second portion 412 of the fourth pinned active pattern is greater than the height h42 of the third portion 413 of the fourth pinned active pattern from the upper surface of the substrate 100 Is higher than the height (h43) to the upper surface.

The first gate electrode 120 may extend in the second direction Y1 and may be formed to intersect the first pinned active pattern 110 and the fourth pinned active pattern 410. [ The first gate electrode 120 may be formed on the first finned active pattern 110, the fourth finned active pattern 410, and the field insulating film 105. [ A first gate electrode 120 is formed on the first portion 111 of the first pinned active pattern and the first portion 411 of the fourth pinned active pattern.

The first gate spacer 140 may extend in the second direction Y1 and may be formed on the second portion 112 of the first pinned active pattern and the second portion 412 of the fourth pinned active pattern.

The first gate insulating layer 125 may be formed between the first finned active pattern 110 and the first gate electrode 120 and between the fourth finned active pattern 410 and the first gate electrode 120. The first gate insulating layer 125 may be formed on the top and sidewalls of the first portion 111 of the first pinned active pattern and on the top and sidewalls of the first portion 411 of the fourth pinned active pattern.

A fourth source / drain 430 is formed on the fourth pinned active pattern 410 on both sides of the first gate electrode 120. In other words, the fourth source / drain 430 may be formed on the third portion 413 of the fourth pinned active pattern.

The outer circumferential surface of the fourth source / drain 430 may have various shapes. For example, the outer circumferential surface of the fourth source / drain 430 may be at least one of a diamond shape, a circular shape, and a rectangular shape. In FIG. 7, a diamond shape (or a pentagon shape) is illustrated as an example, but the present invention is not limited thereto.

The fourth source / drain 430 may have the same conductivity type as the first source / drain 130. In addition, the fourth source / drain 430 may include the same material as the first source / drain 130.

In the semiconductor device 3 according to the third embodiment of the present invention, the fourth source / drain 430 may be in contact with and connected to the first source / drain 130. That is, the fourth source / drain 430 may be electrically connected to the first source / drain 130.

The interlayer insulating layer 150 is not formed between the first source / drain 130 and the fourth source / drain 430 because the first source / drain 130 and the fourth source / drain 430 are in contact with each other , And an air gap 155 may be disposed.

A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 10 to 13. FIG.

10 is a perspective view illustrating a semiconductor device according to a fourth embodiment of the present invention. 11 is a cross-sectional view taken along line A-A and E-E in Fig. 12 is a cross-sectional view taken along line C-C and F-F in Fig. 13 is a cross-sectional view taken along line D-D and G-G in Fig.

10 to 13, a semiconductor device 4 according to a fourth embodiment of the present invention includes a substrate 100, a second pinned active pattern 210, a third pinned active pattern 310, The second gate spacer 240, the third gate spacer 340, the second source / drain 230, the third source / drain 330, and the like .

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be spaced apart from each other or may be connected to each other.

The first transistor 201 may be formed in the first region I and the second transistor 301 may be formed in the second region II.

The first transistor 201 includes a second finned active pattern 210, a second gate electrode 220, a second gate spacer 240, a second source / drain 230, and the like.

The description of the second pinned active pattern 210 may be substantially the same as the description of the first pinned active pattern 110 described in Figs. 1 to 4, and therefore will be briefly described.

The second fin-shaped active pattern 210 may be extended on the substrate 100 along the third direction X2. The second pinned active pattern 210 protrudes above the field insulating film 105 formed on the substrate 100. The second pinned active pattern 210 is defined by a field insulating film 105.

The second finned active pattern 210 includes a first portion 211, a second portion 212, and a third portion 213. The first portion 211, the second portion 212 and the third portion 213 of the second pinned active pattern 210 may be sequentially arranged in the third direction X2.

The second portion 212 of the second pinned active pattern and the third portion 213 of the second pinned active pattern are formed on both sides in the third direction X2 about the first portion 211 of the second pinned active pattern, .

The upper surface of the first portion 211 of the second pinned active pattern and the upper surface of the second portion 212 of the second pinned active pattern protrude above the upper surface 105u of the field insulating film.

The top surface 213u of the third portion 213 of the second pinned active pattern may not protrude above the top surface 105u of the field insulating film, but is not limited thereto. That is, the sidewalls of the third portion 213 of the second fin-shaped active pattern can be entirely in contact with the field insulating film 105.

The height h4 from the top surface of the substrate 100 to the top surface of the first portion 211 of the second pinned active pattern is from the top surface of the substrate 100 to the top surface of the second portion 212 of the second pinned active pattern (H5). The height h5 from the upper surface of the substrate 100 to the upper surface of the second portion 212 of the second pinned active pattern is greater than the height h3 of the third portion 213 of the second pinned active pattern from the upper surface of the substrate 100 Is higher than the height h6 to the upper surface.

For example, the top surface of the first portion 211 of the second pinned active pattern and the top surface of the second portion 212 of the second pinned active pattern may not be continuous. That is, between the top surface of the first portion 211 of the second fin-shaped active pattern and the second portion 212 of the second fin-shaped active pattern, there may be a step such as a step, for example.

12, in the second portion 212 of the second pinned active pattern, the width of the second portion 212 of the second fin-shaped active pattern protruding above the upper surface 105u of the field insulating film is larger than the width of the field insulating film 105 Is greater than the width of the second portion 212 of the second pinned active pattern which is in contact with the first pinned active pattern. However, the present invention is not limited thereto.

The second gate electrode 220 may extend in the fourth direction Y2 and may be formed on the first portion 211 of the second pinned active pattern. The second gate electrode 220 may include metal layers MG3 and MG4. The second gate electrode 220 may be formed by stacking two or more metal layers MG3 and MG4, as shown in FIG. The second gate electrode 220 may include a material included in the first gate electrode 120 described with reference to FIGS.

The second gate spacers 240 may be formed on the sidewalls of the second gate electrode 220 extending in the fourth direction Y2. A second gate spacer 240 may be formed on the second portion 212 of the second pinned active pattern.

The second gate insulating layer 225 may be formed between the second finned active pattern 210 and the second gate electrode 220. In addition, a second gate insulating film 225 may be formed between the second gate spacer 240 and the second gate electrode 220. The second gate insulating film 225 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film.

A second gate insulating layer 225 is formed on the first portion 211 of the second pinned active pattern and a second gate spacer 240 is formed on the second portion 212 of the second pinned active pattern. The height of the second gate insulating film 225 formed along the sidewalls of the second gate spacer 240 on the upper surface of the first portion 211 of the second pinned active pattern is greater than the height of the second portion 212 of the second pinned active pattern, Is lower than the height of the second gate spacer (240) on the upper surface of the second gate spacer (240).

The second source / drain 230 is formed on the second pinned active pattern 210 on both sides of the second gate electrode 220. A second source / drain 230 is formed on the third portion 213 of the second fin-shaped active pattern.

More specifically, the second source / drain 230 is connected to the upper surface 213u of the third portion 213 of the second pinned active pattern and the connecting side 212c of the second portion 212 of the second pinned active pattern, As shown in FIG.

The second transistor 301 includes a third pinned active pattern 310, a third gate electrode 320, a third gate spacer 340, a third source / drain 330, and the like.

The third pinned active pattern 310 may be extended on the substrate 100 along the fifth direction X3. The third pinned active pattern 310 protrudes above the field insulating film 105 formed on the substrate 100. The third pinned active pattern 310 is defined by the field insulating film 105.

The third pinned active pattern 310 includes a first portion 311, a second portion 312, and a third portion 313. The first portion 311, the second portion 312 and the third portion 313 of the third pinned active pattern 310 may be sequentially arranged in the fifth direction X3.

The second portion 312 of the third pinned active pattern and the third portion 313 of the third pinned active pattern are formed on both sides in the fifth direction X3 about the first portion 311 of the third pinned active pattern, .

The upper surface of the first portion 311 of the third pinned active pattern and the upper surface of the second portion 312 of the third pinned active pattern protrude above the upper surface 105u of the field insulating film.

The upper surface 313u of the third portion 313 of the third pinned active pattern may not protrude above the upper surface 105u of the field insulating film, but is not limited thereto. That is, the side wall of the third portion 313 of the third fin-shaped active pattern can be entirely in contact with the field insulating film 105.

The height h7 from the top surface of the substrate 100 to the top surface of the first portion 311 of the third pinned active pattern is set to be from the top surface of the substrate 100 to the top surface of the third portion 312 of the third pinned active pattern (H9). The height h8 from the upper surface of the substrate 100 to the upper surface of the second portion 312 of the third pinned active pattern is greater than the height h3 of the third portion 313 of the third pinned active pattern from the upper surface of the substrate 100 Is higher than the height h9 to the upper surface.

In the semiconductor device according to the fourth embodiment of the present invention, the height h7 from the upper surface of the substrate 100 to the upper surface of the first portion 311 of the third pinned active pattern extends from the upper surface of the substrate 100 to the upper surface May be the same as the height h8 to the top surface of the second portion 312 of the pin-shaped active pattern.

That is, the top surface of the first portion 311 of the third pinned active pattern and the top surface of the second portion 312 of the third pinned active pattern may be continuous.

12, in the vicinity of the boundary between the second portion 312 of the third pinned active pattern and the upper surface 105u of the field insulating film, the width of the second portion 312 of the third pinned active pattern May not decrease rapidly.

The third gate electrode 320 may extend in the sixth direction Y3 and be formed on the first portion 311 of the third pinned active pattern. The third gate electrode 320 may include metal layers MG5 and MG6. As shown in the figure, the third gate electrode 320 may be formed by stacking two or more metal layers MG5 and MG6. The third gate electrode 320 may include a material included in the first gate electrode 120 described with reference to FIGS.

The third gate spacer 340 may be formed on the sidewall of the third gate electrode 320 extending in the sixth direction Y3. A third gate spacer 340 may be formed on the second portion 312 of the third pinned active pattern.

A third gate insulating layer 325 may be formed between the third fin active pattern 310 and the third gate electrode 320. Also, a third gate insulating film 325 may be formed between the third gate spacer 340 and the third gate electrode 320. The third gate insulating film 325 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film.

A third gate insulating film 325 is formed on the first portion 311 of the third pinned active pattern and a third gate spacer 340 is formed on the second portion 312 of the third pinned active pattern.

The height h7 from the upper surface of the substrate 100 to the upper surface of the first portion 311 of the third pinned active pattern is greater than the height h7 from the upper surface of the substrate 100 to the upper surface of the second portion 312 of the third pinned active pattern The height of the third gate insulating film 225 formed along the sidewall of the third gate spacer 340 on the upper surface of the first portion 311 of the third pinned active pattern is the same as the height of the third fin- Is substantially the same as the height of the third gate spacer 240 on the upper surface of the second portion 312 of the pattern.

A third source / drain 330 is formed on the third pinned active pattern 310, on both sides of the third gate electrode 320. A third source / drain 330 is formed on the third portion 313 of the third pinned active pattern.

More specifically, the third source / drain 330 is connected to the upper surface 313u of the third portion 313 of the third pinned active pattern and the connecting side 312c of the second portion 312 of the third pinned active pattern, As shown in FIG.

In the semiconductor device according to the fourth embodiment of the present invention, the height h4 from the top surface of the substrate 100 to the top surface of the first portion 211 of the second pinned active pattern extends from the top surface of the substrate 100 to the top surface May be substantially the same as the height h7 to the top surface of the first portion 311 of the pin-shaped active pattern.

The height h8 from the top surface of the substrate 100 to the top surface of the second portion 312 of the third pinned active pattern is greater than the height h2 from the top surface of the substrate 100 to the top surface of the second portion 212 of the second pinned active pattern Is higher than the height h5 to the upper surface.

In the semiconductor device according to the fourth embodiment of the present invention, the width S2 in the sixth direction Y3 of the third source / drain 330 is greater than the width S2 in the fourth direction Y2 of the second source / (S1). Also, the height D2 of the third source / drain 330 is higher than the height D1 of the second source / drain 230.

More specifically, the second source / drain 230 is formed on the upper surface 213u of the third portion 213 of the second fin-shaped active pattern while the second portion 212 of the second fin- (Not shown). That is, the height D1 of the second source / drain 230 is affected by the height of the second portion 212 of the second pinned active pattern protruding above the top surface 105u of the field insulating film.

In other words, when the height of the second portion 212 of the second fin-shaped active pattern protruded above the upper surface 105u of the field insulating film is increased, the height D1 of the second source / drain 230 is increased. Conversely, when the height of the second portion 212 of the second pinned active pattern protruded above the upper surface 105u of the field insulating film is reduced, the height D1 of the second source / drain 230 is lowered.

Thus, the second portion 312 of the third pinned active pattern, which is protruded above the top surface 105u of the field insulating film, has a second portion 212 of the second pinned active pattern protruding above the top surface 105u of the field insulating film The height D2 of the third source / drain 330 may be higher than the height D1 of the second source / drain 230. In this case,

In addition, for example, the second source / drain 230 and the third source / drain 330 may be the epitaxial films grown on the second pinned active pattern 210 and the third pinned active pattern 310, have. Although there may be differences depending on the conditions for growing the epitaxial film, the epitaxial film may develop a facet. The width S1 in the fourth direction Y2 of the second source / drain 230 is affected by the height D1 of the second source / drain 230 due to the development of the facet.

Therefore, since the height D2 of the third source / drain 330 is higher than the height D1 of the second source / drain 230, the height D2 of the third source / drain 330 in the sixth direction Y3 of the third source / The width S2 is larger than the width S1 of the second source / drain 230 in the fourth direction Y2.

14 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention. For convenience of explanation, differences from those described with reference to Figs. 10 to 13 will be mainly described. For reference, Fig. 14 is a cross-sectional view taken along line A-A and E-E in Fig.

14, in the semiconductor device 5 according to the fifth embodiment of the present invention, the height h4 from the upper surface of the substrate 100 to the upper surface of the first portion 211 of the second pinned active pattern is May be the same as the height h5 from the upper surface of the substrate 100 to the upper surface of the second portion 212 of the second fin-shaped active pattern.

That is, the profile of the top surface of the first portion 211 of the second pinned active pattern and the top surface of the second portion 212 of the second pinned active pattern may be continuous.

In addition, the cross section of the first portion 211 of the second fin-shaped active pattern taken along the Y2-Z2 plane may be similar to the cross section taken along the line C-C of Fig.

In the semiconductor device according to the fifth embodiment of the present invention, the height h7 from the upper surface of the substrate 100 to the upper surface of the first portion 311 of the third pinned active pattern extends from the upper surface of the substrate 100 to the upper surface Is higher than the height h4 to the top surface of the first portion 211 of the pinned active pattern.

The height h8 from the upper surface of the substrate 100 to the upper surface of the second portion 312 of the third pinned active pattern is greater than the height h2 of the second portion 212 of the second pinned active pattern from the upper surface of the substrate 100 Is higher than the height h5 to the upper surface.

Therefore, the third pinned active pattern 310 protruded above the field insulating film 105 is higher than the second pinned active pattern 210 protruded above the field insulating film 105.

The width S2 in the sixth direction Y3 of the third source / drain 330 is larger than the width S1 in the fourth direction Y2 of the second source / drain 230, and the width S2 of the third source / The height D2 of the drain 330 is higher than the height D1 of the second source / drain 230.

15 to 17 are views for explaining a semiconductor device according to a sixth embodiment of the present invention. For convenience of explanation, differences from those described with reference to Figs. 10 to 13 will be mainly described.

15 is a perspective view for explaining a semiconductor device according to a sixth embodiment of the present invention. 16 is a cross-sectional view taken along line A-A and E-E in Fig. 17 is a cross-sectional view taken along line D-D and G-G in Fig.

Referring to Figs. 15 to 17, the semiconductor device 6 according to the sixth embodiment of the present invention further includes a second pin spacer 235. Fig. More specifically, the first transistor 201 further includes a second pin spacer 235.

In the semiconductor device according to the sixth embodiment of the present invention, the upper surface 213u of the third portion 213 of the second fin-shaped active pattern may protrude above the upper surface 105u of the field insulating film. That is, the third portion 213 of the second fin-shaped active pattern protrudes above the field insulating film 105.

The width of the third portion 213 of the second fin-shaped active pattern at the boundary between the third portion 213 of the second fin-shaped active pattern and the top surface 105u of the field insulating film is greater than the width of the third portion 213 of the second fin- 213, but the present invention is not limited thereto.

The second pin spacer 235 is formed on the sidewall of the third portion 213 of the second pinned active pattern protruding above the top surface 105u of the field insulating film.

The height from the top surface 105u of the field insulating film to the top of the second pin spacer 235 is shown to be equal to the height of the third portion 213 of the second pinned active pattern protruding above the top surface 105u of the field insulating film , But is not limited thereto.

Since the second pin spacer 235 is formed on the sidewall of the third portion 213 of the protruding second pinned active pattern, the second pin spacer 235 may extend in the third direction X2.

Second pin spacers 235 are materially interconnected with second gate spacers 240 formed on the sidewalls of second gate electrode 220. Also, the second fin spacers 235 may comprise the same material as the second gate spacers 240.

18 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment of the present invention. For convenience of explanation, differences from those described with reference to Figs. 15 to 17 will be mainly described.

15, the perspective view of the semiconductor device according to the seventh embodiment of the present invention may be substantially the same as that of FIG. 15 when the size of the third source / drain 330 is reduced. At this time, Fig. 18 is a sectional view taken along line A-A and E-E in Fig.

18, in the semiconductor device 7 according to the seventh embodiment of the present invention, the height h7 from the top surface of the substrate 100 to the top surface of the first portion 311 of the third pinned active pattern is May be higher than the height h8 from the top surface of the substrate 100 to the top surface of the second portion 312 of the third pinned active pattern.

In the semiconductor device according to the seventh embodiment of the present invention, the height h4 from the top surface of the substrate 100 to the top surface of the first portion 211 of the second pinned active pattern extends from the top surface of the substrate 100 to the top surface May be the same as the height h7 to the top surface of the first portion 311 of the pin-shaped active pattern. The height h5 from the upper surface of the substrate 100 to the upper surface of the second portion 212 of the second pinned active pattern is greater than the height h2 of the second portion 312 of the third pinned active pattern from the upper surface of the substrate 100. [ And may be equal to the height h8 to the top surface.

The top surface 213u of the third portion 213 of the second pinned active pattern protrudes above the top surface 105u of the field insulating film but the top surface 313u of the third portion 313 of the third pinned active pattern, May not protrude above the upper surface 105u of the field insulating film. That is, the side wall of the third portion 313 of the third fin-shaped active pattern can be entirely in contact with the field insulating film 105.

The height h6 from the top surface of the substrate 100 to the top surface 213u of the third portion 213 of the second pinned active pattern extends from the top surface of the substrate 100 to the third portion of the third pinned active pattern 313u to the top surface 313u of the second substrate 313.

In other words, the height of the connecting sidewall 212c of the second portion 212 of the second fin-shaped active pattern in which the second source / drain 230 is formed is larger than that of the third fin- Is lower than the height of the connecting side wall 312c of the second portion 312 of the active pattern.

The width of the third source / drain 330 in the sixth direction Y3 is greater than the width of the second source / drain 230 in the fourth direction Y2, and the third source / drain 330 May be higher than the height of the second source / drain (230).

19 to 21 are views for explaining a semiconductor device according to an eighth embodiment of the present invention. For convenience of explanation, differences from those described with reference to Figs. 10 to 13 will be mainly described.

20 is a sectional view taken along line J - J and K - K in FIG. 19, and FIG. 21 is a sectional view taken along line D - D and G - G in FIG. A sectional view taken along line A-A and E-E in Fig. 19 can be the same as Fig.

19 to 21, in the semiconductor device 8 according to the eighth embodiment of the present invention, the second finned active pattern 210 and the fifth finned active pattern 260 are formed on the substrate 100 It can be elongated along three directions X2. The second finned active pattern 210 and the fifth finned active pattern 260 are formed adjacent to each other with the field insulating film 105 therebetween.

The third pinned active pattern 310 and the sixth pinned active pattern 360 may be elongated along the fifth direction X3 on the substrate 100. [ The third pinned active pattern 310 and the sixth pinned active pattern 360 are formed adjacent to each other with the field insulating film 105 therebetween.

The fifth pinned active pattern 260 and the sixth pinned active pattern 360 protrude above the field insulating film 105 formed on the substrate 100. The fifth pinned active pattern 260 and the sixth pinned active pattern 360 are defined by the field insulating film 105.

The fifth pinned active pattern 260 includes a first portion 261, a second portion 262, and a third portion 263. The first portion 261, the second portion 262 and the third portion 263 of the fifth pinned active pattern 260 may be sequentially arranged in the third direction X2.

The sixth pinned active pattern 360 includes a first portion 361, a second portion 362, and a third portion 363. The first portion 361, the second portion 362 and the third portion 363 of the sixth pinned active pattern 360 may be sequentially arranged in the fifth direction X3.

Like the second pinned active pattern 210, the second portion 262 of the fifth pinned active pattern is recessed relative to the first portion 261 of the fifth pinned active pattern, and the third portion 262 of the fifth pinned active pattern is recessed The portion 263 is recessed relative to the second portion 262 of the fifth pinned active pattern.

However, the sixth pinned active pattern 360 may be similar to the description of the third pinned active pattern 310. [

In other words, the height from the top surface of the substrate 100 to the top surface of the first portion 361 of the sixth pinned active pattern is the height from the top surface of the substrate 100 to the top surface of the third portion 362 of the sixth pinned active pattern It is higher than the height. The height from the upper surface of the substrate 100 to the upper surface of the second portion 362 of the sixth pinned active pattern is set to a height from the upper surface of the substrate 100 to the upper surface of the third portion 363 of the sixth pinned active pattern Respectively.

However, the height from the top surface of the substrate 100 to the top surface of the first portion 361 of the sixth pinned active pattern is the height from the top surface of the substrate 100 to the top surface of the second portion 362 of the sixth pinned active pattern ≪ / RTI > That is, the top surface of the first portion 361 of the sixth pinned active pattern and the top surface of the second portion 362 of the sixth pinned active pattern may be on the same plane.

The second gate electrode 220 extends in the fourth direction Y2 and may be formed on the first portion 211 of the second pinned active pattern and the first portion 261 of the fifth pinned active pattern. The third gate electrode 320 may extend in the sixth direction Y3 and may be formed on the first portion 311 of the third pinned active pattern and the first portion 361 of the sixth pinned active pattern.

The second gate spacer 240 may extend in the fourth direction Y2 and may be formed on the second portion 212 of the second pinned active pattern and the second portion 262 of the fifth pinned active pattern. A third gate spacer 340 extends in a sixth direction Y3 and may be formed on the second portion 312 of the third pinned active pattern and the second portion 362 of the sixth pinned active pattern.

A fifth source / drain 280 is formed on the fifth pinned active pattern 260 on both sides of the second gate electrode 220. In other words, the fifth source / drain 280 may be formed on the third portion 263 of the fifth pinned active pattern.

A sixth source / drain 380 is formed on the sixth pinned active pattern 360 on both sides of the third gate electrode 320. In other words, the sixth source / drain 380 may be formed on the third portion 363 of the sixth pinned active pattern.

The fifth source / drain 280 may have the same conductivity type as the second source / drain 230 and may include the same material as the second source / drain 230. Similarly, the sixth source / drain 380 may have the same conductivity type as the third source / drain 330 and may include the same material as the third source / drain 330.

In the semiconductor device according to the eighth embodiment of the present invention, the second source / drain 230 and the fifth source / drain 280 are not connected to each other but are spaced apart from each other. However, the third source / drain 330 and the sixth source / drain 380 may be connected to each other in contact with each other.

The spaced distance between the second pinned active pattern 210 and the fifth pinned active pattern 260 is such that the spaced distance between the third pinned active pattern 310 and the sixth pinned active pattern 360 is < RTI ID = 0.0 > Can be the same.

13, the width of the second source / drain 230 in the fourth direction Y2 is narrower than the width of the third source / drain 330 in the sixth direction Y3. Similarly, the width of the fifth source / drain 280 in the fourth direction Y2 is narrower than the width of the sixth source / drain 380 in the sixth direction Y3.

Therefore, the third source / drain 330 and the sixth source / drain 380 having a large width in the sixth direction Y3 can be connected to each other in contact with each other. However, the second source / drain 230 and the fifth source / drain 280 having a small width in the fourth direction Y2 may be spaced apart from each other.

22 and 23 are a circuit diagram and a layout diagram for explaining a semiconductor device according to a ninth embodiment of the present invention.

22, a semiconductor device 9 according to the ninth embodiment of the present invention includes a pair of inverters INV1 and INV2 connected in parallel between a power supply node Vcc and a ground node Vss, And a first pass transistor PS1 and a second pass transistor PS2 connected to the output node of each inverter INV1 and INV2. The first pass transistor PS1 and the second pass transistor PS2 may be connected to the bit line BL and the complementary bit line / BL, respectively. The gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series and a second inverter INV2 includes a second pull-up transistor PU2 and a second pull- And a transistor PD2. The first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

The first inverter INV1 and the second inverter INV2 are connected to the output node of the second inverter INV2 so that the input node of the first inverter INV1 is configured to constitute one latch circuit , The input node of the second inverter INV2 is connected to the output node of the first inverter INV1.

Referring to FIGS. 22 and 23, a seventh pinned active pattern 510, an eighth pinned active pattern 520, a ninth finned active pattern 530, and a tenth finned active pattern 540, which are spaced apart from each other, (For example, the up-and-down direction in Fig. 23). The eighth pinned active pattern 520 and the ninth finned active pattern 530 may be shorter in extension than the seventh pinned active pattern 510 and the tenth pinned active pattern 540.

The fifth gate electrode 551, the sixth gate electrode 552, the seventh gate electrode 553 and the eighth gate electrode 554 are elongated in the other direction (for example, the left-right direction in FIG. 23) And are formed so as to intersect the seventh pinned active pattern 510 to the tenth pinned active pattern 540. Specifically, the fifth gate electrode 551 completely intersects the seventh pinned active pattern 510 and the eighth pinned active pattern 520, and may partially overlap the end of the ninth pinned active pattern 530. [ The seventh gate electrode 553 completely overlaps the tenth pinned active pattern 540 and the ninth pinned active pattern 530 and may partially overlap the end of the eighth pinned active pattern 520. [ The sixth gate electrode 552 and the eighth gate electrode 554 are formed so as to intersect the seventh pinned active pattern 510 and the tenth pinned active pattern 540, respectively.

As shown, the first pull-up transistor PU1 is defined around the region where the fifth gate electrode 551 and the eighth pinned active pattern 520 intersect, the first pull-down transistor PD1 is defined around the fifth gate electrode 551, The first pass transistor PS1 is defined around the region where the seventh pinned active pattern 510 intersects with the seventh pinned active pattern 510. The first pass transistor PS1 is defined around the region where the sixth gate electrode 552 and the seventh pinned active pattern 510 cross Lt; / RTI > The second pull-down transistor PD2 is defined around the region where the seventh gate electrode 553 and the ninth fin active pattern 530 intersect and the second pull-down transistor PD2 is defined around the region where the seventh gate electrode 553 and the ninth fin- The second pass transistor PS2 is defined around the region where the eighth gate electrode 554 and the tenth pinned active pattern 540 intersect.

Recesses are formed on both sides of the region where the fifth to eighth gate electrodes 551 to 554 and the seventh to tenth pinned active patterns 510, 520, 530 and 540 intersect, The source / drain can be formed in the recess.

Also, a plurality of contacts 550 may be formed.

In addition, the shared contact 561 connects the eighth pinned active pattern 520, the seventh gate electrode 553, and the wiring 571 at the same time. The shared contact 562 connects the ninth pinned active pattern 530, the fifth gate electrode 551, and the wiring 572 at the same time.

The first pull-up transistor PU1, the first pull-down transistor PD1, the first pass transistor PS1, the second pull-up transistor PU2, the second pull-down transistor PD2 and the second pass transistor PS2 are all of a pin- And may have the above-described configuration using Figs. 10 to 21. Fig.

For example, the cross-sectional view of the first pull-up transistor PU1 taken along the line H-H may be substantially the same as the cross-sectional view taken along line A-A of FIGS. 11, 14, 16, and 18. Also, the cross-sectional view of the first pull-down transistor PD1 taken along the line I - I may be substantially the same as the cross-sectional view taken along line E - E of FIGS. 11, 14, 16, and 18. In addition, the first pass transistor PS1 may have substantially the same cross section as the first pull-down transistor PD1.

24 is a conceptual diagram for explaining a semiconductor device according to a tenth embodiment of the present invention.

24, in the semiconductor device 10 according to the tenth embodiment of the present invention, the first fin type transistor 611 is arranged in the SRAM region 610 and the second fin type transistor 611 is provided in the logic region 620 621 may be disposed.

The first fin type transistor 611 may be the first transistor 201 described with reference to FIGS. 10 to 17 and FIGS. 19 to 21, and the second fin type transistor 621 may be the same as that shown in FIGS. 10 to 17 and FIGS. The second transistor 301 described with reference to FIG.

The size (e.g., width, height, volume, etc.) of the source / drain of the first fin type transistor 611 is smaller than the size of the source / drain of the second fin type transistor 621.

25 to 32, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. The semiconductor device formed through the processes of FIGS. 25 to 32 may be the semiconductor device 4 described with reference to FIGS. 10 to 13. FIG.

FIGS. 25 to 32 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

25, a first pre-finned active pattern 210p is formed on a first region I on a substrate 100 and a second pre-finned active pattern 210p is formed on a second region II on a substrate 100 310p.

Specifically, a first mask pattern 2103a and a second mask pattern 2103b are formed on the first region I and the second region II, respectively, on the substrate 100, 1 free-fin-shaped active pattern 210p and a second free-fin-shaped active pattern 310p are formed.

The first free pin type active pattern 210p may extend along the third direction X2 and the second free pin type active pattern 310p may extend along the fifth direction X3. A trench is formed around each of the first free-fin-shaped active pattern 210p and the second free-fin-shaped active pattern 310p. The first mask pattern 2103a and the second mask pattern 2103b may be formed of a material including at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring to FIG. 26, a field insulating film 105 is formed on a substrate 100. The field insulating film 105 may be formed of a material including at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Specifically, a field insulating film 105 is formed on the substrate 100 so as to cover the first free-form active pattern 210p and the second free-form active pattern 310p. Through the planarization process, the second finned active pattern 210, the third finned active pattern 310, and the field insulating film 105 can be placed on the same plane. While the planarization process is being performed, the first mask pattern 2103a and the second mask pattern 2103b can be removed, but are not limited thereto. That is, the first mask pattern 2103a and the second mask pattern 2103b may be removed prior to the formation of the field insulating film 105, or may be removed after the subsequent field insulating film 105 recessing process.

Subsequently, a part of the field insulating film 105 is recessed. Accordingly, the second pinned active pattern 210 and the third pinned active pattern 310 protrude above the upper surface of the field insulating film 105. That is, the field insulating film 105 is formed to contact a part of the side wall of the second fin-shaped active pattern 210 and the third fin-shaped active pattern 310.

In this way, the second fin-shaped active pattern 210 and the third fin-shaped active pattern 310 can be defined by the field insulating film 105. The second pinned active pattern 210 includes a first portion 211, a second portion 212 and a third portion 213 sequentially arranged in a third direction X2. The third pinned active pattern 310 includes a first portion 311, a second portion 312 and a third portion 313 which are sequentially arranged in the fifth direction X3.

On the other hand, a part of the second finned active pattern 210 protruding above the field insulating film 105 and a part of the third finned active pattern 310 may be formed by an epitaxial process. Specifically, after forming the field insulating film 105 through the planarization process, the second pinned active pattern 210 and the third pinned active pattern 310 exposed by the field insulating film 105 without recessing the field insulating film 105 ) Are seeded, respectively. Thereby, portions of the second pinned active pattern 210 and the third pinned active pattern 310 can be respectively formed.

Also, doping for threshold voltage adjustment may be performed on the second pinned active pattern 210 and the third pinned active pattern 310, respectively. When the NMOS finned transistor is fabricated using the second pinned active pattern 210, the impurity may be boron (B). When an NMOS finned transistor is fabricated using the second pinned active pattern 210, the impurity may be phosphorous (P) or arsenic (As). Depending on the type of the pin-type transistor fabricated using the third pinned active pattern 310, doped impurities may vary.

27, the etching process is performed using the third mask pattern 2104a to form a first dummy gate pattern 226 which intersects the second fin-shaped active pattern 210 and extends in the fourth direction Y2, . The etch process is performed using the fourth mask pattern 2104b to form a second dummy gate pattern 326 that intersects the third pinned active pattern 310 and extends in the sixth direction Y3.

For example, a first dummy gate pattern 226 is formed on the first portion 211 of the second fin-shaped active pattern and a second dummy gate pattern 326 is formed on the first portion 311 of the third fin- ). ≪ / RTI >

The first dummy gate pattern 226 includes a first dummy gate insulating film 227 and a first dummy gate electrode 228. The second dummy gate pattern 326 includes a second dummy gate insulating film 327 and a second dummy gate electrode 328. For example, the first dummy gate insulating film 227 and the second dummy gate insulating film 327 may be silicon oxide films, and the first dummy gate electrode 228 and the second dummy gate electrode 328 may be polysilicon have.

The first dummy gate pattern 226 and the second dummy gate pattern 326 are formed to form the replacement gate electrode in the semiconductor device manufacturing method according to the embodiment of the present invention, It is not. That is, it is needless to say that a gate pattern can be formed by using a material to be used as a gate insulating film and a gate electrode of a transistor, not a dummy gate pattern.

A protective film covering the first dummy gate pattern 226, the second dummy gate pattern 326, the second finned active pattern 210, and the third finned active pattern 310 can be formed have. The protective film may serve to prevent the first dummy gate electrode 228 of the first dummy gate pattern 226 from being exposed to the etching process in a subsequent trimming process.

Referring to FIG. 28, a blocking pattern 20 covering the second region II is formed. Since the blocking pattern 20 is formed only in the second region II, the first region I is exposed by the blocking pattern 20.

The blocking pattern 20 is formed on the field insulating film 105. The blocking pattern 20 covers the second dummy gate pattern 326 and the third pinned active pattern 310.

On the other hand, the first dummy gate pattern 226 and the second fin-shaped active pattern 210 formed in the first region I are exposed.

29, the second portion 212 of the second fin-shaped active pattern protruding above the upper surface of the field insulating film 105 is formed by using the first dummy gate pattern 226 as a mask in the first region I And the third portion 213 of the second fin-shaped active pattern.

The trimming of the second portion 212 of the second pinned active pattern and the third portion 213 of the second pinned active pattern may be performed by trimming the second portion of the second pinned active pattern 212 and the third portion 213 of the second fin-shaped active pattern.

The second pinned active pattern 210 may be trimmed, for example, using the etching process 30. For example, the etch process 30 may utilize a material having an etch selectivity for the second finned active pattern 210. That is, only the second portion 212 and the third portion 213 of the second fin-shaped active pattern are etched by the etching process 30, and the field insulating film 105 may not be etched.

Then, the blocking pattern 20 covering the second region II is removed.

Referring to FIG. 30, a second gate spacer 240 is formed on the sidewalls of the first dummy gate pattern 226. A third gate spacer 340 is also formed on the sidewalls of the second dummy gate pattern 326.

A second gate spacer 240 may be formed on the second portion 212 of the second pinned active pattern and a third gate spacer 340 may be formed on the second portion 312 of the third pinned active pattern have.

Specifically, a spacer film covering the first dummy gate pattern 226, the second dummy gate pattern 326, the second finned active pattern 210, and the third finned active pattern 310 is formed. Thereafter, the etch back process may be performed to form the second gate spacer 240 and the third gate spacer 340.

A part of the third portion 213 of the second pinned active pattern exposed on both sides of the first dummy gate pattern 226 is removed using the first dummy gate pattern 226 as a mask, The first recess 230r is formed in the third portion 213 of the active pattern.

A part of the third portion 313 of the third pinned active pattern exposed on both sides of the second dummy gate pattern 326 is removed using the second dummy gate pattern 326 as a mask, The second recess 330r is formed in the third portion 313 of the second substrate 310. [

At this time, the height h22 of the second portion 312 of the third pinned active pattern exposed by the second recess 330r is equal to the height h22 of the second pinned active pattern exposed by the first recess 230r Is higher than the height (h21) of the two portions (212).

The second portion 212 of the second pinned active pattern has been trimming to a reduced height, but the second portion 312 of the third pinned active pattern has not been trimmed.

Referring to FIG. 31, a second source / drain 230 filling the first recess 230r is formed on the third portion 213 of the second fin-shaped active pattern.

On the third portion 313 of the third pinned active pattern, a third source / drain 330 filling the second recess 330r is formed.

The second source / drain 230 and the third source / drain 330 can be formed by, for example, epitaxial growth.

32, an interlayer insulating film 150 covering the second source / drain 230, the third source / drain 330, the first dummy gate pattern 226, the second dummy gate pattern 326, Is formed on the field insulating film 105.

The interlayer insulating film 150 may include at least one of a low dielectric constant material, an oxide film, a nitride film, and an oxynitride film. Low dielectric constant materials include, for example, FOX (Flowable Oxide), TONZ Silicon (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilaca Glass (PSG), Borophosphosilicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate, Fluoride Silicate Glass (FSG), High Density Plasma (HDP) oxide, Plasma Enhanced Oxide (PEOX), FCVD (Flowable CVD) oxide or a combination thereof.

Then, the interlayer insulating film 150 is planarized until the upper surfaces of the first dummy gate electrode 228 and the second dummy gate electrode 328 are exposed. As a result, the third mask pattern 2104a and the fourth mask pattern 2104b may be removed and the top surfaces of the first dummy gate electrode 228 and the second dummy gate electrode 328 may be exposed.

Subsequently, the first dummy gate pattern 226 and the second dummy gate pattern 326 are removed. The second gate electrode 220 and the third gate electrode 320 shown in FIG. 10 are formed by filling the space formed by removing the first dummy gate pattern 226 and the second dummy gate pattern 326, respectively, do.

A method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS. 25 to 27 and 30 to 34. FIG. The semiconductor device formed through the processes of FIGS. 25 to 27 and 30 to 34 may be the semiconductor device 5 described with reference to FIG.

33 and 34 are intermediate diagrams for explaining a semiconductor device manufacturing method according to another embodiment of the present invention.

Referring to Fig. 33, a blocking pattern 20 covering the second region II is formed. Since the blocking pattern 20 is formed only in the second region II, the first region I is exposed by the blocking pattern 20.

The blocking pattern 20 is formed on the field insulating film 105. The blocking pattern 20 covers the third pinned active pattern 310. On the other hand, the second pinned active pattern 210 formed in the first region I is exposed.

34, the second pinned active pattern 210 protruding above the upper surface of the field insulating film 105 is trimmed by using the blocking pattern 20 as a mask. Specifically, the first portion 211, the second portion 212, and the third portion 213 of the second pinned active pattern 210 are trimmed.

Trimming the second fin-shaped active pattern 210 includes reducing the height and width of the second fin-shaped active pattern 210 protruding above the top surface of the field insulating film 105.

Then, the blocking pattern 20 covering the second region II is removed.

Referring to FIGS. 27 and 30 to 32, the etching process is performed using the third mask pattern 2104a to form the first dummy gate pattern 226 extending in the fourth direction Y2 as the second fin- Is formed on the first portion 211 of the pattern. The etching process is performed by using the fourth mask pattern 2104b so that the second dummy gate pattern 326 extending in the sixth direction Y3 is formed on the first portion 311 of the third pinned active pattern .

A second gate spacer 240 is then formed on the second portion 212 of the second pinned active pattern and a third gate spacer 340 is formed on the second portion 312 of the third pinned active pattern do.

The first recess 230r is formed in the third portion 213 of the second fin-shaped active pattern using the first dummy gate pattern 226 as a mask, To form a second recess 330r in the third portion 313 of the third pinned active pattern.

Then, on the third portion 213 of the second fin-shaped active pattern, a second source / drain 230 filling the first recess 230r is formed. On the third portion 313 of the third pinned active pattern, a third source / drain 330 filling the second recess 330r is formed.

35 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the present invention.

35, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an SRAM. The semiconductor device according to the embodiments of the present invention may be provided in the storage device 1130 or may be provided as a part of the controller 1110, the input / output device 1120, the I / O, and the like.

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

36 and 37 are exemplary semiconductor systems to which a semiconductor device according to some embodiments of the present invention may be applied. Fig. 36 is a tablet PC, and Fig. 37 is a notebook. At least one of the semiconductor devices 1 to 10 according to the embodiments of the present invention can be used for a tablet PC, a notebook computer, and the like. It will be apparent to those skilled in the art that semiconductor devices according to some embodiments of the present invention may be applied to other integrated circuit devices not illustrated.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: substrate 105: field insulating film
110, 210, 260, 310, 360, 410: a pinned active pattern
120, 220, 320: gate electrode
130, 230, 280, 330, 380, 430: source / drain
135, 235: pin spacer 140, 240, 340: gate spacer

Claims (20)

  1. A first pinned active pattern formed on a substrate and extending in a first direction, the first pinned active pattern comprising first through third portions, wherein the first through third portions are sequentially arranged in the first direction, Wherein the height from the upper surface to the upper surface of the first portion is higher than the height from the upper surface of the substrate to the upper surface of the second portion and the height from the upper surface of the substrate to the upper surface of the second portion, A first pinned active pattern higher than a height to an upper surface of the portion;
    A gate electrode extending in a second direction different from the first direction, the gate electrode being formed on the first portion; And
    And a first source / drain formed on the third portion.
  2. The method according to claim 1,
    Further comprising a field insulating film formed on the substrate and in contact with a part of a side wall of the first pinned active pattern,
    And the sidewalls of the third portion are entirely in contact with the field insulating film.
  3. 3. The method of claim 2,
    Wherein a width of the first portion is greater than a width of the second portion at a first height from an upper surface of the field insulating film.
  4. The method according to claim 1,
    The upper surface of the second portion and the upper surface of the first portion are discontinuous,
    Wherein both side walls of the second portion facing in the second direction and the profiles of both side walls of the first portion facing the second direction are discontinuous.
  5. 5. The method of claim 4,
    The first portion including a connecting sidewall,
    The connecting sidewall connects an upper surface of the first portion and an upper surface of the second portion, and connects both sidewalls of the first portion and both sidewalls of the second portion.
  6. 6. The method of claim 5,
    And a gate spacer formed on the second portion and extending in the second direction,
    And the gate spacer overlaps with the connection sidewall.
  7. A substrate comprising a first region and a second region;
    Wherein the first transistor is formed on the substrate and extends in a first direction and includes first to third portions and the first to third portions are formed in the first direction A first gate electrode extending in a second direction different from the first direction and formed on the first portion; and a second source / drain region formed on the first portion, the first source / A first transistor including a drain; And
    A second transistor formed in the second region, the second transistor being formed on the substrate and extending in a third direction and including fourth to sixth portions, the fourth to sixth portions being formed in the third direction A second gate electrode extending in a fourth direction different from the third direction and formed on the fourth portion; and a second source / drain region formed on the sixth portion, the second source / And a second transistor including a drain,
    Wherein a height from an upper surface of the substrate to an upper surface of the first portion is higher than a height from an upper surface of the substrate to an upper surface of the second portion, The height of the third portion is higher than the height of the third portion,
    Wherein the height from the upper surface of the substrate to the upper surface of the fourth portion and the height from the upper surface of the substrate to the upper surface of the fifth portion are higher than the height from the upper surface of the substrate to the upper surface of the sixth portion.
  8. 8. The method of claim 7,
    Wherein a height from an upper surface of the substrate to an upper surface of the fourth portion is equal to a height from an upper surface of the substrate to an upper surface of the fifth portion.
  9. 9. The method of claim 8,
    Wherein the first transistor further comprises a first gate spacer formed on the second portion,
    And the second transistor further comprises a second gate spacer formed on the fifth portion.
  10. 9. The method of claim 8,
    Further comprising a field insulating film formed on the substrate and in contact with a part of a side wall of the first pinned active pattern,
    And the sidewalls of the third portion are entirely in contact with the field insulating film.
  11. 11. The method of claim 10,
    Wherein the first region is an SRAM region and the second region is a logic region.
  12. 11. The method of claim 10,
    Wherein the first region is a PMOS formation region of the SRAM, and the second region is an NMOS formation region of the SRAM.
  13. 8. The method of claim 7,
    And the width of the second source / drain in the fourth direction is larger than the width of the first source / drain in the second direction.
  14. A substrate comprising a first region and a second region;
    Wherein the first transistor is formed on the substrate and extends in a first direction and includes a first portion and a second portion and the second portion includes a first portion formed in the first region, A first gate electrode formed on the first portion and extending in a second direction different from the first direction and formed on the second portion; A first transistor including a first source / drain; And
    Wherein the second transistor is formed on the substrate and extends in a third direction and includes a third portion and a fourth portion and the fourth portion is formed in the second region, A second gate electrode formed on the third portion and extending in a fourth direction different from the third direction and formed on the fourth portion; And a second transistor including a second source / drain,
    And the width of the second source / drain in the fourth direction is larger than the width of the first source / drain in the second direction.
  15. 15. The method of claim 14,
    The height from the upper surface of the substrate to the upper surface of the first portion is higher than the height from the upper surface of the substrate to the upper surface of the second portion,
    Wherein the height from the upper surface of the substrate to the upper surface of the third portion is higher than the height from the upper surface of the substrate to the upper surface of the fourth portion.
  16. 16. The method of claim 15,
    The first pinned active pattern comprising a fifth portion disposed between the first portion and the second portion,
    Wherein the height from the upper surface of the substrate to the upper surface of the fifth portion is lower than the height from the upper surface of the substrate to the upper surface of the first portion and higher than the height from the upper surface of the substrate to the upper surface of the second portion.
  17. 16. The method of claim 15,
    Wherein the height from the upper surface of the substrate to the upper surface of the third portion is higher than the height from the upper surface of the substrate to the upper surface of the first portion.
  18. 15. The method of claim 14,
    And the height of the second source / drain is higher than the height of the first source / drain.
  19. A substrate comprising a first region and a second region;
    Wherein the first transistor is formed on the substrate and extends in a first direction and includes a first portion and a second portion and the second portion includes a first portion formed in the first region, A first gate electrode formed on the first portion and extending in a second direction different from the first direction and formed on the second portion; A first transistor including a first source / drain; And
    Wherein the second transistor is formed on the substrate and extends in a third direction and includes a third portion and a fourth portion and the fourth portion is formed in the second region, A second gate electrode formed on the third portion and extending in a fourth direction different from the third direction and formed on the fourth portion; And a second transistor including a second source / drain,
    The height from the upper surface of the substrate to the upper surface of the first portion is higher than the height from the upper surface of the substrate to the upper surface of the second portion,
    The height from the upper surface of the substrate to the upper surface of the third portion is higher than the height from the upper surface of the substrate to the upper surface of the fourth portion,
    Wherein the height from the upper surface of the substrate to the upper surface of the third portion is higher than the height from the upper surface of the substrate to the upper surface of the first portion.
  20. Forming a pinned active pattern which is defined by a field insulating film and extends in a first direction and which includes first to third portions sequentially arranged in the first direction and which protrudes above the upper surface of the field insulating film,
    Forming a dummy gate electrode on the first portion, the dummy gate electrode extending in a second direction different from the first direction and intersecting the pinned active pattern,
    Using the dummy gate electrode as a mask, trimming the second portion and the third portion protruding above the upper surface of the field insulating film,
    After the trimming, a gate spacer is formed on the sidewalls of the second portion and the dummy gate electrode,
    Forming a recess in the third portion using the dummy gate electrode as a mask,
    And forming a source / drain on the third portion to fill the recess.
KR1020140117063A 2014-09-03 2014-09-03 Semiconductor device and method for fabricating the same KR20160028242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020140117063A KR20160028242A (en) 2014-09-03 2014-09-03 Semiconductor device and method for fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020140117063A KR20160028242A (en) 2014-09-03 2014-09-03 Semiconductor device and method for fabricating the same
US14/750,303 US9490258B2 (en) 2014-09-03 2015-06-25 Semiconductor device and method for fabricating the same
US15/344,834 US10163913B2 (en) 2014-09-03 2016-11-07 Semiconductor device and method for fabricating the same
US16/196,197 US20190088662A1 (en) 2014-09-03 2018-11-20 Semiconductor device and method for fabricating the same

Publications (1)

Publication Number Publication Date
KR20160028242A true KR20160028242A (en) 2016-03-11

Family

ID=55403401

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140117063A KR20160028242A (en) 2014-09-03 2014-09-03 Semiconductor device and method for fabricating the same

Country Status (2)

Country Link
US (3) US9490258B2 (en)
KR (1) KR20160028242A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160028242A (en) * 2014-09-03 2016-03-11 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR20160114391A (en) * 2015-03-24 2016-10-05 삼성전자주식회사 Semiconductor device having stressor and method of fabricating the same
US20160300949A1 (en) * 2015-04-10 2016-10-13 Tae-Jong Lee Semiconductor devices and methods of fabricating the same
KR20170065729A (en) * 2015-12-03 2017-06-14 삼성전자주식회사 Method of fabricating the semiconductor device
US9935199B2 (en) 2016-01-15 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with source/drain structure
KR20170135510A (en) * 2016-05-31 2017-12-08 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR20180015399A (en) * 2016-08-03 2018-02-13 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9748382B1 (en) 2016-10-24 2017-08-29 International Business Machines Corporation Self aligned top extension formation for vertical transistors
CN108122976A (en) * 2016-11-29 2018-06-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof and sram
US10453943B2 (en) * 2016-11-29 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. FETS and methods of forming FETS
US10290738B2 (en) 2017-04-10 2019-05-14 Globalfoundries Inc. Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device
US10483266B2 (en) * 2017-04-20 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible merge scheme for source/drain epitaxy regions
US10121868B1 (en) * 2017-05-03 2018-11-06 Globalfoundries Inc. Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device
KR20190021102A (en) 2017-08-22 2019-03-05 삼성전자주식회사 Integrated circuit devices

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050062088A1 (en) * 2003-09-22 2005-03-24 Texas Instruments Incorporated Multi-gate one-transistor dynamic random access memory
KR100550343B1 (en) * 2003-11-21 2006-02-08 삼성전자주식회사 Method of manufacturing semiconductor device having multiple channels MOS transistor
KR100594282B1 (en) 2004-06-28 2006-06-30 삼성전자주식회사 Semiconductor device comprising FinFET and fabricating method thereof
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
KR20090011886A (en) * 2007-07-27 2009-02-02 삼성전자주식회사 Capacitorless dram and methods of manufacturing and operating the same
KR20100081667A (en) 2009-01-07 2010-07-15 삼성전자주식회사 Semiconductor devices having strained channels and methods of manufacturing the same
US8373238B2 (en) 2009-12-03 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with multiple Fin heights
US8313999B2 (en) * 2009-12-23 2012-11-20 Intel Corporation Multi-gate semiconductor device with self-aligned epitaxial source and drain
US8937353B2 (en) 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
US9076817B2 (en) * 2011-08-04 2015-07-07 International Business Machines Corporation Epitaxial extension CMOS transistor
US8643108B2 (en) 2011-08-19 2014-02-04 Altera Corporation Buffered finFET device
US8658505B2 (en) * 2011-12-14 2014-02-25 International Business Machines Corporation Embedded stressors for multigate transistor devices
JP5816560B2 (en) 2012-01-10 2015-11-18 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR101823105B1 (en) * 2012-03-19 2018-01-30 삼성전자주식회사 Method for fabricating field effect transistor
US9368388B2 (en) * 2012-04-13 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for FinFETs
KR101912582B1 (en) 2012-04-25 2018-12-28 삼성전자 주식회사 Semiconductor device and fabricated method thereof
US8901615B2 (en) * 2012-06-13 2014-12-02 Synopsys, Inc. N-channel and P-channel end-to-end finfet cell architecture
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
KR20150093543A (en) * 2014-02-07 2015-08-18 삼성전자주식회사 Semiconductor device including fin-type field effect transistor
KR20160028242A (en) * 2014-09-03 2016-03-11 삼성전자주식회사 Semiconductor device and method for fabricating the same

Also Published As

Publication number Publication date
US20170053921A1 (en) 2017-02-23
US10163913B2 (en) 2018-12-25
US20160064387A1 (en) 2016-03-03
US20190088662A1 (en) 2019-03-21
US9490258B2 (en) 2016-11-08

Similar Documents

Publication Publication Date Title
US7208815B2 (en) CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
KR20140095297A (en) Semiconductor device and fabricated method thereof
US9627542B2 (en) Semiconductor device and method for fabricating the same
TWI594423B (en) Field effect transistors including fin structures with different doped regions and semiconductor devices including the same
US8878309B1 (en) Semiconductor device having 3D channels, and methods of fabricating semiconductor devices having 3D channels
US9947672B2 (en) Semiconductor devices including a dummy gate structure on a fin
US20140299934A1 (en) Semiconductor Device and Method for Fabricating the Same
US9721952B2 (en) Semiconductor devices having gate patterns in trenches with widened openings
US9490177B2 (en) Integrated circuit devices including stress proximity effects and methods of fabricating the same
US10269928B2 (en) Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels
US20140374827A1 (en) Semiconductor device and method for fabricating the same
JP2013069885A (en) Semiconductor device and method for manufacturing the same
US8927373B2 (en) Methods of fabricating non-planar transistors including current enhancing structures
US10096688B2 (en) Integrated circuit device and method of manufacturing the same
US8716156B1 (en) Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
US9515182B2 (en) High-integration semiconductor device and method for fabricating the same
US9299811B2 (en) Methods of fabricating semiconductor devices
KR20150056307A (en) Semiconductor device having fin field effect transistor and methods of forming the same
US9379244B2 (en) Semiconductor device having fin-type field effect transistor and method of manufacturing the same
US9362397B2 (en) Semiconductor devices
KR20160011742A (en) Semiconductor device
US9673099B2 (en) Method of fabricating integrated circuit devices
US9269813B2 (en) Field effect transistor
KR20150077543A (en) Semiconductor device and method for fabricating the same
US9412816B2 (en) Semiconductor device including multiple nanowire transistor

Legal Events

Date Code Title Description
A201 Request for examination