KR102410135B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device may include first and second active fins extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, and on the first and second active fins, the first and second active fins A gate structure extending in two directions, a first semiconductor pattern formed on the first active fin and disposed on at least one side of the gate structure, is formed on the second active fin, and is formed on at least one side of the gate structure a second semiconductor pattern disposed below, wherein the first semiconductor pattern is disposed under the first pattern between the first pattern including a first semiconductor material and the first and second active fins; a second pattern including a second semiconductor material different from a first semiconductor material, wherein the second semiconductor pattern is formed between a third pattern including the first semiconductor material and the first and second active fins. A fourth pattern is disposed under the third pattern, includes the second semiconductor material, and is in contact with the second pattern.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

Recently, semiconductor devices have been developed in a direction capable of high-speed operation at a low voltage, and semiconductor device manufacturing processes have been developed in a direction to improve integration.

Interest in fin field-effect transistors (FinFETs), in which channels are formed in a three-dimensional spatial structure, to better withstand short channel effects and provide higher driving currents at low voltages compared to traditional field-effect transistors this is rising

The technical problem to be solved by the present invention is to reduce a void space in forming an elevated source/drain in a process of manufacturing a finFET device having merged active fins. An object of the present invention is to provide a semiconductor device having a structure in which an etchant is provided to prevent a portion of a source/drain from being etched.

Another technical problem to be solved by the present invention is to form an elevated source / drain (elevated Source / Drain) in a process for manufacturing a FinFET device having a merged active fin (void) space To provide a method of manufacturing a semiconductor device capable of preventing a portion of a source/drain from being etched by providing an etchant through the etchant.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention provides first and second active fins extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction , a gate structure formed on the first and second active fins to extend in the second direction, a first semiconductor pattern formed on the first active fin and disposed on at least one side of the gate structure, and the second a second semiconductor pattern formed on an active fin and disposed on at least one side of the gate structure, wherein the first semiconductor pattern includes a first pattern including a first semiconductor material, and the first and second active patterns a second pattern disposed under the first pattern between fins and including a second semiconductor material different from the first semiconductor material, wherein the second semiconductor pattern includes a second pattern including the first semiconductor material a third pattern and a fourth pattern disposed below the third pattern between the first and second active fins, including the second semiconductor material, and in contact with the second pattern.

In some embodiments of the present invention, the first pattern and the third pattern may be in contact.

In some embodiments of the present disclosure, the first pattern includes a first sub-pattern and a second sub-pattern on the first sub-pattern, and the third pattern includes a third sub-pattern and on the third sub-pattern. A fourth sub-pattern may be included.

In some embodiments of the present disclosure, concentrations of impurities included in the first semiconductor material may be different between the first sub-pattern and the second sub-pattern.

In some embodiments, the third sub-pattern and the fourth sub-pattern may have different concentrations of impurities included in the first semiconductor material.

In some embodiments of the present disclosure, the second pattern may be formed to cover the entire lower surface of the first pattern between the first and second active fins.

In some embodiments of the present disclosure, the fourth pattern may be formed to cover the entire lower surface of the third pattern between the first and second active fins.

In some embodiments of the present invention, the second pattern may be formed to cover the entire outer surface of the first pattern.

In some embodiments of the present invention, the fourth pattern may be formed to cover the entire outer surface of the third pattern.

In some embodiments of the present invention, the first semiconductor material may include at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the second semiconductor material may include SiGe.

In some embodiments of the present invention, the second semiconductor material may include 5 to 10% Ge.

In some embodiments of the present invention, the first semiconductor material may have a smaller lattice constant than the second semiconductor material.

In accordance with another embodiment of the present invention, there is provided a semiconductor device, first and second active fins extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction , a gate structure formed on the first and second active fins and extending in the second direction; a first semiconductor pattern formed on the first active fin; a second semiconductor pattern formed on the second active fin; A first field insulating layer formed between the first and second active fins and on the field insulating layer between the first and second active fins is spaced apart from the field insulating layer to be in contact with the first and second semiconductor patterns. a first pattern including a semiconductor material, and a second pattern formed on the first pattern and including a second semiconductor material different from the first semiconductor material.

In some embodiments of the present disclosure, the first and second semiconductor patterns may include the second semiconductor material.

In some embodiments of the present disclosure, a concentration of an impurity of the first semiconductor material included in the second pattern may be higher than a concentration of an impurity of the first semiconductor material included in the first and second semiconductor patterns. .

In some embodiments of the present invention, the first semiconductor material may include an n-type impurity.

In some embodiments of the present invention, the first semiconductor material may include at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the first pattern may include SiGe.

In some embodiments of the present invention, the first pattern may include 5 to 10% of Ge.

In some embodiments of the present disclosure, a lattice constant of the second semiconductor material may be lower than a lattice constant of the first semiconductor material.

A semiconductor device according to another embodiment of the present invention for solving the above technical problem includes a substrate in which a first region and a second region are defined, the substrate extending in the first region of the substrate, and the first direction First and second active fins formed to be spaced apart from each other in a second direction intersecting the , a first gate structure formed on the first and second active fins to extend in the second direction, and the first and second active fins a first semiconductor pattern formed on at least one side of the first gate structure, a first semiconductor pattern including a first semiconductor material, and a lower portion of the first semiconductor pattern between the first and second active fins; a second semiconductor pattern including a second semiconductor material different from a first semiconductor material, third and fourth active fins extending in the first direction in a second region of the substrate and spaced apart from each other in the second direction; a second gate structure formed on the third and fourth active fins extending in the second direction, and formed on the third and fourth active fins, disposed on at least one side of the second gate structure, and and a third semiconductor pattern including a second semiconductor material.

In some embodiments of the present invention, the first semiconductor material may include an n-type impurity.

In some embodiments of the present invention, the second semiconductor material may include germanium.

In some embodiments of the present invention, the first semiconductor material may include at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the second semiconductor material may include SiGe.

In some embodiments of the present invention, the second semiconductor pattern may include 5 to 10% Ge.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention for solving the above technical problem, first and second fins extending in a first direction are formed on a substrate, and the first and second fins are formed on the first and second fins. , forming a dummy gate electrode extending in a second direction intersecting the first direction, and epitaxially forming first and second semiconductor patterns on the first and second fins disposed on at least one side of the dummy gate electrode growing, but not contacting the first and second semiconductor patterns, and forming a blocking epitaxial layer under the first and second semiconductor patterns between the first and second semiconductor patterns, wherein the blocking epitaxial layer is formed The layer includes a material different from that of the first and second semiconductor patterns, and includes removing the dummy gate electrode.

In some embodiments of the present invention, the blocking epitaxial layer is formed on lower surfaces of the first and second semiconductor patterns by merging the first and second semiconductor patterns, and is formed on the first and second semiconductor patterns. 2 It is possible to protect the semiconductor pattern. The semiconductor material included in the blocking layer may have a smaller lattice constant than the semiconductor material included in the first and second semiconductor patterns.

In some embodiments of the present invention, the method may further include removing a portion of the blocking layer formed on the externally exposed surfaces of the first and second semiconductor patterns.

In some embodiments of the present invention, removing the blocking film may use HCl or GeH4.

In some embodiments of the present invention, after removing the blocking layer, the method further comprises growing an epitaxial layer on the first and second semiconductor patterns exposed to the outside, wherein the epitaxial layer includes the first and second semiconductor patterns. It may include the same material as the material included in the second semiconductor pattern.

The details of other embodiments are included in the detailed description and drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA of FIG. 1 .
3 is a cross-sectional view taken along line BB of FIG. 1 .
4 and 5 are cross-sectional views of a semiconductor device according to a second embodiment of the present invention.
6 and 7 are cross-sectional views of a semiconductor device according to a third embodiment of the present invention.
8 and 9 are cross-sectional views of a semiconductor device according to a fourth embodiment of the present invention.
10 and 11 are cross-sectional views of a semiconductor device according to a fifth embodiment of the present invention.
12 and 13 are cross-sectional views of a semiconductor device according to a sixth embodiment of the present invention.
14 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention.
15 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention.
16 is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention.
17 to 19 are circuit diagrams and layout diagrams for explaining a semiconductor device according to a tenth embodiment of the present invention.
20 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
22 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
23 to 31 are intermediate steps for explaining a method of manufacturing a semiconductor device according to the present invention.
32 is a schematic block diagram illustrating an electronic system including a semiconductor device according to some embodiments of the present invention.
33 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When one component is referred to as “connected to” or “coupled to” with another component, it means that it is directly connected or coupled to another component or intervening another component. including all cases. On the other hand, when one component is referred to as “directly connected to” or “directly coupled to” with another component, it indicates that another component is not interposed therebetween. “and/or” includes each and every combination of one or more of the recited items.

When a component is referred to as “on” or “on” another component, it includes all cases in which another component is interposed in the middle as well as directly above the other component. On the other hand, when a component is referred to as “directly on” or “directly above” another component, it indicates that other components are not interposed therebetween.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between components and other components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, when an element shown in the drawings is turned over, a component described as "beneath" or "beneath" of another element may be placed "above" the other element. . Accordingly, the exemplary term “below” may include both directions below and above. Components may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and/or "comprising" refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1 . 3 is a cross-sectional view taken along line B-B of FIG. 1 .

1 to 3 , a semiconductor device 1 according to a first embodiment of the present invention includes a substrate 100 , a field insulating layer 110 , a first active fin F1 , and a second active fin F2 . ), a first gate structure TR1 , a second gate structure TR2 , a first semiconductor pattern 210 , a second semiconductor pattern 220 , a blocking layer 300 , and the like.

The substrate 100 may be a rigid substrate such as a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, or polyimide, polyester. ) may be a flexible plastic substrate such as polycarbonate, polyethersulfone, polymethylmethacrylate, polyethylene naphthalate, or polyethyleneterephthalate.

The substrate 100 may include a first region (I) and a second region (II). The first region (I) and the second region (II) may be separated by a field insulating layer 110 such as shallow trench isolation (STI). Here, the first region (I) may be an NMOS region and the second region (II) may be a PMOS region, but is not limited thereto, and the first region (I) is a PMOS region and the second region (II) is an NMOS region. It can be an area.

However, hereinafter, for convenience of description, the NMOS region of the substrate 100 will be described.

The field insulating layer 110 is formed on the substrate 100 and is used for device isolation. The field insulating film 110 is an insulating film, and may be an HDP oxide film, an SOG oxide film, a CVD oxide film, or the like, but is not limited thereto.

The first active fin F1 and the second active fin F2 are formed on the substrate 100 . For example, the first active fin F1 and the second active fin F2 may protrude from the substrate 100 . For example, the first active fin F1 and the second active fin F2 may be formed to protrude from the substrate 100 in the third direction Z.

The first active fin F1 and the second active fin F2 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The first active fin F1 and the second active fin F2 may extend long in the first direction X. The field insulating layer 110 may cover an upper surface of the substrate 100 and a portion of side surfaces of the first and second active fins F1 and F2 .

The first active fin F1 and the second active fin F2 may have a long side and a short side. The first active fin F1 and the second active fin F2 may be spaced apart from each other and disposed on the substrate 100 . For example, the first active fin F1 and the second active fin F2 may be spaced apart from each other in the second direction Y. In FIG. 1 , the long side direction is illustrated as the first direction (X) and the short side direction as the second direction (Y), but the present invention is not limited thereto. For example, the long side direction of the first active fin F1 and the second active fin F2 may be the second direction Y and the short side direction may be the first direction X.

The first gate structure TR1 may be formed on the first active fin F1 and the second active fin F2 in a direction crossing the first and second active fins F1 and F2 . The first gate structure TR1 may extend long in the second direction Y.

The first gate structure TR1 includes the interface layer 120 , the gate insulating layer 130 , the work function control layer 140 , and the gate metal sequentially formed on the first active fin F1 and the second active fin F2 . 150 and a gate spacer 160 may be included. Channels may be formed on both sides and top surfaces of the first active fin F1 and the second active fin F2 covered by the first gate structure TR1 .

The interface layer 120 may be formed on the field insulating layer 110 and the first and second active fins F1 and F2 . The interface layer 120 may serve to prevent a defective interface between the field insulating layer 110 and the gate insulating layer 130 .

The interface film 120 is a low-k material layer having a dielectric constant (k) of 9 or less, for example, a silicon oxide film (k is about 4) or a silicon oxynitride film (k is about 4-8 depending on the content of oxygen atoms and nitrogen atoms) may include According to some embodiments, the interface layer 120 may be made of silicate or a combination of the aforementioned layers. According to other embodiments, the interface layer 120 may not be formed.

The gate insulating layer 130 may be formed on the interface layer 120 . However, when the interface layer 120 does not exist, the gate insulating layer 130 may be formed on the field insulating layer 110 and the first and second active fins F1 and F2 .

The gate insulating layer 130 may include a material having a high dielectric constant (high-k). Specifically, the gate insulating layer 130 may include, for example, HfSiON, HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ , BaTiO ₃ , and/or SrTiO ₃ .

Meanwhile, the gate insulating layer 130 may be formed to have an appropriate thickness according to the type of device to be formed. For example, when the gate insulating layer 130 is made of HfO ₂ , the gate insulating layer 130 may be formed to a thickness of about 50 Å or less (about 5 Å to 50 Å), but is not limited thereto. According to some embodiments of the present invention, as shown in FIG. 1 , the gate insulating layer 130 may extend upward along the sidewall of the gate spacer 160 , which will be described later.

The work function control layer 140 may be formed on the gate insulating layer 130 . The work function control layer 140 may be formed in contact with the gate insulating layer 130 . The work function control layer 140 is used to control the work function.

The work function control layer 140 may include, for example, a metal nitride. Specifically, the work function control layer 140 may include at least one of Mo, Pd, Ru, Pt, TiN, WN, TaN, Ir, TaC, RuN, TiAl, TaAlC, TiAlN, and MoN. More specifically, the work function control layer 140 may be formed of, for example, a single layer made of TiN or a double layer made of a TiN lower layer and a TaN upper layer, but is not limited thereto.

According to some embodiments of the present disclosure, as shown in FIG. 1 , the work function control layer 140 may also extend upward along the sidewall of the gate spacer 160 , which will be described later.

The gate metal 150 may be formed on the work function control layer 140 . As illustrated, the gate metal 150 may be formed in contact with the work function control layer 140 . That is, the gate metal 150 may be formed to fill the space created by the work function control layer 140 . The gate metal 150 may include a conductive material, for example, W or Al, but is not limited thereto.

The gate spacer 160 may be formed on at least one side of the side surfaces of the first gate structure TR1 . The gate spacer 160 may include at least one of a nitride layer, an oxynitride layer, and a low-k material.

In addition, although one side of the gate spacer 160 is shown as a curved line, the present invention is not limited thereto, and the shape of the gate spacer 160 may be different from this. For example, the gate spacer 160 may have an I-shape or an L-shape, different from that illustrated.

In addition, although it is illustrated that the gate spacer 160 is formed of a single layer in the drawings, the present invention is not limited thereto, and may be formed of a plurality of layers.

Meanwhile, the source/drain regions may be formed on at least one side of both sides of the first gate structure TR1 and may be formed in the first and second active fins F1 and F2 . The source/drain region and the first gate structure TR1 may be insulated by the gate spacer 160 .

When the semiconductor device 1 is an NMOS transistor, the source/drain regions may include the same material as the substrate 100 or a tensile stress material. For example, when the substrate 100 is Si, the source/drain regions may be Si or a material having a lattice constant smaller than Si (eg, SiC, SiP, and/or SiCP). The tensile stress material may improve carrier mobility in the channel region by applying tensile stress to the first and second active fins F1 and F2 under the first gate structure TR1 , that is, the channel region.

Meanwhile, when the semiconductor device 1 is a PMOS transistor, the source/drain regions may include a compressive stress material. For example, the compressive stress material may be a material having a lattice constant larger than that of Si, for example, SiGe. The compressive stress material may apply compressive stress to the first and second active fins F1 and F2 under the first gate structure TR1 , ie, the channel region, to improve carrier mobility in the channel region.

In some embodiments of the present invention, the source/drain regions may be formed through epitaxial growth, but the present invention is not limited thereto.

The second gate structure TR2 may be formed on the first active fin F1 and the second active fin F2 in a direction crossing the first and second active fins F1 and F2 . The second gate structure TR2 may extend long in the second direction Y.

The second gate structure TR2 may have substantially the same configuration as the first gate structure TR1 described above.

The first semiconductor pattern 210 is formed on the first active fin F1 and is disposed on at least one side of the first gate structure TR1 . Specifically, the first semiconductor pattern 210 may be formed on the first active fin F1 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a portion of the first active fin F1 . Even in this case, the first semiconductor pattern 210 may be formed using the SEG process.

In the NMOS region of the FinFET device, when the first semiconductor pattern 210 is formed, it may be formed of a material capable of providing tensile stress. That is, a tensile stress may be applied to the channel region by the first semiconductor pattern 210 . Accordingly, the first semiconductor pattern 210 may be formed of a material having a smaller lattice constant than the substrate 100 . For example, when the substrate 100 is made of silicon (Si), the first semiconductor pattern 210 may be formed of silicon (Si). may include SiP. SiP may be silicon doped with phosphorus (P). According to some embodiments, the first semiconductor pattern 210 may include silicon carbon (SiC) or silicon carbon (SiCP) doped with phosphorus (P). The second semiconductor pattern 220 is formed on the second active fin F2 . Specifically, the second semiconductor pattern 220 may be formed on the second active fin F2 using an SEG process.

Alternatively, the second semiconductor pattern 220 may be formed by filling a recess formed in at least a portion of the second active fin F2 . Even in this case, the second semiconductor pattern 220 may be formed using the SEG process.

Like the first semiconductor pattern 210 , the second semiconductor pattern 220 may be formed of a material capable of providing a tensile stress to the channel region. The second semiconductor pattern 220 may include the same material as the first semiconductor pattern 22 . The second semiconductor pattern 220 may be formed together in the process of forming the first semiconductor pattern 210 , but if necessary, the first semiconductor pattern 210 and the second semiconductor pattern 220 may be separately formed. may be

When the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed by the SEG process, the first semiconductor pattern 210 and the second semiconductor pattern 220 have a <100> direction due to the characteristics of the fin structure. A facet is formed to have a diamond-shaped profile.

If the first semiconductor pattern 210 and the second semiconductor pattern 220 are grown to form a merged fin structure, the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 due to profile characteristics. A void space is generated in the lower part of the In a subsequent process, when an etchant (eg, aqueous ammonia (NH ₃ )) is introduced into the void space, lower surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 may be etched.

That is, ammonia water can be used as an etchant in the process of removing the dummy gate electrode. If a path is formed between the dummy gate electrode and the void space, the etchant (eg, ammonia water) flows through this path. It may flow into the void space, and lower surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 exposed to the void space may be etched.

Therefore, in the present invention, before forming the merged fin structure by merging the adjacent first semiconductor pattern 210 and the second semiconductor pattern 220 , the first semiconductor pattern 210 and the second semiconductor pattern 220 are It is intended to protect the first semiconductor pattern 210 and the second semiconductor pattern 220 from the etchant (eg, ammonia water) flowing into the void space by forming the blocking film 300 under the void space. If the first semiconductor pattern 210 and the second semiconductor pattern 220 are etched, characteristics of the semiconductor device may be affected and reliability problems may occur.

The blocking layer 300 should be formed of a material different from that of the first semiconductor pattern 210 and the second semiconductor pattern 220 . That is, if, for example, SiP is included in the first semiconductor pattern 210 and the second semiconductor pattern 220 in the NMOS region, the blocking film 300 is formed with respect to an etchant (eg, ammonia water) rather than SiP. It needs to be formed by including a relatively resistant material. As such a material, for example, SiGe can be used. However, the blocking film 300 is not limited thereto, as long as it is a material having relatively strong resistance to an etchant (eg, aqueous ammonia), and may include other materials.

The blocking layer 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 and below the first semiconductor pattern 210 and the second semiconductor pattern 220 . For example, the blocking layer 300 may be formed to merge the first semiconductor pattern 210 and the second semiconductor pattern 220 . The blocking layer 300 may be formed on a lower surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 between the first semiconductor pattern 210 and the second semiconductor pattern 220 . The blocking layer 300 may be formed to entirely cover the lower surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 between the first semiconductor pattern 210 and the second semiconductor pattern 220 . .

According to the present invention, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The blocking layer 300 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe.

Here, when SiGe is included in the blocking layer 300 , 5 to 10% of Ge may be included. Ge included in the blocking film 300 serves to protect the lower portions of the first semiconductor pattern 210 and the second semiconductor pattern 220 , but when the Ge concentration is too high, the first semiconductor pattern 210 And since it may affect the stress characteristics of the second semiconductor pattern, the blocking layer 300 may contain 5 to 10% of Ge.

Hereinafter, semiconductor devices according to other embodiments of the present invention will be described.

4 and 5 are cross-sectional views of a semiconductor device according to a second embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

4 and 5 , in the semiconductor device 2 according to the second embodiment of the present invention, the blocking layer 310 is formed on the outer surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 . It is formed to cover the whole.

Specifically, the blocking layer 310 is formed on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged. It can be formed by epi-growth based on the. In this state, if the blocking layer 310 is removed except for the blocking layer 310 positioned below the gap between the first semiconductor pattern 210 and the second semiconductor pattern 220 , the first embodiment of the present invention The blocking film 300 having the same shape as the semiconductor device 1 according to the example may be formed.

According to the semiconductor device 2 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). ) and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The blocking layer 310 is relatively resistant to an etchant (eg, aqueous ammonia). This strong semiconductor material may be included, for example, SiGe, Here, when SiGe is included in the blocking layer 310, Ge may be included in an amount of 5 to 10%.

6 and 7 are cross-sectional views of a semiconductor device according to a third embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

6 and 7 , in the semiconductor device 3 according to the third embodiment of the present invention, the blocking layer 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 , It is disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and the cap epitaxial layer 400 is exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 . placed on top According to some embodiments, unlike the blocking layer 300 connecting the first and second semiconductor patterns 210 and 220 illustrated in FIG. 7 , the blocking layer 300 includes the first and second semiconductor patterns. It may be separated between 210 and 220 , and the first and second semiconductor patterns 210 and 220 may be connected or merged by the CAP epitaxial layer 400 .

Specifically, in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 is used as a base for epitaxial growth. After forming the blocking film, the blocking film on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, and the blocking film 300 in the semiconductor device 3 is removed. can form. According to some embodiments, a portion of the blocking layer 300 connecting between the first and second semiconductor patterns 210 and 220 is further etched to form the first semiconductor pattern 210 and the second semiconductor pattern 220 . may be separated from each other. In this state, the first semiconductor pattern 210 and the second semiconductor pattern 220 are on the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 . The cap epitaxial layer 400 may be formed by epitaxial growth based on the surface exposed to the outside of the .

According to the semiconductor device 3 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The blocking layer 300 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. Here, when SiGe is included in the blocking layer 300 , 5 to 10% of Ge may be included.

Also, like the first semiconductor pattern 210 and the second semiconductor pattern 220 , the cap epitaxial layer 400 may include n-type impurities. For example, the cap epitaxial layer 400 may include The first semiconductor pattern 210 and the second semiconductor pattern 220 may include the same material. For example, the cap epitaxial layer 400 may also include SiP, but is not limited thereto. The concentration of phosphorus (P) included in the cap epitaxial layer 400 may be higher than the concentration of phosphorus (P) included in the first semiconductor pattern 210 and the second semiconductor pattern 220 .

When the blocking film material on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, the first semiconductor pattern 210 and the second semiconductor pattern 220 are outside. The exposed surface may be damaged, and the cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance stress characteristics.

8 and 9 are cross-sectional views of a semiconductor device according to a fourth embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

8 and 9 , in the semiconductor device 4 according to the fourth embodiment of the present invention, the first blocking layer 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 . is disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and the second blocking film 301 is disposed on the lower surface exposed to the outside of the first semiconductor pattern 210 , , the third blocking layer 302 is disposed on the lower surface exposed to the outside of the second semiconductor pattern 220 .

Specifically, in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 is used as a base for epitaxial growth. After forming the blocking film, the blocking film on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, but the first semiconductor pattern 210 and the second semiconductor pattern ( By removing only the blocking film on the upper surface of 220 , the first to third blocking films 300 , 301 , and 302 may be formed.

In this case, a dry etching process may be used to remove the blocking film on the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 , for example, HCl and/or The blocking film can be removed using GeH4.

According to the semiconductor device 4 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The first to third blocking layers 300 , 301 , and 302 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. . Here, when SiGe is included in the first to third blocking layers 300 , 301 , and 302 , 5 to 10% of Ge may be included.

10 and 11 are cross-sectional views of a semiconductor device according to a fifth embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

10 and 11 , in the semiconductor device 5 according to the fifth embodiment of the present invention, the blocking film 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 , It is disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and the upper pattern 401 is disposed on upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

Specifically, in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 is used as a base for epitaxial growth. After forming the blocking layer, the blocking layer 300 may be formed by removing the blocking layer on the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

In addition, the upper pattern 401 may be formed on the upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 using an ALD or PVD process.

According to the semiconductor device 5 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The blocking layer 300 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. Here, when SiGe is included in the blocking layer 300 , 5 to 10% of Ge may be included.

Also, the upper pattern 401 may include an n-type impurity like the first semiconductor pattern 210 and the second semiconductor pattern 220 . For example, the upper pattern 401 may include the first semiconductor pattern ( 210 and the second semiconductor pattern 220 may include the same material. For example, the upper pattern 401 may also include SiP. However, the concentration of P included in the upper pattern 401 is P included in the first semiconductor pattern 210 and the second semiconductor pattern 220 . may be higher than the concentration of

12 and 13 are cross-sectional views of a semiconductor device according to a sixth embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

12 and 13 , in the semiconductor device 6 according to the sixth embodiment of the present invention, the first blocking layer 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 . is disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and the second blocking film 301 is disposed on the lower surface exposed to the outside of the first semiconductor pattern 210 , , the third blocking layer 302 is disposed on the lower surface exposed to the outside of the second semiconductor pattern 220 .

In addition, the upper pattern 401 is disposed on the upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

Specifically, in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 is used as a base for epitaxial growth. After forming the blocking film, the blocking film on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, but the first semiconductor pattern 210 and the second semiconductor pattern ( By removing only the blocking film on the upper surface of 220 , the first to third blocking films 300 , 301 , and 302 may be formed.

In addition, the upper pattern 401 may be formed on the upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 using an ALD or PVD process or an epitaxial process.

According to the semiconductor device 6 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The first to third blocking layers 300 , 301 , and 302 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. . Here, when SiGe is included in the first to third blocking layers 300 , 301 , and 302 , 5 to 10% of Ge may be included.

Also, the upper pattern 401 may include an n-type impurity like the first semiconductor pattern 210 and the second semiconductor pattern 220 . For example, the upper pattern 401 may include the first semiconductor pattern ( 210 and the second semiconductor pattern 220 may include the same material. For example, the upper pattern 401 may also include SiP. However, the concentration of P included in the upper pattern 401 is P included in the first semiconductor pattern 210 and the second semiconductor pattern 220 . may be higher than the concentration of

14 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 14 , in the semiconductor device 7 according to the seventh embodiment of the present invention, the first gate structure TR1 is sequentially formed on the first active fin F1 and the second active fin F2 . It may include an interface layer 120 , a gate insulating layer 130 , a work function control layer 140 , a gate metal 150 , a dummy gate spacer 161 , a normal gate spacer 162 , and the like.

In the semiconductor device 7 , the second gate structure TR2 may have substantially the same configuration as the first gate structure TR1 .

The interface layer 120 , the gate insulating layer 130 , the work function control layer 140 , and the gate metal 150 are substantially the same as described above. According to some embodiments, the interface layer 120 and the dummy gate spacer 161 may not be formed.

In the process of manufacturing the semiconductor device 7 , after the dummy gate structure is formed, the dummy gate spare 161 and the normal gate spacer 162 are formed on the side surface of the dummy gate structure, and the first semiconductor pattern 210 is formed. , the second semiconductor pattern 220 and the blocking layer 300 are formed, and the dummy gate electrode is removed and then the gate structure (eg, the first gate structure TR1 and the second gate structure TR2) In this case, the dummy gate spacer 161 may remain in a shape in which the dummy gate spacer 161 is left in the process of removing the dummy gate structure. The normal gate spacer 162 includes the first and second semiconductor patterns 210 and 220. The poles of the normal gate structure (eg, the first gate structure TR1 and the second gate structure TR2 ) may be insulated. The gate structure may be a normal gate structure.

15 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 15 , a semiconductor device 8 according to an eighth embodiment of the present invention includes a substrate 100 in which a first region I and a second region are defined.

A first active fin F1 and a second active fin F2 are formed on the first region I of the substrate 100 . For example, the first active fin F1 and the second active fin F2 may protrude from the substrate 100 .

The first active fin F1 and the second active fin F2 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The field insulating layer 110 may cover an upper surface of the substrate 100 and a portion of side surfaces of the first and second active fins F1 and F2 .

The first semiconductor pattern 210 is formed on the first active fin F1 . Specifically, the first semiconductor pattern 210 may be formed on the first active fin F1 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a portion of the first active fin F1 . Even in this case, the first semiconductor pattern 210 may be formed using the SEG process.

The second semiconductor pattern 220 is formed on the second active fin F2 . Specifically, the second semiconductor pattern 220 may be formed on the second active fin F2 using an SEG process.

Alternatively, the second semiconductor pattern 220 may be formed by filling a recess formed in at least a portion of the second active fin F2 . Even in this case, the second semiconductor pattern 220 may be formed using the SEG process.

The blocking layer 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 , under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and is a cap epitaxial layer. Reference numeral 400 is disposed on surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

In a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the blocking film is epitaxially grown based on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 . After forming, the blocking film on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed to form the blocking film 300 in the semiconductor device 8 . can In this state, the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed on the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 . The cap epitaxial layer 400 may be formed by epitaxial growth using the base.

According to the semiconductor device 8 , the first region I may be an NMOS region, and the first semiconductor pattern 210 and the second semiconductor pattern 220 may include n-type impurities (eg, phosphorus (P)). may include The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The blocking layer 300 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. Here, when SiGe is included in the blocking layer 300 , 5 to 10% of Ge may be included.

In addition, the keep epitaxial layer 400 may include n-type impurities like the first semiconductor pattern 210 and the second semiconductor pattern 220 , and for example, the cap epitaxial layer 400 may include the first semiconductor pattern 210 and the second semiconductor pattern 220 . The first semiconductor pattern 210 and the second semiconductor pattern 220 may include the same material. For example, the cap epitaxial layer 400 may also include SiP. However, the concentration of phosphorus (P) included in the cap epitaxial layer 400 is determined by the first semiconductor pattern 210 and the second semiconductor pattern. It may be higher than the concentration of P contained in (220).

When the blocking film material on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, the first semiconductor pattern 210 and the second semiconductor pattern 220 are outside. The exposed surface may be damaged, and the cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance tensile stress characteristics.

A third active fin F3 and a fourth active fin F4 are formed on the second region II of the substrate 100 . For example, the third active fin F3 and the fourth active fin F4 may protrude from the substrate 100 .

The third active fin F3 and the fourth active fin F4 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The field insulating layer 110 may cover an upper surface of the substrate 100 and a portion of side surfaces of the third and fourth active fins F3 and F4 .

The third semiconductor pattern 230 is formed on the third and fourth active fins F3 and F4 . Specifically, the third semiconductor pattern 230 may be formed on the third and fourth active fins F3 and F4 using a selective epitaxial growth (SEG) process.

The third semiconductor pattern 230 may include, for example, the same material as the material included in the blocking layer 300 . The second region II may be, for example, a PMOS region, and may include a p-type impurity (eg, boron) in the third semiconductor pattern 230 . The third semiconductor pattern 230 may include, for example, SiGe.

16 is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 16 , a semiconductor device 9 according to a ninth embodiment of the present invention includes a substrate 100 in which a first region I and a second region are defined.

A fifth active fin F5 and a sixth active fin F6 are formed on the first region I of the substrate 100 . For example, the fifth active fin F5 and the sixth active fin F6 may protrude from the substrate 100 .

The fifth active fin F5 and the sixth active fin F6 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The field insulating layer 110 may cover an upper surface of the substrate 100 and a portion of side surfaces of the fifth and sixth active fins F5 and F6 .

The first semiconductor pattern 210 is formed on the fifth active fin F5 . Specifically, the first semiconductor pattern 210 may be formed on the fifth active fin F5 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a portion of the fifth active fin F5 . Even in this case, the first semiconductor pattern 210 may be formed using the SEG process.

The second semiconductor pattern 220 is formed on the sixth active fin F6 . Specifically, the second semiconductor pattern 220 may be formed on the sixth active fin F6 using an SEG process.

Alternatively, the second semiconductor pattern 220 may be formed by filling a recess formed in at least a portion of the sixth active fin F6 . Even in this case, the second semiconductor pattern 220 may be formed using the SEG process.

The blocking layer 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 , under the first semiconductor pattern 210 and the second semiconductor pattern 220 , and is a cap epitaxial layer. Reference numeral 400 is disposed on surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

In a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, the blocking film is epitaxially grown based on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 . After forming, the blocking film on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed to form the blocking film 300 in the semiconductor device 8 . can In this state, the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed on the surfaces exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 . The cap epitaxial layer 400 may be formed by epitaxial growth using the base.

According to the semiconductor device 9 , the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). For example, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The blocking film 300 may include a semiconductor material having relatively strong resistance to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. . Here, when SiGe is included in the blocking layer 300 , 5 to 10% of Ge may be included.

Also, like the first semiconductor pattern 210 and the second semiconductor pattern 220 , the cap epitaxial layer 400 may include n-type impurities. For example, the cap epitaxial layer 400 may include The first semiconductor pattern 210 and the second semiconductor pattern 220 may include the same material. For example, the cap epitaxial layer 400 may also include SiP. However, the concentration of phosphorus (P) included in the cap epitaxial layer 400 is determined by the first semiconductor pattern 210 and the second semiconductor pattern. It may be higher than the concentration of P contained in (220).

A seventh active fin F7 and an eighth active fin F8 are formed on the second region II of the substrate 100 . For example, the seventh active fin F7 and the eighth active fin F8 may protrude from the substrate 100 .

The seventh active fin F7 and the eighth active fin F8 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The field insulating layer 110 may cover an upper surface of the substrate 100 and a portion of side surfaces of the seventh and eighth active fins F7 and F8 .

The fourth semiconductor pattern 240 is formed on the seventh active fin F7 , and the fifth semiconductor pattern 250 is formed on the eighth active fin F8 . Specifically, the fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 may be formed on the seventh active fin F7 and the eighth active fin F8 using a selective epitaxial growth (SEG) process, respectively. can

The fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 may include an n-type impurity (eg, phosphorus (P)). The fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 may include: ) may include, for example, SiP.

In the second region II of the substrate 100 , a blocking film 300 ′ is formed between the fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 , and the fourth semiconductor pattern 240 and the fifth semiconductor pattern 240 . It may be disposed under the pattern 250 .

The blocking layer 300 ′ may include, for example, SiGe.

17 to 19 are circuit diagrams and layout diagrams for explaining a semiconductor device according to a tenth embodiment of the present invention.

17 and 18 are circuit diagrams and layout diagrams for explaining a semiconductor device according to a tenth embodiment of the present invention. 19 illustrates only a plurality of fins and a plurality of gate structures in the layout diagram of FIG. 18 . Although the above-described semiconductor device according to some embodiments of the present invention is applicable to all devices including general logic devices using pin-type transistors, FIGS. 17 to 19 show SRAMs by way of example.

First, referring to FIG. 17 , a semiconductor device according to a tenth embodiment of the present invention includes a pair of inverters INV1 and INV2 connected in parallel between a power node Vcc and a ground node Vss, respectively. may include a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of the inverters INV1 and INV2.

The first pass transistor PS1 and the second pass transistor PS2 may be respectively connected to the bit line BL and the complementary bit line /BL. Gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 includes a second pull-up transistor PU2 and a second pull-down transistor PU2 connected in series. and a transistor PD2.

The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

In addition, the input node of the first inverter INV1 is connected to the output node of the second inverter INV2 so that the first inverter INV1 and the second inverter INV2 constitute one latch circuit. and an input node of the second inverter INV2 may be connected to an output node of the first inverter INV1 .

Here, referring to FIGS. 17 to 19 , the first fin F1 , the second fin F2 , the third fin F3 , and the fourth fin F4 spaced apart from each other in one direction (eg, FIG. 18 in the vertical direction) is formed to extend long. The length of the second fin F2 and the third fin F3 may be shorter than those of the first fin F1 and the fourth fin F4.

In addition, the first gate structure 351 , the second gate structure 352 , the third gate structure 353 , and the fourth gate structure 354 extend long in the other direction (eg, the left-right direction of FIG. 18 ). and is formed in a direction crossing the first fins F1 to the fourth fins F4.

Specifically, the first gate structure 351 may be formed to completely cross the first fin F1 and the second fin F2 and overlap a portion of an end of the third fin F3 . The third gate structure 353 may be formed to completely cross the fourth fin F4 and the third fin F3 and overlap a portion of an end of the second fin F2 . The second gate structure 352 and the fourth gate structure 354 may be formed to cross the first fin F1 and the fourth fin F4, respectively.

18 , the first pull-up transistor PU1 is defined around a region where the first gate structure 351 and the second fin F2 intersect, and the first pull-down transistor PD1 has the first gate The structure 351 is defined around a region where the first fin F1 intersects, and the first pass transistor PS1 is defined around a region where the second gate structure 352 and the first fin F1 intersect. .

The second pull-up transistor PU2 is defined around a region where the third gate structure 353 and the third fin F3 intersect, and the second pull-down transistor PD2 includes the third gate structure 353 and the fourth fin F3 . A periphery of a region where F4 intersects is defined, and a second pass transistor PS2 is defined around a region where the fourth gate structure 354 and the fourth fin F4 intersect.

Although not clearly illustrated, sources/drains may be formed on both sides of a region where the first to fourth gate structures 351 to 354 and the first to fourth fins F1 to F4 intersect. According to the example, recesses are formed on both sides of a region where the first to fourth gate structures 351 to 354 and the first to fourth fins F1 to F4 intersect, and a source/drain is formed in the recesses. can be A plurality of contacts 361 may be formed.

In addition, the shared contact 362 simultaneously connects the second fin F2 , the third gate structure 353 and the wiring 371 . The shared contact 363 simultaneously connects the third fin F3 , the first gate structure 351 , and the wiring 372 .

Examples of the first pull-up transistor PU1 , the first pull-down transistor PD1 , the first pass transistor PS1 , the second pull-up transistor PU2 , the second pull-down transistor PD2 , and the second pass transistor PS2 include For example, the semiconductor device according to the embodiments of the present invention described above may be employed.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described.

20 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 22 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 23 to 31 are intermediate steps for explaining a method of manufacturing a semiconductor device according to the present invention.

20, 21, 22, and 23 , in the method of manufacturing a semiconductor device according to an embodiment of the present invention, first, first and/or the first and the The second fins 101 and 102 are formed (S100). The first active fin F1 and the second active fin F2 may protrude from the substrate 100 .

The first and second fins 101 and 102 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .

The first fin 101 and the second fin 102 may extend long in the first direction (X). The field insulating layer 110 may cover a top surface of the substrate 100 and a portion of side surfaces of the first and second fins 101 and 102 .

Subsequently, referring to FIGS. 20 , 21 , 22 , and 24 , a dummy gate structure DS extending in the second direction Y is formed on the first and second fins 101 and 102 . (S110). The dummy gate structure DS may include a dummy gate DG and a capping mask pattern DM on the dummy gate. The dummy gate structure DS may further include a dummy gate insulating layer interposed between the dummy gate DG and the first and second fins 10 and 102 .

Next, referring to FIGS. 20, 21, 22, 25 and 26 , a dummy gate spacer 161 and a normal gate spacer 162 are formed on at least one side of the dummy gate electrode DS, and the first A first semiconductor pattern 210 is epi-grown on the fin 101 , and a second semiconductor pattern 220 is epi-grown on the second fin 102 ( S120 ). In this case, the first semiconductor pattern 210 and the second semiconductor pattern 220 are grown only to a state in which they do not contact each other. According to some embodiments, after the normal gate spacer 162 is formed, the first and second semiconductor patterns 210 and 220 on both sides of the dummy gate structure DS are respectively recessed and the first semiconducting pattern 210 is formed. and the second semiconductor patterns 220 may be epi-grown (S120). According to other embodiments, the dummy gate spacer 161 may not be formed.

Next, referring to FIGS. 20 , 21 , 22 , and 27 , a first blocking layer 310 is formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 ( S130 ). In this case, the first blocking layer 310 may be formed to cover the entire outer surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 .

The first blocking layer 310 is formed by merging the first semiconductor pattern 210 and the second semiconductor pattern 220 , and lower surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 . It is formed thereon to protect the first semiconductor pattern 210 and the second semiconductor pattern 220 .

The first blocking layer 310 is formed on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 in a state in which the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged. It can be formed by epi-growth based on the.

In addition, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (eg, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. According to some embodiments, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include SiC or SiCP. The first semiconductor pattern 210 and the second semiconductor pattern 220 may be provided as source/drain regions. The first blocking layer 310 may include a semiconductor material that is relatively resistant to an etchant (eg, aqueous ammonia), and may include, for example, SiGe. Here, when SiGe is included in the first blocking layer 310, 5 to 10% of Ge may be included.

21 and 28 , in a method of manufacturing a semiconductor device according to another embodiment of the present invention, a portion of the first blocking film 310 is removed to form a second blocking film 300 ( S160) is further included. The second blocking layer 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 and below the lower surface of the first semiconductor pattern 210 and the lower surface of the second semiconductor pattern 220 . The second blocking film 300 on the lower surface of the first semiconductor pattern 210 and the second blocking film on the lower surface of the first semiconductor pattern 220 ( 300) can be separated from each other,

In this case, removing a portion of the first blocking layer 310 may use HCl and/or GeH ₄ .

The reason for forming the second blocking film 300 by removing a portion of the first blocking film 310 is to strengthen the tensile stress characteristics of the first semiconductor pattern 210 and the second semiconductor pattern 220 . it is for That is, the first semiconductor pattern 210 and the second semiconductor pattern 220 include SiP (or SiC, SiCP) to provide tensile stress to the channel region, and the first blocking film 310 is formed of SiGe. This is because the tensile stress characteristics of the first semiconductor pattern 210 and the second semiconductor pattern 220 may be weakened.

22 and 29 , in the method of manufacturing a semiconductor device according to another embodiment of the present invention, the cap epitaxial layer 400 is formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 . It further includes forming (S150).

When a portion of the first blocking layer 310 on the surface exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, the first semiconductor pattern 210 and the second semiconductor pattern 220 are removed. The surface exposed to the outside of the pattern 220 may be damaged, and the cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance tensile stress characteristics. can Accordingly, the cap epitaxial layer 400 may include the same material as the first semiconductor pattern 210 and the second semiconductor pattern 220 . The cap epitaxial layer 400 may include n-type impurities. For example, the cap epitaxial layer 400 may be phosphorous (P). The concentration of phosphorus (P) included in the cap epitaxial layer 400 may be higher than the concentration of phosphorus (P) included in the first semiconductor pattern 210 and the second semiconductor pattern 220 .

Subsequently, referring to FIGS. 20 , 21 , 22 , and 30 , the dummy gate structure DS may be removed ( S160 ). The opening DO may be formed by removing the dummy gate structure DS. According to some embodiments, forming the opening DO covers the first semiconductor pattern 210 and the second semiconductor pattern 220 having the epitaxial layer 400 and exposes the dummy gate structure DS. This may include forming an interlayer insulating layer and removing the dummy gate structure DS to form the opening DO.

Referring to FIGS. 20 , 21 , 22 , and 30 , a gate structure TR is formed. The gate structure TR may be formed in the opening DO. The gate structure TR may be a normal gate structure. The gate structure TR may include an interface layer 120 , a gate insulating layer 130 , a work function control layer 140 , and a gate metal 150 sequentially formed in the opening DO. The gate structure TR may further include a dummy gate spacer 161 and a normal gate spacer NS. The gate structure TR is formed on the first and second fins 101 and 102 and may cross the first and second fins 101 and 102 . The gate structure TR may extend in the second direction Y. According to some embodiments, the interface layer 120 may not be formed.

Hereinafter, an electronic system including a semiconductor device according to some embodiments of the present invention will be described. 32 is a schematic block diagram illustrating an electronic system including a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 32 , the electronic system includes a control device 510 (CONTROLLER), an interface 520 (INTERFACE), an input/output device 530 (I/O), a storage device 540 MEMORY, and a power supply device 550 POWER SUPPLY. ), and a bus 560 (BUS).

The control device 510 , the interface 520 , the input/output device 530 , the memory device 540 , and the power supply device 550 may be coupled to each other through the bus 560 . The bus 560 corresponds to a path through which data is moved.

The control device 510 may process data by including at least one of a microprocessor, a microcontroller, and logic elements capable of performing a function similar thereto.

The interface 520 may perform a function of transmitting data to or receiving data from a communication network. The interface 520 may be in a wired or wireless form. For example, the interface 520 may include an antenna or a wired/wireless transceiver.

The input/output device 530 may input/output data including a keypad and a display device.

The storage device 540 may store data and/or instructions. The semiconductor device according to some embodiments of the present invention may be provided as some components of the memory device 540 .

The power supply 550 may convert externally input power and provide it to each of the components 510 to 540 .

33 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 33 , the electronic system includes a central processing unit 610 (CPU), an interface 620; INTERFACE, a peripheral device 630; PERIPHERAL DEVICE, a main memory device 640; MAIN MEMORY, and an auxiliary storage device 650; SECONDARY MEMORY) and a bus 660 (BUS).

The central processing unit 610 , the interface 620 , the peripheral unit 630 , the main memory unit 640 , and the auxiliary memory unit 650 may be coupled to each other through the bus 660 . The bus 660 corresponds to a path through which data is moved.

The central processing unit 610 may include a control unit, an arithmetic unit, and the like to execute a program and process data.

The interface 620 may perform a function of transmitting data to or receiving data from a communication network. The interface 520 may be in a wired or wireless form. For example, the interface 520 may include an antenna or a wired/wireless transceiver.

The peripheral device 630 may input/output data including a mouse, a keyboard, a display device, and a printer device.

The main memory device 640 may transmit/receive data to/from the central processing unit 610 and may store data and/or instructions required for program execution. The semiconductor device according to some embodiments of the present invention may be provided as some components of the main memory device 640 .

The auxiliary storage device 650 may include a non-volatile storage device such as a magnetic tape, a magnetic disk, a floppy disk, a hard disk, or an optical disk to store data and/or instructions. The auxiliary storage device 650 may store data even when the power of the electronic system is cut off.

In addition, the semiconductor device according to some embodiments of the present invention includes a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, and a web tablet. ), wireless phone, mobile phone, smart phone, e-book, PMP (portable multimedia player), portable game machine, navigation device, black box (black box), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital A digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer Provided as one of various components of an electronic device, such as one of various electronic devices constituting a network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system can be

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 110: field insulating film
F1: first active pin F2: second active pin
TR1: first gate structure TR2: second gate structure
210: first semiconductor pattern 220: second semiconductor pattern
300: blocking film

Claims (20)

first and second active fins extending in a first direction on the substrate and spaced apart from each other in a second direction crossing the first direction;
a gate structure formed on the first and second active fins to extend in the second direction;
a first semiconductor pattern formed on the first active fin and disposed on at least one side of the gate structure;
a second semiconductor pattern formed on the second active fin and disposed on at least one side of the gate structure;
The first semiconductor pattern,
a first pattern comprising a first semiconductor material;
a second pattern disposed under the first pattern between the first and second active fins and including a second semiconductor material different from the first semiconductor material;
The second semiconductor pattern,
a third pattern comprising the first semiconductor material;
and a fourth pattern disposed under the third pattern between the first and second active fins, the fourth pattern including the second semiconductor material, and in contact with the second pattern. The method of claim 1,
The first pattern and the third pattern are in contact with each other. The method of claim 1,
The first pattern includes a first sub-pattern and a second sub-pattern on the first sub-pattern,
The third pattern includes a third sub-pattern and a fourth sub-pattern on the third sub-pattern. 4. The method of claim 3,
The first sub-pattern and the second sub-pattern have different concentrations of impurities included in the first semiconductor material. 4. The method of claim 3,
The third sub-pattern and the fourth sub-pattern have different concentrations of impurities included in the first semiconductor material. The method of claim 1,
The second pattern is formed to cover an entire lower surface of the first pattern between the first and second active fins. The method of claim 1,
The fourth pattern is formed to cover an entire lower surface of the third pattern between the first and second active fins. The method of claim 1,
The second pattern is formed to cover the entire outer surface of the first pattern. The method of claim 1,
The fourth pattern is formed to cover the entire outer surface of the third pattern. The method of claim 1,
The first semiconductor material includes at least one of SiP, SiC, and SiCP. The method of claim 1,
The second semiconductor material comprises SiGe. The method of claim 1,
wherein the first semiconductor material has a lattice constant that is less than that of the second semiconductor material. first and second active fins extending in a first direction on a substrate and formed to be spaced apart from each other in a second direction crossing the first direction;
a gate structure formed on the first and second active fins to extend in the second direction;
a first semiconductor pattern formed on the first active fin;
a second semiconductor pattern formed on the second active fin;
a field insulating layer formed between the first and second active fins;
formed on the field insulating layer between the first and second active fins to be spaced apart from the field insulating layer to contact the first and second semiconductor patterns along lower profiles of the first and second semiconductor patterns; a first pattern comprising 1 semiconductor material;
a second pattern formed along upper profiles of the first and second semiconductor patterns on the first pattern and including a second semiconductor material different from the first semiconductor material; and
and a void surrounded by the first pattern and the field insulating layer. 14. The method of claim 13,
The first and second semiconductor patterns may include the second semiconductor material. 15. The method of claim 14,
A semiconductor device in which a concentration of an impurity included in the second semiconductor material included in the second pattern is higher than a concentration of an impurity included in the second semiconductor material included in the first and second semiconductor patterns. a substrate having a first region and a second region defined thereon;
first and second active fins extending in a first direction in the first region of the substrate and spaced apart from each other in a second direction crossing the first direction;
a first gate structure formed on the first and second active fins to extend in the second direction;
a first semiconductor pattern formed on the first and second active fins, disposed on at least one side of the first gate structure, and including a first semiconductor material;
a second semiconductor pattern formed between the first and second active fins along a lower profile of the first semiconductor pattern and including a second semiconductor material different from the first semiconductor material;
third and fourth active fins extending in the first direction and spaced apart from each other in the second direction on the second region of the substrate;
a second gate structure formed on the third and fourth active fins to extend in the second direction; and
and a third semiconductor pattern formed on the third and fourth active fins, disposed on at least one side of the second gate structure, and including the second semiconductor material. 17. The method of claim 16,
The first semiconductor material includes at least one of SiP, SiC, and SiCP. 18. The method of claim 17,
The second semiconductor material comprises SiGe. forming first and second fins extending in a first direction on the substrate;
forming a dummy gate structure extending in a second direction crossing the first direction on the first and second fins;
Epitaxially growing first and second semiconductor patterns on the first and second fins disposed on at least one side of the dummy gate structure, wherein the first and second semiconductor patterns do not contact each other;
A blocking epitaxial layer is selectively formed along lower profiles of the first and second semiconductor patterns between the first and second fins, wherein the blocking epitaxial layer is formed between the first and second semiconductor patterns. and other substances,
removing the dummy gate structure;
The blocking epitaxial layer connects between the first and second semiconductor patterns that are not in contact with each other. 20. The method of claim 19,
The method of manufacturing a semiconductor device further comprising removing a portion of the blocking epitaxial layer formed on externally exposed surfaces of the first and second semiconductor patterns.

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