KR20160031399A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device comprises: first and second active pins which extend in a first direction on a substrate and are formed separately in a second direction intersecting with the first direction; a gate structure which is formed to extend in the second direction on the first and second active pins; a first semiconductor pattern which is formed on the first active pin and is disposed on at least one side of the gate structure; and a second semiconductor pattern which is formed on the second active pin and is disposed on at least one side of the gate structure. The first semiconductor pattern includes a first pattern which includes a first semiconductor material, and a second pattern which is disposed under the first pattern between the first and second active pins and includes a second semiconductor material different from the first semiconductor material. The second semiconductor pattern includes a third pattern which includes the first semiconductor material, and a fourth pattern which is disposed under the third pattern between the first and second active pins, includes the semiconductor material, and comes in contact with the second pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

The present invention relates to a semiconductor device and a manufacturing method thereof.

BACKGROUND ART [0002] Recent semiconductor devices are being developed in a direction capable of high-speed operation at a low voltage, and the manufacturing process of semiconductor devices is being developed in a direction of improving the degree of integration.

Interest in fin field effect transistors (FinFETs), where channels are formed in a three-dimensional spatial structure to better withstand short channel effects and provide higher drive currents at lower voltages than traditional field effect transistors Is increasing.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming an elevated source / drain in a process for manufacturing a pinned device having a merged active fin, And an etchant is provided to prevent a part of the source / drain from being etched.

Another object of the present invention is to provide a method of forming an elevated source / drain in a process for manufacturing a pinned device having a merged active fin, And a method of manufacturing a semiconductor device capable of preventing an etching of a part of a source / drain by providing an etchant through the via hole.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; first and second active pins extending in a first direction on the substrate and spaced apart from each other in a second direction crossing the first direction; A gate structure formed on the first and second active pins, the gate structure being formed in the second direction; a first semiconductor pattern formed on the first active pin and disposed on at least one side of the gate structure; And a second semiconductor pattern formed on the active fin and disposed on at least one side of the gate structure, wherein the first semiconductor pattern includes a first pattern including a first semiconductor material, And a second pattern disposed below the first pattern between the fins and including a second semiconductor material different from the first semiconductor material, wherein the second semiconductor pattern comprises a first semiconductor material, And a fourth pattern disposed below the third pattern between the first and second active pins and including the second semiconductor material and in contact with the second pattern.

In some embodiments of the present invention, the first pattern and the third pattern may be in contact with each other.

In some embodiments of the present invention, the first pattern includes a first subpattern and a second subpattern on the first subpattern, the third pattern includes a third subpattern and a third subpattern, And a fourth sub-pattern.

In some embodiments of the present invention, the concentration of impurities contained in the first semiconductor material may be different between the first subpattern and the second subpattern.

In some embodiments of the present invention, the third subpattern and the fourth subpattern may have different concentrations of impurities contained in the first semiconductor material.

In some embodiments of the present invention, the second pattern may be formed to cover the entire lower surface of the first pattern between the first and second active pins.

In some embodiments of the present invention, the fourth pattern may be formed to cover the entire lower surface of the third pattern between the first and second active pins.

In some embodiments of the present invention, the second pattern may be formed to cover the entire outer surface of the first pattern.

In some embodiments of the present invention, the fourth pattern may be formed to cover the entire outer surface of the third pattern.

In some embodiments of the present invention, the first semiconductor material may comprise at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the second semiconductor material may comprise SiGe.

In some embodiments of the present invention, the second semiconductor material may comprise 5 to 10% Ge.

In some embodiments of the present invention, the first semiconductor material may have a smaller lattice constant than the second semiconductor material.

According to another aspect of the present invention, there is provided a semiconductor device including first and second active pins extending in a first direction and spaced apart from each other in a second direction crossing the first direction, , A gate structure formed on the first and second active pins in the second direction, a first semiconductor pattern formed on the first active pin, a second semiconductor pattern formed on the second active pin, A field insulating film formed between the first and second active pins, a field insulating film formed between the first and second active pins, the field insulating film being formed to be in contact with the first and second semiconductor patterns, A first pattern comprising a semiconductor material and a second pattern formed on the first pattern and comprising a second semiconductor material different from the first first semiconductor material.

In some embodiments of the present invention, the first and second semiconductor patterns may comprise the second semiconductor material.

In some embodiments of the present invention, the impurity concentration of the first semiconductor material included in the second pattern may be higher than the impurity concentration of the first semiconductor material included in the first and second semiconductor patterns .

In some embodiments of the present invention, the first semiconductor material may comprise an n-type impurity.

In some embodiments of the present invention, the first semiconductor material may comprise at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the first pattern may comprise SiGe.

In some embodiments of the present invention, the first pattern may comprise 5 to 10% Ge.

In some embodiments of the present invention, the lattice constant of the second semiconductor material may be lower than the lattice constant of the first semiconductor material.

According to another aspect of the present invention, there is provided a semiconductor device including a substrate having a first region and a second region defined therein, a first region extending in a first direction in the first region, First and second active pins spaced apart in a second direction intersecting the first active pin, a first gate structure formed in the second direction on the first and second active pins, A first semiconductor pattern formed on the first semiconductor structure and formed on at least one side of the first gate structure and including a first semiconductor material; a second semiconductor pattern formed under the first semiconductor pattern between the first and second active pins, A second semiconductor pattern comprising a second semiconductor material different from the first semiconductor material, third and fourth active pins extending in the first direction in the second region of the substrate and spaced apart in the second direction, Third and fourth A second gate structure formed on the active pin and extending in the second direction and a second gate structure formed on the third and fourth active pins and disposed on at least one side of the second gate structure, And a second semiconductor pattern.

In some embodiments of the present invention, the first semiconductor material may comprise an n-type impurity.

In some embodiments of the present invention, the second semiconductor material may comprise germanium.

In some embodiments of the present invention, the first semiconductor material may comprise at least one of SiP, SiC, and SiCP.

In some embodiments of the present invention, the second semiconductor material may comprise SiGe.

In some embodiments of the present invention, the second semiconductor pattern may include 5 to 10% Ge.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming first and second fins extending in a first direction on a substrate, forming first and second fins on the first and second fins, And forming a dummy gate electrode extending in a second direction intersecting with the first direction, and epitaxially forming first and second semiconductor patterns on the first and second pins disposed on at least one side of the dummy gate electrode, Forming a blocking epitaxial film below the first and second semiconductor patterns between the first and second semiconductor patterns without contacting the first and second semiconductor patterns, The film includes a material different from the first and second semiconductor patterns and includes removing the dummy gate electrode.

In some embodiments of the present invention, the blocking epitaxial film may be formed by merge the first and second semiconductor patterns, and may be formed on the lower surface of the first and second semiconductor patterns, 2 Semiconductor pattern can be protected. The semiconductor material included in the blocking layer may have a smaller lattice constant than the semiconductor material included in the first and second semiconductor patterns.

In some embodiments of the present invention, the method may further include removing a portion of the blocking film formed on the exposed surface of the first and second semiconductor patterns.

In some embodiments of the present invention, removing the blocking film may utilize HCl or GeH4.

In some embodiments of the present invention, the method further comprises: after removing the blocking film, growing an epitaxial layer on the first and second semiconductor patterns exposed to the outside, And may include the same material as the material included in the second semiconductor pattern.

The details of other embodiments are included in the detailed description and drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional view taken along line AA in Fig.
3 is a cross-sectional view taken along line BB of Fig.
4 and 5 are sectional views of a semiconductor device according to a second embodiment of the present invention.
6 and 7 are sectional views of a semiconductor device according to a third embodiment of the present invention.
8 and 9 are cross-sectional views of a semiconductor device according to a fourth embodiment of the present invention.
10 and 11 are sectional views of a semiconductor device according to a fifth embodiment of the present invention.
12 and 13 are sectional views of a semiconductor device according to a sixth embodiment of the present invention.
14 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention.
15 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention.
16 is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention.
17 to 19 are a circuit diagram and a layout diagram for explaining a semiconductor device according to a tenth embodiment of the present invention.
20 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
22 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
FIGS. 23 to 31 are intermediate steps for explaining a method of manufacturing a semiconductor device according to the present invention.
32 is a schematic block diagram for describing an electronic system including a semiconductor device according to some embodiments of the present invention.
33 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

It is to be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to another element, One case. On the other hand, when an element is referred to as being "directly coupled to" or "directly coupled to " another element, it means that it does not intervene in another element. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that an element is referred to as being "on" or " on "of another element includes both elements immediately above and beyond other elements. On the other hand, when an element is referred to as being "directly on" or "directly above" another element, it means that it does not intervene another element in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" Can be used to easily describe the correlation of components with other components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element . Thus, the exemplary term "below" can include both downward and upward directions. The components can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the technical scope of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. 2 is a sectional view taken along line A-A in Fig. 3 is a cross-sectional view taken along line B-B in Fig.

1 to 3, a semiconductor device 1 according to a first embodiment of the present invention includes a substrate 100, a field insulating film 110, a first active pin F1, a second active pin F2 A first gate structure TR1, a second gate structure TR2, a first semiconductor pattern 210, a second semiconductor pattern 220, a blocking layer 300, and the like.

The substrate 100 may be a rigid substrate such as a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display or a polyimide, polyester ) May be a flexible plastic substrate such as polycarbonate, polyethersulfone, polymethylmethacrylate, polyethylene naphthalate, and polyethylene terephthalate.

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be separated by a field insulating film 110 such as STI (Shallow Trench Isolation). Here, the first region I may be an NMOS region and the second region II may be a PMOS region. However, the present invention is not limited thereto. The first region I may be a PMOS region and the second region II may be an NMOS region. Lt; / RTI >

Hereinafter, for convenience of explanation, the NMOS region of the substrate 100 will be described.

A field insulating film 110 is formed on the substrate 100 and used for device isolation. The field insulating film 110 may be an HDP oxide film, an SOG oxide film, a CVD oxide film, or the like, but is not limited thereto.

The first active pin F1 and the second active pin F2 are formed on the substrate 100. [ For example, the first active pin F1 and the second active pin F2 may be formed on the substrate 100 so as to protrude therefrom. For example, the first active pin F1 and the second active pin F2 may protrude from the substrate 100 in the third direction Z.

The first active pin F1 and the second active pin F2 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. [

The first active pin F1 and the second active pin F2 can be elongated along the first direction X. [ The field insulating film 110 may cover a portion of the upper surface of the substrate 100 and a side surface of the first and second active pins F1 and F2.

The first active pin F1 and the second active pin F2 may have a long side and a short side. The first active pin F1 and the second active pin F2 may be disposed on the substrate 100 so as to be spaced apart from each other. For example, the first active pin F1 and the second active pin F2 may be spaced apart in the second direction Y. [ 1, the long side direction is shown as a first direction (X) and the short side direction is shown as a second direction (Y), but the present invention is not limited thereto. For example, the first active pin F1 and the second active pin F2 may have a long-side direction in the second direction Y and a short-side direction in the first direction X. [

The first gate structure TR1 may be formed on the first active pin F1 and the second active pin F2 in a direction crossing the first and second active pins F1 and F2. The first gate structure TR1 may be elongated along the second direction Y. [

The first gate structure TR1 includes an interface film 120 sequentially formed on the first active pin F1 and the second active pin F2, a gate insulating film 130, a work function control film 140, A gate spacer 150, a gate spacer 160, and the like. Channels can be formed on both sides and top surfaces of the first active pin F1 and the second active pin F2 covered by the first gate structure TR1.

The interface film 120 may be formed on the field insulating film 110 and the first and second active pins F1 and F2. The interface film 120 can prevent a poor interface between the field insulating film 110 and the gate insulating film 130.

The interface film 120 is a low dielectric material layer having a dielectric constant k of 9 or less such as a silicon oxide film (k is about 4) or a silicon oxynitride film (k is about 4 to 8 depending on oxygen atom and nitrogen atom content) . ≪ / RTI > According to some embodiments, the interface film 120 may be made of a silicate, or a combination of the previously exemplified membranes. According to other embodiments, the interface film 120 may not be formed.

The gate insulating film 130 may be formed on the interface film 120. However, when the interface film 120 is not present, the gate insulating film 130 may be formed on the field insulating film 110 and the first and second active pins F1 and F2.

The gate insulating film 130 may include a material having a high-k. Specifically, the gate insulating film 130 may include, for example, HfSiON, HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ , BaTiO ₃ , and / or SrTiO ₃ .

Meanwhile, the gate insulating layer 130 may be formed to have an appropriate thickness depending on the type of device to be formed. For example, in the case where the gate insulating film 130 is HfO ₂ , the gate insulating film 130 may be formed to a thickness of about 50 Å or less (about 5 Å to 50 Å), but the present invention is not limited thereto. According to some embodiments of the present invention, as shown in FIG. 1, the gate insulating layer 130 may extend upward along the sidewalls of the gate spacer 160, which will be described later.

The work function adjusting film 140 may be formed on the gate insulating film 130. [ The work function adjusting film 140 may be formed in contact with the gate insulating film 130. The work function control film 140 is used for work function control.

The work function regulating film 140 may include, for example, a metal nitride. Specifically, the work function adjusting film 140 may include at least one of Mo, Pd, Ru, Pt, TiN, WN, TaN, Ir, TaC, RuN, TiAl, TaAlC, TiAlN, and MoN. More specifically, the work function regulating film 140 may comprise, for example, a single film made of TiN or a double film made of a TiN bottom film and a TaN top film, but is not limited thereto.

According to some embodiments of the present invention, as shown in FIG. 1, the work function regulating film 140 may also extend upward along the sidewalls of the gate spacer 160, which will be described later.

The gate metal 150 may be formed on the work function adjusting film 140. The gate metal 150 may be formed in contact with the work function adjusting film 140, as shown in the figure. That is, the gate metal 150 may be formed to fill a space created by the work function adjusting film 140. The gate metal 150 may include a material having conductivity, for example, W or Al, but is not limited thereto.

The gate spacer 160 may be formed on at least one side of the side surface of the first gate structure TR1. The gate spacer 160 may include at least one of a nitride film, an oxynitride film, and a low-k material.

Although the gate spacer 160 has a curved shape on one side, the present invention is not limited thereto, and the shape of the gate spacer 160 may be different. For example, the shape of the gate spacer 160 may be formed in an I-shape or an L-shape, unlike the shape shown in the figure.

Although the gate spacer 160 is illustrated as being formed as a single layer in the drawing, the present invention is not limited thereto, and the gate spacer 160 may be formed of a plurality of layers.

On the other hand, the source / drain regions are formed on at least one side of both sides of the first gate structure TR1 and can be formed in the first and second active pins F1 and F2. The source / drain region and the first gate structure TR1 may be insulated by a gate spacer 160.

When the semiconductor device 1 is an NMOS transistor, the source / drain region may comprise the same material as the substrate 100, or a tensile stress material. For example, when the substrate 100 is Si, the source / drain region may be Si or a material with a lower lattice constant than Si (e.g., SiC, SiP, and / or SiCP). The tensile stress material can increase the mobility of carriers in the channel region by applying tensile stress to the first and second active fins F1 and F2, i.e., the channel region under the first gate structure TR1.

On the other hand, when the semiconductor device 1 is a PMOS transistor, the source / drain region may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The compressive stress material can increase the mobility of carriers in the channel region by applying a compressive stress to the first and second active fins F1 and F2, that is, the channel region under the first gate structure TR1.

In some embodiments of the present invention, such source / drain regions may be formed through epitaxial growth, but the present invention is not limited thereto.

The second gate structure TR2 may be formed on the first active pin F1 and the second active pin F2 in a direction crossing the first and second active pins F1 and F2. The second gate structure TR2 may extend longer along the second direction Y. [

The second gate structure TR2 may comprise substantially the same configuration as the first gate structure TR1 described above.

The first semiconductor pattern 210 is formed on the first active pin F1 and disposed on at least one side of the first gate structure TR1. Specifically, the first semiconductor pattern 210 may be formed on the first active pin F1 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a part of the first active pin F1. Also in this case, the first semiconductor pattern 210 can be formed using the SEG process.

In the NMOS region of the pin-shaped device, the first semiconductor pattern 210 may be formed of a material capable of providing tensile stress. That is, the first semiconductor pattern 210 can provide tensile stress to the channel region. The first semiconductor pattern 210 may be formed of a material having a smaller lattice constant than the substrate 100. For example, when the substrate 100 is made of silicon (Si) SiP. ≪ / RTI > SiP may be phosphorus (P) doped silicon. According to some embodiments, the first semiconductor pattern 210 may comprise silicon carbon (SiC), or phosphorus (P) -doped silicon carbon (SiCP). And the second semiconductor pattern 220 is formed on the second active pin F2. Specifically, the second semiconductor pattern 220 may be formed using the SEG process on the second active pin F2.

Alternatively, the second semiconductor pattern 220 may be formed filling the recess formed in at least a part of the second active pin F2. Also in this case, the second semiconductor pattern 220 can be formed using the SEG process.

The second semiconductor pattern 220, like the first semiconductor pattern 210, may be formed of a material capable of providing a tensile stress to the channel region. The second semiconductor pattern 220 may include the same material as the first semiconductor pattern 22. The second semiconductor pattern 220 may be formed together with the first semiconductor pattern 210 while the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed separately It is possible.

In the case where the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed by the SEG process, the first semiconductor pattern 210 and the second semiconductor pattern 220 are formed in the <100> direction Facets are formed to have a diamond-like profile.

If the first semiconductor pattern 210 and the second semiconductor pattern 220 are grown to form a merged fin structure, the first semiconductor pattern 210 and the second semiconductor pattern 220 A void space is generated in the lower part of the substrate. In the subsequent process, when the etchant (for example, ammonia water (NH ₃ )) flows into the void space, the first semiconductor pattern 210 and the lower surface of the second semiconductor pattern 220 may be etched.

That is, in the process of removing the dummy gate electrode, ammonia water may be used as the etchant. If a path is formed between the dummy gate electrode and the void space, an etchant (for example, ammonia water) The first semiconductor pattern 210 exposed in the void space and the lower surface of the second semiconductor pattern 220 may be etched.

The first semiconductor pattern 210 and the second semiconductor pattern 220 may be formed by merging adjacent first and second semiconductor patterns 210 and 220 to form a merged fin structure, The blocking film 300 is formed on the lower part of the void space to protect the first semiconductor pattern 210 and the second semiconductor pattern 220 from the etchant (for example, ammonia water) flowing into the void space. If the first semiconductor pattern 210 and the second semiconductor pattern 220 are etched, the characteristics of the semiconductor device may be affected and a reliability problem may occur.

The blocking layer 300 may be formed of a material different from that of the first semiconductor pattern 210 and the second semiconductor pattern 220. That is, if the first semiconductor pattern 210 and the second semiconductor pattern 220 include, for example, SiP in the NMOS region, the blocking layer 300 may be formed on the etchant (for example, ammonia water) It is necessary to include a material having relatively high resistance. As such a material, for example, SiGe can be used. However, the blocking layer 300 is not limited to the material resistant to the etchant (for example, ammonia water), and may include other materials.

The blocking film 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 and below the first semiconductor pattern 210 and the second semiconductor pattern 220. For example, the blocking layer 300 may be formed to merge the first semiconductor pattern 210 and the second semiconductor pattern 220. The blocking layer 300 may be formed on the lower surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 between the first semiconductor pattern 210 and the second semiconductor pattern 220. The blocking layer 300 may be formed so as to cover the first semiconductor pattern 210 and the second semiconductor pattern 220 entirely between the first semiconductor pattern 210 and the second semiconductor pattern 220 .

According to the present invention, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220, for example, SiP. Blocking film 300 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe.

Here, when Si is contained in the blocking film 300, Ge may be contained in an amount of 5 to 10%. The Ge contained in the blocking film 300 serves to protect the first semiconductor pattern 210 and the lower portion of the second semiconductor pattern 220. When the Ge concentration is excessively high, And stress characteristics of the second semiconductor pattern, the blocking film 300 may contain 5 to 10% of Ge.

Hereinafter, a semiconductor device according to another embodiment of the present invention will be described.

4 and 5 are sectional views of a semiconductor device according to a second embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

4 and 5, the semiconductor device 2 according to the second embodiment of the present invention is a semiconductor device in which the blocking film 310 is formed on the outer surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 As shown in FIG.

Specifically, the blocking film 310 is formed on the surface of the first semiconductor pattern 210 and the surface of the second semiconductor pattern 220 in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, As a base, by epitaxial growth. In this state, if the blocking film 310 is removed except for the blocking film 310 located below the first semiconductor pattern 210 and the second semiconductor pattern 220, A blocking film 300 of the same type as that of the semiconductor device 1 according to the example can be formed.

According to the semiconductor device 2, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 And the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited to this. The blocking film 310 is relatively resistant to an etchant (for example, ammonia water) For example, SiGe. Here, in the case where SiGe is included in the blocking film 310, Ge may be included in an amount of 5 to 10%.

6 and 7 are sectional views of a semiconductor device according to a third embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

6 and 7, in the semiconductor device 3 according to the third embodiment of the present invention, the blocking film 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220, The cap epitaxial layer 400 is disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220. The cap epitaxial layer 400 is formed on the exposed surface of the first semiconductor pattern 210 and the second semiconductor pattern 220, . According to some embodiments, unlike the blocking film 300 connecting the first and second semiconductor patterns 210 and 220 shown in FIG. 7, the blocking film 300 may be formed by patterning the first and second semiconductor patterns 210 and 220, The first and second semiconductor patterns 210 and 220 may be separated or joined together by the epitaxial layer 400,

Specifically, the first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 as a base in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged The blocking film on the exposed surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed to form the blocking film 300 in the semiconductor device 3, Can be formed. A portion of the blocking layer 300 connecting the first and second semiconductor patterns 210 and 220 is further etched to form the first semiconductor pattern 210 and the second semiconductor pattern 220, The first semiconductor pattern 210 and the second semiconductor pattern 220 are formed on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220, The cap epitaxial layer 400 may be formed by epitaxial growth using a surface exposed to the outside of the cap epitaxial layer 400 as a base.

According to the semiconductor device 3, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. Blocking film 300 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe. Here, when Si is contained in the blocking film 300, Ge may be contained in an amount of 5 to 10%.

Like the first semiconductor pattern 210 and the second semiconductor pattern 220, the cap epitaxial layer 400 may include n-type impurities. For example, the cap epitaxial layer 400 may include n- 1 semiconductor pattern 210 and the second semiconductor pattern 220. In this case, For example, the cap epitaxial layer 400 may also include, but is not limited to, SiP. The concentration of phosphorus (P) contained in the cap epitaxial layer 400 may be higher than the concentration of phosphorus (P) contained in the first semiconductor pattern 210 and the second semiconductor pattern 220.

The first semiconductor pattern 210 and the second semiconductor pattern 220 may be exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220, And the cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance the stress characteristics.

8 and 9 are cross-sectional views of a semiconductor device according to a fourth embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

8 and 9, in the semiconductor device 4 according to the fourth embodiment of the present invention, the first blocking film 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 And the second blocking film 301 is disposed on the lower surface exposed to the outside of the first semiconductor pattern 210. The first semiconductor pattern 210 and the second blocking film 301 are disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220, And the third blocking film 302 is disposed on the lower surface exposed to the outside of the second semiconductor pattern 220.

Specifically, the first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 as a base in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged After the blocking film is formed, the blocking film on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, and the first semiconductor pattern 210 and the second semiconductor pattern 220 The first to third blocking films 300, 301 and 302 can be formed by removing only the blocking film on the upper surface of the first to third blocking films 220 and 220.

At this time, the removal of the blocking film on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 may use a dry etching process, for example, using HCl and / or The block-k film can be removed using GeH4.

According to the semiconductor device 4, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The first through third blocking layers 300, 301 and 302 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe . Here, when SiGe is included in the first to third blocking films 300, 301, and 302, Ge may be contained in an amount of 5 to 10%.

10 and 11 are sectional views of a semiconductor device according to a fifth embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

10 and 11, in the semiconductor device 5 according to the fifth embodiment of the present invention, the blocking film 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220, The first semiconductor pattern 210 and the second semiconductor pattern 220 are disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220, respectively.

Specifically, the first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 as a base in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged After the blocking film is formed, the blocking film on the exposed surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 may be removed to form the blocking film 300.

The upper pattern 401 may be formed on the upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 using an ALD or PVD process.

According to the semiconductor device 5, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. Blocking film 300 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe. Here, when Si is contained in the blocking film 300, Ge may be contained in an amount of 5 to 10%.

Like the first semiconductor pattern 210 and the second semiconductor pattern 220, the upper pattern 401 may include n-type impurities. For example, the upper pattern 401 may include an n- 210 and the second semiconductor pattern 220 may be the same. For example, the upper pattern 401 may include SiP, but the concentration of P contained in the upper pattern 401 may be different from the concentration of P contained in the first semiconductor pattern 210 and the second semiconductor pattern 220 &Lt; / RTI &gt;

12 and 13 are sectional views of a semiconductor device according to a sixth embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

12 and 13, in the semiconductor device 6 according to the sixth embodiment of the present invention, the first blocking film 300 is formed between the first semiconductor pattern 210 and the second semiconductor pattern 220 And the second blocking film 301 is disposed on the lower surface exposed to the outside of the first semiconductor pattern 210. The first semiconductor pattern 210 and the second blocking film 301 are disposed under the first semiconductor pattern 210 and the second semiconductor pattern 220, And the third blocking film 302 is disposed on the lower surface exposed to the outside of the second semiconductor pattern 220.

The upper pattern 401 is disposed on the upper surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220.

Specifically, the first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 as a base in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged After the blocking film is formed, the blocking film on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed, and the first semiconductor pattern 210 and the second semiconductor pattern 220 The first to third blocking films 300, 301 and 302 can be formed by removing only the blocking film on the upper surface of the first to third blocking films 220 and 220.

The upper pattern 401 may be formed on the upper surface of the first semiconductor pattern 210 and the upper surface of the second semiconductor pattern 220 using an ALD or PVD process or an epi process.

According to the semiconductor device 6, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. The first through third blocking layers 300, 301 and 302 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe . Here, when SiGe is included in the first to third blocking films 300, 301, and 302, Ge may be contained in an amount of 5 to 10%.

Like the first semiconductor pattern 210 and the second semiconductor pattern 220, the upper pattern 401 may include n-type impurities. For example, the upper pattern 401 may include an n- 210 and the second semiconductor pattern 220 may be the same. For example, the upper pattern 401 may include SiP, but the concentration of P contained in the upper pattern 401 may be different from the concentration of P contained in the first semiconductor pattern 210 and the second semiconductor pattern 220 &Lt; / RTI &gt;

14 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

14, in the semiconductor device 7 according to the seventh embodiment of the present invention, the first gate structure TR1 is formed sequentially on the first active pin F1 and the second active pin F2 And may include an interface film 120, a gate insulating film 130, a work function adjusting film 140, a gate metal 150, a dummy gate spacer 161, a normal gate spacer 162, and the like.

In the semiconductor device 7, the second gate structure TR2 may comprise substantially the same configuration as the first gate structure TR1.

The interface film 120, the gate insulating film 130, the work function adjusting film 140, and the gate metal 150 are substantially the same as those described above. According to some embodiments, the interface film 120 and the dummy gate spacers 161 may not be formed.

The dummy gate spacers 161 and the normal gate spacers 162 are formed on the side surfaces of the dummy gate structure and the first semiconductor pattern 210 is formed on the side surfaces of the dummy gate structure after the dummy gate structure is formed. The first gate structure TR1 and the second gate structure TR2) after forming the second semiconductor pattern 220 and the blocking film 300, removing the dummy gate electrode, The dummy gate spacers 161 may remain in the process of removing the dummy gate structure 162. The normal gate spacers 162 may be formed on the first and second semiconductor patterns 210 and 220, (E.g., the first gate structure TR1 and the second gate structure TR2). The gate structure may be a normal gate structure.

15 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to Fig. 15, a semiconductor device 8 according to an eighth embodiment of the present invention includes a substrate 100 in which a first region I and a second region are defined.

On the first region I of the substrate 100, the first active pin F1 and the second active pin F2 are formed. For example, the first active pin F1 and the second active pin F2 may be formed on the substrate 100 so as to protrude therefrom.

The first active pin F1 and the second active pin F2 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. [

The field insulating film 110 may cover a portion of the upper surface of the substrate 100 and a side surface of the first and second active pins F1 and F2.

The first semiconductor pattern 210 is formed on the first active pin F1. Specifically, the first semiconductor pattern 210 may be formed on the first active pin F1 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a part of the first active pin F1. Also in this case, the first semiconductor pattern 210 can be formed using the SEG process.

And the second semiconductor pattern 220 is formed on the second active pin F2. Specifically, the second semiconductor pattern 220 may be formed using the SEG process on the second active pin F2.

Alternatively, the second semiconductor pattern 220 may be formed filling the recess formed in at least a part of the second active pin F2. Also in this case, the second semiconductor pattern 220 can be formed using the SEG process.

The blocking film 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 and below the first semiconductor pattern 210 and the second semiconductor pattern 220, The first semiconductor pattern 210 and the second semiconductor pattern 220 are disposed on the exposed surface of the first semiconductor pattern 210 and the second semiconductor pattern 220, respectively.

The first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, The blocking film on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed to form the blocking film 300 in the semiconductor device 8 . The first semiconductor pattern 210 and the second semiconductor pattern 220 are exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220, The cap epitaxial layer 400 can be formed by epitaxial growth.

According to the semiconductor device 8, the first region I may be an NMOS region, and the first semiconductor pattern 210 and the second semiconductor pattern 220 may be n-type impurities (for example, phosphorus (P)). . &Lt; / RTI &gt; The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. The present invention is not limited thereto. Blocking film 300 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe. Here, when Si is contained in the blocking film 300, Ge may be contained in an amount of 5 to 10%.

The epitaxial layer 400 may include n-type impurities as well as the first semiconductor pattern 210 and the second semiconductor pattern 220. For example, the cap epitaxial layer 400 may include an n- 1 semiconductor pattern 210 and the second semiconductor pattern 220. In this case, For example, the cap epitaxial layer 400 may include SiP, but the concentration of phosphorus (P) contained in the epitaxial layer 400 may be lower than the concentration of the phosphorus (P) May be higher than the concentration of P contained in the adsorbent (220).

The first semiconductor pattern 210 and the second semiconductor pattern 220 may be exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220, The cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance tensile stress characteristics.

On the second region II of the substrate 100, the third active pin F3 and the fourth active pin F4 are formed. For example, the third active pin F3 and the fourth active pin F4 may be formed on the substrate 100 so as to protrude therefrom.

The third active pin F3 and the fourth active pin F4 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. [

The field insulating film 110 may cover a part of the upper surface of the substrate 100 and a side surface of the third and fourth active pins F3 and F4.

A third semiconductor pattern 230 is formed on the third and fourth active pins F3 and F4. Specifically, the third semiconductor pattern 230 may be formed on the third and fourth active pins F3 and F4 using a selective epitaxial growth (SEG) process.

The third semiconductor pattern 230 may include, for example, the same material as the material contained in the blocking film 300. The second region II may be, for example, a PMOS region, and the third semiconductor pattern 230 may include a p-type impurity (e.g., boron). The third semiconductor pattern 230 may include, for example, SiGe.

16 is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 16, a semiconductor device 9 according to a ninth embodiment of the present invention includes a substrate 100 in which a first region I and a second region are defined.

On the first region I of the substrate 100, the fifth active pin F5 and the sixth active pin F6 are formed. For example, the fifth active pin F5 and the sixth active pin F6 may protrude from the substrate 100.

The fifth active pin F5 and the sixth active pin F6 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. [

The field insulating film 110 may cover a part of the upper surface of the substrate 100 and the side surfaces of the fifth and sixth active pins F5 and F6.

The first semiconductor pattern 210 is formed on the fifth active pin F5. Specifically, the first semiconductor pattern 210 may be formed on the fifth active pin F5 using a selective epitaxial growth (SEG) process.

Alternatively, the first semiconductor pattern 210 may be formed by filling a recess formed in at least a part of the fifth active pin F5. Also in this case, the first semiconductor pattern 210 can be formed using the SEG process.

And the second semiconductor pattern 220 is formed on the sixth active pin F6. Specifically, the second semiconductor pattern 220 may be formed using the SEG process on the sixth active pin F6.

Alternatively, the second semiconductor pattern 220 may be formed filling the recess formed in at least a part of the sixth active pin F6. Also in this case, the second semiconductor pattern 220 can be formed using the SEG process.

The blocking film 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 and below the first semiconductor pattern 210 and the second semiconductor pattern 220, The first semiconductor pattern 210 and the second semiconductor pattern 220 are disposed on the exposed surface of the first semiconductor pattern 210 and the second semiconductor pattern 220, respectively.

The first semiconductor pattern 210 and the second semiconductor pattern 220 are epitaxially grown on the surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged, The blocking film on the exposed surfaces of the first semiconductor pattern 210 and the second semiconductor pattern 220 is removed to form the blocking film 300 in the semiconductor device 8 . The first semiconductor pattern 210 and the second semiconductor pattern 220 are exposed to the outside of the first semiconductor pattern 210 and the second semiconductor pattern 220, The cap epitaxial layer 400 can be formed by epitaxial growth.

According to the semiconductor device 9, the first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). For example, the first semiconductor pattern 210 and the second semiconductor pattern 220 may comprise, for example, SiP. The blocking layer 300 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe . Here, when Si is contained in the blocking film 300, Ge may be contained in an amount of 5 to 10%.

Like the first semiconductor pattern 210 and the second semiconductor pattern 220, the cap epitaxial layer 400 may include n-type impurities. For example, the cap epitaxial layer 400 may include n- 1 semiconductor pattern 210 and the second semiconductor pattern 220. In this case, For example, the cap epitaxial layer 400 may include SiP, but the concentration of phosphorus (P) contained in the cap epitaxial layer 400 may be lower than the concentration of the phosphorus (P) May be higher than the concentration of P contained in the adsorbent (220).

On the second region II of the substrate 100, the seventh active pin F7 and the eighth active pin F8 are formed. For example, the seventh active pin F7 and the eighth active pin F8 may be formed on the substrate 100 so as to protrude therefrom.

The seventh active pin F7 and the eighth active pin F8 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. [

The field insulating film 110 may cover a part of the upper surface of the substrate 100 and the side surfaces of the seventh and eighth active pins F7 and F8.

The fourth semiconductor pattern 240 is formed on the seventh active pin F7 and the fifth semiconductor pattern 250 is formed on the eighth active pin F8. Specifically, the fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 are formed using a SEG (Selective Epitaxial Growth) process on the seventh active pin F7 and the eighth active pin F8, respectively .

The fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 may include an n-type impurity (for example, phosphorus (P)). The fourth semiconductor pattern 240 and the fifth semiconductor pattern 250 For example, SiP.

In the second region II of the substrate 100, the blocking film 300 'is formed between the fourth semiconductor pattern 240 and the fifth semiconductor pattern 250, And may be disposed under the pattern 250.

The blocking film 300 'may comprise, for example, SiGe.

17 to 19 are a circuit diagram and a layout diagram for explaining a semiconductor device according to a tenth embodiment of the present invention.

17 and 18 are a circuit diagram and a layout diagram for explaining a semiconductor device according to a tenth embodiment of the present invention. Fig. 19 shows only a plurality of fins and a plurality of gate structures in the layout diagram of Fig. Although the semiconductor device according to some embodiments of the present invention described above is applicable to all devices composed of general logic devices using a pin-type transistor, FIGS. 17 to 19 illustrate an SRAM as an example.

17, a semiconductor device according to a tenth embodiment of the present invention includes a pair of inverters INV1 and INV2 connected in parallel between a power supply node Vcc and a ground node Vss, And a first pass transistor PS1 and a second pass transistor PS2 connected to the output nodes of the inverters INV1 and INV2 of FIG.

The first pass transistor PS1 and the second pass transistor PS2 may be connected to the bit line BL and the complementary bit line / BL, respectively. The gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series and a second inverter INV2 includes a second pull-up transistor PU2 and a second pull- And a transistor PD2.

The first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

In order for the first inverter INV1 and the second inverter INV2 to constitute one latch circuit, the input node of the first inverter INV1 is connected to the output node of the second inverter INV2 And the input node of the second inverter INV2 may be connected to the output node of the first inverter INV1.

17 to 19, the first pin F1, the second pin F2, the third pin F3 and the fourth pin F4 which are spaced apart from each other are moved in one direction (for example, 18 in the vertical direction). The second pin F2 and the third pin F3 may be shorter in length than the first pin F1 and the fourth pin F4.

The first gate structure 351, the second gate structure 352, the third gate structure 353 and the fourth gate structure 354 are elongated in the other direction (for example, the left-right direction in FIG. 18) And is formed in a direction intersecting the first to fourth pins F1 to F4.

Specifically, the first gate structure 351 may be formed to completely intersect the first fin F1 and the second fin F2, and overlap with a part of the end of the third fin F3. The third gate structure 353 may be formed to completely intersect the fourth pin F4 and the third pin F3 and overlap with a part of the end of the second pin F2. The second gate structure 352 and the fourth gate structure 354 may be formed to intersect the first pin F 1 and the fourth pin F 4, respectively.

18, the first pull-up transistor PU1 is defined around the region where the first gate structure 351 and the second fin F2 intersect, the first pull-down transistor PD1 is defined around the region where the first gate structure 351 and the second fin F2 intersect, The first pass transistor PS1 is defined around the region where the structure 351 and the first fin F1 cross each other and the first pass transistor PS1 is defined around the region where the second gate structure 352 and the first fin F1 cross each other .

The second pull-up transistor PU2 is defined around the region where the third gate structure 353 and the third pin F3 intersect and the second pull-down transistor PD2 is defined around the third gate structure 353 and the fourth pin And the second pass transistor PS2 is defined around the region where the fourth gate structure 354 and the fourth pin F4 intersect.

The source / drain may be formed on both sides of the region where the first to fourth gate structures 351 to 354 intersect with the first to fourth fins F1 to F4, although not clearly shown. In some embodiments Recesses are formed on both sides of a region where the first to fourth gate structures 351 to 354 intersect with the first to fourth fins F1 to F4 and source and drain are formed in the recess . A plurality of contacts 361 can be formed.

In addition, the shared contact 362 connects the second fin F2, the third gate structure 353, and the wiring 371 at the same time. The shared contact 363 connects the third pin F3, the first gate structure 351 and the wiring 372 at the same time.

As the first pull-up transistor PU1, the first pull-down transistor PD1, the first pass transistor PS1, the second pull-up transistor PU2, the second pull-down transistor PD2 and the second pass transistor PS2, For example, a semiconductor device according to the above-described embodiments of the present invention can be employed.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described.

20 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 22 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. 23 to 31 are intermediate steps for explaining a method of manufacturing a semiconductor device according to the present invention.

20 and 21, 22, and 23, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes first and second steps of forming, on a substrate 100, The second pins 101 and 102 are formed (S100). The first active pin F1 and the second active pin F2 may protrude from the substrate 100.

The first and second fins 101 and 102 may be part of the substrate 100 and may include an epitaxial layer grown from the substrate 100.

The first pin 101 and the second pin 102 may be elongated along the first direction X. [ The field insulating film 110 may cover the upper surface of the substrate 100 and a part of the side surfaces of the first and second pins 101 and 102.

Next, referring to FIGS. 20, 21, 22, and 24, a dummy gate structure DS extending in the second direction Y is formed on the first and second fins 101 and 102 (S110). The dummy gate structure DS may include a dummy gate DG and a capping mask pattern DM on the dummy gate. The dummy gate structure DS may further include a dummy gate insulating film interposed between the dummy gate DG and the first and second fins 10 and 102,

20, 21, 22, 25, and 26, a dummy gate spacer 161 and a normal gate spacer 162 are formed on at least one side of the dummy gate electrode DS, The first semiconductor pattern 210 is epitaxially grown on the fin 101 and the second semiconductor pattern 220 is epitaxially grown on the second fin 102 at step S120. At this time, the first semiconductor pattern 210 and the second semiconductor pattern 220 are grown only to a non-contact state. According to some embodiments, after forming the normal gate spacers 162, the first and second semiconductor patterns 210 and 220 on both sides of the dummy gate structure DS are respectively recessed and the first semi- And the second semiconductor patterns 220 (S120). According to other embodiments, dummy gate spacers 161 may not be formed,

Next, referring to FIGS. 20, 21, 22, and 27, a first blocking layer 310 is formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 (S130). At this time, the first blocking layer 310 may be formed to cover the entire outer surface of the first semiconductor pattern 210 and the second semiconductor pattern 220.

The first blocking layer 310 may be formed by merge the first semiconductor pattern 210 and the second semiconductor pattern 220 and may be formed on the lower surface of the first semiconductor pattern 210 and the second semiconductor pattern 220. [ To protect the first semiconductor pattern 210 and the second semiconductor pattern 220.

The first blocking layer 310 is formed on the surface of the first semiconductor pattern 210 and the second semiconductor pattern 220 in a state where the first semiconductor pattern 210 and the second semiconductor pattern 220 are not completely merged. As a base, by epitaxial growth.

The first semiconductor pattern 210 and the second semiconductor pattern 220 may include an n-type impurity (for example, phosphorus (P)). The first semiconductor pattern 210 and the second semiconductor pattern 220 may include, for example, SiP. According to some embodiments, the first semiconductor pattern 210 and the second semiconductor pattern 220 may comprise SiC, or SiCP. The first semiconductor pattern 210 and the second semiconductor pattern 220 may be provided as source / drain regions. The first blocking layer 310 may comprise a semiconductor material that is relatively resistant to an etchant (e.g., ammonia water) and may include, for example, SiGe. Here, when SiGe is included in the first blocking film 310, Ge may be contained in an amount of 5 to 10%.

21 and 28, a method of manufacturing a semiconductor device according to another embodiment of the present invention includes forming a second blocking layer 300 by removing a portion of a first blocking layer 310 S160). The second blocking film 300 is disposed between the first semiconductor pattern 210 and the second semiconductor pattern 220 under the lower surface of the first semiconductor pattern 210 and the lower surface of the second semiconductor pattern 220 The second blocking film 300 on the bottom surface of the first semiconductor pattern 210 and the second blocking film 300 on the bottom surface of the first semiconductor pattern 220 are removed by the process of removing the first blocking film 310 300 can be separated from each other,

At this time, to remove a part of the first blocking film 310, HCl and / or GeH ₄ may be used.

The reason why the first blocking film 310 is partially removed to form the second blocking film 300 is to strengthen the tensile stress characteristics of the first semiconductor pattern 210 and the second semiconductor pattern 220 It is for this reason. That is, the first semiconductor pattern 210 and the second semiconductor pattern 220 include SiP (or SiC, SiCP) to provide tensile stress to the channel region. The first blocking layer 310 may be made of SiGe The tensile stress characteristics of the first semiconductor pattern 210 and the second semiconductor pattern 220 can be weakened.

22 and 29, a method of manufacturing a semiconductor device according to another embodiment of the present invention includes forming a cap epitaxial layer 400 on a first semiconductor pattern 210 and a second semiconductor pattern 220 (S150).

When the first semiconductor pattern 210 and the second semiconductor pattern 220 are partially removed from the exposed surface of the first blocking film 310, The exposed surface of the pattern 220 may be damaged and a cap epitaxial layer 400 may be formed on the first semiconductor pattern 210 and the second semiconductor pattern 220 to enhance tensile stress characteristics . Accordingly, the cap epitaxial layer 400 may include the same material as the first semiconductor pattern 210 and the second semiconductor pattern 220. [ The cap epitaxial layer 400 may include an n-type impurity. For example, the cap epitaxial layer 400 may be phosphorous (P). The concentration of phosphorus (P) contained in the cap epitaxial layer 400 may be higher than the concentration of phosphorus (P) contained in the first semiconductor pattern 210 and the second semiconductor pattern 220.

Next, referring to FIGS. 20, 21, 22, and 30, the dummy gate structure DS may be removed (S160). The opening (DO) can be formed by removing the dummy gate structure DS. According to some embodiments, forming the opening DO may include exposing the dummy gate structure DS, covering the first semiconductor pattern 210 having the epitaxial layer 400 and the second semiconductor pattern 220, Forming an interlayer insulating film, and removing the dummy gate structure DS to form an opening (DO).

20, 21, 22, and 30, a gate structure TR is formed. The gate structure TR may be formed in the opening DO. The gate structure TR may be a normal gate structure. The gate structure TR may include an interface film 120, a gate insulating film 130, a work function control film 140, and a gate metal 150 sequentially formed in the opening DO. The gate structure TR may further include a dummy gate spacer 161 and a normal gate spacer NS. The gate structure TR may be formed on the first and second fins 101 and 102 and may traverse the first and second fins 101 and 102. The gate structure TR may extend in the second direction Y. [ According to some embodiments, the interfacial film 120 may not be formed.

Hereinafter, an electronic system including a semiconductor device according to some embodiments of the present invention will be described. 32 is a schematic block diagram for describing an electronic system including a semiconductor device according to some embodiments of the present invention.

32, an electronic system includes a controller 510, an interface 520, an input / output device 530, a memory 540, a power supply 550, , And a bus 560 (BUS).

The control device 510, the interface 520, the input / output device 530, the storage device 540, and the power supply device 550 may be coupled to each other via the bus 560. The bus 560 corresponds to a path through which data is moved.

The control device 510 may process data including at least one of a microprocessor, a microcontroller, and logic elements capable of performing similar functions.

The interface 520 may perform functions to transmit data to or receive data from the communication network. The interface 520 may be in wired or wireless form. For example, the interface 520 may include an antenna or a wired or wireless transceiver.

The input / output device 530 can input and output data including a keypad and a display device.

The storage device 540 may store data and / or instructions and the like. The semiconductor device according to some embodiments of the present invention may be provided as a part of the storage device 540. [

The power supply unit 550 may convert the power input from the outside and provide the power to the respective components 510 to 540.

33 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

33, an electronic system includes a central processing unit (CPU) 630, an interface 630, a peripheral device 630, a main memory 640, an auxiliary memory 650, SECONDARY MEMORY), and a bus 660 (BUS).

The central processing unit 610, the interface 620, the peripheral unit 630, the main storage unit 640, and the auxiliary storage unit 650 may be coupled to each other via the bus 660. [ The bus 660 corresponds to a path through which data is moved.

The central processing unit 610 may include a control device, a computing device, and the like to execute a program and process data.

The interface 620 may perform functions to transmit data to or receive data from the communication network. The interface 520 may be in wired or wireless form. For example, the interface 520 may include an antenna or a wired or wireless transceiver.

The peripheral device 630 can input and output data including a mouse, a keyboard, a display device, and a printer device.

The main storage device 640 transmits and receives data to and from the central processing unit 610, and may store data and / or commands necessary for executing the program. The semiconductor device according to some embodiments of the present invention may be provided as a part of the main storage device 640. [

The auxiliary storage device 650 may store data and / or instructions, etc., including non-volatile storage such as magnetic tape, magnetic disk, floppy disk, hard disk, optical disk, The auxiliary storage device 650 can store data even when the power of the electronic system is shut off.

In addition, the semiconductor device according to some embodiments of the present invention may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box a digital audio recorder, a digital audio player, a digital picture recorder, a digital audio recorder, a digital audio recorder, a digital audio recorder, A digital video player, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer Is provided as one of various components of an electronic device such as one of various electronic devices constituting a network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: substrate 110: field insulating film
F1: first active pin F2: second active pin
TR1: first gate structure TR2: second gate structure
210: first semiconductor pattern 220: second semiconductor pattern
300: Blocking membrane

Claims (20)

First and second active pins extending in a first direction on the substrate and spaced apart in a second direction intersecting with the first direction;
A gate structure formed on the first and second active pins, the gate structure extending in the second direction;
A first semiconductor pattern formed on the first active pin and disposed on at least one side of the gate structure;
And a second semiconductor pattern formed on the second active pin and disposed on at least one side of the gate structure,
The first semiconductor pattern may include:
A first pattern comprising a first semiconductor material,
And a second pattern disposed below the first pattern between the first and second active pins and including a second semiconductor material different from the first semiconductor material,
Wherein the second semiconductor pattern is formed by:
A third pattern comprising the first semiconductor material;
And a fourth pattern disposed below the third pattern between the first and second active pins and including the second semiconductor material and in contact with the second pattern. The method according to claim 1,
Wherein the first pattern and the third pattern are in contact with each other. The method according to claim 1,
Wherein the first pattern includes a first subpattern and a second subpattern on the first subpattern,
And the third pattern includes a third sub pattern and a fourth sub pattern on the third sub pattern. The method of claim 3,
Wherein the first sub pattern and the second sub pattern have different concentrations of impurities contained in the first semiconductor material. The method of claim 3,
Wherein the third sub pattern and the fourth sub pattern have different concentrations of impurities contained in the first semiconductor material. The method according to claim 1,
And the second pattern is formed so as to cover the entire lower surface of the first pattern between the first and second active pins. The method according to claim 1,
And the fourth pattern is formed so as to cover the entire lower surface of the third pattern between the first and second active pins. The method according to claim 1,
And the second pattern is formed so as to cover the entire outer surface of the first pattern. The method according to claim 1,
And the fourth pattern is formed so as to cover the entire outer surface of the third pattern. The method according to claim 1,
Wherein the first semiconductor material comprises at least one of SiP, SiC, and SiCP. The method according to claim 1,
Wherein the second semiconductor material comprises SiGe. The method according to claim 1,
Wherein the first semiconductor material has a smaller lattice constant than the second semiconductor material. First and second active pins extending in a first direction on the substrate and spaced apart in a second direction intersecting the first direction;
A gate structure formed on the first and second active pins, the gate structure extending in the second direction;
A first semiconductor pattern formed on the first active pin;
A second semiconductor pattern formed on the second active pin;
A field insulating film formed between the first and second active pins;
A first pattern formed on the field insulating film between the first and second active fins and spaced apart from the field insulating film so as to be in contact with the first and second semiconductor patterns and including a first semiconductor material; And
And a second pattern formed on the first pattern, the second pattern including a second semiconductor material different from the first semiconductor material. 14. The method of claim 13,
Wherein the first and second semiconductor patterns comprise the second semiconductor material. 15. The method of claim 14,
Wherein a concentration of an impurity contained in the second semiconductor material included in the second pattern is higher than a concentration of an impurity contained in the second semiconductor material included in the first and second semiconductor patterns. A substrate defining a first region and a second region;
First and second active pins extending in a first direction in the first region of the substrate and spaced apart in a second direction intersecting the first direction;
A first gate structure formed on the first and second active pins, the first gate structure extending in the second direction;
A first semiconductor pattern formed on the first and second active pins and disposed on at least one side of the first gate structure, the first semiconductor pattern comprising a first semiconductor material;
A second semiconductor pattern formed below the first semiconductor pattern between the first and second active fins and including a second semiconductor material different from the first semiconductor material;
Third and fourth active pins extending in the first direction in the second region of the substrate and spaced apart in the second direction;
A second gate structure formed on the third and fourth active pins, the second gate structure extending in the second direction; And
And a third semiconductor pattern formed on the third and fourth active pins and disposed on at least one side of the second gate structure, the third semiconductor pattern including the second semiconductor material. 17. The method of claim 16,
Wherein the first semiconductor material comprises at least one of SiP, SiC, and SiCP. 18. The method of claim 17,
Wherein the second semiconductor material comprises SiGe. Forming first and second pins extending in a first direction on the substrate,
Forming a dummy gate structure on the first and second pins, the dummy gate structure extending in a second direction intersecting with the first direction,
Epitaxially growing first and second semiconductor patterns on the first and second fins disposed on at least one side of the dummy gate structure, wherein the first and second semiconductor patterns are not in contact with each other,
Selectively forming a blocking epitaxial film under the first and second semiconductor patterns between the first and second semiconductor patterns, wherein the blocking epitaxial film is formed on the first and second semiconductor patterns, &Lt; / RTI &gt; and other materials,
And removing the dummy gate electrode. 20. The method of claim 19,
Further comprising removing a portion of the blocking epitaxial film formed on the surfaces exposed to the outside of the first and second semiconductor patterns.

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